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LM5108
SLUSDP6 – MAY 2019
LM5108 Robust and Compact 100-V Half-Bridge Gate Driver
1 Features
3 Description
•
The LM5108 is a high frequency half-bridge gate
driver with maximum switch node (HS) voltage rating
of 100 V. It allows for two N-channel MOSFETs to be
controlled in half-bridge configuration based
topologies such as synchronous buck, full bridge,
active clamp forward, LLC, and synchronous boost.
1
•
•
•
•
•
•
•
•
•
•
•
•
Drives two N-channel MOSFETs in high-side lowside configuration
Available in 3-mm x 3-mm package
Interlock or cross-conduction protection
Enable/disable functionality
Absolute maximum negative voltage handling on
HS (–5 V)
5-V typical under voltage lockout
20-ns typical propagation delay
11-ns rise, 8-ns typical fall time with 1000-pF load
1-ns typical delay matching
2.6-A sink, 1.6-A source output currents
Absolute maximum boot voltage 110 V
Low current (7-µA) consumption when disabled
Integrated bootstrap diode
2 Applications
•
•
•
Motor drives and power tools
Switch-mode power supplies
Auxiliary inverters
Simplified Application Diagram
7V
75V
VDD
EN
HO
NC
HI
HB
LI
HS
VSS
LO
To Load
The device has interlock functionality which, prevents
both outputs from being high at the same time, in the
case when both of the inputs are high. This interlock
feature improves system robustness in motor drive
and power tools applications. Enable and disable
functionality allows for the flexible and fast control of
the power stage. Battery powered tools can also use
enable feature of the LM5108 to reduce the standby
current as well as to respond to system fault. The
inputs are independent of supply voltage and can
have independent pulse width. This allows maximum
control flexibility. Both inputs and enable have
sufficient hysteresis to improve the system
robustness in noise prone applications such as motor
drives.
The low-side and the high-side outputs are matched
to 1-ns between the turn-on and turn-off of each
other. This allows for dead-time optimization which inturn improves efficiency. 5-V UVLO allows the driver
to operate at lower bias supplies which further allows
the power stage to operate at higher switching
frequency without increasing switching losses. VDD
and HB UVLO threshold specifications are designed
in such as way that both the high-side and low-side
driver turns on typically at 5 V. If both VDD and HB
UVLO thresholds are the same then designer would
need higher bias supply than the VDD UVLO
threshold to turn-on both high-side and low-side
driver.
An on-board bootstrap diode eliminates the need for
an external discrete diode which improves board
space utilization. Small package enables dense
power designs such as power tools.
Device Information(1)
PART NUMBER
LM5108
PACKAGE (SIZE)
SON10 (3 mm x 3 mm)
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
LM5108
SLUSDP6 – MAY 2019
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Table of Contents
1
2
3
4
5
6
7
Features ..................................................................
Applications ...........................................................
Description .............................................................
Revision History.....................................................
Pin Configuration and Functions .........................
Specifications.........................................................
1
1
1
2
3
4
6.1
6.2
6.3
6.4
6.5
6.6
6.7
4
4
4
5
5
6
7
Absolute Maximum Ratings ......................................
ESD Ratings..............................................................
Recommended Operating Conditions.......................
Thermal Information ..................................................
Electrical Characteristics...........................................
Switching Characteristics ..........................................
Typical Characteristics ..............................................
7.3 Feature Description................................................. 13
7.4 Device Functional Modes........................................ 15
8
Application and Implementation ........................ 16
8.1 Application Information............................................ 16
8.2 Typical Application ................................................. 17
9 Power Supply Recommendations...................... 24
10 Layout................................................................... 25
10.1 Layout Guidelines ................................................. 25
10.2 Layout Example .................................................... 25
11 Device and Documentation Support ................. 26
11.1
11.2
11.3
11.4
11.5
Detailed Description ............................................ 12
7.1 Overview ................................................................. 12
7.2 Functional Block Diagram ....................................... 12
Receiving Notification of Documentation Updates
Community Resources..........................................
Trademarks ...........................................................
Electrostatic Discharge Caution ............................
Glossary ................................................................
26
26
26
26
26
12 Mechanical, Packaging, and Orderable
Information ........................................................... 26
4 Revision History
2
DATE
REVISION
NOTES
May 2019
*
Initial release.
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5 Pin Configuration and Functions
DRC Package
10-Pin VSON With Exposed Thermal Pad
Top View
VDD
1
NC
2
10
Thermal
Pad
LO
9
VSS
8
LI
HB
3
HO
4
7
HI
HS
5
6
EN
Not to scale
Pin Functions
PIN
NAME
EN
DRC
6
I/O (1)
DESCRIPTION
I
Enable input. When this pin is pulled high, it will enable the driver. If left floating or
pulled low, it will disable the driver. 1 nF filter capacitor is recommended for highnoise systems.
HB
3
P
High-side bootstrap supply. The bootstrap diode is on-chip but the external bootstrap
capacitor is required. Connect positive side of the bootstrap capacitor to this pin.
Typical recommended value of HB bypass capacitor is 0.1 μF, This value primarily
depends on the gate charge of the high-side MOSFET. When using external boot
diode, connect cathode of the diode to this pin.
HI
7
I
High-side input.
HO
4
O
High-side output. Connect to the gate of the high-side power MOSFET or one end of
external gate resistor, when used.
HS
5
P
High-side source connection. Connect to source of high-side power MOSFET.
Connect negative side of bootstrap capacitor to this pin.
LI
8
I
Low-side input
LO
10
O
Low-side output. Connect to the gate of the low-side power MOSFET or one end of
external gate resistor, when used.
NC
2
—
Not connected internally.
VDD
1
P
Positive supply to the low-side gate driver. Decouple this pin to VSS. Typical
decoupling capacitor value is 1 μF. When using an external boot diode, connect the
anode to this pin.
VSS
9
G
Negative supply terminal for the device which is generally the system ground.
—
Connect to a large thermal mass trace (generally IC ground plane) to improve
thermal performance. This can only be electrically connected to VSS.
Thermal pad
(1)
P = Power, G = Ground, I = Input, O = Output, I/O = Input/Output
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6 Specifications
6.1 Absolute Maximum Ratings
All voltages are with respect to Vss (1) (2)
MIN
MAX
UNIT
VDD
Supply voltage
–0.3
20
V
VEN, VHI, VLI
Input voltages on EN, HI and LI
–0.3
20
V
VLO
Output voltage on LO
–0.3
VDD + 0.3
V
VHO
Output voltage on HO
VHS – 0.3
VHB + 0.3
V
VHS
Voltage on HS
–5
105
V
VHB
Voltage on HB
–0.3
110
V
VHB-HS
Voltage on HB with respect to HS
–0.3
20
V
TJ
Operating junction temperature
–40
150
°C
300
°C
150
°C
Lead temperature (soldering, 10 sec.)
Tstg
(1)
(2)
Storage temperature
–65
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
All voltages are with respect to Vss. Currents are positive into, negative out of the specified terminal.
6.2 ESD Ratings
VALUE
V(ESD)
(1)
(2)
(3)
Electrostatic discharge
Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001 (1) (2)
±2000
Charged-device model (CDM), per JEDEC specification JESD22-C101 (3)
±1500
UNIT
V
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
Pins HS, HB and HO are rated at 500V HBM
JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
6.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
VDD
Supply voltage
VEN, VHI, VLI
Input Voltage
VLO
Low side output voltage
VHO
High side output voltage
(1)
VHS
Voltage on HS
VHB
Voltage on HB
Vsr
Voltage slew rate on HS
TJ
Operating junction temperature
(1)
4
MIN
NOM
MAX
UNIT
5.5
12
16
V
0
VDD
V
0
VDD
V
VHS
VHB
V
–1
100
V
VHS + 5.5
VHS+16
V
50
V/ns
125
°C
–40
VHB-HS < 16V (Voltage on HB with respect to HS must be less than 16V)
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6.4 Thermal Information
LM5108
THERMAL METRIC (1)
DRC
UNIT
10 PINS
RθJA
Junction-to-ambient thermal resistance
47.3
°C/W
RθJC(top)
Junction-to-case (top) thermal resistance
50.3
°C/W
RθJB
Junction-to-board thermal resistance
21.3
°C/W
ψJT
Junction-to-top characterization parameter
1.0
°C/W
ψJB
Junction-to-board characterization parameter
21.2
°C/W
RθJC(bot)
Junction-to-case (bottom) thermal resistance
4.4
°C/W
(1)
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report, SPRA953.
6.5 Electrical Characteristics
VDD = VHB = VEN =12 V, VHS = VSS = 0 V, No load on LO or HO, TA = 25°C (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX UNIT
SUPPLY CURRENTS
IDD
VDD quiescent current
VLI = VHI = 0
0.28
0.29
mA
IDDO
VDD operating current
f = 500 kHz
2.3
2.4
mA
IHB
HB quiescent current
VLI = VHI = 0 V
0.13
0.14
mA
IHBO
HB operating current
f = 500 kHz
2.5
2.8
mA
ILK
Leakage current
VHS = VHB = 110 V
2.0
μA
IDD_DIS
IDD when driver is disabled
VEN = 0
7.0
μA
INPUT
VHIT
Input rising threshold
VLIT
Input falling threshold
2.3
VIHYS
Input voltage Hysteresis
0.7
V
RIN
Input pulldown resistance
250
kΩ
1.0
V
V
ENABLE
VEN
Voltage threshold on EN pin to enable the driver
1.65
VDIS
Voltage threshold on EN pin to disable the driver
VENHYS
Enable pin hysteresis
0.12
V
REN
EN pin internal pull-down resistor
250
kΩ
1.0
V
V
UNDERVOLTAGE LOCKOUT PROTECTION (UVLO)
VDDR
VDD rising threshold
4.8
5.0
5.2
V
VDDF
VDD falling threshold
4.3
4.5
4.8
V
VDDHYS
VDD threshold hysteresis
VHBR
HB rising threshold with respect to HS pin
3.4
3.7
4.1
V
VHBF
HB falling threshold with respect to HS pin
3.1
3.4
3.8
V
VHBHYS
HB threshold hysteresis
0.5
V
0.3
V
V
BOOTSTRAP DIODE
VF
Low-current forward voltage
IVDD-HB = 100 μA
0.55
VFI
High-current forward voltage
IVDD-HB = 80 mA
0.9
V
RD
Dynamic resistance, ΔVF/ΔI
IVDD-HB = 100 mA and 80 mA
2.0
Ω
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Electrical Characteristics (continued)
VDD = VHB = VEN =12 V, VHS = VSS = 0 V, No load on LO or HO, TA = 25°C (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX UNIT
LO GATE DRIVER
VLOL
Low level output voltage
ILO = 100 mA
0.13
V
VLOH
High level output voltage
ILO = -100 mA, VLOH = VDD – VLO
0.4
V
Peak pullup current
VLO = 0 V
1.6
A
Peak pulldown current
VLO = 12 V
2.6
A
V
HO GATE DRIVER
VHOL
Low level output voltage
IHO = 100 mA
0.13
VHOH
High level output voltage
IHO = –100 mA, VHOH = VHB- VHO
0.4
Peak pullup current
VHO = 0 V
1.6
A
Peak pulldown current
VHO = 12 V
2.6
A
6.6 Switching Characteristics
VDD = VHB = VEN = 12 V, VHS = VSS = 0 V, No load on LO or HO, TA = 25°C, (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
PROPAGATION DELAYS
tDLFF
VLI falling to VLO falling
See Figure 1
20
ns
tDHFF
VHI falling to VHO falling
See Figure 1
20
ns
tDLRR
VLI rising to VLO rising
See Figure 1
20
ns
tDHRR
VHI rising to VHO rising
See Figure 1
20
ns
DELAY MATCHING
tMON
From LO being ON to HO being OFF
See Figure 1
1
5
ns
tMOFF
From LO being OFF to HO being ON
See Figure 1
1
5
ns
OUTPUT RISE AND FALL TIME
tR
LO, HO rise time
CLOAD = 1000 pF
11
ns
tF
LO, HO fall time
CLOAD = 1000 pF
8
ns
IF = 20 mA, IREV = 0.5 A
20
MISCELLANEOUS
TPW,min
Minimum input pulse width that changes the output
Bootstrap diode turnoff time
6
40
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ns
ns
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LI
Voltage (V)
Voltage (V)
HI
Input
(HI, LI)
LO
TDLRR, TDHRR
Output
(HO, LO)
HO
Time (s)
TDLFF,
TDHFF
Time (s)
TMOFF
TMON
Figure 1. Timing Diagram
6.7 Typical Characteristics
Unless otherwise specified VVDD=VHB = 12 V, VHS=VVSS = 0 V, No load on outputs
0.3
0.22
0.26
HB Quiescent Current (mA)
VDD Quiescent Current (mA)
0.28
0.24
0.22
0.2
0.18
0.16
0.14
5.5V
12V
16V
0.12
0.1
-40
-15
10
35
60
Temperature (°C)
85
110 125
0.18
0.14
0.1
0.06
0.02
-40
IDDQ
5.5V
12V
16V
-15
10
35
60
Temperature (°C)
85
VHI = VLI = 0 V
VHI = VLI = 0 V
Figure 2. VDD Quiescent Current
Figure 3. HB Quiescent Current
110 125
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Typical Characteristics (continued)
Unless otherwise specified VVDD=VHB = 12 V, VHS=VVSS = 0 V, No load on outputs
4.5
6
-40°C
25°°C
125°°C
5
3.5
3
IHBO (mA)
4
IDDO (mA)
-40°C
25°C
125°C
4
3
2.5
2
1.5
2
1
1
0.5
0
0
1
2
3 4 5 67 10
CL = 0 F
20 30 50 70100
Frequency (kHz)
200
1
500 1000
2
3 4 5 67 10
IDDO
VDD =VHB= 12V
CL = 0 F
Figure 4. VDD Operating Current
5.5V
12V
16V
IHBO
VDD =VHB= 12V
2.21
Input Rising Threshold (V)
IDD_DIS (PA)
500 1000
2.22
10
8
6
4
2.2
2.19
2.18
5.5V
12V
16V
2.17
2
0
-40
200
Figure 5. HB Operating Current
14
12
20 30 50 70100
Frequency (kHz)
-15
10
CL = 0 F
35
60
Temperature (°C)
85
2.16
-40
110 125
-15
10
IDD_
35
60
Temperature (°C)
85
110 125
IN_R
VEN = 0 V
Figure 6. VDD Current When Disabled
Figure 7. Input Rising Threshold
1.145
280
270
1.135
Input Resistance (k:)
Input Falling Threshold (V)
1.14
1.13
1.125
1.12
1.115
1.105
-40
-15
10
35
60
Temperature (°C)
85
250
240
5.5V
12V
16V
1.11
260
110 125
230
-40
IN_F
Figure 8. Input Falling Threshold
8
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-15
10
35
60
Temperature (°C)
85
110 125
R_IN
Figure 9. Input Pull-down Resistor
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Typical Characteristics (continued)
Unless otherwise specified VVDD=VHB = 12 V, VHS=VVSS = 0 V, No load on outputs
1.8
1.35
5.5V
12V
16V
5.5V
12V
16V
1.3
Disable Threshold (V)
Enable Threshold (V)
1.7
1.6
1.5
1.4
1.25
1.2
1.15
1.1
1.05
1
1.3
0.95
1.2
-40
-15
10
35
60
Temperature (°C)
85
0.9
-40
110 125
-15
5.2
5
3.8
4.8
4.6
110 125
Dis_
3.6
3.4
Rise
Fall
Rise
Fall
-15
10
35
60
Temperature (°C)
85
3
-40
110 125
-15
10
VDDU
Figure 12. VDD UVLO Threshold
35
60
Temperature (°C)
85
110 125
HBUV
Figure 13. HB UVLO Threshold
1.8
1
Diode Dynamic Resistance (:)
100uA
80mA
Diode Forward Voltage (V)
85
3.2
4.4
0.8
0.6
0.4
0.2
-40
35
60
Temperature (°C)
Figure 11. Disable Threshold
4
HB UVLO (V)
VDD UVLO (V)
Figure 10. Enable Threshold
4.2
-40
10
EN_T
-15
10
35
60
Temperature (°C)
85
1.7
1.6
1.5
1.4
1.3
1.2
-40
110 125
Vf
Figure 14. Boot Diode Forward Voltage Drop
-15
10
35
60
Temperature (°C)
85
110 125
Figure 15. Boot Diode Dynamic Resistance
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Typical Characteristics (continued)
Unless otherwise specified VVDD=VHB = 12 V, VHS=VVSS = 0 V, No load on outputs
10.5
15
5.5V
12V
16V
5.5V
12V
16V
10
LO Fall Time (ns)
LO Rise Time (ns)
14
13
12
11
9.5
9
8.5
10
9
-40
-15
10
35
60
Temperature (°C)
85
8
-40
110 125
-15
10
LO_R
CL=1000pF
35
60
Temperature (°C)
85
110 125
LO_F
CL=1000pF
Figure 16. LO Rise Time
Figure 17. LO Fall Time
9
18
5.5V
12V
16V
5.5V
12V
16V
8.7
HO Fall Time (ns)
HO Rise Time (ns)
15
12
8.4
8.1
7.8
9
7.5
6
-40
-15
10
35
60
Temperature (°C)
85
7.2
-40
110 125
-15
CL=1000pF
85
110 125
HO_F
Figure 19. HO Fall Time
20
21
19
20
19
Time (ns)
18
Time (ns)
35
60
Temperature (°C)
CL=1000pF
Figure 18. HO Rise Time
17
16
18
17
16
5.5V
12V
16V
15
14
-40
-15
10
35
60
Temperature (°C)
85
110 125
5.5V
12V
16V
15
14
-40
-15
TDHR
CL=No Load
10
35
60
Temperature (°C)
85
110 125
TDHF
CL= No Load
Figure 20. HO Rising Propagation Delay (TDHRR)
10
10
HO_R
Figure 21. HO Falling Propagation Delay (TDHFF)
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Typical Characteristics (continued)
Unless otherwise specified VVDD=VHB = 12 V, VHS=VVSS = 0 V, No load on outputs
20
19
19.5
18.5
19
18
17.5
18
Time (ns)
Time (ns)
18.5
17.5
17
17
16.5
16
16.5
16
15.5
5.5V
12V
16V
15.5
15
-40
-15
10
35
60
Temperature (°C)
85
5.5V
12V
16V
15
110 125
14.5
-40
-15
TDLR
CL= No Load
10
35
60
Temperature (°C)
85
110 125
TDLF
CL= No Load
Figure 22. LO Rising Propagation Delay (TDLRR)
Figure 23. LO Falling Propagation Delay (TDLFF)
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7 Detailed Description
7.1 Overview
The LM5108 is a high-voltage gate driver designed to drive both the high-side and the low-side N-channel FETs
in a synchronous buck or a half-bridge configurations. The two outputs are independently controlled with two
TTL-compatible input signals. The device can also work with CMOS type control signals at its inputs as long as
signals meet turn-on and turn-off threshold specifications of the LM5108. The floating high-side driver is capable
of working with HS voltage up to 100 V with respect to VSS. A 100 V bootstrap diode is integrated in the LM5108
device to charge high-side gate drive bootstrap capacitor. A robust level shifter operates at high speed while
consuming low power and provides clean level transitions from the control logic to the high-side gate driver.
Undervoltage lockout (UVLO) is provided on both the low-side and the high-side power rails. EN pin is provided
(in DRC packaged parts) to enable or disable the driver. The driver also has input interlock functionality, which
shuts off both the outputs when the two inputs overlap.
7.2 Functional Block Diagram
HB
UVLO
DRIVER
STAGE
LEVEL
SHIFT
HO
HS
HI
VDD
EN
UVLO
DRIVER
STAGE
LO
Interlock Logic
VSS
LI
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7.3 Feature Description
7.3.1 Enable
The device in DRC package has an enable (EN) pin. The outputs will be active only if the EN pin voltage is
above the threshold voltage. Outputs will be held low if EN pin is left floating or pulled-down to ground. An
internal 250 kΩ resistor connects EN pin to VSS pin. Thus, leaving the EN pin floating disables the device.
Externally pulling EN pin to ground shall also disable the device. If the EN pin is not used, then it is
recommended to connect it to VDD pin. If a pull-up resistor needs to be used then a strong pull-up resistor is
recommended. For 12V supply voltage, a 10kΩ pull-up is suggested. In noise prone application, a small filter
capacitor, 1nF, should be connected from the EN pin to VSS pin as close to the device as possible. An analog or
a digital controller output pin could be connected to EN pin to enable or disable the device. Built-in hysteresis
helps prevent any nuisance tripping or chattering of the outputs.
7.3.2 Start-up and UVLO
Both the high-side and the low-side driver stages include UVLO protection circuitry which monitors the supply
voltage (VDD) and the bootstrap capacitor voltage (VHB–HS). The UVLO circuit inhibits each output until sufficient
supply voltage is available to turn on the external MOSFETs. The built-in UVLO hysteresis prevents chattering
during supply voltage variations. When the supply voltage is applied to the VDD pin of the device, both the
outputs are held low until VDD exceeds the UVLO threshold, typically 5 V. Any UVLO condition on the bootstrap
capacitor (VHB–HS) disables only the high- side output (HO).
Table 1. VDD UVLO Logic Operation
Condition (VHB-HS > VHBR and VEN > Enable Threshold)
VDD-VSS < VDDR during device start-up
VDD-VSS < VDDR – VDDH after device start-up
HI
LI
HO
LO
H
L
L
L
L
H
L
L
H
H
L
L
L
L
L
L
H
L
L
L
L
H
L
L
H
H
L
L
L
L
L
L
HI
LI
HO
LO
H
L
L
L
L
H
L
H
H
H
L
L
L
Table 2. HB UVLO Logic Operation
Condition (VDD > VDDR and VEN > Enable Threshold)
VHB-HS < VHBR during device start-up
VHB-HS < VHBR – VHBH after device start-up
L
L
L
H
L
L
L
L
H
L
H
H
H
L
L
L
L
L
L
7.3.3 Input Stages and Interlock Protection
The two inputs operate independently, with an exception that both outputs will be pulled low when both inputs
are high or overlap. The independence allows for full control of two outputs compared to the gate drivers that
have a single input. The device has input interlock or cross-conduction protection. Whenever both the inputs are
high, the internal logic turns both the outputs off. Once the device is in shoot-through mode, when one of the
inputs goes low, the outputs follow the input logic. There is no other fixed time de-glitch filter implemented in the
device and therefore propagation delay and delay matching are not sacrificed. In other words, there is no built-in
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dead-time due to the interlock feature. Any noise on the input that could cause the output to shoot-through will be
filtered by this feature and the system stays protected. Because the inputs are independent of supply voltage,
they can be connected to outputs of either digital controller or analog controller. Small filter at the inputs of the
driver further improves system robustness in noise prone applications. The inputs have internal pull down
resistors with typical value of 250 kΩ. Thus, when the inputs are floating, the outputs are held low.
HI
LI
LO
Interlock
HO
Time
Figure 24. Interlock or Input Shoot-through Protection
7.3.4 Level Shifter
The level shift circuit is the interface from the high-side input, which is a VSS referenced signal, to the high-side
driver stage which is referenced to the switch node (HS pin). The level shift allows control of the HO output which
is referenced to the HS pin. The delay introduced by the level shifter is kept as low as possible and therefore the
device provides excellent propagation delay characteristic and delay matching with the low-side driver output.
Low delay matching allows power stages to operate with less dead time. The reduction in dead-time is very
important in applications where high efficiency is required.
7.3.5 Output Stage
The output stages are the interface from level shifter output to the power MOSFETs in the power train. High slew
rate, low resistance, and moderate peak current capability of both outputs allow for efficient switching of the
power MOSFETs. The low-side output stage is referenced to VSS and the high-side is referenced to HS. The
device output stages are robust to handle harsh environment. The device output stages feature a pull-up
structure which delivers the peak current when it is most needed, during the Miller plateau region of the power
switch turn on transition. The output pull-up and pull-down structure of the device is totem pole NMOS-PMOS
structure.
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7.3.6 Negative Voltage Transients
In most applications, the body diode of the external low-side power MOSFET clamps the HS node to ground. In
some situations, board capacitances and inductances can cause the HS node to transiently swing several volts
below ground, before the body diode of the external low-side MOSFET clamps this swing. When used in
conjunction with the LM5108, the HS node can swing below ground as long as specifications are not violated and
conditions mentioned in this section are followed.
HS must always be at a lower potential than HO. Pulling HO more negative than specified conditions can
activate parasitic transistors which may result in excessive current flow from the HB supply. This may result in
damage to the device. The same relationship is true with LO and VSS. If necessary, a Schottky diode can be
placed externally between HO and HS or LO and VSS to protect the device from this type of transient. The diode
must be placed as close to the device pins as possible in order to be effective.
Ensure that the HB to HS operating voltage is 16 V or less. Hence, if the HS pin transient voltage is –5 V, then
VDD (and thus HB) is ideally limited to 11 V to keep the HB to HS voltage below 16 V. Generally when HS
swings negative, HB follows HS instantaneously and therefore the HB to HS voltage does not significantly
overshoot.
Low ESR bypass capacitors from HB to HS and from VDD to VSS are essential for proper operation of the gate
driver device. The capacitor should be located at the leads of the device to minimize series inductance. The peak
currents from LO and HO can be quite large. Any series inductances with the bypass capacitor causes voltage
ringing at the leads of the device which must be avoided for reliable operation.
7.4 Device Functional Modes
When the device is enabled, the device operates in normal mode and UVLO mode. See Start-up and UVLO for
more information on UVLO operation mode. In normal mode when the VDD and VHB–HS are above UVLO
threshold, the output stage is dependent on the states of the EN, HI and LI pins. The output HO and LO will be
low if input state is floating.
Table 3. Input/Output Logic in Normal Mode of Operation
EN
L
Floating
(1)
(2)
LI
HO
LO
H
H
L
L
L
H
L
L
H
L
L
L
L
L
L
L
H
H
L
L
L
H
L
H
H
L
H
L
L
L
L
L
Floating
L
L
L
Floating
H
L
H
L
Floating
L
L
H
Floating
H
L
Floating
Floating
L
L
H
H
(1)
HI
(2)
HO is measured with respect to HS
LO is measured with respect to VSS
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8 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
8.1 Application Information
Most electronic devices and applications are becoming more and more power hungry. These applications are
also reducing in overall size. One way to achieve both high power and low size is to improve the efficiency and
distribute the power loss optimally. Most of these applications employ power MOSFETs and they are being
switched at higher and higher frequencies. To operate power MOSFETs at high switching frequencies and to
reduce associated switching losses, a powerful gate driver is employed between the PWM output of controller
and the gates of the power semiconductor devices, such as power MOSFETs, IGBTs, SiC FETs, and GaN FETs.
Many of these applications require proper UVLO protection so that power semiconductor devices are turned ON
and OFF optimally. Also, gate drivers are indispensable when it is impossible for the PWM controller to directly
drive the gates of the switching devices. With the advent of digital power, this situation is often encountered
because the PWM signal from the digital controller is often a 3.3-V logic signal which cannot effectively turn on a
power switch. A level-shift circuit is needed to boost the 3.3-V signal to the gate-drive voltage (such as 12 V or 5
V) in order to fully turn-on the power device, minimize conduction losses, and minimize the switching losses.
Traditional buffer drive circuits based on NPN/PNP bipolar transistors in totem-pole arrangement prove
inadequate with digital power because they lack level-shifting capability and under voltage lockout protection.
Gate drivers effectively combine both the level-shifting and buffer-drive functions. Gate drivers also solve other
problems such as minimizing the effect of high-frequency switching noise (by placing the high-current driver
device physically close to the power switch), driving gate-drive transformers and controlling floating power device
gates. This helps reduce power dissipation and thermal stress in controllers by moving gate charge power losses
from the controller IC to the gate driver.
LM5108 gate drivers offer high voltage (100 V), small delays (20 ns), and good driving capability (1.6 A/2.6 A) in
a single device. The floating high-side driver is capable of operating with switch node voltages up to 100 V. This
allows for N-channel MOSFETs control in half-bridge, full-bridge, synchronous buck, synchronous boost, and
active clamp topologies. LM5108 gate driver IC also has built-in bootstrap diode to help power supply designers
optimize PWB area and to help reduce bill of material cost in most applications. The driver has an enable/disable
functionality to be used in applications where driver needs to be enabled or disabled based on fault condition in
other parts of the circuit. Interlock functionality of the device is very useful in applications where overall reliability
of the system is of utmost criteria and redundant protection is desired. Each channel is controlled by its
respective input pins (HI and LI), allowing flexibility to control ON and OFF state of the output. Both the outputs
are forced OFF when the two inputs overlap.
Switching power devices such as MOSFETs have two main loss components; switching losses and conduction
losses. Conduction loss is dominated by current through the device and ON resistance of the device. Switching
losses are dominated by gate charge of the switching device, gate voltage of the switching device, and switching
frequency. Applications where operating switching frequency is very high, the switching losses start to
significantly impact overall system efficiency. In such applications, to reduce the switching losses it becomes
essential to reduce the gate voltage. The gate voltage is determined by the supply voltage the gate driver ICs,
therefore, the gate driver IC needs to operate at lower supply voltage in such applications. LM5108 gate driver
has typical UVLO level of 5V and therefore, they are perfectly suitable for such applications. There is enough
UVLO hysteresis provided to avoid any chattering or nuisance tripping which improves system robustness.
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8.2 Typical Application
7V
75 V
EN
VDD
SECONDARY
SIDE
CIRCUIT
HB
HI
LI
CONTROL
PWM
CONTROLLER
DRIVE
HI
HO
HS
DRIVE
LO
LO
LM5108
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Figure 25. Typical Application
8.2.1 Design Requirements
Table below lists the system parameters. LM5108 needs to operate satisfactorily in conjunction with them.
Table 4. Design Requirements
Parameter
Value
MOSFET
CSD19535KTT
Maximum Bus/Input Voltage, Vin
75V
Operating Bias Votage, VDD
7V
Switching Frequency, Fsw
300kHz
Total Gate Charge of FET at given VDD, QG
52nC
MOSFET Internal Gate Resistance,
RGFET_Int
1.4
Maximum Duty Cycle, DMax
0.5
Gate Driver
LM5108
8.2.2 Detailed Design Procedure
8.2.2.1 Select Bootstrap and VDD Capacitor
The bootstrap capacitor must maintain the VHB-HS voltage above the UVLO threshold for normal operation.
Calculate the maximum allowable drop across the bootstrap capacitor, ΔVHB, with Equation 1.
¿VHB = VDD F VDH F VHBL
= :7 V 1 V (3.7 V 0.3 V); = 2.6 V
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where
•
•
•
VDD is the supply voltage of gate driver device
VDH is the bootstrap diode forward voltage drop
VHBL is the HB falling threshold ( VHBR(max) – VHBH)
(1)
In this example the allowed voltage drop across bootstrap capacitor is 2.6 V.
It is generally recommended that ripple voltage on both the bootstrap capacitor and VDD capacitor should be
minimized as much as possible. Many of commercial, industrial, and automotive applications use ripple value of
0.5 V.
Use Equation 2 to estimate the total charge needed per switching cycle from bootstrap capacitor.
DMAX
IHB
QTOTAL = QG + ILK × l
p+l p
fSW
fSW
= 52 nC + 0.003 nC + 0.43 nC = 52.43 nC
where
•
•
•
•
QG is the total MOSFET gate charge
ILK is the HB to VSS leakage current from datasheet
DMax is the converter maximum duty cycle
IHB is the HB quiescent current from the datasheet
(2)
The caculated total charge is 52.43 nC.
Next, use Equation 3 to estimate the minimum bootstrap capacitor value.
CBOOT :min ; =
52.43 nC
Q TOTAL
=
= 20.16 nF
¿VHB
2.6 V
(3)
The calculated value of minimum bootstrap capacitor is 20.16 nF. It should be noted that, this value of
capacitance is needed at full bias voltage. In practice, the value of the bootstrap capacitor must be greater than
calculated value to allow for situations where the power stage may skip pulse due to various transient conditions.
It is recommended to use a 100-nF bootstrap capacitor in this example. It is also recommenced to include
enough margin and place the bootstrap capacitor as close to the HB and HS pins as possible. Also place a small
size, 0402, low value, 1000 pF, capacitor to filter high frequency noise, in parallel with main bypass capacitor.
For this application, choose a CBOOT capacitor that has the following specifications: 0.1 µF, 25 V, X7R
As a general rule the local VDD bypass capacitor must be greater than the value of bootstrap capacitor value
(generally 10 times the bootstrap capacitor value). For this application choose a CVDD capacitor with the following
specifications: 1 µF , 25 V, X7R
CVDD capacitor is placed across VDD and VSS pin of the gate driver. Similar to bootstrap capacitors, place a
small size and low value capacitor in parallel with the main bypass capacitor. For this application, choose 0402,
1000 pF, capacitance in parallel with main bypass capacitor to filter high frequency noise.
The bootstrap and bias capacitors must be ceramic types with X7R dielectric or better. Choose a capacitor with a
voltage rating at least twice the maximum voltage that it will be exposed to. Choose this value because most
ceramic capacitors lose significant capacitance when biased. This value also improves the long term reliability of
the system.
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8.2.2.2 Estimate Driver Power Losses
The total power loss in gate driver device such as the LM5108 is the summation of the power loss in different
functional blocks of the gate driver device. These power loss components are explained in this section.
1. Equation 4 describes how quiescent currents (IDD and IHB) affect the static power losses, PQC.
PQC = :VDD × IDD ; + :VDD F VDH ; × IHB
= 7 V × 0.28 mA + 6 V × 0.13 mA = 2.74 mW
(4)
it is not shown here, but for better approximation, no load operating current, IDDO and IHBO can be added in
above equation.
2. Equation 5 shows how high-side to low-side leakage current (ILK) affects level-shifter losses (PILK).
PILK = VHB × ILK × D = 82 V × 2 µA × 0.5 = 0.082 mW
where
•
•
D is the high-side MOSFET duty cycle
VHB is the sum of input voltage and voltage across bootstrap capacitor.
(5)
3. Equation 6 shows how MOSFETs gate charge (QG) affects the dynamic losses, PQG.
R GD _R
R GD _R + R GATE + R GFET :int ;
= 2 × 7 V × 52 nC × 300 kHz × 0.74 = 0.16 W
PQG = 2 × VDD × Q G × fSW ×
where
•
•
•
•
•
QG is the total MOSFET gate charge
fSW is the switching frequency
RGD_R is the average value of pullup and pulldown resistor
RGATE is the external gate drive resistor
RGFET(int) is the power MOSFETs internal gate resistor
(6)
Assume there is no external gate resistor in this example. For simplicity, the resistance of the pull-up
MOSFET of the driver output section is considered here, which is typically 4 Ω. Substitute the application
values to calculate the dynamic loss due to gate charge, which is 160 mW here.
4. Equation 7 shows how parasitic level-shifter charge (QP) on each switching cycle affects dynamic losses,
(PLS) during high-side switching.
PLS = VHB × QP × fSW
(7)
For this example and simplicity, it is assumed that value of parasitic charge QP is 1 nC. Substituting values
results in 24.6 mW as level shifter dynamic loss. This estimate is very high for level shifter dynamic losses.
The sum of all the losses is 187.42 mW as a total gate driver loss. As shown in this example, in most
applications the dynamic loss due to gate charge dominates the total power loss in gate driver device. For gate
drivers that include bootstrap diode, one should also estimate losses in bootstrap diode. Diode forward
conduction loss is computed as product of average forward voltage drop and average forward current.
Equation 8 estimates the maximum allowable power loss of the device for a given ambient temperature.
PMAX =
kTJ F TA o
REJA
where
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•
•
•
•
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PMAX is the maximum allowed power dissipation in the gate driver device
TJ is the recommended maximum operating junction temperature
TA is hte ambient temperature of the gate driver device
RθJA is the junction-to-ambient thermal resistance
(8)
To better estimate the junction temperature of the gate driver device in the application, it is recommended to first
accurately measure the case temperature and then determine the power dissipation in a given application. Then
use ψJT to calculate junction temperature. After estimating junction temperature and measuring ambient
temperature in the application, calculate θJA(effective). Then, if design parameters (such as the value of an external
gate resistor or power MOSFET) change during the development of the project, use θJA(effective) to estimate how
these changes affect junction temperature of the gate driver device.
The Thermal Information table summarizes the thermal metrics for the driver package. For detailed information
regarding the thermal information table, please refer to the Semiconductor and Device Package Thermal Metrics
application report.
8.2.2.3 Selecting External Gate Resistor
In high-frequency switching power supply applications where high-current gate drivers such as the LM5108 are
used, parasitic inductances, parasitic capacitances and high-current loops can cause noise and ringing on the
gate of power MOSFETs. Often external gate resistors are used to damp this ringing and noise. In some
applications the gate charge, which is load on gate driver device, is significantly larger than gate driver peak
output current capability. In such applications external gate resistors can limit the peak output current of the gate
driver. it is recommended that there should be provision of external gate resistor whenever the layout or
application permits.
Use Equation 9 to calculate the driver high-side pull-up current.
IOHH =
VDD F VDH
R HOH + RGATE + RGFET:int;
where
•
•
•
•
•
IOHH is the high-side, peak pull-up current
VDH is the bootstrap diode forward voltage drop
RHOH is the gate driver internal high-side pull-up resistor. Value either directly provided in datasheet or can be
calculated from test conditions (RHOH = VHOH/IHO)
RGATE is the external gate resistance connected between driver output and power MOSFET gate
RGFET(int) is the MOSFET internal gate resistance provided by MOSFET datasheet
(9)
Use Equation 10 to calculate the driver high-side sink current.
IOLH =
VDD F VDH
R HOL + RGATE + RGFET:int;
where
•
RHOL is the gate driver internal high-side pull-down resistance
(10)
Use Equation 11 to calculate the driver low-side source current.
IOHL =
VDD
R LOH + RGATE + RGFET:int;
where
•
RLOH is the gate driver internal low-side pull-up resistance
(11)
Use Equation 12 to calculate the driver low-side sink current.
IOLL =
VDD
R LOL + RGATE + RGFET:int;
where
•
20
RLOL is the gate driver internal low-side pull-down resistance
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Typical peak pull up and pull down current of the device is 1.6 A and 2.6 A respectively. These equations help
reduce the peak current if needed. To establish different rise time value compared to fall time value, external
gate resistor can be anti-paralleled with diode-resistor combination as shown in Figure 25. Generally selecting an
optimal value or configuration of external gate resistor is an iterative process. For additional information on
selecting external gate resistor please refer to External Gate Resistor Design Guide for Gate Drivers
8.2.2.4 Delays and Pulse Width
The total delay encountered in the PWM, driver and power stage need to be considered for a number of reasons,
primarily delay in current limit response. Also to be considered are differences in delays between the drivers
which can lead to various concerns depending on the topology. The synchronous buck topology switching
requires careful selection of dead-time between the high-side and low-side switches to avoid cross conduction as
well as excessive body diode conduction.
Bridge topologies can be affected by a volt-second imbalance on the transformer if there is imbalance in the
high-side and low-side pulse widths in any operating condition. The LM5108 device has typical propagation delay
of 20 ns and typical delay matching of 1 ns.
Narrow input pulse width performance is an important consideration in gate driver devices, because output may
not follow input signals satisfactorily when input pulse widths are very narrow. Although there may be relatively
wide steady state PWM output signals from controller, very narrow pulses may be encountered under following
operating conditions.
• soft-start period
• large load transients
• short circuit conditions
These narrow pulses appear as an input signal to the gate driver device and the gate driver device need to
respond properly to these narrow signals.
The LM5108 device produces reliable output pulse even when the input pulses are very narrow and bias
voltages are very low. The propagation delay and delay matching do not get affected when the input pulse width
is very narrow.
8.2.2.5 External Bootstrap Diode
The LM5108 incorporates the bootstrap diode necessary to generate the high-side bias for HO to work
satisfactorily. The characteristics of this diode are important to achieve efficient, reliable operation. The
characteristics to consider are forward voltage drop and dynamic resistance. Generally, low forward voltage drop
diodes are preferred for low power loss during charging of the bootstrap capacitor. The device has a boot diode
forward voltage drop rated at 0.9 V and dynamic resistance of 2 Ω for reliable charge transfer to the bootstrap
capacitor. The dynamic characteristics to consider are diode recovery time and stored charge. Diode recovery
times that are specified without operating conditions, can be misleading. Diode recovery times at no forward
current (IF) can be noticeably less than with forward current applied. The LM5108 boot diode recovery is
specified as 20 ns at IF = 20 mA, IREV = 0.5 A. Dynamic impedance of LM5108 bootstrap diode helps limit the
peak forward current.
In applications where switching frequencies are very high, for example in excess of 1 MHz, and the low-side
minimum pulse widths are very small, the diode peak forward current could be very high and peak reverse
current could also be very high, specifically if high bootstrap capacitor value has been chosen. In such
applications it might be advisable to use external Schottky diode as bootstrap diode. It is safe to at least make a
provision for such diode on the board if possible.
8.2.2.6 VDD and Input Filter
Some switching power supply applications are extremely noisy. Noise may come from ground bouncing and
ringing at the inputs, (which are the HI and LI pins of the gate driver device). To mitigate such situations, the
LM5108 offers wide input threshold hysteresis. If these features are not enough, then the application might need
an input filter. Small filter such as 10-Ω resistor and 47-pF capacitor might be sufficient to filter noise at the inputs
of the gate driver device. This RC filter would introduce delay and therefore need to be considered carefully. High
frequency noise on bias supply can cause problems in performance of the gate driver device. To filter this noise
it is recommended to use 1-Ω resistor in series with VDD pin as shown in Figure 25. This resistor also acts as a
current limiting element. In the event of short circuit on the bias rail, this resistor opens up and prevents further
damage. This resistor can also be helpful in debugging the design during development phase.
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8.2.2.7 Transient Protection
As mentioned in previous sections, high power high switching frequency power supplies are inherently noisy.
High dV/dt and dI/dt in the circuit can cause negative voltage on different pins such as HO, LO, and HS. The
device tolerates negative voltage on HS pin as mentioned in specification tables. If parasitic elements of the
circuit cause very large negative swings, circuit might require additional protection. In such cases fast acting and
low leakage type Schottky diode should be used. This diode must be placed as close to the gate driver device
pin as possible for it to be effective in clamping excessive negative voltage on the gate driver device pin.
Sometimes a small resistor, (for example 2 Ω, in series with HS pin) is also effective in improving performance
reliability. To avoid the possibility of driver device damage due to over-voltage on its output pins or supply pins,
low leakage Zener diode can be used. A 15-V Zener diode is often sufficient to clamp the voltage below the
maximum recommended value of 16 V.
8.2.3 Application Curves
To minimize the switching losses in power supplies, turn-ON and turn-OFF of the power MOSFETs need to be
as fast as possible. Higher the drive current capability of the driver, faster the switching. Therefore, the LM5108
is designed with high drive current capability and low resistance of the output stages. One of the common way to
test the drive capability of the gate driver device , is to test it under heavy load. Rise time and fall time of the
outputs would provide idea of drive capability of the gate driver device. There must not be any resistance in this
test circuit. Figure 26 and Figure 27 shows rise time and fall time of HO respectively of LM5108. Figure 28 and
Figure 29 shows rise time and fall time of LO respectively of LM5108. For accuracy purpose, the VDD and HB
pin of the gate driver device were connected together. HS and VSS pins are also connected together for this test.
Peak current capability can be estimated using the fastest dV/dt along the rise and fall curve of the plot. This
method is also useful in comparing performance of two or more gate driver devices.
As explained in Delays and Pulse Width, propagation delay plays an important role in reliable operation of many
applications. Figure 30 and Figure 31 shows propagation delays of LM5108. In many switching power supply
applications input signals to the gate driver have large amplitude high frequency noise. If there is no filter
employed at the input, then there is a possibility of false signal passing through the gate driver and causing
shoot-through on the output. LM5108 prevents such shoot-through. If two inputs are high at the same time,
LM5108 shuts both the outputs off. Figure 32 shows interlock feature of LM5108.
VDD=VHB=12 V,
HS=VSS
CLOAD=68 nF
Ch1=HI, Ch3=HO
VDD=VHB=12 V, HS=VSS
Figure 26. HO Rise Time
22
CLOAD=68
nF
Ch1=HI, Ch3=HO
Figure 27. HO Fall Time
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VDD=VHB=12 V, HS=VSS
CLOAD=68 nF
Ch2=LI,
Ch4=LO
VDD=VHB=12 V, HS=VSS
Figure 28. LO Rise Time
VDD=VHB=
12 V,
HS=VSS
CLOAD=No
load
CLOAD=68 nF
Ch2=LI,
Ch4=LO
Figure 29. LO Fall Time
Ch1=HI Ch2=LI Ch3=HO Ch4=LO
VDD=VHB
=12 V,
HS=VSS
Figure 30. Propagation Delay
CLOAD=No
load
Ch1=HI Ch2=LI Ch3=HO Ch4=LO
Figure 31. Propagation Delay
HI (2V/div)
LI (2V/div)
HO (5V/div)
LO (5V/div)
VDD=VHB=12 V, HS=VSS
CLOAD=0 nF
Figure 32. Shoot-through Protection or Interlock
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9 Power Supply Recommendations
The recommended bias supply voltage range for LM5108 is from 5.5 V to 16 V. The lower end of this range is
governed by the internal under voltage-lockout (UVLO) protection feature, 5 V typical, of the VDD supply circuit
block. The upper end of this range is driven by the 16-V recomended maximum voltage rating of the VDD. It is
recommended that voltage on VDD pin should be lower than maximum recommended voltage.
The UVLO protection feature also involves a hysteresis function. This means that once the device is operating in
normal mode, if the VDD voltage drops, the device continues to operate in normal mode as far as the voltage
drop do not exceeds the hysteresis specification, VDDHYS. If the voltage drop is more than hysteresis
specification, the device shuts down. Therefore, while operating at or near the 5.5-V range, the voltage ripple on
the auxiliary power supply output should be smaller than the hysteresis specification of LM5108 to avoid
triggering device shutdown.
A local bypass capacitor should be placed between the VDD and GND pins. This capacitor should be located as
close to the device as possible. A low ESR, ceramic surface mount capacitor is recommended. It is
recommended to use two capacitors across VDD and GND: a low capacitance ceramic surface-mount capacitor
for high frequency filtering placed very close to VDD and GND pin, and another high capacitance value surfacemount capacitor for device bias requirements. In a similar manner, the current pulses delivered by the HO pin are
sourced from the HB pin. Therefore, two capacitors across the HB to HS are recommended. One low value small
size capacitor for high frequency filtering and another one high capacitance value capacitor to deliver HO pulses.
LM5108 has enable/disable functionality through EN pin. Therefore, signal at the EN pin should be as clean as
possible. If EN pin is not used, then it is recommended to connect the pin to VDD pin. If EN pin is pulled up
through a resistor, then the pull-up resistor needs to be strong. In noise prone applications, it is recommended to
filter the EN pin with small capacitor, such as X7R 0402 1nF.
In power supplies where noise is very dominant and there is space on the PWB (Printed Wiring Board), it is
recommended to place a small RC filter at the inputs. This allows for improving the overall performance of the
design. In such applications. it is also recommended to have a place holder for power MOSFET external gate
resistor. This resistor allows the control of not only the drive capability but also the slew rate on HS, which
impacts the performance of the high-side circuit. If diode is used across the external gate resistor, it is
recommended to use a resistor in series with the diode, which provides further control of fall time.
In power supply applications such as motor drives, there exist a lot of transients through-out the system. This
sometime causes over voltage and under voltage spikes on almost all pins of the gate driver device. To increase
the robustness of the design, it is recommended that the clamp diode should be used on the those pins. If user
does not wish to use power MOSFET parasitic diode, external clamp diode on HS pin is recommended, which
needs to be high voltage high current type (same rating as MOSFET) and very fast acting. The leakage of these
diodes across the temperature needs to be minimal.
In power supply applications where it is almost certain that there is excessive negative HS voltage, it is
recommended to place a small resistor between the HS pin and the switch node. This resistance helps limit
current into the driver device up to some extent. This resistor will impact the high side drive capability and
therefore needs to be considered carefully.
24
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LM5108
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10 Layout
10.1 Layout Guidelines
To achieve optimum performance of high-side and low-side gate drivers, one must consider following printed
wiring board (PWB) layout guidelines.
• Low ESR/ESL capacitors must be connected close to the device between VDD and VSS pins and between
HB and HS pins to support high peak currents drawn from VDD and HB pins during the turn-on of the
external MOSFETs.
• To prevent large voltage transients at the drain of the top MOSFET, a low ESR electrolytic capacitor and a
good quality ceramic capacitor must be connected between the high side MOSFET drain and ground (VSS).
• In order to avoid large negative transients on the switch node (HS) pin, the parasitic inductances between the
source of the high-side MOSFET and the drain of the low-side MOSFET (synchronous rectifier) must be
minimized.
• Overlapping of HS plane and ground (VSS) plane should be minimized as much as possible so that coupling
of switching noise into the ground plane is minimized.
• Thermal pad should be connected to large heavy copper plane to improve the thermal performance of the
device. Generally it is connected to the ground plane which is the same as VSS of the device. It is
recommended to connect this pad to the VSS pin only.
• Grounding considerations:
– The first priority in designing grounding connections is to confine the high peak currents that charge and
discharge the MOSFET gates to a minimal physical area. This confinement decreases the loop inductance
and minimize noise issues on the gate terminals of the MOSFETs. Place the gate driver as close to the
MOSFETs as possible.
– The second consideration is the high current path that includes the bootstrap capacitor, the bootstrap
diode, the local ground referenced bypass capacitor, and the low-side MOSFET body diode. The
bootstrap capacitor is recharged on a cycle-by-cycle basis through the bootstrap diode from the ground
referenced VDD bypass capacitor. The recharging occurs in a short time interval and involves high peak
current. Minimizing this loop length and area on the circuit board is important to ensure reliable operation.
10.2 Layout Example
VSS Plane
(Top and Bottom Layer)
To High Side MOSFET
Input Filters
(Top Layer)
Boot Diode & Capacitor
(Bottom Layer)
Input PWMs
To Low Side
MOSFET
VDD Capacitors
(Top Layer)
Figure 33. Layout Example
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11 Device and Documentation Support
11.1 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper
right corner, click on Alert me to register and receive a weekly digest of any product information that has
changed. For change details, review the revision history included in any revised document.
11.2 Community Resources
The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.
11.3 Trademarks
E2E is a trademark of Texas Instruments.
11.4 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
11.5 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
12 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
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PACKAGE OPTION ADDENDUM
www.ti.com
28-Sep-2021
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
(4/5)
(6)
LM5108DRCR
ACTIVE
VSON
DRC
10
3000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
LM5108
LM5108DRCT
ACTIVE
VSON
DRC
10
250
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
LM5108
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of
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