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LM5113
SNVS725I – JUNE 2011 – REVISED OCTOBER 2019
LM5113 80-V, 1.2-A, 5-A, Half Bridge GaN Driver
1 Features
3 Description
•
The LM5113 device is designed to drive both the
high-side and the low-side enhancement mode
Gallium Nitride (GaN) FETs in a synchronous buck or
a half bridge configuration. The floating high-side
driver is capable of driving a high-side enhancement
mode GaN FET operating up to 100 V. The high-side
bias voltage is generated using a bootstrap technique
and is internally clamped at 5.2 V, which prevents the
gate voltage from exceeding the maximum gatesource voltage rating of enhancement mode GaN
FETs. The inputs of the LM5113 are TTL logic
compatible, and can withstand input voltages up to 14
V regardless of the VDD voltage. The LM5113 has
split gate outputs, providing flexibility to adjust the
turnon and turnoff strength independently.
1
•
•
•
•
•
•
•
•
•
Independent high-side and low-side
TTL logic inputs
1.2 A / 5 A peak source/sink current
High-side floating bias voltage rail
Operates up to 100 VDC
Internal bootstrap supply voltage clamping
Split outputs for adjustable
turnon/turnoff strength
0.6-Ω / 2.1-Ω pulldown/pullup resistance
Fast propagation times (28 ns typical)
Excellent propagation delay matching
(1.5 ns typical)
Supply rail undervoltage lockout
Low power consumption
The LMG1205 is an enhancement over the LM5113.
The LMG1205 takes the design of the LM5113 and
includes start-up logic, level shifter, and power-off
Vgs clamp enhancements to provide a more robust
solution.
2 Applications
•
•
•
•
•
Merchant telecom rectifiers
Merchant DC/DC
Closed loop stepper motor drive
Baseband unit (BBU)
Macro remote radio unit (RRU)
In addition, the strong sink capability of the LM5113
maintains the gate in the low state, preventing
unintended turnon during switching. The LM5113 can
operate up to several MHz. The LM5113 is available
in a standard WSON-10 pin package and a 12-bump
DSBGA package. The WSON-10 pin package
contains an exposed pad to aid power dissipation.
The DSBGA package offers a compact footprint and
minimized package inductance.
Device Information(1)
PART NUMBER
LM5113
PACKAGE
BODY SIZE (NOM)
WSON (10)
4.00 mm × 4.00 mm
DSBGA (12)
2.00 mm × 2.00 mm
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
Simplified Application Diagram
0.1 F
VIN
HB
HOH
VDD
HOL
1 F
Input
Filter 1
HI
Input
Filter 2
LI
HS
LM5113
Load
LOH
LOL
EP
VSS
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
LM5113
SNVS725I – JUNE 2011 – REVISED OCTOBER 2019
www.ti.com
Table of Contents
1
2
3
4
5
6
7
Features ..................................................................
Applications ...........................................................
Description .............................................................
Revision History.....................................................
Pin Configuration and Functions .........................
Specifications.........................................................
1
1
1
2
4
5
6.1
6.2
6.3
6.4
6.5
6.6
6.7
5
5
5
5
6
7
8
Absolute Maximum Ratings ......................................
ESD Ratings..............................................................
Recommended Operating Conditions.......................
Thermal Information .................................................
Electrical Characteristics ..........................................
Switching Characteristics ..........................................
Typical Characteristics ..............................................
Detailed Description ............................................ 11
7.1 Overview ................................................................. 11
7.2 Functional Block Diagram ....................................... 11
7.3 Feature Description................................................. 11
7.4 Device Functional Modes........................................ 13
8
Application and Implementation ........................ 14
8.1 Application Information............................................ 14
8.2 Typical Application ................................................. 14
9 Power Supply Recommendations...................... 18
10 Layout................................................................... 19
10.1 Layout Guidelines ................................................. 19
10.2 Layout Examples................................................... 20
11 Device and Documentation Support ................. 21
11.1
11.2
11.3
11.4
11.5
Documentation Support ........................................
Support Resources ...............................................
Trademarks ...........................................................
Electrostatic Discharge Caution ............................
Glossary ................................................................
21
21
21
21
21
12 Mechanical, Packaging, and Orderable
Information ........................................................... 21
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision H (January 2018) to Revision I
Page
•
Removed "NRND" from data sheet title.................................................................................................................................. 1
•
Removed NRND disclosure statement .................................................................................................................................. 1
Changes from Revision G (January 2016) to Revision H
Page
•
Changed data sheet title from: LM5113 100 V 1.2-A / 5-A, Half-Bridge Gate Driver for Enhancement Mode GaN
FETs to: LM5113 80-V, 1.2-A, 5-A, Half Bridge GaN Driver .................................................................................................. 1
•
Added Not Recommended for New Designs statement to the data sheet............................................................................. 1
•
Added content to the Description section .............................................................................................................................. 1
•
Changed the first page key graphic ....................................................................................................................................... 1
•
Removed HB to VDD parameter from the Absolute Maximum Ratings table........................................................................ 5
•
Changed the HS to VSS maximum from: 100 V to: 93 V....................................................................................................... 5
•
Changed the HB to VSS maximum from: 107 V to: V(HS) + 7 V........................................................................................... 5
•
Changed the human-body model value from: ±2000 to: ±1000 ............................................................................................. 5
•
Changed HS maximum from: 100 V to: 90 V ........................................................................................................................ 5
•
Changed the Functional Block Diagram ............................................................................................................................... 11
•
Changed the last paragraph and add new images to the Input and Output section ........................................................... 11
•
Added content to the Start-up and UVLO section ............................................................................................................... 12
Changes from Revision F (April 2013) to Revision G
•
2
Page
Added ESD Ratings table, Feature Description section, Device Functional Modes, Application and Implementation
section, Power Supply Recommendations section, Layout section, Device and Documentation Support section, and
Mechanical, Packaging, and Orderable Information section .................................................................................................. 1
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Changes from Revision E (April 2013) to Revision F
•
Page
Changed layout of National Data Sheet to TI format ............................................................................................................. 1
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LM5113
SNVS725I – JUNE 2011 – REVISED OCTOBER 2019
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5 Pin Configuration and Functions
DPR Package
10-Pin WSON With Exposed Thermal Pad
Top View
VDD
1
10 LOH
HB
2
9
LOL
HOH
3
8
VSS
HOL
4
7
LI
HS
5
6
HI
Thermal Pad
YFX Package
12-Pin DSBGA
Top View
A
LOL
B
LOH
HI
C
HS
VDD
D
HOL
HOH
HB
HS
1
2
3
4
VSS
VDD
LI
Pin Functions
PIN
NAME
TYPE
(1)
DESCRIPTION
WSON
DSBGA
VDD
1
A3, C4 (2)
P
5-V Positive gate drive supply: locally decouple to VSS using low ESR/ESL capacitor
located as close to the IC as possible.
HB
2
D3
P
High-side gate driver bootstrap rail: connect the positive terminal of the bootstrap capacitor
to HB and the negative terminal to HS. The bootstrap capacitor should be placed as close
to the IC as possible.
HOH
3
D2
O
High-side gate driver turnon output: connect to the gate of high-side GaN FET with a short,
low inductance path. A gate resistor can be used to adjust the turnon speed.
HOL
4
D1
O
High-side gate driver turnoff output: connect to the gate of high-side GaN FET with a short,
low inductance path. A gate resistor can be used to adjust the turnoff speed.
HS
5
C1, D4 (2)
P
High-side GaN FET source connection: connect to the bootstrap capacitor negative
terminal and the source of the high-side GaN FET.
HI
6
B4
I
High-side driver control input. The LM5113 inputs have TTL type thresholds. Unused
inputs should be tied to ground and not left open.
LI
7
A4
I
Low-side driver control input. The LM5113 inputs have TTL type thresholds. Unused inputs
should be tied to ground and not left open.
VSS
8
A2
G
Ground return: all signals are referenced to this ground.
LOL
9
A1
O
Low-side gate driver sink-current output: connect to the gate of the low-side GaN FET with
a short, low inductance path. A gate resistor can be used to adjust the turnoff speed.
LOH
10
B1
O
Low-side gate driver source-current output: connect to the gate of high-side GaN FET with
a short, low inductance path. A gate resistor can be used to adjust the turnon speed.
Exposed
Pad
EP
—
—
Exposed pad: TI recommends that the exposed pad on the bottom of the package be
soldered to ground plane on the printed-circuit board to aid thermal dissipation.
(1)
(2)
4
I = Input, O = Output, G = Ground, P = Power
A3 and C4, C1 and D4 are internally connected
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6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted) (1)
MIN
MAX
UNIT
VDD to VSS
–0.3
7
V
HB to HS
–0.3
7
V
LI or HI input
–0.3
15
V
LOH, LOL output
–0.3
VDD + 0.3
V
HOH, HOL output
VHS – 0.3
VHB +0.3
V
HS to VSS
–5
93
V
HB to VSS
0
VHS + 7
V
150
°C
150
°C
Operating junction temperature
Storage temperature, Tstg
(1)
–55
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
6.2 ESD Ratings
VALUE
V(ESD)
(1)
(2)
Electrostatic discharge
Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001 (1)
±2000
Charged-device model (CDM), per JEDEC specification JESD22-C101 (2)
±1000
UNIT
V
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
6.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
MIN
VDD
NOM
MAX
UNIT
4.5
5.5
V
0
14
V
HS
–5
90
V
HB
VHS + 4
VHS + 5.5
V
50
V/ns
–40
125
°C
LI or HI input
HS slew rate
Operating junction temperature
6.4 Thermal Information
LM5113
THERMAL METRIC (1)
DPR (WSON)
YFX (DSBGA)
UNIT
10 PINS
12 PINS
RθJA
Junction-to-ambient thermal resistance
37.5
76.8
°C/W
RθJC(top)
Junction-to-case (top) thermal resistance
35.8
0.6
°C/W
RθJB
Junction-to-board thermal resistance
14.7
12.0
°C/W
ψJT
Junction-to-top characterization parameter
0.3
1.6
°C/W
ψJB
Junction-to-board characterization parameter
14.9
12.0
°C/W
RθJC(bot)
Junction-to-case (bottom) thermal resistance
4.1
–
°C/W
(1)
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
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6.5 Electrical Characteristics
Specifications are TJ = 25°C. Unless otherwise specified: VDD = VHB = 5 V, VSS = VHS = 0 V.
No load on LOL and HOL or HOH and HOL (1).
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
SUPPLY CURRENTS
IDD
VDD quiescent current
LI = HI = 0 V
IDDO
VDD operating current
f = 500 kHz
IHB
Total HB quiescent current
LI = HI = 0 V
IHBO
Total HB operating current
f = 500 kHz
IHBS
HB to VSS quiescent current
HS = HB = 100 V
IHBSO
HB to VSS operating current
f = 500 kHz
TJ = 25°C
0.07
TJ = –40°C to 125°C
0.1
TJ = 25°C
2.0
TJ = –40°C to 125°C
3.0
TJ = 25°C
0.08
TJ = –40°C to 125°C
0.1
TJ = 25°C
1.5
TJ = –40°C to 125°C
2.5
TJ = 25°C
0.1
TJ = –40°C to 125°C
8
TJ = 25°C
0.4
TJ = –40°C to 125°C
1.0
mA
mA
mA
mA
µA
mA
INPUT PINS
VIR
Input voltage threshold
Rising edge
VIF
Input voltage threshold
Falling edge
VIHYS
Input voltage hysteresis
RI
Input pulldown resistance
TJ = 25°C
2.06
TJ = –40°C to 125°C
1.89
TJ = 25°C
2.18
1.66
TJ = –40°C to 125°C
1.48
1.76
400
TJ = 25°C
100
V
mV
200
TJ = –40°C to 125°C
V
300
kΩ
UNDERVOLTAGE PROTECTION
VDDR
VDD rising threshold
VDDH
VDD threshold hysteresis
VHBR
HB rising threshold
VHBH
HB threshold hysteresis
TJ = 25°C
3.8
TJ = –40°C to 125°C
3.2
4.5
0.2
TJ = 25°C
V
3.2
TJ = –40°C to 125°C
2.5
V
3.9
0.2
V
V
BOOTSTRAP DIODE
VDL
Low-current forward voltage
IVDD-HB = 100 µA
VDH
High-current forward voltage
IVDD-HB = 100 mA
RD
Dynamic resistance
IVDD-HB = 100 mA
HB-HS clamp
Regulation voltage
(1)
6
TJ = 25°C
0.45
TJ = –40°C to 125°C
0.65
TJ = 25°C
0.90
TJ = –40°C to 125°C
1.00
TJ = 25°C
1.85
TJ = –40°C to 125°C
3.60
TJ = 25°C
5.2
TJ = –40°C to 125°C
4.7
5.45
V
V
Ω
V
Minimum and maximum limits are 100% production tested at 25°C. Limits over the operating temperature range are ensured through
correlation using Statistical Quality Control (SQC) methods. Limits are used to calculate Average Outgoing Quality Level (AOQL).
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Electrical Characteristics (continued)
Specifications are TJ = 25°C. Unless otherwise specified: VDD = VHB = 5 V, VSS = VHS = 0 V.
No load on LOL and HOL or HOH and HOL(1).
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
LOW- AND HIGH-SIDE GATE DRIVER
TJ = 25°C
0.06
VOL
Low-level output voltage
IHOL = ILOL = 100 mA
VOH
High-level output voltage
VOH = VDD – LOH
or VOH = HB – HOH
IHOH = ILOH = 100 mA
IOHL
Peak source current
HOH, LOH = 0 V
IOLL
Peak sink current
HOL, LOL = 5 V
IOHLK
High-level output leakage current
HOH, LOH = 0 V
TJ = –40°C to 125°C
1.5
µA
IOLLK
Low-level output leakage current
HOL, LOL = 5 V
TJ = –40°C to 125°C
1.5
µA
MAX
UNIT
TJ = –40°C to 125°C
0.10
TJ = 25°C
V
0.21
TJ = –40°C to 125°C
0.31
V
1.2
A
5
A
6.6 Switching Characteristics
over operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
TJ = 25°C
MIN
TYP
26.5
tLPHL
LO turnoff propagation delay
LI falling to LOL falling
tLPLH
LO turnon propagation delay
LI rising to LOH rising
tHPHL
HO turnoff propagation delay
HI falling to HOL falling
tHPLH
HO turnon propagation delay
HI rising to HOH rising
tMON
Delay matching
LO on & HO off
TJ = 25°C
tMOFF
Delay matching
LO off & HO on
TJ = 25°C
tHRC
HO rise time (0.5 V – 4.5 V)
CL = 1000 pF
7.0
ns
tLRC
LO rise time (0.5 V – 4.5 V)
CL = 1000 pF
7.0
ns
tHFC
HO fall time (0.5 V – 4.5 V)
CL = 1000 pF
1.5
ns
tLFC
LO fall time (0.5 V – 4.5 V)
CL = 1000 pF
1.5
ns
tPW
Minimum input pulse width
that changes the output
10
ns
tBS
Bootstrap diode
reverse recovery time
40
ns
TJ = –40°C to 125°C
TJ = 25°C
45.0
28.0
TJ = –40°C to 125°C
TJ = 25°C
45.0
26.5
TJ = –40°C to 125°C
TJ = 25°C
45.0
28.0
TJ = –40°C to 125°C
45.0
1.5
TJ = –40°C to 125°C
8.0
1.5
TJ = –40°C to 125°C
IF = 100 mA, IR = 100 mA
8.0
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ns
ns
ns
ns
ns
ns
7
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SNVS725I – JUNE 2011 – REVISED OCTOBER 2019
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LI
LI
HI
HI
tHPLH
tLPLH
tHPHL
tLPHL
LO
LO
HO
HO
tMON
tMOFF
Figure 1. Timing Diagram
6.7 Typical Characteristics
8
Figure 2. Peak Source Current vs Output Voltage
Figure 3. Peak Sink Current vs Output Voltage
Figure 4. IDDO vs Frequency
Figure 5. IHBO vs Frequency
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Typical Characteristics (continued)
Figure 6. IDD vs Temperature
Figure 7. IHB vs Temperature
Figure 8. UVLO Rising Thresholds vs Temperature
Figure 9. UVLO Falling Thresholds vs Temperature
Figure 10. Input Thresholds vs Temperature
Figure 11. Input Threshold Hysteresis vs Temperature
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Typical Characteristics (continued)
Figure 12. Bootstrap Diode Forward Voltage
10
Figure 13. Propagation Delay vs Temperature
Note: Unless otherwise specified,
VDD = VHB = 5 V, VSS = VHS = 0 V.
Note: Unless otherwise specified,
VDD = VHB = 5 V, VSS = VHS = 0 V.
Figure 14. LO & HO Gate Drive – High/Low Level
Output Voltage vs Temperature
Figure 15. HB Regulation Voltage vs Temperature
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7 Detailed Description
7.1 Overview
The LM5113 is a high frequency high- and low- side gate driver for enhancement mode Gallium Nitride (GaN)
FETs in a synchronous buck or a half bridge configuration. The floating high-side driver is capable of driving a
high-side enhancement mode GaN FET operating up to 100 V. The high-side bias voltage is generated using a
bootstrap technique and is internally clamped at 5.2 V, which prevents the gate voltage from exceeding the
maximum gate-source voltage rating of enhancement mode GaN FETs. The LM5113 has split gate outputs with
strong sink capability, providing flexibility to adjust the turnon and turnoff strength independently.
The LM5113 can operate up to several MHz, and available in a standard WSON-10 pin package and a 12-bump
DSBGA package. The WSON-10 pin package contains an exposed pad to aid power dissipation. The DSBGA
package offers a compact footprint and minimized package inductance.
7.2 Functional Block Diagram
HB
UVLO
& CLAMP
HOH
HOL
LEVEL
SHIFT
EXT HI
HS
HI
VDD
UVLO
EXT LI
LOH
LOL
LI
VSS
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7.3 Feature Description
7.3.1 Input and Output
The inputs are independently controlled with TTL input thresholds, and can withstand voltages up to 14 V
regardless of the VDD voltage, which means it could be directly connected to the outputs of PWM controllers
with up to 14-V power supply, saving a buffer stage between output of higher-voltage powered controller, for
example LM5025 with 10 V, and input of the LM5113.
The output pulldown and pullup resistance of LM5113 is optimized for enhancement mode GaN FETs to achieve
high frequency and efficient operation. The 0.6-Ω pulldown resistance provides a robust low impedance turnoff
path necessary to eliminate undesired turnon induced by high dv/dt or high di/dt. The 2.1-Ω pullup resistance
helps reduce the ringing and over-shoot of the switch node voltage. The split outputs of the LM5113 offer
flexibility to adjust the turnon and turnoff speed by independently adding additional impedance in either the
turnon path, the turnoff path, or both.
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Feature Description (continued)
It is very important that the input signal of the two channels HI and LI, which has logic compatible threshold and
hysteresis, must be tied to either VDD or VSS if they are not used. This inputs must not be left floating.
Additionally, the input signals avoid pulses shorter than 3 ns by using the input filter to the HI and LI input pins.
The values and part numbers of the circuit components are shown in the Figure 16.
EXT HI
1k
HI
22 pF
Figure 16. Input Filter 1 (High-Side Input Filter)
If short pulses or short delays are required, the circuit in Figure 17 is recommended.
SN74LVC2G32YZP
HI
EXT HI
100 k
50 pF
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Figure 17. Input Filter 1 for Short Pulses (High-Side Input Filter)
7.3.2 Start-Up and UVLO
The start-up voltage sequencing for this device is as follows: VDD voltage first, with the VIN voltage present
thereafter.
The LM5113 requires an external bootstrap diode with a 20-Ω series resistor to charge the high-side supply on a
cycle-by-cycle basis. The recommended bootstrap diode options are BAT46, BAT41, or LL4148.
The LM5113 has an Undervoltage Lockout (UVLO) on both the VDD and bootstrap supplies. When the VDD
voltage is below the threshold voltage of 3.8 V, both the HI and LI inputs are ignored, to prevent the GaN FETs
from being partially turned on. Also if there is insufficient VDD voltage, the UVLO will actively pull the LOL and
HOL low. When the HB to HS bootstrap voltage is below the UVLO threshold of 3.2 V, only HOL is pulled low.
Both UVLO threshold voltages have 200 mV of hysteresis to avoid chattering.
Table 1. VDD UVLO Feature Logic Operation
12
CONDITION (VHB-HS > VHBR for all cases below)
HI
LI
HO
LO
VDD - VSS < VDDR during device start-up
H
L
L
L
VDD - VSS < VDDR during device start-up
L
H
L
L
VDD - VSS < VDDR during device start-up
H
H
L
L
VDD - VSS < VDDR during device start-up
L
L
L
L
VDD - VSS < VDDR - VDDH after device start-up
H
L
L
L
VDD - VSS < VDDR - VDDH after device start-up
L
H
L
L
VDD - VSS < VDDR - VDDH after device start-up
H
H
L
L
VDD - VSS < VDDR - VDDH after device start-up
L
L
L
L
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Table 2. VHB-HS UVLO Feature Logic Operation
CONDITION (VDD > VDDR for all cases below)
HI
LI
HO
LO
VHB-HS < VHBR during device start-up
H
L
L
L
VHB-HS < VHBR during device start-up
L
H
L
H
VHB-HS < VHBR during device start-up
H
H
L
H
VHB-HS < VHBR during device start-up
L
L
L
L
VHB-HS < VHBR - VHBH after device start-up
H
L
L
L
VHB-HS < VHBR - VHBH after device start-up
L
H
L
H
VHB-HS < VHBR - VHBH after device start-up
H
H
L
H
VHB-HS < VHBR - VHBH after device start-up
L
L
L
L
7.3.3 HS Negative Voltage and Bootstrap Supply Voltage Clamping
Due to the intrinsic feature of enhancement mode GaN FETs, the source-to-drain voltage of the bottom switch, is
usually higher than a diode forward voltage drop when the gate is pulled low. This will cause negative voltage on
HS pin. Moreover, this negative voltage transient will be even worse, considering layout and device drain/source
parasitic inductances. With high side driver using the floating bootstrap configuration, Negative HS voltage can
lead to an excessive bootstrap voltage which can damage the high-side GaN FET. The LM5113 solves this
problem with an internal clamping circuit that prevents the bootstrap voltage from exceeding 5.2 V typical.
7.3.4 Level Shift
The level shift circuit is the interface from the high-side input to the high-side driver stage which is referenced to
the switch node (HS). The level shift allows control of the HO output which is referenced to the HS pin and
provides excellent delay matching with the low-side driver. Typical delay matching between LO and HO is around
1.5 ns.
7.4 Device Functional Modes
Table 3 shows the device truth table.
Table 3. Truth Table
HI
LI
HOH
HOL
LOH
LOL
L
L
Open
L
Open
L
Open
L
H
Open
L
H
H
L
H
Open
Open
L
H
H
H
Open
H
Open
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8 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
8.1 Application Information
To operate GaN transistors at very high switching frequencies and to reduce associated switching losses, a
powerful gate driver is employed between the PWM output of controller and the gates of the GaN transistor.
Also, gate drivers are indispensable when it is impossible for the PWM controller to directly drive the gates of the
switching devices. With the advent of digital power, this situation is often encountered because the PWM signal
from the digital controller is often a 3.3-V logic signal which cannot effectively turn on a power switch. Level shift
circuit is required to boost the 3.3-V signal to the gate-drive voltage (such as 12 V) in order to fully turn on the
power device and minimize conduction losses. Traditional buffer drive circuits based on NPN/PNP bipolar
transistors in totem-pole arrangement prove inadequate with digital power because they lack level-shifting
capability. Gate drivers effectively combine both the level-shifting and buffer-drive functions. Gate drivers also
find other needs such as minimizing the effect of high-frequency switching noise (by placing the high-current
driver IC physically close to the power switch), driving gate-drive transformers and controlling floating powerdevice gates, reducing power dissipation and thermal stress in controllers by moving gate charge power losses
from the controller into the driver.
The LM5113 is a MHz high- and low-side gate driver for enhancement mode Gallium Nitride (GaN) FETs in a
synchronous buck or a half bridge configuration. The floating high-side driver is capable of driving a high-side
enhancement mode GaN FET operating up to 100 V. The high-side bias voltage is generated using a bootstrap
technique and is internally clamped at 5.2 V, which prevents the gate voltage from exceeding the maximum gatesource voltage rating of enhancement mode GaN FETs. The LM5113 has split gate outputs with strong sink
capability, providing flexibility to adjust the turnon and turnoff strength independently.
8.2 Typical Application
The circuit in Figure 18 shows a synchronous buck converter to evaluate LM5113. Detailed synchronous buck
converter specifications are listed in Design Requirements. The active clamping voltage mode controller LM5025
is used for close-loop control and generates the PWM signals of the buck switch and the synchronous switch.
For more information, refer to the Related Documentation section.
14
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J3
VIN
C30
0.01 F
GND
GND
C16
220 pF
R2
100k
±1%
C3
2.2 F
2.2 F
C17
NU
2.2 F
R17
7.50k
GND
C31
0.1 F
R7
33.2k
R3
150k
2.2 F
2.2 F
C32
1 F
C18
0.1 F
R4
±1%
49.9
4
3
3
LM5025
15
¬ SYNC COMP
14
¬ RT
TIME
6 REF
AGND
7
VCC PGND
5
13
11
10
GND
ON/OFF
GND
GND
GND
4
R15
4.02k
BYP
U1 LP2982AIM5-5.0
5
1
OUT
IN
8
2
¬ RAMP OUTA ¬
12
¬ SS
OUTB ¬9
CS1
CS2
C19
1 F
VIN
1
D1
TP1
EX VCC
MBR130T1G
16
¬ UVLO
U4
GND
TP4
2.2 F
C7
GND
C6
2
0R
NU
R14
D4
0R
R11
NU
D3
C20
100 pF
GND
C8
0.1 uF
C27
NU
C28
NU
C24
1 F
6.3V
GND
C21
2.2 F
5V
C9
0.01 uF
HB
LI
10
4
3
5
LM5113
LOL 9
LOH
HOL
GND
8 VSS
7
6 HI
HS
HOH
0.1 F
1 VDD
2
U3
C25
11
9
7
5
3
1
0
R18
R9
2R
R10
0R
Q1
EPC2001
10
8
6
4
2
21.0k
R19
L1
GND
C26
1 F
MBR130T1G
D2
SER1360-272KL
2.7 H
MBR130T1G
1N4148W-7-F
D6
D5
Q2
EPC2001
1
3
5
7
9
11
2
4
6
8
10
C5
TP3
C13
NU
1
1500 pF
C23
C14
1 uF
GND
3
4
R8
C12
22 F
GND
R16
21.0k
U2
LM8261M5
16.9k
330 pF
C22
GND
+ C1
330 F
5
2
C4
¬
C2
¬
Product Folder Links: LM5113
EP
¬
Copyright © 2011–2019, Texas Instruments Incorporated
¬
VIN
+
-
J1
C29
1 F
C15
1.5 nF
R5
374
R13
6.98k
R6
21.0k
GND
TP2
R1
10.0
GND
C11
1 F
TP5
C10
22 F
VOUT
J4
VOUT
10V
J2
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LM5113
Typical Application (continued)
Input 15 V to 60 V, output 10 V, 800 kHz
Figure 18. Application Circuit
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Typical Application (continued)
8.2.1 Design Requirements
Table 4 lists the design requirements for the typical application.
Table 4. Design Parameters
PARAMETER
SPECIFICATION
Input operating range
15 – 60 V
Output voltage
10 V
Output current, 48-V input
10 A
Output current, 60-V input
7A
Efficiency at 48 V, 10 A
>90%
Frequency
800 kHz
8.2.2 Detailed Design Procedure
This procedure outlines the design considerations of LM5113 in a synchronous buck converter with enhancement
mode Gallium Nitride (GaN) FET. Refer to Figure 18 for component names and network locations. For additional
design help, see Related Documentation.
8.2.2.1 VDD Bypass Capacitor
The VDD bypass capacitor provides the gate charge for the low-side and high-side transistors and to absorb the
reverse recovery charge of the bootstrap diode. The required bypass capacitance can be calculated with
Equation 1.
(1)
QgH and QgL are gate charge of the high-side and low-side transistors respectively. Qrr is the reverse recovery
charge of the bootstrap diode, which is typically around 4 nC. ΔV is the maximum allowable voltage drop across
the bypass capacitor. A 0.1-µF or larger value, good-quality, ceramic capacitor is recommended. The bypass
capacitor should be placed as close to the pins of the IC as possible to minimize the parasitic inductance.
8.2.2.2 Bootstrap Capacitor
The bootstrap capacitor provides the gate charge for the high-side switch, DC bias power for HB undervoltage
lockout circuit, and the reverse recovery charge of the bootstrap diode. The required bypass capacitance can be
calculated with Equation 2.
(2)
IHB is the quiescent current of the high-side driver. ton is the maximum on-time period of the high-side transistor.
A good-quality, ceramic capacitor should be used for the bootstrap capacitor. TI recommends placing the
bootstrap capacitor as close to the HB and HS pins as possible.
8.2.2.3 Power Dissipation
The power consumption of the driver is an important measure that determines the maximum achievable
operating frequency of the driver. It should be kept below the maximum power dissipation limit of the package at
the operating temperature. The total power dissipation of the LM5113 is the sum of the gate driver losses and the
bootstrap diode power loss.
The gate driver losses are incurred by charge and discharge of the capacitive load. It can be approximated as:
(3)
CLoadH and CLoadL are the high-side and the low-side capacitive loads, respectively. It can also be calculated with
the total input gate charge of the high-side and the low-side transistors as:
(4)
16
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There are some additional losses in the gate drivers due to the internal CMOS stages used to buffer the LO and
HO outputs. The following plot shows the measured gate driver power dissipation versus frequency and load
capacitance. At higher frequencies and load capacitance values, the power dissipation is dominated by the
power losses driving the output loads and agrees well with the above equations. This plot can be used to
approximate the power losses due to the gate drivers.
Gate Driver Power Dissipation (LO+HO), VDD = +5 V
Figure 19. Neglecting Bootstrap Diode Losses
The bootstrap diode power loss is the sum of the forward bias power loss that occurs while charging the
bootstrap capacitor and the reverse bias power loss that occurs during reverse recovery. Because each of these
events happens once per cycle, the diode power loss is proportional to the operating frequency. Larger
capacitive loads require more energy to recharge the bootstrap capacitor resulting in more losses. Higher input
voltages (VIN) to the half bridge also result in higher reverse recovery losses.
The following two plots illustrate the forward bias power loss and the reverse bias power loss of the bootstrap
diode respectively. The plots are generated based on calculations and lab measurements of the diode reverse
time and current under several operating conditions. The plots can be used to predict the bootstrap diode power
loss under different operating conditions.
The Load of High-Side Driver is a GaN FET with Total Gate Charge
of 10 nC.
Figure 20. Forward Bias Power Loss of
Bootstrap Diode VIN = 50 V
The Load of High-Side Driver is a GaN FET with Total Gate Charge
of 10 nC.
Figure 21. Reverse Recovery Power Loss of
Bootstrap Diode VIN = 50 V
The sum of the driver loss and the bootstrap diode loss is the total power loss of the IC. For a given ambient
temperature, the maximum allowable power loss of the IC can be defined as Equation 5.
(TJ - TA)
P=
TJA
(5)
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8.2.3 Application Curves
Conditions:
Input Voltage = 48 V DC, Load Current = 5 A
Traces:
Top Trace: Gate of Low-Side eGaN FET, Volt/div = 2 V
Bottom Trace: LI of LM5113, Volt/div = 5 V
Bandwidth Limit = 600 MHz
Horizontal Resolution = 0.2 µs/div
Figure 22. Low-Side Driver Input and Output
Conditions:
Input Voltage = 48 V DC,
Load Current = 10 A
Traces:
Trace: Switch-Node Voltage, Volts/div = 20 V
Bandwidth Limit = 600 MHz
Horizontal Resolution = 50 ns/div
Figure 23. Switch-Node Voltage
9 Power Supply Recommendations
The recommended bias supply voltage range for LM5113 is from 4.5 V to 5.5 V. The lower end of this range is
governed by the internal undervoltage lockout (UVLO) protection feature of the VDD supply circuit. The upper
end of this range is driven by the 7-V absolute maximum voltage rating of the VDD or the GaN transistor gate
breakdown voltage limit, whichever is lower. TI recommends keeping a proper margin to allow for transient
voltage spikes.
The UVLO protection feature also involves a hysteresis function. This means that once the device is operating in
normal mode, if the VDD voltage drops, the device continues to operate in normal mode as far as the voltage
drop do not exceeds the hysteresis specification, VDDH. If the voltage drop is more than hysteresis specification,
the device shuts down. Therefore, while operating at or near the 4.5-V range, the voltage ripple on the auxiliary
power supply output should be smaller than the hysteresis specification of LM5113 to avoid triggering device
shutdown.
A local bypass capacitor should be placed between the VDD and VSS pins. And this capacitor should be located
as close to the device as possible. A low-ESR, ceramic surface mount capacitor is recommended. TI
recommends using 2 capacitors across VDD and GND: a 100-nF ceramic surface-mount capacitor for high
frequency filtering placed very close to VDD and GND pin, and another surface-mount capacitor, 220-nF to 10μF, for IC bias requirements.
18
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10 Layout
10.1 Layout Guidelines
Small gate capacitance and miller capacitance enable enhancement mode GaN FETs to operate with fast
switching speed. The induced high dv/dt and di/dt, coupled with a low gate threshold voltage and limited
headroom of enhancement mode GaN FETs gate voltage, make the circuit layout crucial to the optimum
performance. Following are some hints.
1. The first priority in designing the layout of the driver is to confine the high peak currents that charge and
discharge the GaN FETs gate into a minimal physical area. This will decrease the loop inductance and
minimize noise issues on the gate terminal of the GaN FETs. The GaN FETs should be placed close to the
driver.
2. The second high current path includes the bootstrap capacitor, the local ground referenced VDD bypass
capacitor and low-side GaN FET. The bootstrap capacitor is recharged on a cycle-by-cycle basis through the
bootstrap diode from the ground referenced VDD capacitor. The recharging occurs in a short time interval
and involves high peak current. Minimizing this loop length and area on the circuit board is important to
ensure reliable operation.
3. The parasitic inductance in series with the source of the high-side FET and the low-side FET can impose
excessive negative voltage transients on the driver. TI recommends connecting the HS pin and VSS pin to
the respective source of the high-side and low-side transistors with a short and low-inductance path.
4. The parasitic source inductance, along with the gate capacitor and the driver pulldown path, can form a LCR
resonant tank, resulting in gate voltage oscillations. An optional resistor or ferrite bead can be used to damp
the ringing.
5. Low ESR/ESL capacitors must be connected close to the IC, between VDD and VSS pins and between the
HB and HS pins to support the high peak current being drawn from VDD during turnon of the FETs. Keeping
bullet #1 (minimized GaN FETs gate driver loop) as the first priority, it is also desirable to place the VDD
decoupling capacitor and the HB to HS bootstrap capacitor on the same side of the printed-circuit board as
the driver. The inductance of vias can impose excessive ringing on the IC pins.
6. To prevent excessive ringing on the input power bus, good decoupling practices are required by placing lowESR ceramic capacitors adjacent to the GaN FETs.
The following figures show recommended layout patterns for WSON-10 package and DSBGA package,
respectively. Two cases are considered: (1) Without any gate resistors; (2) With an optional turnon gate resistor.
It should be noted that 0402 DSBGA package is assumed for the passive components in the drawings. For
information on DSBGA package assembly, refer to Related Documentation.
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Bootstrap
Capacitor
HO
To Hi-Side FET
HS
To Hi-Side FET
2
3
4
5
VDD 1
HB
HS
2
3
4
5
VDD 1
HB
HS
HO
HS
HOL
Bootstrap
Capacitor
HOH
10.2 Layout Examples
Bypass
Capacitor
Bypass
Capacitor
9
10
LOL
LOH
LI
To Low-Side FET
8 VSS
7
HI
LOH
6
10
LOL
LI
9
7
HI
8 VSS
6
LO
GND
LO
To Low-Side FET
GND
Figure 24. WSON-10 Without Gate Resistors
Bootstrap
Capacitor
HO
HS
Figure 25. WSON-10 With HOH
and LOH Gate Resistors
Bootstrap
Capacitor
HS
HOL
D
HS
C
VDD
HS
C
VDD
HS
B
HI
LOH
B
HI
LOH
LOL
A
LI
VDD
VSS
4
3
2
HB
HOH
LI
VDD
VSS
4
3
2
1
LO
Bypass
Capacitor
To Hi-Side FET
HS
D
A
To Low-Side FET
GND
Bypass
Capacitor
HB
HOH
HOL
LOL
1
LO
GND
Figure 26. DSBGA Without Gate Resistors
20
HO
To Hi-Side FET
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To Low-Side FET
Figure 27. DSBGA With HOH
and LOH Gate Resistors
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11 Device and Documentation Support
11.1 Documentation Support
11.1.1 Related Documentation
For related documentation see the following:
• Texas Instruments, AN-1112 DSBGA Wafer Level Chip Scale Package Application Report
• Texas Instruments, AN-2149 LM5113 Evaluation Board Application Report
11.2 Support Resources
TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straight
from the experts. Search existing answers or ask your own question to get the quick design help you need.
Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do
not necessarily reflect TI's views; see TI's Terms of Use.
11.3 Trademarks
E2E is a trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
11.4 Electrostatic Discharge Caution
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
11.5 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
12 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this datasheet, refer to the left-hand navigation.
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PACKAGE OPTION ADDENDUM
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10-Dec-2020
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
(4/5)
(6)
LM5113SD/NOPB
NRND
WSON
DPR
10
1000
RoHS & Green
SN
Level-1-260C-UNLIM
-40 to 125
L5113
LM5113SDE/NOPB
NRND
WSON
DPR
10
250
RoHS & Green
SN
Level-1-260C-UNLIM
-40 to 125
L5113
LM5113SDX/NOPB
NRND
WSON
DPR
10
4500
RoHS & Green
SN
Level-1-260C-UNLIM
-40 to 125
L5113
LM5113TME/NOPB
NRND
DSBGA
YFX
12
250
RoHS & Green
SNAGCU
Level-1-260C-UNLIM
5113
LM5113TMX/NOPB
NRND
DSBGA
YFX
12
3000
RoHS & Green
SNAGCU
Level-1-260C-UNLIM
5113
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of
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