User's Guide
SNVA192B – December 2006 – Revised April 2013
AN-1542 LM5115A Evaluation Board
1
Introduction
The LM5115A/LM5025A evaluation board provides a typical application circuit of a secondary side post
regulated (SSPR) output from an existing Active Clamp Forward converter. This SSPR output voltage
tracks the output voltage of the active clamp forward converter during Power-Up/Power-Down. Information
on the LM5025A active clamp evaluation board can be found in AN-1345 LM5025A Evaluation Board
User's Guide (SNVA097). Note that other types of isolated power converters (for example, push-pull, halfbridge, and full-bridge) can be used in the place of the LM5025A active clamp forward converter to drive
the LM5115A AC evaluation board.
The evaluation board specifications are:
• Input voltage: 36V to 72V, 48V nominal on LM5025A
• Output voltage Main: 3.3V nominal
• Output current Main: 0 to 30A
• Current limit Main: ≊30A
• Output voltage Secondary: 2.5V
• Output current Secondary: 0 to 9A
• Current limit Secondary: ≊10A
• Measured efficiency on secondary only: 98% at 36V, Iload = 1A, 93% at 48V, Iload = 4A
• Load regulation: 2mV change from 1A-7A, 36V < Vin < 72V
• Size: 2.175 × 1.125 × 0.0375 in.
The printed circuit board consists of 4 layers of 2 oz copper on FR4 material, with a thickness of 0.050 in.
It is designed for continuous operation at rated load with a minimum airflow of 200 LFPM.
2
Theory of Operation
The LM5115A controller contains all of the features necessary to produce multiple tracking outputs using
the Secondary Side Post Regulation (SSPR) technique. The SSPR technique develops a highly efficient
and well regulated auxiliary output from the secondary side switching waveform of an isolated power
converter.
Synchronization of the LM5115A comes from the main pulsed signal of the transformer secondary
winding. Resistors R2 and R4 sense the pulsing signal to form an internal synchronization current signal.
The LM5115A controls the buck power stage with leading edge pulse width modulation (PWM). Leading
edge modulation delays the rising edge of the main pulsed signal by holding off the LM5115A high-side
gate driver therefore, establishing the required voltage*seconds to regulate the SSPR output.
Representative waveforms are shown in Figure 8.
Bias to the part comes from a rectified pulse signal. Note that the pulse signals vary from 6Vpp to 12Vpp,
with Vin varying from 36V to 72V, respectively. Therefore, the Vcc regulator will not regulate at 7V until the
peak to peak voltage is slightly higher than 7.5V (accounting for the diode drop to the bias). This set up
shows that even with unregulated Vcc the LM5115A is still capable of providing the secondary voltage of
2.5V from the main 3.3V. Adaptive deadtime control delays the top and bottom drivers to avoid shoot
through currents (Figure 9 and Figure 10).
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SNVA192B – December 2006 – Revised April 2013
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AN-1542 LM5115A Evaluation Board
1
Board Layout and Probing
3
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Board Layout and Probing
Figure 1, Figure 2, and Figure 3 show the board layout, main components, and critical probe points for
testing the LM5115A AC evaluation board in conjunction with the LM5025A board. The following notes
should be considered prior to applying power to the board:
1. Main input power (36V to 72V) is applied to points J1 and J4 of the LM5025A board, connected to VIN
and GND respectively.
2. The main current carrying components (LM5115A board: L1, Q1, and Q2; LM5025A board L2, Q3-Q6)
will be hot to the touch at maximum load current. USE CAUTION. When operating at load currents in
excess of 5A the use of a fan to provide forced air flow is necessary.
3. The diameter and length of the wire used to connect the load is important. To ensure that there is not a
significant voltage drop in the wires, a minimum of 14 gauge wire is recommended.
NATIONAL
SEMICONDUCTOR
LM5115A AC
EVALUATION
BOARD
L1
P/N 551012942-001
R10
G
S
D
+
J1 (+)
+
R16
Q1
R7 R8 R9
Connect to LM5025 Main
Transformer Secondary
Winding
J1 to J7 and J2 to J10
Q2
G
R15
S
D
J3 (+)
-
D1
+OUTPUT-
R5
R2
C5
C3
C1
D2
TP3
TP1
TP1 Must Be Connected to the
J9 Terminal (LM5025A) for the
Proper Power-Up/Power-Down
Tracking Sequence
U1
C7 R3
D3
C6
D6
R1
C13 C12 C11
R19
R4
TP2
-
+OUT
+OUT
J2 (-)
GND
GND
C4
C2
R13
J4 (-)
R12
R21
R22
Top Side
Bottom Side
Figure 1. LM5115A Evaluation Board
2
AN-1542 LM5115A Evaluation Board
SNVA192B – December 2006 – Revised April 2013
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Board Layout and Probing
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J9 Must Be Connected to the
TP1 Terminal (LM5115A) for
the Proper Power-Up/PowerDown Tracking Sequence
LM5025A
EVALUATION
BOARD
L1
NATIONAL
SEMICONDUCTOR
P/N 551012240-001
REV C
IN(+)
J1
C19
D3
OUT(+)
J9
J8
C11
R11
C22
L2
3.3V
+OUTPUT-
36V to 72V
-INPUT+
J2
T2
J3
J6
C21
T1
U4
R14
R9
C9
R8
D4
J4
C10
C8
U2
R12
IN(-)
U1
C31
C32
R18
OUT(-)
R35
U3
R15
C14
J5
R36
C20
R32
R30
R28
C12
C33
R2
R13
TP1
VCC
C13
R33
TP4
SB
C29
Figure 2. LM5025A Evaluation Board Top Side
C1
R1
IN(+)
C2
C17
J10
S
D5
R10
S
G
Q5
R22
Q2
R17
J7
D
R20
D
C23
G
Q6
S
D2
D
S
G
C25
Q1
R16
C5
C6
OUT(-)
C27 D8
R3
R7
Cut
R27
R4
C7
R31
R26
C16
C24
C15
3.3V
-OUTPUT+
C18
D26
36V to 72V
-INPUT+
G
R24
C4
S
R19
Q3
G
R25
D
Q4
C3
D
R21
R23
OUT(+)
IN(-)
R5
R34
D7
O ohm
C30
Figure 3. LM5025A Evaluation Board Bottom Side
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AN-1542 LM5115A Evaluation Board
3
Board Connections/Start-Up
4
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Board Connections/Start-Up
The input power connections are made to terminals J1 (+) and J4 (-) of the LM5025A evaluation board.
The input source must be capable of supplying the load on both the output of the LM5025A board and
LM5115A board. The input to the LM5115A is supplied by the secondary winding of the LM5025A board.
J7 (LM5025A) connects to J1 (LM5115A) and J10 (LM5025A) connects to J2 (LM5115A) (see Figure 1,
Figure 2, and Figure 3). The main load is connected to terminals J9 (+) and J5 (-) for the LM5025A.
Terminals J3 (+) and J4 (-) are the load connections for the LM5115A. Before start-up, a voltmeter should
be connected to the input terminals and to the output terminals. The input current should be monitored
with an ammeter or a current probe.
Note that for the proper Power-Up/Power-Down tracking sequence, the J9(+) terminal, the LM5025A Vout
(+) terminal, must be connected to the TP1 terminal, the LM5115A TRACK post, (see Figure 1, Figure 2,
and Figure 3). To disable the tracking feature R21 and R22 should be removed from the LM5115A
evaluation board and the soft start capacitor C2 (.1µF) should be added to the board.
5
Performance LM5115A Secondary Side Post Regulator
Performance of the LM5115A evaluation board can be seen in the following figures:
1. Power Conversion Efficiency (Figure 4 and Figure 5)
2. Load Regulation (Figure 6)
3. Secondary Closed Loop Frequency Response (Figure 7)
4. Representative Waveforms (Figure 8)
5. Gate Delays (Figure 9 and Figure 10)
6. Short Circuit Response (Figure 11)
7. Step Load Response (Figure 12 and Figure 13)
8. Power-up/Power-Down Tracking (Figure 14 and Figure 15)
9. Output Voltage Ripple (Figure 16)
6
VCC
The LM5115A produces a LDO 7V regulated output (VCC) that can supply up to 40mA of DC current. The
VCC regulator supplies power for the high current gate drive for the low-side MOSFET and the bootstrap
capacitor of the high side MOSFET driver.
7
Tracking/Soft-Start
Connecting the J9(+) terminal to the TP1 terminal will force the output voltage of the LM5115A evaluation
board to track the master power supply output voltage (the LM5025A evaluation board output voltage) at
Power-Up/Power-Down. TP1 is connected through a resistor divider (R21and R22) to the LM5115A
TRACK pin (Figure 23). Therefore, the output voltage slew rate of the LM5115A evaluation board will be
controlled by the master supply at Start-Up/Shut-Down. The LM5115A evaluation board is configured to
demonstrate that the LM5115A can be used in applications that require precise sequencing. To disable
the Tracking feature, R21 and R22 should be removed from the LM5115A evaluation board and the soft
start capacitor C2 (.1uF) should be added to the board. For more information regarding the Tracking
feature, please refer to LM5115A Secondary Side Post Regulator/DC-DC Converter with Power-up/Powerdown Tracking (SNVS467).
4
AN-1542 LM5115A Evaluation Board
SNVA192B – December 2006 – Revised April 2013
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Copyright © 2006–2013, Texas Instruments Incorporated
Current Limit Operation
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8
Current Limit Operation
The inductor current is sensed through resistor R8. The resistor value is designed for a current limit of
~10A. The LM5115A has two current limit amplifiers that monitor the sensed current signal across R8. The
common output port of these current limit amplifiers, the CO pin, is connected to the COMP pin through a
diode (D3). The slow current limit amplifier provides constant current operation at the desired current limit
set point. The fast current limit amplifier provides protection against fast over-current conditions. During
normal operation, the voltage error amplifier controls the COMP pin voltage which adjusts the PWM duty
cycle. However when the current sense input voltage exceeds 45mV, the slow current limit amplifier
gradually pulls down on COMP through the CO pin. Pulling COMP low reduces the operating duty cycle.
By controlling the operating duty cycle, the slow current limit amplifier will force constant current operation
at the desired current limit set point. R19 and C6 are connected in series from the CO Pin to ground to
provide adequate control loop compensation for the slow current limit (Figure 23). The desired current limit
set point, ILimit, can be programmed by selecting the proper current sense resistor, RSENSE,using the
following equation:
RSENSE = 0.045 V/ ILimit
(1)
In the event that the current sense input voltage exceeds 60mV, the fast current limit amplifier will pull
down hard on COMP through the CO pin. Therefore, the PWM comparator will inhibit output pulses. Once
the fault condition is removed, the fast current limit amplifier will release COMP. Therefore, the switching
will resume .
The current limit scheme explained above provides an average current limit mode of operation. The
LM5115A evaluation board can be also configured for cycle by cycle current limiting. In this mode, the CO
pin will pull the SYNC pin to ground through the diode D6 once the voltage across the sense resistor, R8,
exceeds 45mV. Therefore the high-side MOSFET will turn-off instantaneously to terminate the on-pulse.
The cycle by cycle current limiting should only be used if the master power supply uses a voltage mode
(or voltage mode with feed forward) control loop scheme. If cycle by cycle current limiting is used while the
master power supply is utilizing current mode control scheme an oscillation will occur. To configure the
LM5115A evaluation board for cycle by cycle current limiting, C9, R19, D3 have to be removed and D6
has to be added to the board.
In cases where a noisy current sense is present, adding a low pass filter to the input of CS and VOUT can
help restore a cleaner waveform (Figure 23 , R16 and C10). Care must be taken not to have a large RC
time constant to avoid instability.
9
Foldback Current Limit
Current limit foldback can be implemented with the following components: R17, R18, C10, D5, and R16
(see Figure 23). At nominal output voltage (VOUT = 2.5V) D5 is reversed biased and the current limit
threshold is still ~45mV. At lower output voltage the resistor divider network along with the forward biased
diode (D5) will increase the voltage across R16. In order to reach the 45mV current limit threshold, the
voltage across the sense resistor (R8) is reduced due to the increase in voltage across R16. Thus, the
current limit is reduced providing current limit foldback. The resistor divider sets the voltage when current
limit foldback kicks in and R16 sets the amount of current limit foldback.
10
Output Ripple Measurement
Accurate Ripple and Noise measurements are difficult to obtain. The most accurate results are obtained
when the measurement is taken as closely as possible to the converter’s output terminals. Since the
signal being measured is in the millivolt range and the measurement is made at a fairly high Bandwidth,
the measurement setup can be susceptible to picking up noise from external sources and distorting the
measurement results. The best way to minimize this effect is to use very short and direct connections to
the oscilloscope probe such that the total loop area in the signal and ground connections is as small as
possible. limiting the oscilloscope’s bandwidth will also help.
SNVA192B – December 2006 – Revised April 2013
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AN-1542 LM5115A Evaluation Board
5
Typical Performance Characteristics
11
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Typical Performance Characteristics
100
90
80
98
VIN = 36V
VIN = 72V
60
EFFICIENCY (%)
EFFICIENCY (%)
VIN = 36V
96
70
50
VIN = 48V
40
30
94
92
90
VIN = 72V
88
20
86
10
84
0
VIN = 48V
82
0
1
2
3
4
5
6
7
0
LOAD (A)
6
1
2
3
4
5
6
7
LOAD (A)
Figure 4. System Efficiency vs. Load Current and VIN
Figure 5. Adjusted Efficiency on Secondary Side vs.
Load Current and VIN
Figure 6. Output vs. Load Current and VIN
Figure 7. Secondary Closed Loop Frequency
Response
AN-1542 LM5115A Evaluation Board
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Typical Performance Characteristics
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Figure 8. Representative Waveform
Figure 9. Gate Turn-on Delay
Figure 10. Gate Turn-off Delay
Figure 11. Secondary Output Short Response
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7
Typical Performance Characteristics
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Figure 12. Secondary Step Load Response
Figure 13. Cross Regulation Step Load
Figure 14. Startup Response
Figure 15. Shutdown Response
Figure 16. Output Voltage Ripple
8
AN-1542 LM5115A Evaluation Board
SNVA192B – December 2006 – Revised April 2013
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Bill of Materials
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12
Bill of Materials
Item
Part Number
Description
Value
C3216X7R1E105K
CAPACITOR, CER, TDK
1.0 µF, 25V
3
C3216X7R1E104K
CAPACITOR, CER, TDK
0.1 µF, 25V
C
4
C2012X7R1H201K
CAPACITOR, CER, TDK
200 pF, 50V
C
5
C2012X7R1H223K
CAPACITOR, CER, TDK
0.022 µF, 50V
C
6
C2012X7R1H332K
CAPACITOR, CER, TDK
3300 pF, 50V
C
7
C2012X7R1H103K
CAPACITOR, CER, TDK
0.01 µF, 50V
C
8
Not Used
C
9
Not Used
C
10
C
11
C4532X7SOG686M
CAPACITOR, CER, TDK
68 µF, 4.0V
C
12
C4532X7SOG686M
CAPACITOR, CER, TDK
68 µF, 4.0V
C
13
C4532X7SOG686M
CAPACITOR, CER, TDK
68 µF, 4.0V
D
1
CMDD4448
DIODE, SIGNAL, CENTRAL, SEMI
D
2
CMDD4448
DIODE, SIGNAL, CENTRAL, SEMI
D
3
CMDD4448
DIODE, SIGNAL, CENTRAL, SEMI
D
4
Not Used
D
5
Not Used
D
6
Not Used
D
7
Not Used
D
8
Not Used
J
1
2515-1-01-01-00-00-07-0
J
2
2515-1-01-01-00-00-07-0
SOLDER TERMINAL SLOTTED, MILL-MAX
J
3
5002
TERMINAL, SMALL TEST POINT, KEYSTONE
C
1
C
2
C
Not Used
Not Used
SOLDER TERMINAL SLOTTED, MILL-MAX
J
4
5002
TERMINAL, SMALL TEST POINT, KEYSTONE
R
1
ERJ-6RNF5R6V
RESISTOR, PANASONIC
5.6
R
2
ERJ-6ENF1622V
RESISTOR, PANASONIC
16.2 K
R
3
ERJ-6RNF4322V
RESISTOR, PANASONIC
43.2 K
R
4
ERJ-6RNF1003V
RESISTOR, PANASONIC
R
5
Not Used
R
6
Not Used
R
7
R
8
R
9
R
10
R
11
R
12
ERJ-6RNF8251V
RESISTOR, PANASONIC
R
13
ERJ-6RNF3571V
RESISTOR, PANASONIC
R
14
R
15
ERJ-6GEY0R00V
RESISTOR, PANASONIC
0 OHMS
R
16
ERJ-6GEY0R00V
RESISTOR, PANASONIC
0 OHMS
R
17
R
18
R
19
R
20
R
R
100 K
Not Used
WSL12063L000FEA
RESISTOR, VISHAY
0.003
Not Used
ERJ-6RNF10R0V
RESISTOR, PANASONIC
10
Not Used
8.25 K
3.57 K
Not Used
Not Used
Not Used
ERJ-6RNF49R9V
RESISTOR, PANASONIC
49.9
21
ERJ-6RNF4321V
RESISTOR, PANASONIC
4.32 K
22
ERJ-6RNF1002V
RESISTOR, PANASONIC
10 K
Not Used
SNVA192B – December 2006 – Revised April 2013
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AN-1542 LM5115A Evaluation Board
9
PCB Layout(s)
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Item
13
Part Number
Description
Q
1
SI7892DP
MOSFET, N-CH, POWER S0-8 PKG, VISHAY
SI7892DP
Q
2
IPD04N03LAG
MOSFET, N-CH, DPAK PKG, INFINEON
IPD04N03LAG
L
1
DR127-2R2-R
INDUCTOR, COOPER, DR127-2R2
2.2 uH - 12A
L
2
TP
1
5012
TEST POINT, KEYSTONE
TP
2
5012
TEST POINT, KEYSTONE
TP
3
5012
TEST POINT, KEYSTONE
U
1
LM5115
CONTROLLER, SINGLE OUT, PWM,
TEXAS INSTRUMENTS
Not Used
LM 5115
PCB Layout(s)
Figure 17. Top Silk Screen LM5115A
10
Value
AN-1542 LM5115A Evaluation Board
Figure 18. Top Layer LM5115A
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PCB Layout(s)
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Figure 19. Layer 2 LM5115A
Figure 20. Layer 3 LM5115A
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11
PCB Layout(s)
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Figure 21. Bottom Layer LM5115A,
as Viewed from Top
12
AN-1542 LM5115A Evaluation Board
Figure 22. Bottom Silk Screen LM5115A
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Application Circuit Schematics
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14
Application Circuit Schematics
Figure 23. LM5115A AC Eval Board Schematic
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Copyright © 2006–2013, Texas Instruments Incorporated
13
Application Circuit Schematics
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Figure 24. LM5025A Eval Board
14
AN-1542 LM5115A Evaluation Board
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Copyright © 2006–2013, Texas Instruments Incorporated
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