LM5116-HT
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SLVSBS8B – OCTOBER 2013 – REVISED JANUARY 2014
WIDE RANGE SYNCHRONOUS BUCK CONTROLLER
Check for Samples: LM5116-HT
FEATURES
1
•
•
•
•
•
•
•
•
•
•
•
•
•
2
Emulated Peak Current Mode
Wide Operating Range Up to 80 V
Low IQ Shutdown (< 10 µA)
Drives Standard or Logic Level MOSFETs
Robust 3.5-A Peak Gate Drive
Free-Run or Synchronous Operation to 1 MHz
Optional Diode Emulation Mode
Programmable Output from 1.215 V to 80 V
Precision 1.5% Voltage Reference
Programmable Current Limit
Programmable Soft-Start
Programmable Line Under-Voltage Lockout
Automatic Switch to External Bias Supply
APPLICATIONS
•
•
SUPPORTS EXTREME TEMPERATURE
APPLICATIONS
•
•
•
•
•
•
•
•
Controlled Baseline
One Assembly and Test Site
One Fabrication Site
Available in Extreme (–55°C to 175°C)
Temperature Range
Extended Product Life Cycle
Extended Product-Change Notification
Product Traceability
Texas Instruments' high temperature products
utilize highly optimized silicon (die) solutions
with design and process enhancements to
maximize performance over extended
temperatures.
Down-Hole Drilling
High Temperature Environments
DESCRIPTION
The LM5116 is a synchronous buck controller intended for step-down regulator applications from a high voltage
or widely varying input supply. The control method is based upon current mode control utilizing an emulated
current ramp. Current mode control provides inherent line feed-forward, cycle by cycle current limiting and ease
of loop compensation. The use of an emulated control ramp reduces noise sensitivity of the pulse-width
modulation circuit, allowing reliable control of very small duty cycles necessary in high input voltage applications.
The operating frequency is programmable from 50 kHz to 1 MHz. The LM5116 drives external high-side and lowside NMOS power switches with adaptive dead-time control. A user-selectable diode emulation mode enables
discontinuous mode operation for improved efficiency at light load conditions. A low quiescent current shutdown
disables the controller and consumes less than 10 µA of total input current. Additional features include a high
voltage bias regulator, automatic switch-over to external bias for improved efficiency, thermal shutdown,
frequency synchronization, cycle by cycle current limit and adjustable line under-voltage lockout.
1
2
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
All trademarks are the property of their respective owners.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2013–2014, Texas Instruments Incorporated
LM5116-HT
SLVSBS8B – OCTOBER 2013 – REVISED JANUARY 2014
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This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
ORDERING INFORMATION (1)
(1)
TJ
PACKAGE
PART NUMBER
TOP-SIDE MARKING
–55°C to 175°C
JD
LM5116HJD
LM5116HJD
For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI
web site at www.ti.com.
Typical Application
VIN
LM5116
VIN
VCC
C VCC
CIN
RUV2
HB
UVLO
R UV1
VIN
CHB
HO
EN
L
VOUT
SW
CSYNC
RT/ SYNC
C OUT
LO
RT
CS
RS
CSG
COMP
C COMP
DEMB
CHF
R COMP
VOUT
FB
SS
RAMP
C SS
AGND PGND
VCCX
R FB2
C RAMP
RFB1
Connection Diagram
JD PACKAGE
(TOP VIEW)
2
VIN
1
20
SW
UVLO
2
19
HO
RT/ SYNC
3
18
HB
EN
4
17
VCCX
RAMP
5
16
VCC
AGND
6
15
LO
SS
7
14
PGND
FB
8
13
CSG
COMP
9
12
CS
VOUT
10
11
DEMB
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Pin Functions
Pin Descriptions
Pin
Name
Description
1
VIN
2
UVLO
If the UVLO pin is below 1.215 V, the regulator will be in standby mode (VCC regulator running, switching regulator
disabled). If the UVLO pin voltage is above 1.215 V, the regulator is operational. An external voltage divider can be
used to set an under-voltage shutdown threshold. There is a fixed 5 µA pull up current on this pin when EN is high.
UVLO is pulled to ground in the event a current limit condition exists for 256 clock cycles.
3
RT/SYNC
The internal oscillator is set with a single resistor between this pin and the AGND pin. The recommended frequency
range is 50 kHz to 1 MHz. The internal oscillator can be synchronized to an external clock by AC coupling a positive
edge onto this node.
4
EN
5
RAMP
Ramp control signal. An external capacitor connected between this pin and the AGND pin sets the ramp slope used
for current mode control.
6
AGND
Analog ground. Connect to PGND through the exposed pad ground connection under the LM5116.
7
SS
An external capacitor and an internal 10 µA current source set the soft start time constant for the rise of the error amp
reference. The SS pin is held low during VCC < 4.5 V, UVLO < 1.215 V, EN input low or thermal shutdown.
8
FB
Feedback signal from the regulated output. This pin is connected to the inverting input of the internal error amplifier.
The regulation threshold is 1.215 V.
9
COMP
Output of the internal error amplifier. The loop compensation network should be connected between this pin and the
FB pin.
10
VOUT
Output monitor. Connect directly to the output voltage.
11
DEMB
Low-side MOSFET source voltage monitor for diode emulation. For start-up into a pre-biased load, tie this pin to
ground at the CSG connection. For fully synchronous operation, use an external series resistor between DEMB and
ground to raise the diode emulation threshold above the low-side SW on-voltage.
12
CS
13
CSG
14
PGND
15
LO
16
VCC
17
VCCX
18
HB
High-side driver supply for bootstrap gate drive. Connect to the cathode of the bootstrap diode and the positive
terminal of the bootstrap capacitor. The bootstrap capacitor supplies current to charge the high-side MOSFET gate
and should be placed as close to the controller as possible.
19
HO
Connect to the gate of the high-side synchronous MOSFET through a short, low inductance path
20
SW
Switch node. Connect to the negative terminal of the bootstrap capacitor and the source terminal of the high-side
MOSFET.
Chip supply voltage, input voltage monitor and input to the VCC regulator.
If the EN pin is below 0.5 V, the regulator will be in a low power state drawing less than 10 µA from VIN. EN must be
pulled above 3.3 V for normal operation. The maximum EN transition time for proper operation is one switching period.
Current sense amplifier input. Connect to the top of the current sense resistor or the drain of the low-sided MOSFET if
RDS(ON) current sensing is used.
Current sense amplifier input. Connect to the bottom of the sense resistor or the source of the low-side MOSFET if
RDS(ON) current sensing is used.
Power ground. Connect to AGND through the exposed pad ground connection under the LM5116.
Connect to the gate of the low-side synchronous MOSFET through a short, low inductance path.
Locally decouple to PGND using a low ESR/ESL capacitor located as close to the controller as possible.
Optional input for an externally supplied VCC. If VCCX > 4.5 V, VCCX is internally connected to VCC and the internal
VCC regulator is disabled. If VCCX is unused, it should be connected to ground.
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Absolute Maximum Ratings
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(1)
VIN to GND
-0.3 to 80
V
-0.3 to 16
V
SW, CS to GND
-3.0 to 80
V
HB to SW
-0.3 to 16
V
HO to SW
-0.3 to HB + 0.3
V
-0.3 to 80
V
-1 to 1
V
LO to GND
-0.3 to VCC + 0.3
V
SS to GND
-0.3 to 7
V
FB to GND
-0.3 to 7
V
VCC, VCCX, UVLO to GND
(2)
VOUT to GND
CSG to GND
DEMB to GND
-0.3 to VCC
V
RT to GND
-0.3 to 7
V
EN to GND
-0.3 to 80
V
ESD Rating
HBM (3)
2
kV
-55 to 190
°C
190
°C
Storage Temperature Range
Junction Temperature
(1)
(2)
(3)
Absolute Maximum Ratings indicate limits beyond which damage to the component may occur. Operating Ratings are conditions under
which operation of the device is guaranteed. Operating Ratings do not imply guaranteed performance limits. For guaranteed
performance limits and associated test conditions, see the Electrical Characteristics tables.
These pins must not exceed VIN.
The human body model is a 100 pF capacitor discharged through a 1.5 kΩ resistor into each pin. 2 kV rating for all pins except VIN
which is rated for 1.5 kV.
THERMAL INFORMATION
LM5116-HT
THERMAL METRIC (1)
JD
UNITS
20 PINS
θJA
Junction-to-ambient thermal resistance (2)
θJCtop
Junction-to-case (top) thermal resistance (3)
θJB
Junction-to-board thermal resistance (4)
21.97
ψJT
Junction-to-top characterization parameter (5)
12.95
ψJB
Junction-to-board characterization parameter (6)
18.21
θJCbot
Junction-to-case (bottom) thermal resistance (7)
5.25
(1)
(2)
(3)
(4)
(5)
(6)
(7)
4
43.2
N/A
°C/W
For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.
The junction-to-ambient thermal resistance under natural convection is obtained in a simulation on a JEDEC-standard, high-K board, as
specified in JESD51-7, in an environment described in JESD51-2a.
The junction-to-case (top) thermal resistance is obtained by simulating a cold plate test on the package top. No specific JEDECstandard test exists, but a close description can be found in the ANSI SEMI standard G30-88.
The junction-to-board thermal resistance is obtained by simulating in an environment with a ring cold plate fixture to control the PCB
temperature, as described in JESD51-8.
The junction-to-top characterization parameter, ψJT, estimates the junction temperature of a device in a real system and is extracted
from the simulation data for obtaining θJA, using a procedure described in JESD51-2a (sections 6 and 7).
The junction-to-board characterization parameter, ψJB, estimates the junction temperature of a device in a real system and is extracted
from the simulation data for obtaining θJA , using a procedure described in JESD51-2a (sections 6 and 7).
The junction-to-case (bottom) thermal resistance is obtained by simulating a cold plate test on the exposed (power) pad. No specific
JEDEC standard test exists, but a close description can be found in the ANSI SEMI standard G30-88.
Spacer
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Operating Ratings
SLVSBS8B – OCTOBER 2013 – REVISED JANUARY 2014
(1)
VIN
6 to 80
V
VCC, VCCX
4.75 to 15
V
HB to SW
4.75 to 15
V
-0.3 to 2
V
-55 to 175
°C
DEMB to GND
Junction Temperature
(1)
Note: RAMP, COMP are output pins. As such they are not specified to have an external voltage applied.
Electrical Characteristics
Limits in standard type are for TJ = 25°C only; limits in boldface type apply over the junction temperature range of -55°C to
+175°C and are provided for reference only. Unless otherwise specified, the following conditions apply: VIN = 48V,
VCC = 7.4 V, VCCX = 0 V, EN = 5 V, RT = 16 kΩ, no load on LO and HO.
Symbol
Parameter
Conditions
VIN Operating Current
Min
Typ
Max
Units
VCCX = 0 V, VIN = 48 V
5
7
mA
VCCX = 0 V, VIN = 80 V
5.9
8
mA
VCCX = 5 V, VIN = 48 V
1.2
1.7
mA
VCCX = 5 V, VIN = 80 V
VIN Supply
IBIAS
IBIASX
VIN Operating Current
ISTDBY
VIN Shutdown Current
1.6
2.3
mA
EN = 0 V, VIN = 48 V
1
10
µA
EN = 0 V, VIN = 80 V
1
µA
VCC Regulator
VCC(REG)
VCC Regulation
7.1
VCC LDO Mode Turn-off
7.4
7.7
10.6
VCC Regulation
VIN = 6 V
5.0
VCC Sourcing Current Limit
VCC = 0 V
12
26
VCCX Switch Threshold
VCCX Rising
4.3
4.5
VCCX Switch Hysteresis
5.9
V
6.0
V
mA
5
0.25
3.8
V
V
V
ICCX = 10 mA
VCCX Leakage
VCCX = 0 V
-200
nA
VCCX Pull- down Resistance
VCCX = 3 V
100
kΩ
VCC Under-voltage Threshold
VCC Rising
4
VCC Under-voltage Hysteresis
HB DC Bias Current
4.5
7
Ω
VCCX Switch RDS(ON)
5
V
200
µA
0.5
V
1
µA
0.2
HB - SW = 15 V
125
V
EN Input
VIL max
EN Input Low Threshold
VIH min
EN Input High Threshold
3.3
EN Input Bias Current
VEN = 3 V
-9
EN Input Bias Current
VEN = 0.5 V
-2
EN Input Bias Current
VEN = 80 V
UVLO Standby Threshold
UVLO Rising
V
-3
0
2
µA
20
90
µA
1.215
1.262
V
UVLO Thresholds
1.170
UVLO Threshold Hysteresis
UVLO Pull-up Current Source
UVLO = 0 V
UVLO Pull-down RDS(ON)
0.1
V
5.4
µA
80
240
Ω
11
14
µA
Soft Start
SS Current Source
SS = 0 V
SS Diode Emulation Ramp Disable
Threshold
SS Rising
SS to FB Offset
SS Output Low Voltage
8
3
V
FB = 1.25 V
160
mV
Sinking 100 µA, UVLO = 0 V
45
mV
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Electrical Characteristics (continued)
Limits in standard type are for TJ = 25°C only; limits in boldface type apply over the junction temperature range of -55°C to
+175°C and are provided for reference only. Unless otherwise specified, the following conditions apply: VIN = 48V,
VCC = 7.4 V, VCCX = 0 V, EN = 5 V, RT = 16 kΩ, no load on LO and HO.
Symbol
Parameter
Conditions
FB Reference Voltage
Measured at FB pin,
FB = COMP
FB Input Bias Current
FB = 2 V
Min
Typ
Max
Units
1.195
1.215
1.231
V
15
600
Error Amplifier
VREF
COMP Sink/Source Current
3
nA
mA
AOL
DC Gain
80
dB
fBW
Unity Gain Bandwidth
3
MHz
PWM Comparators
tHO(OFF)
Forced HO Off-time
320
tON(min)
Minimum HO On-time
VIN = 80 V, CRAMP = 50 pF
fSW1
Frequency 1
RT = 16 kΩ
fSW2
Frequency 2
RT = 5 kΩ
450
600
100
ns
ns
Oscillator
175
200
225
kHz
470
535
610
kHz
1.191
1.215
1.239
V
RT sync positive threshold
2.6
3.5
4.4
V
VCS(TH)
Cycle-by-cycle Sense Voltage Threshold VCCX = 0 V, RAMP = 0 V
(CSG - CS)
94
110
126
mV
VCS(THX)
Cycle-by-cycle Sense Voltage Threshold VCCX = 5 V, RAMP = 0 V
(CSG - CS)
105
122
139
mV
RT output voltage
Current Limit
CS Bias Current
CS = 100 V
5
µA
CS Bias Current
CS = 0 V
-5
90
125
µA
CSG Bias Current
CSG = 0 V
90
125
µA
Current Limit Fault Timer
RT = 16 kΩ, (200 kHz),
(256 clock cycles)
IR1
RAMP Current 1
VIN = 60 V, VOUT = 10 V
235
285
335
µA
IR2
RAMP Current 2
VIN = 10 V, VOUT = 10 V
21
28
35
µA
VOUT Bias Current
VOUT = 36 V
200
µA
RAMP Output Low Voltage
VIN = 60 V, VOUT = 10 V
265
mV
1.28
ms
RAMP Generator
Diode Emulation
SW Zero Cross Threshold
-6
mV
DEMB Output Current
DEMB = 0 V, SS = 1.25 V
1.6
2.7
4.5
µA
DEMB Output Current
DEMB =0 V, SS = 2.8 V
28
38
48
µA
DEMB Output Current
DEMB = 0 V, SS = Regulated
by FB
45
65
85
µA
VOLL
LO Low-state Output Voltage
ILO = 100 mA
0.08
0.18
V
VOHL
LO High-state Output Voltage
ILO = -100 mA,
VOHL = VCC - VLO
0.25
V
LO Rise Time
C-load = 1000 pF
18
ns
LO Fall Time
C-load = 1000 pF
12
ns
IOHL
Peak LO Source Current
VLO = 0 V
1.8
A
IOLL
Peak LO Sink Current
VLO = VCC
3.5
A
LO Gate Driver
6
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Electrical Characteristics (continued)
Limits in standard type are for TJ = 25°C only; limits in boldface type apply over the junction temperature range of -55°C to
+175°C and are provided for reference only. Unless otherwise specified, the following conditions apply: VIN = 48V,
VCC = 7.4 V, VCCX = 0 V, EN = 5 V, RT = 16 kΩ, no load on LO and HO.
Symbol
Parameter
Conditions
VOLH
HO Low-state Output Voltage
VOHH
Min
Typ
Max
Units
IHO = 100 mA
0.17
0.8
V
HO High-state Output Voltage
IHO = -100 mA,
VOHH = VHB – VHO
0.45
V
HO Rise Time
C-load = 1000 pF
19
ns
HO High-side Fall Time
C-load = 1000 pF
13
ns
IOHH
Peak HO Source Current
VHO = 0 V
1
A
IOLH
Peak HO Sink Current
VHO = VCC
2.2
A
3
V
HO Gate Driver
HB to SW under-voltage
Switching Characteristics
LO Fall to HO Rise Delay
C-load = 0
75
ns
HO Fall to LO Rise Delay
C-load = 0
70
ns
xxx
1000000.00
Estimated Life (Hrs)
100000.00
10000.00
1000.00
100.00
120
130
140
150
160
170
180
Continuous T J (°C)
(1)
See datasheet for absolute maximum and minimum recommended operating conditions.
(2)
Silicon operating life design goal is 10 years at 105°C junction temperature (does not include package interconnect
life).
(3)
The predicted operating lifetime vs. junction temperature is based on reliability modeling using electromigration as the
dominant failure mechanism affecting device wearout for the specific device process and design characteristics.
(4)
This device is qualified for 1000 hours of continuous operation at maximum rated temperature.
Figure 1. LM5116-HT Operating Life Derating Chart
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Typical Performance Characteristics
Typical Application Circuit Efficiency
Driver Source Current
vs
VCC
Driver Dead-time
vs
Temperature
Driver Sink Current
vs
VCC
120
LO Fall to
HO Rise (ns)
110
HO Fall to
LO Rise (ns)
100
Delay (ns)
90
80
70
60
50
40
-55
-5
45
95
145
195
Temperature (ºC)
C001
EN Input Threshold
vs
Temperature
HB to SW UVLO
vs
Temperature
3.6
2.6
Falling (V)
Falling (V)
Rising (V)
Rising (V)
2.4
3.4
HB - SW UVLO (V)
EN Threshold (V)
2.2
2.0
1.8
1.6
3.2
3.0
2.8
1.4
2.6
1.2
1.0
2.4
-55
-5
45
95
145
195
Temperature (ºC)
-5
45
95
145
195
Temperature (ºC)
C003
8
-55
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Typical Performance Characteristics (continued)
Forced HO Off-time
vs
Temperature
VCCX = 5V
HB DC Bias Current
vs
Temperature
560
180
540
160
HB-SW = 15 V
HB-SW = 7.7 V
140
520
Current (µA)
Time (ns)
120
500
480
100
80
460
60
440
40
420
20
±55
±5
45
95
145
195
Temperature (ºC)
±55
±5
45
95
145
C005
Frequency
vs
RT
Error Amp Gain
vs
Frequency
Frequency
vs
Temperature
Error Amp Phase
vs
Frequency
558
195
Temperature (ºC)
C002
RT = 5 kW
556
Frequency (kHz)
554
552
550
548
546
544
542
-55
-5
45
95
145
195
Temperature (ºC)
C006
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Typical Performance Characteristics (continued)
Frequency
vs
Temperature
Current Limit Threshold
vs
Temperature
130
210
RT = 16 kW
Vccx = 5 V
Vccx = 6 V
125
CSG - CS Threshold (mA)
Frequency (kHz)
208
206
204
202
120
115
110
105
200
100
-55
-5
45
95
145
195
-55
-5
Termperature (ºC)
45
95
145
195
Temperature (ºC)
C007
C008
VIN Operating Current
vs
Temperature
VCC
vs
Temperature
7.6
1.6
VIN = 80 V
VIN = 48 V
1.4
7.5
1.2
VCC (V)
Current (mA)
7.5
1.0
0.8
0.6
7.4
7.4
0.4
7.3
Current (mA)
VCCX = 0V
0.2
Current (mA)
VCCX = 5V
0.0
±55
±5
45
95
7.3
145
195
-55
-5
45
95
145
195
Temperature (ºC)
Temperature (ºC)
C011
C009
VCC UVLO
vs
Temperature
VCC
vs
VIN
4.6
4.6
4.5
VCC (V)
4.5
Rising (V)
4.4
Falling (V)
4.4
4.3
4.3
4.2
-55
-5
45
95
145
195
Temperature (ºC)
C010
10
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Typical Performance Characteristics (continued)
VCCX Switch RDS(ON)
vs
VCCX
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Block Diagram and Typical Application Circuit
VCCX
17
VCCX
LM 5116
VIN
4.5V
6V -100V
C IN
1 VIN
R UV2
VCC 16
UVLO
SLEEP
MODE
SHUTDOWN
1.215V
STANDBY
D2
HB 18
THERMAL
SHUTDOWN
5 PA
UVLO
LOGIC
C FT
HICCUP FAULT TIMER
256 CLOCK CYCLES
UVLO
DIS
CHB
VIN
DRIVER
HO 19
CLK
7 SS
10 PA
3V
PWM
CSS
C COMP
ADAPTIVE
TIMER
TRACK
SAMPLE
and
HOLD
1.6V
COMP
+
10 x RS V/A
LO 15
A =10
VOUT
Q2
CSNUB
COUT
R SNUB
RS
0.5V
CSG 13
SW
DIODE
EMULATION
CONTROL
VIN
OSCILLATOR
IR
RAMP
11
VOUT
10
R FB1
AGND
5
DEMB
R FB2
RAMP GENERATOR
I R = 5PA / V x ( VIN - VOUT ) + 25PA
RT
L1
CLK
CLK
3 RT/SYNC
Q1
20
CS 12
SS
C SYNC
SW
VCC
DRIVER
R COMP
9
Q
Q
CURRENT
LIMIT
ERROR
AMP
CHF
S
R
1V
1.215 V
8 FB
SYNC
C VCC
D1
4 EN
2 UVLO
R UV1
+
-
7. 4 V
REGULATOR
R EN
EN
C VCCX
PGND
6
14
CRAMP
Figure 2. Typical Application
Detailed Operating Description
The LM5116 high voltage switching regulator features all of the functions necessary to implement an efficient
high voltage buck regulator using a minimum of external components. This easy to use regulator integrates highside and low-side MOSFET drivers capable of supplying peak currents of 2 A. The regulator control method is
based on current mode control utilizing an emulated current ramp. Emulated peak current mode control provides
inherent line feed-forward, cycle by cycle current limiting and ease of loop compensation. The use of an
emulated control ramp reduces noise sensitivity of the pulse-width modulation circuit, allowing reliable processing
of the very small duty cycles necessary in high input voltage applications. The operating frequency is user
programmable from 50 kHz to 1 MHz. An oscillator/synchronization pin allows the operating frequency to be set
by a single resistor or synchronized to an external clock. Fault protection features include current limiting, thermal
shutdown and remote shutdown capability. An under-voltage lockout input allows regulator shutdown when the
input voltage is below a user selected threshold, and an enable function will put the regulator into an extremely
low current shutdown via the enable input.
High Voltage Start-Up Regulator
The LM5116 contains a dual mode internal high voltage startup regulator that provides the VCC bias supply for
the PWM controller and a boot-strap gate drive for the high-side buck MOSFET. The input pin (VIN) can be
connected directly to an input voltage source as high as 100 V. For input voltages below 10.6 V, a low dropout
switch connects VCC directly to VIN. In this supply range, VCC is approximately equal to VIN. For VIN voltages
greater than 10.6 V, the low dropout switch is disabled and the VCC regulator is enabled to maintain VCC at
approximately 7.4 V. The wide operating range of 6 V to 80 V is achieved through the use of this dual mode
regulator.
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Upon power-up, the regulator sources current into the capacitor connected to the VCC pin. When the voltage at
the VCC pin exceeds 4.5 V and the UVLO pin is greater than 1.215 V, the output switch is enabled and a softstart sequence begins. The output switch remains enabled until VCC falls below 4.5 V, EN is pulled low, the
UVLO pin falls below 1.215 V or the die temperature exceeds the thermal limit threshold.
VCCX
CVCCX
VOUT
SW
L
COUT
Figure 3. VCCX Bias Supply with Additional Inductor Winding
An output voltage derived bias supply can be applied to the VCCX pin to reduce the IC power dissipation. If the
bias supply voltage is greater than 4.5 V, the internal regulator will essentially shut off, reducing the IC power
dissipation. The VCC regulator series pass transistor includes a diode between VCC and VIN that should not be
forward biased in normal operation. For an output voltage between 5 V and 15 V, VOUT can be connected
directly to VCCX. For VOUT < 5 V, a bias winding on the output inductor can be added to VOUT. If the bias
winding can supply VCCX greater than VIN, an external blocking diode is required from the input power supply to
the VIN pin to prevent VCC from discharging into the input supply.
The output of the VCC regulator is current limited to 15 mA minimum. The VCC current is determined by the
MOSFET gate charge, switching frequency and quiescent current (see MOSFETs section in the Application
Information). If VCCX is powered by the output voltage or an inductor winding, the VCC current should be
evaluated during startup to ensure that it is less than the 15 mA minimum current limit specification. IF VCCX is
powered by an external regulator derived from VIN, there is no restriction on the VCC current.
VIN
1
VIN
0.1 PF
6
AGND
Figure 4. Input Blocking Diode for VCCX > VIN
In high voltage applications extra care should be taken to ensure the VIN pin does not exceed the absolute
maximum voltage rating of 80 V. During line or load transients, voltage ringing on the VIN line that exceeds the
Absolute Maximum Ratings can damage the IC. Both careful PC board layout and the use of quality bypass
capacitors located close to the VIN and GND pins are essential.
Enable
The LM5116 contains an enable function allowing a very low input current shutdown. If the enable pin is pulled
below 0.5 V, the regulator enters shutdown, drawing less than 10 µA from the VIN pin. Raising the EN input
above 3.3 V returns the regulator to normal operation. The maximum EN transition time for proper operation is
one switching period. For example, the enable rise time must be less than 4 μs for 250 kHz operation.
A 1 MΩ pull-up resistor to VIN can be used to interface with an open collector control signal. At low input voltage
the pull-up resistor may be reduced to 100 kΩ to speed up the EN transition time. The EN pin can be tied directly
to VIN if this function is not needed. It must not be left floating. If low-power shutdown is not needed, the UVLO
pin should be used as an on/off control.
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Internal 5V rail
3 PA
EN
6V
Figure 5. Enable Circuit
Figure 6. EN Bias Current vs Voltage
UVLO
An under-voltage lockout pin is provided to disable the regulator without entering shutdown. If the UVLO pin is
pulled below 1.215 V, the regulator enters a standby mode of operation with the soft-start capacitor discharged
and outputs disabled, but with the VCC regulator running. If the UVLO input is pulled above 1.215 V, the
controller will resume normal operation. A voltage divider from input to ground can be used to set a VIN threshold
to disable the supply in brown-out conditions or for low input faults. The UVLO pin has a 5 µA internal pull up
current that allows this pin to left open if the input under-voltage lockout function is not needed. For applications
which require fast on/off cycling, the UVLO pin with an open collector control signal may be used to ensure
proper start-up sequencing.
The UVLO pin is also used to implement a “hiccup” current limit. If a current limit fault exists for more than 256
consecutive clock cycles, the UVLO pin will be internally pulled down to 200 mV and then released, and a new
SS cycle initiated. A capacitor to ground connected to the UVLO pin will set the timing for hiccup mode current
limit. When this feature is used in conjunction with the voltage divider, a diode across the top resistor may be
used to discharge the capacitor in the event of an input under-voltage condition. There is a 5 µs filter at the input
to the fault comparator. At higher switching frequency (greater than approximately 250 kHz) the hiccup timer may
be disabled if the fault capacitor is not used.
Oscillator and Sync Capability
The LM5116 oscillator frequency is set by a single external resistor connected between the RT/SYNC pin and
the AGND pin. The resistor should be located very close to the device and connected directly to the pins of the
IC (RT/SYNC and AGND). To set a desired oscillator frequency (fSW), the necessary value for the resistor can be
calculated from the following equation:
RT =
T - 450 ns
284 pF
(1)
Where T = 1 / fSW and RT is in ohms. 450 ns represents the fixed minimum off time.
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The LM5116 oscillator has a maximum programmable frequency that is dependent on the VCC voltage. If VCC is
above 6 V, the frequency can be programmed up to 1 MHz. If VCCX is used to bias VCC and VCCX < 6 V, the
maximum programmable oscillator frequency is 750 kHz.
The RT/SYNC pin can be used to synchronize the internal oscillator to an external clock. The external clock must
be a higher frequency than the free-running frequency set by the RT resistor. The internal oscillator can be
synchronized to an external clock by AC coupling a positive edge into the RT/SYNC pin. The voltage at the
RT/SYNC pin is nominally 1.215 V and must exceed 4 V to trip the internal synchronization pulse detection. A
5-V amplitude signal and 100 pF coupling capacitor are recommended. The free-running frequency should be set
nominally 15% below the external clock. Synchronizing above twice the free-running frequency may result in
abnormal behavior of the pulse width modulator.
Error Amplifier and PWM Comparator
The internal high-gain error amplifier generates an error signal proportional to the difference between the
regulated output voltage and an internal precision reference (1.215 V). The output of the error amplifier is
connected to the COMP pin allowing the user to provide loop compensation components, generally a type II
network. This network creates a pole at very low frequency, a mid-band zero, and a noise reducing high
frequency pole. The PWM comparator compares the emulated current sense signal from the RAMP generator to
the error amplifier output voltage at the COMP pin.
Ramp Generator
The ramp signal used in the pulse width modulator for current mode control is typically derived directly from the
buck switch current. This switch current corresponds to the positive slope portion of the inductor current. Using
this signal for the PWM ramp simplifies the control loop transfer function to a single pole response and provides
inherent input voltage feed-forward compensation. The disadvantage of using the buck switch current signal for
PWM control is the large leading edge spike due to circuit parasitics that must be filtered or blanked. Also, the
current measurement may introduce significant propagation delays. The filtering, blanking time and propagation
delay limit the minimal achievable pulse width. In applications where the input voltage may be relatively large in
comparison to the output voltage, controlling small pulse widths and duty cycles is necessary for regulation. The
LM5116 utilizes a unique ramp generator which does not actually measure the buck switch current but rather
reconstructs the signal. Representing or emulating the inductor current provides a ramp signal to the PWM
comparator that is free of leading edge spikes and measurement or filtering delays. The current reconstruction is
comprised of two elements, a sample-and-hold DC level and an emulated current ramp.
(5 PA/V x (VIN-VOUT) + 25 PA) x
tON
CRAMP
RAMP
Sample and Hold
DC Level
10 x RS V/A
tON
Figure 7. Composition of Current Sense Signal
The sample-and-hold DC level is derived from a measurement of the recirculating current through either the lowside MOSFET or current sense resistor. The voltage level across the MOSFET or sense resistor is sampled and
held just prior to the onset of the next conduction interval of the buck switch. The current sensing and sampleand-hold provide the DC level of the reconstructed current signal. The positive slope inductor current ramp is
emulated by an external capacitor connected from the RAMP pin to the AGND and an internal voltage controlled
current source. The ramp current source that emulates the inductor current is a function of the VIN and VOUT
voltages per the following equation:
IR = 5 µA/V x (VIN - VOUT) + 25 µA
(2)
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Proper selection of the RAMP capacitor (CRAMP) depends upon the value of the output inductor (L) and the
current sense resistor (RS). For proper current emulation, the DC sample and hold value and the ramp amplitude
must have the same dependence on the load current. That is:
RS x A =
CRAMP =
gm x L
, so
CRAMP
gm x L
A x RS
(3)
Where gm is the ramp generator transconductance (5 µA/V) and A is the current sense amplifier gain (10 V/V).
The ramp capacitor should be located very close to the device and connected directly to the pins of the IC
(RAMP and AGND).
The difference between the average inductor current and the DC value of the sampled inductor current can
cause instability for certain operating conditions. This instability is known as sub-harmonic oscillation, which
occurs when the inductor ripple current does not return to its initial value by the start of next switching cycle.
Sub-harmonic oscillation is normally characterized by observing alternating wide and narrow pulses at the switch
node. Adding a fixed slope voltage ramp (slope compensation) to the current sense signal prevents this
oscillation. The 25 µA of offset current provided from the emulated current source adds the optimal slope
compensation to the ramp signal for a 5-V output. For higher output voltages, additional slope compensation may
be required. In these applications, a resistor is added between RAMP and VCC to increase the ramp slope
compensation.
SW
LO
RG
CS
RG
CSG
DEMB
RDEMB
Figure 8. RDS(ON) Current Sensing without Diode Emulation
The DC current sample is obtained using the CS and CSG pins connected to either a source sense resistor (RS)
or the RDS(ON) of the low-side MOSFET. For RDS(ON) sensing, RS = RDS(ON) of the low-side MOSFET. In this case
it is sometimes helpful to adjust the current sense amplifier gain (A) to a lower value in order to obtain the
desired current limit. Adding external resistors RG in series with CS and CSG, the current sense amplifier gain, A,
becomes:
A,
10k
1k + RG
(4)
Current Limit
The LM5116 contains a current limit monitoring scheme to protect the circuit from possible over-current
conditions. When set correctly, the emulated current sense signal is proportional to the buck switch current with a
scale factor determined by the current limit sense resistor. The emulated ramp signal is applied to the current
limit comparator. If the emulated ramp signal exceeds 1.6 V, the current cycle is terminated (cycle-by-cycle
current limiting). Since the ramp amplitude is proportional to VIN - VOUT, if VOUT is shorted, there is an immediate
reduction in duty cycle. To further protect the external switches during prolonged current limit conditions, an
internal counter counts clock pulses when in current limit. When the counter detects 256 consecutive clock
cycles, the regulator enters a low power dissipation hiccup mode of current limit. The regulator is shut down by
momentarily pulling UVLO low, and the soft-start capacitor discharged. The regulator is restarted with a full softstart cycle once UVLO charges back to 1.215 V. This process is repeated until the fault is removed. The hiccup
off-time can be controlled by a capacitor to ground on the UVLO pin. In applications with low output inductance
and high input voltage, the switch current may overshoot due to the propagation delay of the current limit
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comparator. If an overshoot should occur, the sample-and-hold circuit will detect the excess recirculating current.
If the sample-and-hold DC level exceeds the internal current limit threshold, the buck switch will be disabled and
skip pulses until the current has decayed below the current limit threshold. This approach prevents current
runaway conditions due to propagation delays or inductor saturation since the inductor current is forced to decay
following any current overshoot.
CURRENT SENSE
CURRENT LIMIT
COMPARATOR
AMPLIFIER
1.6V
-
10k
LO
1k
CS
RG
1k
CSG
RG
+
-RS
++
gm x (VIN - VOUT) + 25 PA
10k
IL
0.5V
HO
RAMP
A=
10k
1k + RG
CRAMP
Figure 9. Current Limit and Ramp Circuit
Using a current sense resistor in the source of the low-side MOSFET provides superior current limit accuracy
compared to RDS(ON) sensing. RDS(ON) sensing is far less accurate due to the large variation of MOSFET RDS(ON)
with temperature and part-to-part variation. The CS and CSG pins should be Kelvin connected to the current
sense resistor or MOSFET drain and source.
The peak current which triggers the current limit comparator is:
1.1V IPEAK =
25 PA x tON
CRAMP
A x RS
,
1.1V
A x RS
(5)
Where tON is the on-time of the high-side MOSFET. The 1.1-V threshold is the difference between the 1.6-V
reference at the current limit comparator and the 0.5-V offset at the current sense amplifier. This offset at the
current sense amplifier allows the inductor ripple current to go negative by 0.5 V / (A x RS) when running full
synchronous operation.
Current limit hysteresis prevents chatter around the threshold when VCCX is powered from VOUT. When 4.5 V <
VCC < 5.8 V, the 1.6-V reference is increased to 1.72 V. The peak current which triggers the current limit
comparator becomes:
1.22V IPEAK =
25 PA x tON
CRAMP
A x RS
,
1.22V
A x RS
(6)
This has the effect of a 10% fold-back of the peak current during a short circuit when VCCX is powered from a
5-V output.
Soft-Start and Diode Emulation
The soft-start feature allows the regulator to gradually reach the initial steady state operating point, thus reducing
start-up stresses and surges. The LM5116 will regulate the FB pin to the SS pin voltage or the internal 1.215-V
reference, whichever is lower. At the beginning of the soft-start sequence when SS = 0 V, the internal 10-µA softstart current source gradually increases the voltage of an external soft-start capacitor (CSS) connected to the SS
pin resulting in a gradual rise of FB and the output voltage.
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DIODE EMULATION
COMPARATOR
+
RS
RDEMB
SW
DEMB
1.215V
5V
40k
SS Latch
+
SS
-
Figure 10. Diode Emulation Control
During this initial charging of CSS to the internal reference voltage, the LM5116 will force diode emulation. That
is, the low-side MOSFET will turn off for the remainder of a cycle if the sensed inductor current becomes
negative. The inductor current is sensed by monitoring the voltage between SW and DEMB. As the SS capacitor
continues to charge beyond 1.215 V to 3 V, the DEMB bias current will increase from 0 µA up to 40 µA. With the
use of an external DEMB resistor (RDEMB), the current sense threshold for diode emulation will increase resulting
in the gradual transition to synchronous operation. Forcing diode emulation during soft-start allows the LM5116
to start up into a pre-biased output without unnecessarily discharging the output capacitor. Full synchronous
operation is obtained if the DEMB pin is always biased to a higher potential than the SW pin when LO is high.
RDEMB = 10 kΩ will bias the DEMB pin to 0.45 V minimum, which is adequate for most applications. The DEMB
bias potential should always be kept below 2 V. At very light loads with larger values of output inductance and
MOSFET capacitance, the switch voltage may fall slowly. If the SW voltage does not fall below the DEMB
threshold before the end of the HO fall to LO rise dead-time, switching will default to diode emulation mode.
When RDEMB = 0 Ω, the LM5116 will always run in diode emulation.
Once SS charges to 3 V the SS latch is set, increasing the DEMB bias current to 65 µA. An amplifier is enabled
that regulates SS to 160 mV above the FB voltage. This feature can prevent overshoot of the output voltage in
the event the output voltage momentarily dips out of regulation. When a fault is detected (VCC under-voltage,
UVLO pin < 1.215, or EN = 0 V) the soft-start capacitor is discharged. Once the fault condition is no longer
present, a new soft-start sequence begins.
HO Ouput
The LM5116 contains a high current, high-side driver and associated high voltage level shift. This gate driver
circuit works in conjunction with an external diode and bootstrap capacitor. A 1-µF ceramic capacitor, connected
with short traces between the HB pin and SW pin, is recommended. During the off-time of the high-side
MOSFET, the SW pin voltage is approximately -0.5 V and the bootstrap capacitor charges from VCC through the
external bootstrap diode. When operating with a high PWM duty cycle, the buck switch will be forced off each
cycle for 450 ns to ensure that the bootstrap capacitor is recharged.
The LO and HO outputs are controlled with an adaptive deadtime methodology which insures that both outputs
are never enabled at the same time. When the controller commands HO to be enabled, the adaptive block first
disables LO and waits for the LO voltage to drop below approximately 25% of VCC. HO is then enabled after a
small delay. Similarly, when HO turns off, LO waits until the SW voltage has fallen to ½ of VCC. LO is then
enabled after a small delay. In the event that SW does not fall within approximately 150 ns, LO is asserted high.
This methodology insures adequate dead-time for appropriately sized MOSFETs.
In some applications it may be desirable to slow down the high-side MOSFET turn-on time in order to control
switching spikes. This may be accomplished by adding a resistor is series with the HO output to the high-side
gate. Values greater than 10 Ω should be avoided so as not to interfere with the adaptive gate drive. Use of an
HB resistor for this function should be carefully evaluated so as not cause potentially harmful negative voltage to
the high-side driver, and is generally limited to 2.2 Ω maximum.
Thermal Protection
For high temperature applications in the ceramic dip package, the internal thermal shutdown circuitry is disabled.
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Application Information
EXTERNAL COMPONENTS
The procedure for calculating the external components is illustrated with the following design example. The Bill of
Materials for this design is listed in Table 1. The circuit shown in Figure 17 is configured for the following
specifications:
• Output voltage = 5 V
• Input voltage = 7 V to 60 V
• Maximum load current = 7 A
• Switching frequency = 250 kHz
Simplified equations are used as a general guideline for the design method. Comprehensive equations are
provided at the end of this section.
TIMING RESISTOR
RT sets the oscillator switching frequency. Generally, higher frequency applications are smaller but have higher
losses. Operation at 250 kHz was selected for this example as a reasonable compromise for both small size and
high efficiency. The value of RT for 250-kHz switching frequency can be calculated as follows:
1
- 450 ns
250 kHz
= 12.5 k:
RT =
284 pF
(7)
The nearest standard value of 12.4 kΩ was chosen for RT.
OUTPUT INDUCTOR
The inductor value is determined based on the operating frequency, load current, ripple current and the input and
output voltages.
IPP
IO
0
T=
1
fSW
Figure 11. Inductor Current
Knowing the switching frequency (fSW), maximum ripple current (IPP), maximum input voltage (VIN(MAX)) and the
nominal output voltage (VOUT), the inductor value can be calculated:
L=
VOUT
IPP x fSW
x 1-
VOUT
VIN(MAX)
(8)
The maximum ripple current occurs at the maximum input voltage. Typically, IPP is 20% to 40% of the full load
current. When running diode emulation mode, the maximum ripple current should be less than twice the
minimum load current. For full synchronous operation, higher ripple current is acceptable. Higher ripple current
allows for a smaller inductor size, but places more of a burden on the output capacitor to smooth the ripple
current for low output ripple voltage. For this example, 40% ripple current was chosen for a smaller sized
inductor.
L=
5V
0.4 x 7A x 250kHz
x 1-
5V
= 6.5 PH
60V
(9)
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The nearest standard value of 6 µH will be used. The inductor must be rated for the peak current to prevent
saturation. During normal operation, the peak current occurs at maximum load current plus maximum ripple.
During overload conditions with properly scaled component values, the peak current is limited to VCS(TH) / RS
(See next section). At the maximum input voltage with a shorted output, the valley current must fall below VCS(TH)
/ RS before the high-side MOSFET is allowed to turn on. The peak current in steady state will increase to VIN(MAX)
x tON(min) / L above this level. The chosen inductor must be evaluated for this condition, especially at elevated
temperature where the saturation current rating may drop significantly.
CURRENT SENSE RESISTOR
The current limit is set by the current sense resistor value (RS).
ILIM =
VCS(TH)
RS
(10)
For a 5-V output, the maximum current sense signal occurs at the minimum input voltage, so RS is calculated
from:
VCS(TH)
RS d
IO +
VOUT
2 x L x fSW
x 1+
VOUT
VIN(MIN)
(11)
For this example VCCX = 0 V, so VCS(TH) = 0.11 V. The current sense resistor is calculated as:
RS d
0.11V
d 0.011:
5V
5V
x 1+
7A +
7V
2 x 6 PH x 250 kHz
(12)
The next lowest standard value of 10 mΩ was chosen for RS.
RAMP CAPACITOR
With the inductor and sense resistor value selected, the value of the ramp capacitor (CRAMP) necessary for the
emulation ramp circuit is:
CRAMP ,
gm x L
A x RS
(13)
Where L is the value of the output inductor in Henrys, gm is the ramp generator transconductance (5 µA/V), and
A is the current sense amplifier gain (10 V/V). For the 5-V output design example, the ramp capacitor is
calculated as:
CRAMP =
5 PA/V x 6 PH
10V/V x 10 m:
= 300 pF
(14)
The next lowest standard value of 270 pF was selected for CRAMP. A COG type capacitor with 5% or better
tolerance is recommended.
OUTPUT CAPACITORS
The output capacitors smooth the inductor ripple current and provide a source of charge for transient loading
conditions. For this design example, five 100-µF ceramic capacitors where selected. Ceramic capacitors provide
very low equivalent series resistance (ESR), but can exhibit a significant reduction in capacitance with DC bias.
From the manufacturer’s data, the ESR at 250 kHz is 2 mΩ / 5 = 0.4 mΩ, with a 36% reduction in capacitance at
5 V. This is verified by measuring the output ripple voltage and frequency response of the circuit. The
fundamental component of the output ripple voltage is calculated as:
'VOUT = IPP x
ESR2 +
1
8 x fSW x COUT
2
(15)
With typical values for the 5-V design example:
'VOUT = 3A x 0.4 m:2 +
1
8 x 250 kHz x 320 PF
2
'VOUT = 4.8 mV
20
(16)
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INPUT CAPACITORS
The regulator supply voltage has a large source impedance at the switching frequency. Good quality input
capacitors are necessary to limit the ripple voltage at the VIN pin while supplying most of the switch current
during the on-time. When the buck switch turns on, the current into the switch steps to the valley of the inductor
current waveform, ramps up to the peak value, and then drops to zero at turn-off. The input capacitors should be
selected for RMS current rating and minimum ripple voltage. A good approximation for the required ripple current
rating is IRMS > IOUT / 2.
Quality ceramic capacitors with a low ESR were selected for the input filter. To allow for capacitor tolerances and
voltage rating, four 2.2-µF, 100-V ceramic capacitors were used for the typical application circuit. With ceramic
capacitors, the input ripple voltage will be triangular and peak at 50% duty cycle. Taking into account the
capacitance change with DC bias, the input ripple voltage is approximated as:
'VIN =
IOUT
4 x fSW x CIN
=
7A
4 x 250 kHz x 7 PF
= 1V
(17)
When the converter is connected to an input power source, a resonant circuit is formed by the line impedance
and the input capacitors. If step input voltage transients are expected near the maximum rating of the LM5116, a
careful evaluation of the ringing and possible overshoot at the device VIN pin should be completed. To minimize
overshoot make CIN > 10 x LIN. The characteristic source impedance and resonant frequency are:
ZS =
LIN
CIN
fS =
1
2S LIN x CIN
(18)
The converter exhibits a negative input impedance which is lowest at the minimum input voltage:
ZIN = -
VIN2
POUT
(19)
The damping factor for the input filter is given by:
G=
1
2
RIN + ESR
ZS
+
ZS
ZIN
(20)
Where RIN is the input wiring resistance and ESR is the series resistance of the input capacitors. The term ZS /
ZIN will always be negative due to ZIN.
When δ = 1, the input filter is critically damped. This may be difficult to achieve with practical component values.
With δ < 0.2, the input filter will exhibit significant ringing. If δ is zero or negative, there is not enough resistance
in the circuit and the input filter will sustain an oscillation. When operating near the minimum input voltage, an
aluminum electrolytic capacitor across CIN may be needed to damp the input for a typical bench test setup. Any
parallel capacitor should be evaluated for its RMS current rating. The current will split between the ceramic and
aluminum capacitors based on the relative impedance at the switching frequency.
VCC CAPACITOR
The primary purpose of the VCC capacitor (CVCC) is to supply the peak transient currents of the LO driver and
bootstrap diode (D1) as well as provide stability for the VCC regulator. These current peaks can be several
amperes. The recommended value of CVCC should be no smaller than 0.47 µF, and should be a good quality, low
ESR, ceramic capacitor located at the pins of the IC to minimize potentially damaging voltage transients caused
by trace inductance. A value of 1 µF was selected for this design.
BOOTSTRAP CAPACITOR
The bootstrap capacitor (CHB) between the HB and SW pins supplies the gate current to charge the high-side
MOSFET gate at each cycle’s turn-on as well as supplying the recovery charge for the bootstrap diode (D1).
These current peaks can be several amperes. The recommended value of the bootstrap capacitor is at least
0.1 µF, and should be a good quality, low ESR, ceramic capacitor located at the pins of the IC to minimize
potentially damaging voltage transients caused by trace inductance. The absolute minimum value for the
bootstrap capacitor is calculated as:
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Qg
CHB t
'VHB
(21)
Where Qg is the high-side MOSFET gate charge and ΔVHB is the tolerable voltage droop on CHB, which is
typically less than 5% of VCC. A value of 1 µF was selected for this design.
SOFT START CAPACITOR
The capacitor at the SS pin (CSS) determines the soft-start time, which is the time for the reference voltage and
the output voltage to reach the final regulated value. The soft-start time tSS should be substantially longer than
the time required to charge COUT to VOUT at the maximum output current. To meet this requirement:
tSS > VOUT x COUT / (ICURRENT LIMIT – IOUT)
(22)
The value of CSS for a given time is determined from:
CSS =
tSS x 10 PA
(23)
1.215V
For this application, a value of 0.01 µF was chosen for a soft-start time of 1.2 ms.
OUTPUT VOLTAGE DIVIDER
RFB1 and RFB2 set the output voltage level, the ratio of these resistors is calculated from:
VOUT
RFB2
-1
=
RFB1 1.215V
(24)
RFB1 is typically 1.21 kΩ for a divider current of 1 mA. The divider current can be reduced to 100 µA with
RFB1=12.1 kΩ. For the 5-V output design example used here, RFB1 = 1.21 kΩ and RFB2 = 3.74 kΩ.
UVLO DIVIDER
A voltage divider and filter can be connected to the UVLO pin to set a minimum operating voltage VIN(MIN) for the
regulator. If this feature is required, the following procedure can be used to determine appropriate resistor values
for RUV2, RUV1 and CFT.
1. RUV2 must be large enough such that in the event of a current limit, the internal UVLO switch can pull UVLO
< 200 mV. This can be guaranteed if:RUV2 > 500 x VIN(MAX)Where VIN(MAX) is the maximum input voltage and
RUV2 is in ohms.
2. With
an
appropriate
value
for
RUV2,
RUV1
can
be
selected
using
the
following
RUV1 = 1.215 x
RUV2
VIN(MIN) + (5 PA x RUV2) - 1.215
equation:
Where VIN(MIN) is the desired shutdown voltage.
3. Capacitor CFT provides filtering for the divider and determines the off-time of the “hiccup” duty cycle during
current limit. When CFT is used in conjunction with the voltage divider, a diode across the top resistor should
be
used
to
discharge
CFT
in
the
event
of
an
input
under-voltage
tOFF = -
condition.
RUV1 x RUV2
RUV1 + RUV2
x CFT x ln 1 -
1.215 x (RUV1 + RUV2)
VIN x RUV1
If under-voltage shutdown is not required, RUV1 and RUV2 can be eliminated and the off-time becomes:
tOFF = CFT x
1.215V
5 PA
(25)
The voltage at the UVLO pin should never exceed 16V when using an external set-point divider. It may be
necessary to clamp the UVLO pin at high input voltages. For the design example, RUV2 = 102 kΩ and
RUV1 = 21 kΩ for a shut-down voltage of 6.6 V. If sustained short circuit protection is required, CFT ≥ 1 µF will
limit the short circuit power dissipation. D2 may be installed when using CFT with RUV1 and RUV2.
MOSFETs
Selection of the power MOSFETs is governed by the same tradeoffs as switching frequency. Breaking down the
losses in the high-side and low-side MOSFETs is one way to determine relative efficiencies between different
devices. When using discrete SO-8 MOSFETs the LM5116 is most efficient for output currents of 2 A to 10 A.
Losses in the power MOSFETs can be broken down into conduction loss, gate charging loss, and switching loss.
Conduction, or I2R loss PDC, is approximately:
22
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PDC(HO-MOSFET) = D x (IO2 x RDS(ON) x 1.3)
PDC(LO-MOSFET) = (1 - D) x (IO2 x RDS(ON) x 1.3)
(26)
(27)
Where D is the duty cycle. The factor 1.3 accounts for the increase in MOSFET on-resistance due to heating.
Alternatively, the factor of 1.3 can be ignored and the on-resistance of the MOSFET can be estimated using the
RDS(ON) vs Temperature curves in the MOSFET datasheet. Gate charging loss, PGC, results from the current
driving the gate capacitance of the power MOSFETs and is approximated as:
PGC = n x VCC x Qg x fSW
(28)
Qg refer to the total gate charge of an individual MOSFET, and ‘n’ is the number of MOSFETs. If different types
of MOSFETs are used, the ‘n’ term can be ignored and their gate charges summed to form a cumulative Qg.
Gate charge loss differs from conduction and switching losses in that the actual dissipation occurs in the LM5116
and not in the MOSFET itself. Further loss in the LM5116 is incurred as the gate driving current is supplied by
the internal linear regulator. The gate drive current supplied by the VCC regulator is calculated as:
IGC =(Qgh + Qgl) x fSW
(29)
Where Qgh + Qgl represent the gate charge of the HO and LO MOSFETs at VGS = VCC. To ensure start-up, IGC
should be less than the VCC current limit rating of 15 mA minimum when powered by the internal 7.4-V
regulator. Failure to observe this rating may result in excessive MOSFET heating and potential damage. The IGC
run current may exceed 15 mA when VCC is powered by VCCX.
PSW = 0.5 x VIN x IO x (tR + tF) x fSW
(30)
Where tR and tF are the rise and fall times of the MOSFET. Switching loss is calculated for the high-side
MOSFET only. Switching loss in the low-side MOSFET is negligible because the body diode of the low-side
MOSFET turns on before the MOSFET itself, minimizing the voltage from drain to source before turn-on. For this
example, the maximum drain-to-source voltage applied to either MOSFET is 60 V. VCC provides the drive
voltage at the gate of the MOSFETs. The selected MOSFETs must be able to withstand 60 V plus any ringing
from drain to source, and be able to handle at least VCC plus ringing from gate to source. A good choice of
MOSFET for the 60-V input design example is the Si7850DP. It has an RDS(ON) of 20 mΩ, total gate charge of 14
nC, and rise and fall times of 10 ns and 12 ns respectively. In applications where a high step-down ratio is
maintained for normal operation, efficiency may be optimized by choosing a high-side MOSFET with lower Qg,
and low-side MOSFET with lower RDS(ON).
For higher voltage MOSFETs which are not true logic level, it is important to use the UVLO feature. Choose a
minimum operating voltage which is high enough for VCC and the bootstrap (HB) supply to fully enhance the
MOSFET gates. This will prevent operation in the linear region during power-on or power-off which can result in
MOSFET failure. Similar consideration must be made when powering VCCX from the output voltage. For the
high-side MOSFET, the gate threshold should be considered and careful evaluation made if the gate threshold
voltage exceeds the HO driver UVLO.
MOSFET SNUBBER
A resistor-capacitor snubber network across the low-side MOSFET reduces ringing and spikes at the switching
node. Excessive ringing and spikes can cause erratic operation and couple spikes and noise to the output.
Selecting the values for the snubber is best accomplished through empirical methods. First, make sure the lead
lengths for the snubber connections are very short. Start with a resistor value between 5 Ω and 50 Ω. Increasing
the value of the snubber capacitor results in more damping, but higher snubber losses. Select a minimum value
for the snubber capacitor that provides adequate damping of the spikes on the switch waveform at high load.
ERROR AMPLIFIER COMPENSATION
RCOMP, CCOMP and CHF configure the error amplifier gain characteristics to accomplish a stable voltage loop gain.
One advantage of current mode control is the ability to close the loop with only two feedback components, RCOMP
and CCOMP. The voltage loop gain is the product of the modulator gain and the error amplifier gain. For the 5-V
output design example, the modulator is treated as an ideal voltage-to-current converter. The DC modulator gain
of the LM5116 can be modeled as:
DC Gain(MOD) = RLOAD / (A x RS)
(31)
The dominant low frequency pole of the modulator is determined by the load resistance (RLOAD) and output
capacitance (COUT). The corner frequency of this pole is:
fP(MOD) = 1 / (2π x RLOAD x COUT)
(32)
For RLOAD = 5 V / 7 A = 0.714 Ω and COUT = 320 µF (effective) then fP(MOD) = 700 Hz
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DC Gain(MOD) = 0.714 Ω / (10 x 10 mΩ) = 7.14 = 17 dB
For the 5-V design example the modulator gain vs. frequency characteristic was measured as shown in
Figure 12.
Figure 12. Modulator Gain and Phase
Components RCOMP and CCOMP configure the error amplifier as a type II configuration. The DC gain of the
amplifier is 80 dB which has a pole at low frequency and a zero at fZEA = 1 / (2π x RCOMP x CCOMP). The error
amplifier zero cancels the modulator pole leaving a single pole response at the crossover frequency of the
voltage loop. A single pole response at the crossover frequency yields a very stable loop with 90° of phase
margin. For the design example, a target loop bandwidth (crossover frequency) of one-tenth the switching
frequency or 25 kHz was selected. The compensation network zero (fZEA) should be selected at least an order of
magnitude less than the target crossover frequency. This constrains the product of RCOMP and CCOMP for a
desired compensation network zero 1 / (2π x RCOMP x CCOMP) to be 2.5 kHz. Increasing RCOMP, while
proportionally decreasing CCOMP, increases the error amp gain. Conversely, decreasing RCOMP while
proportionally increasing CCOMP, decreases the error amp gain. For the design example CCOMP was selected as
3300 pF and RCOMP was selected as 18 kΩ. These values configure the compensation network zero at 2.7 kHz.
The error amp gain at frequencies greater than fZEA is: RCOMP / RFB2, which is approximately 4.8 (13.6 dB).
Figure 13. Error Amplifier Gain and Phase
The overall voltage loop gain can be predicted as the sum (in dB) of the modulator gain and the error amp gain.
24
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Figure 14. Overall Voltage Loop Gain and Phase
If a network analyzer is available, the modulator gain can be measured and the error amplifier gain can be
configured for the desired loop transfer function. If a network analyzer is not available, the error amplifier
compensation components can be designed with the guidelines given. Step load transient tests can be
performed to verify acceptable performance. The step load goal is minimum overshoot with a damped response.
CHF can be added to the compensation network to decrease noise susceptibility of the error amplifier. The value
of CHF must be sufficiently small since the addition of this capacitor adds a pole in the error amplifier transfer
function. This pole must be well beyond the loop crossover frequency. A good approximation of the location of
the pole added by CHF is: fP2 = fZEA x CCOMP / CHF. The value of CHF was selected as 100 pF for the design
example.
PCB LAYOUT AND THERMAL CONSIDERATIONS
In a buck regulator the primary switching loop consists of the input capacitor, MOSFETs and current sense
resistor. Minimizing the area of this loop reduces the stray inductance and minimizes noise and possible erratic
operation. The input capacitor should be placed as close as possible to the MOSFETs, with the VIN side of the
capacitor connected directly to the high-side MOSFET drain, and the GND side of the capacitor connected as
close as possible to the low-side source or current sense resistor ground connection. A ground plane in the PC
board is recommended as a means to connect the quiet end (input voltage ground side) of the input filter
capacitors to the output filter capacitors and the PGND pin of the regulator. Connect all of the low power ground
connections (CSS, RT, CRAMP) directly to the regulator AGND pin. Connect the AGND and PGND pins together
through to a topside copper area covering the entire underside of the device. Place several vias in this underside
copper area to the ground plane.
The highest power dissipating components are the two power MOSFETs. The easiest way to determine the
power dissipated in the MOSFETs is to measure the total conversion losses (PIN - POUT), then subtract the power
losses in the output inductor and any snubber resistors. The resulting power losses are primarily in the switching
MOSFETs.
If a snubber is used, the power loss can be estimated with an oscilloscope by observation of the resistor voltage
drop at both turn-on and turn-off transitions. Assuming that the RC time constant is 7.5 V, install a resistor from the RAMP pin to VCC.
RRAMP =
VCC - VRAMP
IOS - 25 PA
(40)
VCC
RRAMP
RAMP
CRAMP
Figure 15. RRAMP to VCC for VOUT > 7.5 V
For VOUT < 7.5 V, a negative VCC is required. This can be made with a simple charge pump from the LO gate
output. Install a resistor from the RAMP pin to the negative VCC.
RRAMP =
26
VCC ± 0.5V + VRAMP
25 PA - IOS
(41)
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LO
10 nF
1N914
RRAMP
10 nF
RAMP
-VCC
CRAMP
Figure 16. RRAMP to -VCC for VOUT < 7.5 V
If a large variation is expected in VCC, say for VIN < 11 V, a Zener regulator may be added to supply a constant
voltage for RRAMP.
MODULATOR TRANSFER FUNCTION
The following equations can be used to calculate the control-to-output transfer function:
VOUT
VCOMP
Km =
=
RLOAD
x
A x RS
1+
1+
Km x A x RS
s
ZP
s
ZZ
x 1+
s
s2
+
Zn x Q
Zn2
(42)
1
(D ± 0.5) x A x RS x T
gm x T
KSL =
Se =
x
RLOAD
L
ZZ =
1+
1
VSL =
CRAMP
1
COUT x ESR
+ (1 - 2 x D) x KSL +
CRAMP
(44)
1
x
+
ZP =
COUT RLOAD Km x A x RS
1
1
T
Se
Sn =
Q=
Sn
(43)
IOS x T
(VIN ± VOUT) x KSL + VSL
mC =
VSL
VIN
S
Zn =
T
(45)
VIN x A x RS
L
1
S x (mC ± 0.5)
(46)
Km is the effective DC gain of the modulating comparator. The duty cycle D = VOUT / VIN. KSL is the proportional
slope compensation term. VSL is the fixed slope compensation term. Slope compensation is set by mc, which is
the ratio of the external ramp to the natural ramp. The switching frequency sampling gain is characterized by ωn
and Q, which accounts for the high frequency inductor pole.
For VSL without RRAMP, use IOS = 25 µA
For VSL with RRAMP to VCC, use IOS = 25 µA + VCC/RRAMP
For VSL with RRAMP to -VCC, use IOS = 25 µA - VCC/RRAMP
ERROR AMPLIFIER TRANSFER FUNCTION
The following equations are used to calculate the error amplifier transfer function:
VCOMP
VOUT(FB)
1
= -GEA(S) x
1+
GEA(S) =
GEA(S)
1
s
1+
+
x 1+
KFB
AOL ZBW
s
ZZEA
s
s
x 1+ Z
HF
ZO
KFB =
(47)
RFB1
RFB1 + RFB2
(48)
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ZZEA =
1
CCOMP x RCOMP
ZHF =
ZO =
www.ti.com
1
(CHF + CCOMP) x RFB2
(CHF + CCOMP)
CHF x CCOMP x RCOMP
(49)
Where AOL = 10,000 (80 dB) and ωBW = 2π x fBW. GEA(S) is the ideal error amplifier gain, which is modified at DC
and high frequency by the open loop gain of the amplifier and the feedback divider ratio.
Figure 17. 5-V 7-A Typical Application Schematic
Table 1. Bill of Materials for 7-V - 60-V Input, 5-V 7-A Output, 250 kHz
ID
Part Number
Type
Size
Parameters
Qty
C1, C2, C14
C2012X7R1E105K
Capacitor, Ceramic
0805
1µF, 25V, X7R
3
Vendor
TDK
C3
VJ0603Y103KXAAT
Capacitor, Ceramic
0603
0.01µF, 50V, X7R
1
Vishay
C4
VJ0603A271JXAAT
Capacitor, Ceramic
0603
270pF, 50V, COG, 5%
1
Vishay
C5, C15
VJ0603Y101KXAT
W1BC
Capacitor, Ceramic
0603
100pF, 50V, X7R
2
Vishay
C6
VJ0603Y332KXXAT
Capacitor, Ceramic
0603
3300pF, 25V, X7R
1
Vishay
Capacitor, Ceramic
0603
Not Used
0
C8, C9, C10,
C11
C7
C4532X7R2A225M
Capacitor, Ceramic
1812
2.2µF, 100V X7R
4
TDK
C12
C3225X7R2A105M
Capacitor, Ceramic
1210
1µF, 100V X7R
1
TDK
C13
C2012X7R2A104M
Capacitor, Ceramic
0805
0.1µF, 100V X7R
1
TDK
C16, C17, C18,
C19, C20
C4532X6S0J107M
Capacitor, Ceramic
1812
100µF, 6.3V, X6S, 105°C
5
TDK
C21, C22
Capacitor, Tantalum
D Case
Not Used
0
C23
Capacitor, Ceramic
0805
Not Used
0
28
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Table 1. Bill of Materials for 7-V - 60-V Input, 5-V 7-A Output, 250 kHz (continued)
ID
Part Number
Type
Size
Parameters
Qty
Vendor
D1
CMPD2003
Diode, Switching
SOT-23
200mA, 200V
1
Central
Semi
D2
CMPD2003
Diode, Switching
SOT-23
Not Used
0
Central
Semi
JMP1
Connector, Jumper
2 pin sq. post
1
L1
HC2LP-6R0
Inductor
6µH, 16.5A
1
Cooper
P1-P4
1514-2
Turret Terminal
.090” dia.
4
Keystone
TP1-TP5
5012
Test Point
.040” dia.
5
Keystone
Q1, Q2
Si7850DP
N-CH MOSFET
SO-8 Power PAK
10.3A, 60V
2
Vishay
Siliconix
R1
CRCW06031023F
Resistor
0603
102kΩ, 1%
1
Vishay
R2
CRCW06032102F
Resistor
0603
21.0kΩ, 1%
1
Vishay
R3
CRCW06033741F
Resistor
0603
3.74kΩ, 1%
1
Vishay
R4
CRCW06031211F
Resistor
0603
1.21kΩ, 1%
1
Vishay
Resistor
0603
Not Used
0
R6, R7
R5
CRCW06030R0J
Resistor
0603
0Ω
2
Vishay
R8
CRCW0603103J
Resistor
0603
10kΩ, 5%
1
Vishay
R9
CRCW06031242F
Resistor
0603
12.4kΩ, 1%
1
Vishay
R10
CRCW0603183J
Resistor
0603
18kΩ, 5%
1
Vishay
R11
LRC-LRF2010-01R010-F
Resistor
2010
0.010Ω, 1%
1
IRC
Resistor
0603
Not Used
0
Resistor
0603
1MΩ, 5%
1
Resistor
1206
Not Used
0
Synchronous Buck
Controller
TSSOP-20EP
R12
R13
CRCW0603105J
R14
U1
LM5116MHX
1
Vishay
NSC
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REVISION HISTORY
Changes from Revision A (October 2013) to Revision B
•
30
Page
Changed EN Input Electrical Characteristics ........................................................................................................................ 5
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Changes from Original (Octoer 2013) to Revision A
•
Page
Changed Operating Life Derating Chart ............................................................................................................................... 7
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PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
(4/5)
(6)
LM5116HJD
ACTIVE
CDIP SB
JD
20
18
RoHS & Green
AU
Level-1-260C-UNLIM
-55 to 175
LM5116HJD
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of
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