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LM5121, LM5121-Q1
SNVS963C – SEPTEMBER 2013 – REVISED JUNE 2016
LM5121/-Q1 Wide Input Synchronous Boost Controller with Disconnection Switch Control
1 Features
2 Applications
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AEC-Q100 Qualified with the following results:
– Device Temperature Grade 1: -40°C to +125°C
Ambient Operating Temperature Range
– Device HBM ESD Classification Level 2
– Device CDM ESD Classification Level C6
Maximum Input Voltage: 65 V
Min Input Voltage: 3.0 V (4.5 V for startup)
Output Voltage Up to 100 V
Bypass (VOUT = VIN) Operation
1.2-V Reference with ±1.0% Accuracy
Free-Run/Synchronizable up to 1 MHz
Peak Current Mode Control
Robust Integrated 3-A Gate Drivers
Adaptive Dead-Time Control
Optional Diode Emulation Mode
Programmable Cycle-by-Cycle Current Limit
Programmable Line UVLO
Programmable Soft-Start
Thermal Shutdown Protection
Low Shutdown Quiescent Current: 9 μA
Programmable Slope Compensation
Programmable Skip Cycle Mode Reduces
Standby Power
Supports External VCC Bias Supply Option
Load Disconnection in Shutdown Mode (True
Shutdown)
Inrush Current Limiting
Hiccup Mode Short Circuit/Overload Protection
Circuit Breaker Function
Capable of Input Transient Suppression
Capable of Reverse Battery Protection
Thermally Enhanced 20-Pin HTSSOP
12-V, 24-V, and 48-V Power Systems
Automotive Start-Stop
High Current Boost Power Supply
Battery Powered System
3 Description
The LM5121 is a synchronous boost controller
intended for high-efficiency, high-power boost
regulator applications. The control method is based
upon peak current mode control. Current mode
control provides inherent line feed-forward, cycle-bycycle current limiting and ease of loop compensation.
The switching frequency is programmable up to 1
MHz. Higher efficiency is achieved using two robust
N-channel MOSFET gate drivers with adaptive deadtime control. A user-selectable diode emulation mode
enables discontinuous mode operation for improved
efficiency at light load conditions.
The LM5121 provides disconnection switch control
which completely disconnects the output from the
input during an output short or a shutdown condition.
During start-up sequence, inrush current is limited by
the disconnection switch control.
An internal charge pump allows 100% duty cycle
operation of the high-side synchronous switch
(Bypass operation). Additional features include
thermal shutdown, frequency synchronization, hiccup
mode current limit and adjustable line undervoltage
lockout.
Device Information(1)
PART NUMBER
LM5121
LM5121-Q1
PACKAGE
BODY SIZE (NOM)
HTSSOP (20)
6.50 mm x 4.40 mm
(1) For all available packages, see the orderable addendum at
the end of the datasheet.
Simplified Application Diagram
VIN
VOUT
+
VCC
DS
BST
DG
CSN
CSP
VIN
UVLO
SLOPE
SYNCIN/RT
LM5121
SW
LO
HO
COMP
FB
RES
SS
MODE
PGND
AGND
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
LM5121, LM5121-Q1
SNVS963C – SEPTEMBER 2013 – REVISED JUNE 2016
www.ti.com
Table of Contents
1
2
3
4
5
6
7
Features ..................................................................
Applications ...........................................................
Description .............................................................
Revision History.....................................................
Pin Configuration and Functions .........................
Specifications.........................................................
1
1
1
2
3
4
6.1
6.2
6.3
6.4
6.5
6.6
6.7
4
5
5
5
5
6
9
Absolute Maximum Ratings ......................................
ESD Ratings: LM5121 ..............................................
ESD Ratings: LM5121-Q1 ........................................
Recommended Operating Conditions.......................
Thermal Information ..................................................
Electrical Characteristics...........................................
Typical Characteristics ..............................................
Detailed Description ............................................ 12
7.1 Overview ................................................................. 12
7.2 Functional Block Diagram ....................................... 12
7.3 Feature Description................................................. 13
7.4 Device Functional Modes........................................ 21
8
Application and Implementation ........................ 24
8.1 Application Information............................................ 24
8.2 Typical Application .................................................. 32
9 Power Supply Recommendations...................... 40
10 Layout................................................................... 40
10.1 Layout Guidelines ................................................. 40
10.2 Layout Example .................................................... 40
11 Device and Documentation Support ................. 41
11.1
11.2
11.3
11.4
11.5
11.6
Related Links ........................................................
Receiving Notification of Documentation Updates
Community Resources..........................................
Trademarks ...........................................................
Electrostatic Discharge Caution ............................
Glossary ................................................................
41
41
41
41
41
41
12 Mechanical, Packaging, and Orderable
Information ........................................................... 41
4 Revision History
Changes from Revision B (December 2014) to Revision C
Page
•
Added Automotive ESD Features........................................................................................................................................... 1
•
Changed equation ............................................................................................................................................................... 20
Changes from Revision A (September 2013) to Revision B
•
2
Page
Added Pin Configuration and Functions section, Handling Rating table, Feature Description section, Device
Functional Modes, Application and Implementation section, Power Supply Recommendations section, Layout
section, Device and Documentation Support section, and Mechanical, Packaging, and Orderable Information
section ................................................................................................................................................................................... 1
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SNVS963C – SEPTEMBER 2013 – REVISED JUNE 2016
5 Pin Configuration and Functions
HTSSOP
PWP Package
TOP VIEW
DS
1
20
BST
DG
2
19
HO
CSN
3
18
SW
CSP
4
17
VCC
VIN
5
16
LO
EP
UVLO
6
15
PGND
SS
7
14
RES
SYNCIN/RT
8
13
MODE
AGND
9
12
SLOPE
FB
10
11
COMP
Pin Functions
PIN
I/O (1)
DESCRIPTION
NAME
NO.
AGND
9
G
Analog ground connection. Return for the internal voltage reference and analog circuits.
BST
20
P/I
High-side driver supply for bootstrap gate drive. Connect to the cathode of the external bootstrap
diode and to the bootstrap capacitor. The bootstrap capacitor supplies current to charge the highside N-channel MOSFET gate and should be placed as close to controller as possible. An internal
BST charge pump will supply 200 µA current into bootstrap capacitor for bypass operation.
COMP
11
O
Output of the internal error amplifier. The loop compensation network should be connected between
this pin and the FB pin.
CSN
3
I
Inverting input of current sense amplifier. Connect to the negative-side of the current sense resistor.
CSP
4
I
Non-inverting input of current sense amplifier. Connect to the positive-side of the current sense
resistor.
DG
2
O
Disconnection switch control pin. Connect to the gate terminal of the N-channel MOSFET
disconnection switch.
DS
1
I/O
Source connection of N-channel MOSFET disconnection switch. Connect to the source terminal of
the disconnection switch, the cathode terminal of the freewheeling diode and the supply input of
boost inductor.
EP
EP
N/A
Exposed pad of the package. No internal electrical connections. Should be soldered to the large
ground plane to reduce thermal resistance.
FB
10
I
Feedback. Inverting input of the internal error amplifier. A resistor divider from the output to this pin
sets the output voltage level. The regulation threshold at the FB pin is 1.2 V.
HO
19
O
High-side N-channel MOSFET gate drive output. Connect to the gate of the high-side synchronous
N-channel MOSFET switch through a short, low inductance path.
LO
16
O
Low-side N-channel MOSFET gate drive output. Connect to the gate of the low-side N-channel
MOSFET switch through a short, low inductance path.
I
Switching mode selection pin. Internal 700 kΩ pull-up and 100 kΩ pull-down resistor hold MODE pin
to 0.15 V as a default. By adding external pull-up or pull-down resistor, MODE pin voltage can be
programmed. When MODE pin voltage is greater than 1.2 V, diode emulation mode threshold,
forced PWM mode is enabled, allowing current to flow in either direction through the high-side Nchannel MOSFET switch. When MODE pin voltage is less than 1.2 V, the controller works in diode
emulation mode. Skip cycle comparator is activated as a default condition when the MODE pin is
left floating. If the MODE pin is grounded, the controller still operates in diode emulation mode, but
the skip cycle comparator will not be triggered in normal operation, this enables pulse skipping
operation at light load.
MODE
(1)
13
G = Ground, I = Input, O = Output, P = Power
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SNVS963C – SEPTEMBER 2013 – REVISED JUNE 2016
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Pin Functions (continued)
PIN
I/O (1)
DESCRIPTION
NAME
NO.
PGND
15
G
Power ground connection pin for low-side N-channel MOSFET gate driver. Connect directly to the
source terminal of the low-side N-channel MOSFET switch.
RES
14
O
The restart timer pin for an external capacitor that configures hiccup mode off-time and restart delay
during over load conditions and hiccup mode short circuit protection. Connect directly to the AGND
when hiccup mode operation is not required.
SLOPE
12
I
Slope compensation is programmed by an external resistor between SLOPE and the AGND.
SS
7
I
Soft-start programming pin. An external capacitor and an internal 10 μA current source set the ramp
rate of the internal error amplifier reference during soft-start.
SW
18
I/O
Switching node of the boost regulator. Connect to the bootstrap capacitor, the source terminal of the
high-side N-channel MOSFET switch and the drain terminal of the low-side N-channel MOSFET
switch through short, low inductance paths.
SYNCIN/RT
8
I
The internal oscillator frequency is programmed by an external resistor between RT and the AGND.
The internal oscillator can be synchronized to an external clock by applying a positive pulse signal
into this pin. The recommended maximum internal oscillator frequency is 2 MHz which leads to 1
MHz maximum switching frequency.
UVLO
6
I
Undervoltage lockout programming pin. If the UVLO pin is below 0.4 V, the regulator is in the
shutdown mode with all functions disabled. If the UVLO pin voltage is greater than 0.4 V and below
1.2 V, the regulator is in standby mode with the VCC regulator operational and no switching at the
HO and LO outputs. If the UVLO pin voltage is above 1.2 V, the startup sequence begins. A 10 μA
current source at UVLO pin is enabled when UVLO exceeds 1.2 V and flows through the external
UVLO resistors to provide hysteresis. The UVLO pin should not be left floating.
VCC
17
P/O/I
VCC bias supply pin. Locally decouple to PGND using a low ESR/ESL capacitor located as close to
controller as possible.
VIN
5
P/I
Supply voltage input source for the VCC regulator. Connect to the input capacitor and source power
supply connection with short, low impedance paths.
6 Specifications
6.1 Absolute Maximum Ratings (1)
Over operating free-air temperature range (unless otherwise noted)
MIN
MAX
VIN, CSP, CSN
–0.3
75
BST to SW, FB, MODE, UVLO, VCC (2)
–0.3
15
SW
–5.0
105
BST
–0.3
115
SS, SLOPE, SYNCIN/RT
–0.3
7
CSP to CSN, PGND
–0.3
0.3
DG to DS
–3.0
18
DG to VIN
–75
15
DS
–3.0
75
HO to SW
–0.3
BST to SW+0.3
LO
–0.3
VCC+0.3
COMP, RES
–0.3
7
Thermal
Junction Temperature
–40
150
ºC
Tstg
Storage temperature range
–55
150
°C
Input
Output (3)
(1)
(2)
(3)
4
UNIT
V
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating
Conditions are not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. Unless
otherwise specified, all voltages are referenced to AGND pin.
See Application Information when input supply voltage is less than the VCC voltage.
All output pins are not specified to have an external voltage applied.
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SNVS963C – SEPTEMBER 2013 – REVISED JUNE 2016
6.2 ESD Ratings: LM5121
VALUE
Human body model (HBM), per ANSI/ESDA/JEDEC JS-001
V(ESD)
Electrostatic discharge
(1)
±2
Charged device model (CDM), per JEDED specification JESD22-C101
kV
±1
(2)
(1)
(2)
UNIT
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
6.3 ESD Ratings: LM5121-Q1
VALUE
Human body model (HBM), per AEC Q100-002 (1)
V(ESD)
(1)
Electrostatic discharge
Charged device model (CDM), per AEC
Q100-011
UNIT
±2
Corner pins
kV
±1
Other pins
AEC Q100-002 indicates HBM stressing is done in accordance with the ANSI/ESDA/JEDEC JS-001 specification.
6.4 Recommended Operating Conditions (1)
Over operating free-air temperature range (unless otherwise noted)
MIN
Input supply voltage (2)
VIN
Disconnection switch
voltage (2)
DG, DS
Low-side driver bias voltage
VCC
High-side driver bias voltage
BST to SW
Current sense common mode
range (2)
CSP, CSN
Switch node voltage
SW
Junction temperature
TJ
(1)
(2)
NOM
MAX
4.5
65
3.0
65
UNIT
14
3.8
14
3.0
65
V
100
–40
125
ºC
Recommended Operating Conditions are conditions under which operation of the device is intended to be functional, but does not
guarantee specific performance limits.
Minimum VIN operating voltage is always 4.5 V. The minimum input power supply voltage can be 3.0 V after start-up, assuming VIN
voltage is supplied from an available external source.
6.5 Thermal Information
THERMAL METRIC (1)
LM5121,
LM5121-Q1
PWP (HTSSOP)
UNIT
20 PINS
RθJA
Junction-to-ambient thermal resistance (Typ.)
40
ºC/W
RθJC(bot)
Junction-to-case (bot) thermal resistance (Typ.)
4
ºC/W
(1)
For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.
Copyright © 2013–2016, Texas Instruments Incorporated
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SNVS963C – SEPTEMBER 2013 – REVISED JUNE 2016
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6.6 Electrical Characteristics
Unless otherwise specified, these specifications apply for –40°C ≤ TJ ≤ +125°C, VVIN = 12 V, VVCC = 8.3 V, RT = 20 kΩ, no
load on LO and HO. Typical values represent the most likely parametric norm at TJ = 25°C, and are provided for reference
purposes only.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
VIN SUPPLY
ISHUTDOWN VIN shutdown current
VUVLO = 0 V
9
17
µA
IBIAS
VUVLO = 2 V, non-switching
4
5
mA
7.6
8.3
VIN operating current (exclude the current
into RT resistor)
VCC REGULATOR
VCC(REG)
VCC regulation
No load
VVIN = 4.5 V, no external load
VCC dropout (VIN to VCC)
IVCC
6.9
0.25
VVIN = 4.5 V, IVCC = 25 mA
0.28
VCC sourcing current limit
VVCC = 0 V
VCC operating current (exclude the current
into RT resistor)
VVCC = 8.3 V
3.5
5
VVCC = 12 V
4.5
8
4.0
4.1
VCC undervoltage threshold
50
VCC rising, VVIN = 4.5 V
3.9
62
VCC falling, VVIN = 4.5 V
VCC undervoltage hysteresis
V
0.5
mA
3.7
V
1.23
V
µA
0.385
UNDERVOLTAGE LOCKOUT
UVLO threshold
UVLO rising
UVLO hysteresis current
VUVLO = 1.4 V
UVLO standby threshold
UVLO rising
1.17
1.20
7
10
13
0.3
0.4
0.5
0.1
0.125
1.24
1.28
UVLO standby hysteresis
V
MODE
Diode emulation mode threshold
MODE rising
1.20
Diode emulation mode hysteresis
0.1
Default MODE voltage
Default skip cycle threshold
Skip cycle hysteresis
145
155
COMP rising, measured at COMP
1.290
COMP falling, measured at COMP
1.245
Measured at COMP
170
V
mV
V
40
mV
ERROR AMPLIFIER
VREF
FB reference voltage
Measured at FB, VFB= VCOMP
FB input bias current
VFB= VREF
VOH
COMP output high voltage
VOL
COMP output low voltage
AOL
DC gain
fBW
Unity gain bandwidth
1.188
1.200
1.212
5
ISOURCE = 2 mA, VVCC = 4.5 V
2.75
ISOURCE = 2 mA, VVCC = 12 V
3.40
V
nA
V
ISINK = 2 mA
0.25
80
dB
3
MHz
OSCILLATOR
fSW1
Switching frequency 1
RT = 20 kΩ
400
450
500
fSW2
Switching frequency 2
RT = 10 kΩ
775
875
975
RT output voltage
kHz
1.2
RT sync rising threshold
RT rising
RT sync falling threshold
RT falling
2.5
1.6
Minimum sync pulse width
2.9
V
2.0
100
ns
DISCONNECTION SWITCH CONTROL
IDIS-
DG current source
UVLO = 2 V, Sourcing
DG current sink
Inrush Control, Sinking
25
SOURCE
IDIS-SINK
6
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uA
67
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SNVS963C – SEPTEMBER 2013 – REVISED JUNE 2016
Electrical Characteristics (continued)
Unless otherwise specified, these specifications apply for –40°C ≤ TJ ≤ +125°C, VVIN = 12 V, VVCC = 8.3 V, RT = 20 kΩ, no
load on LO and HO. Typical values represent the most likely parametric norm at TJ = 25°C, and are provided for reference
purposes only.
PARAMETER
TEST CONDITIONS
DG discharge switch RDS-ON
Circuit Breaker
DG charge pump regulation
DG to VIN, No load, VVIN = 4.5 V
MIN
TYP
9.5
10.5
4.0
5.4
DG to VIN, No load, VVIN = 12 V
VGS-DET
VGS detection threshold
DG to DS, Rising, VVIN = 12 V
MAX
11.5
12.5
VGS detection hysteresis
UNIT
Ω
38
6.5
V
0.2
Transconductance gain
CSP to CSN to IDG
12
uA/mV
SLOPE COMPENSATION
SLOPE output voltage
VSLOPE
Slope compensation amplitude
1.17
1.20
1.23
RSLOPE = 20 kΩ, fSW = 100 kHz, 50%
duty cycle, TJ = –40ºC to +125ºC
1.375
1.650
1.925
RSLOPE= 20 kΩ, fSW= 100 kHz, 50%
duty cycle, TJ = 25ºC
1.400
1.650
1.900
7.5
10
12
V
SOFT-START
ISS-SOURCE SS current source
VSS = 0 V
SS discharge switch RDS-ON
µA
Ω
13
PWM COMPARATOR
tLO-OFF
tON-MIN
Forced LO off-time
Minimum LO on-time
VVCC = 5.5 V
420
550
VVCC = 4.5 V
360
500
RSLOPE = 20 kΩ
150
RSLOPE = 200 kΩ
COMP to PWM voltage drop
ns
300
TJ = –40ºC to +125ºC
0.95
1.10
1.25
TJ = 25ºC
1.00
1.10
1.20
CSP to CSN, TJ = –40ºC to +125ºC
65.5
75.0
87.5
CSP to CSN, TJ = 25ºC
67.0
75.0
86.0
80
110
133
143
160
170
11.5
16.0
V
CURRENT SENSE / CYCLE-BY-CYCLE CURRENT LIMIT
VCS-TH1
Cycle-by-cycle current limit threshold
VCS-TH2
Inrush current limit threshold
CSP to CSN
VCS-TH3
Circuit breaker enable threshold
CSP to CSN, Rising
VCS-TH2 –VCS-TH1
VCS-TH4
VCS-ZCD
Circuit breaker disable threshold
5
VCS-TH3 – VCS-TH2
20
CSP to CSN, Falling
4.0
CSP to CSN, Rising
Zero cross detection threshold
CSP to CSN, Falling
7
0.3
6
Current sense amplifier gain
10
ICSP
CSP input bias current
12
ICSN
CSN input bias current
11
Bias current matching
ICSP to ICSN
CS to LO delay
Current sense / current limit delay
mV
–1.75
1
12
V/V
µA
3.75
150
ns
HICCUP MODE RESTART
VRES
Restart threshold
VHCP-
Hiccup counter upper threshold
RES rising
RES rising
1.15
1.20
4.2
UPPER
RES rising, VVIN = VVCC = 4.5 V
VHCP-
RES falling
2.15
RES falling, VVIN = VVCC = 4.5 V
1.85
Hiccup counter lower threshold
LOWER
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1.25
3.6
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Electrical Characteristics (continued)
Unless otherwise specified, these specifications apply for –40°C ≤ TJ ≤ +125°C, VVIN = 12 V, VVCC = 8.3 V, RT = 20 kΩ, no
load on LO and HO. Typical values represent the most likely parametric norm at TJ = 25°C, and are provided for reference
purposes only.
PARAMETER
IRES-
TEST CONDITIONS
RES current source1
Fault-state charging current
IRES-SINK1
RES current sink1
Normal-state discharging current
IRES-
RES current source2
Hiccup mode off-time charging current
RES current sink2
Hiccup mode off-time discharging
current
MIN
TYP
MAX
20
30
40
UNIT
SOURCE1
5
µA
10
SOURCE2
IRES-SINK2
5
Hiccup cycle
RES discharge switch RDS-ON
Ratio of hiccup mode off-time to restart
delay time
8
Cycles
40
Ω
122
HO GATE DRIVER
VOHH
HO high-state voltage drop
IHO = –100 mA, VOHH = VBST – VHO
0.15
0.24
VOLH
HO low-state voltage drop
IHO = 100 mA, VOLH = VHO – VSW
0.1
0.18
HO rise time (10% to 90%)
CLOAD = 4700 pF, VBST = 12 V
25
HO fall time (90% to 10%)
CLOAD = 4700 pF, VBST = 12 V
20
VHO = 0 V, VSW = 0 V, VBST = 4.5 V
0.8
VHO = 0 V, VSW = 0 V, VBST = 7.6 V
1.9
VHO = VBST = 4.5 V
1.9
IOHH
Peak HO source current
IOLH
Peak HO sink current
IBST
BST charge pump sourcing current
BST charge pump regulation
VHO = VBST = 7.6 V
ns
A
3.2
VVIN = VSW = 9.0 V , VBST - VSW = 5.0 V
90
200
BST to SW, IBST= –70 μA,
VVIN = VSW = 9.0 V
5.3
6.2
6.75
7
8.5
9
2.0
3.0
3.5
30
45
0.15
0.25
0.17
BST to SW, IBST = –70 μA,
VVIN = VSW = 12 V
BST to SW undervoltage
BST DC bias current
V
VBST - VSW = 12 V, VSW = 0 V
µA
V
µA
LO GATE DRIVER
VOHL
LO high-state voltage drop
ILO = –100 mA, VOHL = VVCC – VLO
VOLL
LO low-state voltage drop
ILO = 100 mA, VOLL = VLO
0.1
LO rise time (10% to 90%)
CLOAD = 4700 pF
25
LO fall time (90% to 10%)
CLOAD = 4700 pF
20
VLO = 0 V, VVCC = 4.5 V
0.8
VLO = 0 V
2.0
VLO = VVCC = 4.5 V
1.8
VLO = VVCC
3.2
IOHL
Peak LO source current
IOLL
Peak LO sink current
V
ns
A
SWITCHING CHARACTERISTICS
tDLH
LO fall to HO rise delay
No load, 50% to 50%
50
80
115
tDHL
HO fall to LO rise delay
No load, 50% to 50%
60
80
105
Thermal shutdown
Temperature rising
ns
THERMAL
TSD
165
Thermal shutdown hysteresis
8
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25
ºC
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SNVS963C – SEPTEMBER 2013 – REVISED JUNE 2016
6.7 Typical Characteristics
6.00
5.00
4.00
3.00
LO PEAK CURRENT [A]
HO PEAK CURRENT [A]
5.00
SINK
2.00
SOURCE
1.00
4.00
SINK
3.00
SOURCE
2.00
1.00
VVIN = 12V
VSW = 0V
VVIN = 12V
0.00
0.00
4
5
6
7
8
9
10
11
12
13
VBST - VSW [V]
4
14
Figure 1. HO Peak Current vs VBST - VSW
7
8
95
80.00
90
70.00
85
Dead-time [ns]
90.00
60.00
tDHL
50.00
40.00
tDLH
VVIN = 12V
VSW = 12V
CLOAD=2600pF
1V to 1V
20.00
10.00
9
10
11
12
13
14
C001
Figure 2. LO Peak Current vs VVCC
100
Dead-time [ns]
6
VVCC [V]
100.00
30.00
5
C001
tDHL
80
75
70
tDLH
65
60
55
0.00
50
4
5
6
7
8
9
10
11
VVCC [V]
12
-50
-25
0
25
50
75
100
125
Temperature [ƒC]
C001
Figure 3. Dead Time vs VVCC
150
C001
Figure 4. Dead Time vs Temperature
100.0
20
90.0
15
70.0
tDHL
ISHUTDOWN [PA]
Dead-time [ns]
80.0
60.0
50.0
40.0
tDLH
30.0
VVIN = 12V
VVCC = 7.6V
CLOAD = 2600pF
1V to 1V
20.0
10.0
10
5
0.0
0
0
10
20
30
40
VSW [V]
50
60
-50
-25
Figure 5. Dead Time vs VSW
0
25
50
75
100
125
Temperature [ƒC]
C001
150
C001
Figure 6. ISHUTDOWN vs Temperature
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Typical Characteristics (continued)
8
8
No load
6
VVCC [V]
VVCC [V]
6
4
4
2
2
0
0
No load
0
10
20
30
40
50
60
70
0
80
IVCC [mA]
1
2
3
4
5
6
40
9
10
11
12
13
14
C001
15
180
ACL=101, COMP unload
ICSP
PHASE
20
90
10
45
0
10000
100000
FREQUENCY [Hz]
10
ICSN
5
0
GAIN
-10
1000
ICSP, ICSN [PA]
135
PHASE [°]
GAIN [dB]
8
Figure 8. VVCC vs VVIN
Figure 7. VVCC vs IVCC
30
7
VVIN [V]
C001
1000000
0
-45
10000000
-50
-25
0
25
50
75
100
125
Temperature [ƒC]
C002
Figure 9. Error Amp Gain
and Phase vs Frequency
150
C001
Figure 10. ICSP, ICSN vs Temperature
15.0
300
280
BST Charging Current [PA]
IBST = -70uA
VBST-SW [V]
10.0
5.0
VVIN=VSW=9V
260
240
220
200
180
160
140
120
100
0.0
4
9
14
19
VSW [V]
-50
-25
0
Figure 11. VBST-SW vs VSW
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25
50
75
100
Temperature [ƒC]
C001
125
150
C001
Figure 12. IBST vs Temperature
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SNVS963C – SEPTEMBER 2013 – REVISED JUNE 2016
Typical Characteristics (continued)
VCS-TH1, VCS-TH2, VCS-TH3 [mV]
VCS-TH1, VCS-TH2, VCS-TH3 [mV]
200
VCS-TH3
150
VCS-TH2
100
VCS-TH1
50
4
5
6
7
8
9
10
11
200
190
180
170
160
150
140
130
120
110
100
90
80
70
60
50
VCS-TH3
VCS-TH2
VCS-TH1
12
VVIN [V]
±50
±25
0
C001
Figure 13. VCS-TH1, VCS-TH2, VCS-TH3 vs VVIN
25
50
75
Temperature [ƒC]
100
125
150
C001
Figure 14. VCS-TH1 VCS-TH2, VCS-TH3 vs Temperature
12
12
11
10
VDG-DS [V]
11
500 kŸ
No Load
8
VDG-DS [V]
9
7
6
5
250 kŸ
10
4
3
9
2
VDS=12V
1
0
8
4
5
6
7
8
9
10
11
12
VVIN [V]
±50
0
±25
25
50
75
100
125
Temperature [ƒC]
C001
Figure 15. VDG-DS vs VVIN
150
C001
Figure 16. VDG-DS vs Temperature
12.00
11.00
10.00
VSW = 12V
9.00
VBST-SW [V]
8.00
7.00
6.00
5.00
VSW = 9V
4.00
3.00
VVIN = VSW
IBST = -70uA
2.00
1.00
0.00
-50
-25
0
25
50
75
100
Temperature [ƒC]
125
150
C001
Figure 17. VBST-SW vs Temperature
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7 Detailed Description
7.1 Overview
The LM5121 wide input range synchronous boost controller features all of the functions necessary to implement
a highly efficient synchronous boost regulator. The regulator control method is based upon peak current mode
control. Peak current mode control provides inherent line feed-forward and ease of loop compensation. This
highly integrated controller provides strong high-side and low-side N-channel MOSFET drivers with adaptive
dead-time control. The switching frequency is user programmable up to 1 MHz, either set by a single resistor or
synchronized to an external clock.
The control mode of high-side synchronous switch can be configured as either forced PWM (FPWM) or diode
emulation mode. Fault protection features include cycle-by-cycle current limiting, hiccup mode over load
protection, hiccup mode short circuit protection, thermal shutdown and remote shutdown capability by pulling
down the UVLO pin. The UVLO input enables the controller when the input voltage reaches a user selected
threshold, and provides tiny 9 μA shutdown quiescent current when pulled low. LM5121's unique disconnection
switch control provides numerous additional advantages. True Shutdown allows disconnecting load from the
input, blocking leakage current paths in shutdown mode. Inrush current control limits input current during initial
charging of the output capacitor. Circuit breaker function quickly switches off the disconnection switch,
terminating any severe over-current condition. Hiccup mode short circuit protection minimizes power dissipation
during prolonged output short condition. Input over voltage suppression can be achieved by connecting a Zener
diode from the disconnection MOSFET gate pin to ground. The device is available in 20-pin HTSSOP package
featuring an exposed pad to aid in thermal dissipation.
7.2 Functional Block Diagram
VIN
QD
RS
CIN
CSP
VIN
10µA
DF
DG Charge Pump
STANDBY
+
1.1V
+
UVLO
RUV1
CS A=10
AMP
0.4V/0.3V
+
SHUTDOWN
9
VSLOPE =
CHF
COMP
+
+
-
- ZCD threshold
+ ERR
+
PWM
Comparator
10µA
SW
COUT
CLK
S
Q
PWM
LO
Adaptive
Timer
QL
R Q
1.2V
RFB2
Skip Cycle
Comparator
700k
20mV
+
MODE
100k
VOUT
CBST
VCC
+
-
SS
Level Shift
Diode Emulation
C/L
Comparator
AMP
CSS
BST
+
-
FB
1.2V
CVCC
DBST
HO
+
750mV
CCOMP RCOMP
BST Charge Pump
QH
VSENSE2
1.2 V
VCC
VCC
Regulator
Circuit Breaker
Comparator
VSENSE1
6 u 10
RSLOPE u FSW
VIN
+
-
1.6V/0.11V
SLOPE
Generator
AMP
+
Inrush Current
Limiter
SLOPE
RSLOPE
VIN
25µA
1.2V
RUV2
LIN
DS
DG
CSN
1.2V
-
+
+
Diode
Emulation
Comparator
30µA
40mV
Hysteresis
Diode
Emulation
LM5121
CLK
10µA
Restart
Timer
RFB1
Clock Generator
/SYNC Detector
RES
5µA
AGND
SYNCIN/RT
CRES
PGND
RT
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7.3 Feature Description
7.3.1 Undervoltage Lockout (UVLO)
The LM5121 features a dual level UVLO circuit. When the UVLO pin voltage is less than the 0.4-V UVLO
standby threshold, the LM5121 is in the shutdown mode with all functions disabled. The shutdown comparator
provides 0.1 V of hysteresis to avoid chatter during transitions. If the UVLO pin voltage is greater than 0.4 V and
below 1.2 V during power up, the controller is in the standby mode with the VCC regulator operational, the
disconnection switch disabled and no switching at the HO and LO outputs. This feature allows the UVLO pin to
be used as a remote shutdown function by pulling the UVLO pin down below the UVLO standby threshold with
an external open collector or open drain device.
VIN
UVLO Hysteresis
Current
RUV2
RUV1
STANDBY
UVLO
UVLO
Threshold
UVLO Standby
Enable Threshold
SHUTDOWN
+
+
STANDBY
SHUTDOWN
Figure 18. UVLO Remote Standby and Shutdown Control
If the UVLO pin voltage is above 1.2-V UVLO threshold and VCC voltage exceeds the VCC UV threshold, the
startup sequence begins. UVLO hysteresis is accomplished with an internal 10-μA current source that is
switched on or off into the impedance of the UVLO setpoint divider. When the UVLO pin voltage exceeds the 1.2
V, the current source is enabled to quickly raise the voltage at the UVLO pin. When the UVLO pin voltage falls
below the 1.2-V UVLO threshold, the current source is disabled causing the voltage at the UVLO pin to quickly
fall. In addition to the UVLO hysteresis current source, a 5-μs deglitch filter on both rising and falling edge of
UVLO toggling helps preventing chatter during power up or down.
An external UVLO setpoint voltage divider from the supply voltage to AGND is used to set the minimum input
operating voltage of the regulator. The divider must be designed such that the voltage at the UVLO pin is greater
than 1.2 V when the input voltage is in the desired operating range. The maximum voltage rating of the UVLO
pin is 16 V. If necessary, the UVLO pin can be clamped with an external zener diode. The UVLO pin should not
be left floating. The values of RUV1 and RUV2 can be determined from Equation 1 and Equation 2.
VHYS
RUV2
ª: º
10 $ ¬ ¼
(1)
1.2V u RUV2
RUV1
ª: º
VIN(STARTUP) 1.2V ¬ ¼
where
•
•
VHYS is the desired UVLO hysteresis
VIN(STARTUP) is the desired startup voltage of the regulator during turn-on.
(2)
Typical shutdown voltage during turn-off can be calculated as follows:
VIN(SHUTDOWN) VIN(STARTUP) VHYS [V]
(3)
7.3.2 High Voltage VCC Regulator
The LM5121 contains an internal high voltage regulator that provides typical 7.6-V VCC bias supply for the
controller and N-channel MOSFET drivers. The input of the VCC regulator, VIN can be connected to a voltage
source as high as 65 V. The VCC regulator turns on when the UVLO pin voltage is greater than 0.4 V. When the
input voltage is below the VCC setpoint level, the VCC output tracks VIN with a small dropout voltage. The
output of the VCC regulator is current limited at 50-mA minimum.
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Feature Description (continued)
Upon power-up, the VCC regulator sources current into the capacitor connected to the VCC pin. The
recommended range for the VCC capacitor is 1.0 μF to 47 μF and it is recommended to be at least 10 times
greater than CBST value. When operating with a VIN voltage less than 6 V, the value of VCC capacitor should be
4.7 µF or greater.
The internal power dissipation of the LM5121 device can be reduced by supplying VCC from an external supply.
If an external VCC bias supply exists and the voltage is greater than 9 V and below 14.5 V. The external VCC
bias supply can be applied to the VCC pin directly through a diode, as shown in Figure 19.
External
VCC
VCC Supply
LM5121
CVCC
Figure 19. External Bias Supply when 9 V < VEXT< 14.5 V
Shown in Figure 20 is a method to derive the VCC bias voltage with an additional winding on the boost inductor.
This circuit must be designed to raise the VCC voltage above VCC regulation voltage to shut off the internal VCC
regulator.
VCC
+
nuVOUT
nuVIN
+
+
nu(VOUT -VIN)
1:n
VIN
VOUT
+
+
Figure 20. External Bias Supply using Transformer
The VCC regulator series pass transistor includes a diode between VCC and VIN, as shown in Figure 21, that
should not be forward biased in normal operation. If the voltage of the external VCC bias supply is greater than
the VIN pin voltage, an external blocking diode is required from the input power supply to the VIN pin to prevent
the external bias supply from passing current to the input supply through VCC. The need for the blocking diode
should be evaluated for all applications when the VCC is supplied by the external bias supply. When the input
power supply voltage is less than 4.5 V, an external VCC supply should be used and the external blocking diode
is required.
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SNVS963C – SEPTEMBER 2013 – REVISED JUNE 2016
Feature Description (continued)
VIN
VIN
LM5121
External
VCC Supply
VCC
Figure 21. VIN Configuration when VVIN
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