LM5145-Q1
SNVSBU9A – JUNE 2021 – REVISED JUNE 2021
LM5145-Q1 Automotive 75-V Synchronous Buck DC/DC Controller With Wide Duty
Cycle Range
1 Features
2 Applications
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AEC-Q100 qualified for automotive applications:
– Device temperature grade 1: –40°C to +125°C
ambient temperature range
Functional Safety-Capable
– Documentation available to aid functional safety
system design
Versatile synchronous buck DC/DC controller
– Wide input voltage range of 5.5 V to 75 V
– 150°C maximum junction temperature
– 0.8-V reference with ±1% feedback accuracy
– Adjustable output voltage from 0.8 V to 60 V
– 40-ns tON(min) for high VIN / VOUT ratio
– 140-ns tOFF(min) for low dropout
– Lossless RDS(on) or shunt current sensing
– Optimized for CISPR 25 Class 5 requirements
Switching frequency from 100 kHz to 1 MHz
– SYNC in and SYNC out capability
– Selectable diode emulation or FPWM
7.5-V gate drivers for standard VTH MOSFETs
– 14-ns adaptive dead-time control
– 2.3-A source and 3.5-A sink capability
Inherent protection features for robust design
– Adjustable output voltage soft start
– Hiccup-mode overcurrent protection
– Input UVLO with hysteresis
– VCC and gate-drive UVLO protection
– Precision enable input and open-drain PGOOD
indicator for sequencing and control
– Thermal shutdown protection with hysteresis
20-pin VQFN package with wettable flanks
Create a custom design using the LM5145-Q1 with
WEBENCH® Power Designer
High-power automotive DC/DC regulator
Automotive motor drives, ADAS
HEV/EV powertrain systems
Body electronics and lighting
Infotainment and cluster
3 Description
The LM5145-Q1 75-V synchronous buck controller
regulates from a high input voltage source or from an
input rail subject to high-voltage transients, minimizing
the need for external surge suppression components.
A high-side switch minimum on-time of 40 ns gives
large step-down ratios, enabling the direct step-down
conversion from a 48-V nominal input to low-voltage
rails for reduced system complexity and solution cost.
The LM5145-Q1 continues to operate during input
voltage dips as low as 5.5 V, at nearly 100% duty
cycle if needed, making it an excellent choice for
high-power automotive DC/DC regulators, automotive
motor drives, and HEV/EV power compliant to LV-148.
Forced-PWM (FPWM) operation eliminates switching
frequency variation to minimize EMI, while
user-selectable diode emulation lowers current
consumption at light-load conditions. The adjustable
switching frequency as high as 1 MHz can be
synchronized to an external clock source to eliminate
beat frequencies in noise-sensitive applications.
Device Information
PART NUMBER
LM5145-Q1
(1)
PACKAGE(1)
VQFN (20)
BODY SIZE (NOM)
4.50 mm × 3.50 mm
For all available packages, see the orderable addendum at
the end of the data sheet.
Typical Application Circuit and Efficiency Performance, VOUT = 12 V, FSW = 400 kHz
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
LM5145-Q1
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SNVSBU9A – JUNE 2021 – REVISED JUNE 2021
Table of Contents
1 Features............................................................................1
2 Applications .................................................................... 1
3 Description.......................................................................1
4 Revision History.............................................................. 2
5 Description (continued).................................................. 3
6 Pin Configuration and Functions...................................4
6.1 Wettable Flanks.......................................................... 5
7 Specifications.................................................................. 6
7.1 Absolute Maximum Ratings ....................................... 6
7.2 ESD Ratings ............................................................. 6
7.3 Recommended Operating Conditions ........................7
7.4 Thermal Information ...................................................7
7.5 Electrical Characteristics ............................................8
7.6 Switching Characteristics .........................................10
7.7 Typical Characteristics.............................................. 11
8 Detailed Description......................................................16
8.1 Overview................................................................... 16
8.2 Functional Block Diagram......................................... 16
8.3 Feature Description...................................................17
8.4 Device Functional Modes..........................................25
9 Application and Implementation.................................. 26
9.1 Application Information............................................. 26
9.2 Typical Applications.................................................. 35
10 Power Supply Recommendations..............................45
11 Layout........................................................................... 46
11.1 Layout Guidelines................................................... 46
11.2 Layout Example...................................................... 49
12 Device and Documentation Support..........................50
12.1 Device Support....................................................... 50
12.2 Documentation Support.......................................... 51
12.3 Receiving Notification of Documentation Updates..51
12.4 Support Resources................................................. 51
12.5 Trademarks............................................................. 52
12.6 Electrostatic Discharge Caution..............................52
12.7 Glossary..................................................................52
13 Mechanical, Packaging, and Orderable
Information.................................................................... 53
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision * (June 2021) to Revision A (June 2021)
Page
• Updated functional safety link.............................................................................................................................1
2
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5 Description (continued)
The LM5145-Q1 voltage-mode controller with line feedforward drives external high-side and low-side N-channel
power switches with robust 7.5-V gate drivers suitable for standard-threshold MOSFETs. Adaptively-timed gate
drivers with 2.3-A source and 3.5-A sink capability minimize body diode conduction during switching transitions,
reducing switching losses and improving thermal performance when driving MOSFETs at high input voltage and
high frequency. The LM5145-Q1 can be powered from the output of the switching regulator or another available
source, further improving efficiency.
A 180° out-of-phase clock output relative to the internal oscillator at SYNCOUT works well for cascaded or
multi-channel power supplies to reduce input capacitor ripple current and EMI filter size. Additional features of
the LM5145-Q1 include a configurable soft start, an open-drain power-good monitor for fault reporting and output
monitoring, monotonic start-up into prebiased loads, integrated VCC bias supply regulator and bootstrap diode,
external power supply tracking, precision enable input with hysteresis for adjustable line undervoltage lockout
(UVLO), hiccup-mode overload protection, and thermal shutdown protection with automatic recovery.
The LM5145-Q1 controller is offered in a 4.5-mm × 3.5-mm thermally enhanced, 20-pin VQFN package with
additional spacing for high-voltage pins and wettable flanks for optical inspection of solder joint fillets.
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EN/UVLO
VIN
1
20
6 Pin Configuration and Functions
RT
2
19
SW
SS/TRK
3
18
HO
COMP
4
17
BST
FB
5
16
NC
AGND
6
15
EP
SYNCOUT
7
14
VCC
SYNCIN
8
13
LO
NC
9
12
PGND
11
ILIM
PGOOD
10
Exposed
Pad
(EP)
Connect Exposed Pad on bottom to AGND and PGND on the PCB.
Figure 6-1. 20-Pin VQFN With Wettable Flanks in RGY Package (Top View)
Table 6-1. Pin Functions
PIN
NO.
4
NAME
I/O(1)
DESCRIPTION
1
EN/UVLO
I
Enable input and undervoltage lockout programming pin. If the EN/UVLO voltage is below 0.4 V, the controller
is in shutdown mode with all functions disabled. If the EN/UVLO voltage is greater than 0.4 V and less than
1.2 V, the regulator is in standby mode with the VCC regulator operational, the SS pin grounded, and no
switching at the HO and LO outputs. If the EN/UVLO voltage is above 1.2 V, the SS/TRK voltage can ramp
and pulse-width modulated gate-drive signals are delivered to the HO and LO pins. A 10-μA current source
is enabled when EN/UVLO exceeds 1.2 V and flows through the external UVLO resistor divider to provide
hysteresis. Hysteresis can be adjusted by varying the resistance of the external divider.
2
RT
I
Oscillator frequency adjust pin. The internal oscillator is programmed with a single resistor between RT and the
AGND. TI recommends a maximum oscillator frequency of 1 MHz. An RT pin resistor is required even when
using the SYNCIN pin to synchronize to an external clock.
3
SS/TRK
I
Soft start and voltage-tracking pin. An external capacitor and an internal 10-μA current source set the ramp
rate of the error amplifier reference during start-up. When the SS/TRK pin voltage is less than 0.8 V, the
SS/TRK voltage controls the noninverting input of the error amp. When the SS/TRK voltage exceeds 0.8 V, the
amplifier is controlled by the internal 0.8-V reference. SS/TRK is discharged to ground during standby and fault
conditions. After start-up, the SS/TRK voltage is clamped 115 mV above the FB pin voltage. If FB falls due to a
load fault, SS/TRK is discharged to a level 115 mV above FB to provide a controlled recovery when the fault is
removed. Voltage tracking can be implemented by connecting a low impedance reference between 0 V and 0.8
V to the SS/TRK pin. The 10-µA SS/TRK charging current flows into the reference and produces a voltage error
if the impedance is not low. Connect a minimum capacitance from SS/TRK to AGND of 2.2 nF.
4
COMP
O
Low impedance output of the internal error amplifier. Connect the loop compensation network between the
COMP pin and the FB pin.
5
FB
I
Feedback connection to the inverting input of the internal error amplifier. A resistor divider from the output to
this pin sets the output voltage level. The regulation threshold at the FB pin is nominally 0.8 V.
6
AGND
P
Analog ground. Return for the internal 0.8-V voltage reference and analog circuits.
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Table 6-1. Pin Functions (continued)
PIN
NO.
7
NAME
SYNCOUT
I/O(1)
DESCRIPTION
O
Synchronization output. Logic output that provides a clock signal that is 180° out-of-phase with the high-side
FET gate drive. Connect SYNCOUT of the master LM5145-Q1 to the SYNCIN pin of a second LM5145-Q1 to
operate two controllers at the same frequency with 180° interleaved high-side FET switch turn-on transitions.
Note that the SYNCOUT pin does not provide 180° interleaving when the controller is operating from an
external clock that is different from the free-running frequency set by the RT resistor.
Dual function pin to provide an optional clock input and enable diode emulation by the low-side MOSFET.
Connecting a clock signal to the SYNCIN pin synchronizes switching to the external clock. Diode emulation
by the low-side MOSFET is disabled when the controller is synchronized to an external clock, and negative
inductor current can flow in the low-side MOSFET with light loads. A continuous logic low state at the
SYNCIN pin enables diode emulation to prevent reverse current flow in the inductor. Diode emulation results in
discontinuous mode operation (DCM) at light loads, which improves efficiency. A logic high state at the SYNCIN
pin disables diode emulation, producing forced-PWM (FPWM) operation. During soft start when SYNCIN is high
or a clock signal is present, the LM5145-Q1 operates in diode emulation mode until the output is in regulation,
then gradually increases the SW zero-cross threshold, resulting in a gradual transition from DCM to FPWM.
8
SYNCIN
I
9
NC
—
No electrical connection
10
PGOOD
O
Power-good indicator. This pin is an open-drain output. A high state indicates that the voltage at the FB pin is
within a specified tolerance window centered at 0.8 V.
11
ILIM
I
Current limit adjust and current sense comparator input. A current sourced from the ILIM pin through an
external resistor programs the threshold voltage for valley current limiting. The opposite end of the threshold
adjust resistor can be connected to either the drain of the low-side MOSFET for RDS(on) sensing or to a current
sense resistor connected to the source of the low-side FET.
12
PGND
P
Power ground return pin for the low-side MOSFET gate driver. Connect directly to the source of the low-side
MOSFET or the ground side of a shunt resistor.
13
LO
P
Low-side MOSFET gate drive output. Connect to the gate of the low-side synchronous rectifier FET through a
short, low inductance path.
14
VCC
O
Output of the 7.5-V bias regulator. Locally decouple to PGND using a low-ESR/ESL capacitor located as close
as possible to the controller. Controller bias can be supplied from an external supply that is greater than the
internal VCC regulation voltage. Use caution when applying external bias to ensure that the applied voltage is
not greater than the minimum VIN voltage and does not exceed the VCC pin maximum operating rating. See the
Recommended Operating Conditions.
15
EP
—
Pin is internally connected to exposed pad of the package. Connect to GND at the exposed pad to improve
heat spreading.
16
NC
—
No electrical connection
17
BST
O
Bootstrap supply for the high-side gate driver. Connect to the bootstrap (boot) capacitor. The bootstrap
capacitor supplies current to the high-side FET gate and must be placed as close as possible to controller.
If an external bootstrap diode is used to reduce the time required to charge the bootstrap capacitor, connect the
cathode of the diode to the BST pin and anode to VCC.
18
HO
P
High-side MOSFET gate drive output. Connect to the gate of the high-side MOSFET through a short, low
inductance path.
19
SW
P
Switching node of the buck controller. Connect to the bootstrap capacitor, the source terminal of the high-side
MOSFET, and the drain terminal of the low-side MOSFET using short, low inductance paths.
20
VIN
P
Supply voltage input for the VCC LDO regulator
—
EP
—
Exposed pad of the package. Electrically isolated. Solder to the system ground plane to reduce thermal
resistance.
(1)
P = Power, G = Ground, I = Input, O = Output
6.1 Wettable Flanks
100% automated visual inspection (AVI) post-assembly is typically required to meet requirements for high
reliability and robustness. Standard quad-flat no-lead (VQFN) packages do not have solderable or exposed pins
and terminals that are easily viewed. Therefore, it is difficult to visually determine whether or not the package
is successfully soldered onto the printed-circuit board (PCB). The wettable-flank process was developed to
resolve the issue of side-lead wetting of leadless packaging. The LM5145-Q1 is assembled using a 20-pin VQFN
package with wettable flanks to provide a visual indicator of solderability, which reduces the inspection time and
manufacturing costs.
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7 Specifications
7.1 Absolute Maximum Ratings
Over the recommended operating junction temperature of –40℃ to +150℃ (unless otherwise noted).(1)
Input voltage
MIN
MAX
VIN
–0.3
100
SW
–1
100
SW (20-ns transient)
–5
100
ILIM
–1
100
EN/UVLO
–0.3
100
VCC
–0.3
14
FB, COMP, SS/TRK, RT
–0.3
6
SYNCIN
–0.3
14
BST
–0.3
BST to VCC
Output voltage
V
110
100
BST to SW
–0.3
14
VCC to BST (20-ns transient)
V
7
LO (20-ns transient)
–3
PGOOD
–0.3
Operating junction temperature, TJ
Storage temperture, Tstg
(1)
UNIT
–55
14
150
°C
150
°C
Operation outside the Absolute Maximum Ratings may cause permanent device damage. Absolute Maximum Ratings do not imply
functional operation of the device at these or any other conditions beyond those listed under Recommended Operating Conditions.
If used outside the Recommended Operating Conditions but within the Absolute Maximum Ratings, the device may not be fully
functional, and this may affect device reliability, functionality, performance, and shorten the device lifetime.
7.2 ESD Ratings
VALUE
Human body model (HBM), per AEC Q100-002 (1) HBM ESD Classification Level 2
V(ESD)
(1)
6
Electrostatic discharge
Charged device model (CDM), per AEC Q100-011
CDM ESD Classification Level C4B
UNIT
±2000
All pins except 1, 2, 9, 10, 11, 12, and 20
±500
Pins 1, 2, 9, 10, 11, 12, 19, and 20
±750
V
AEC Q100-002 indicates that HBM stressing shall be in accordance with the ANSI/ESDA/JEDEC JS-001 specification.
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7.3 Recommended Operating Conditions
Over the recommended operating junction temperature range of –40℃ to 150℃ (unless otherwise noted).
MIN
UNIT
5.5
75
V
SW
–1
75
V
0
75
V
8
13
V
EN/UVLO
–0.3
75
V
BST
–0.3
88
V
75
V
13
V
13
V
1
mA
2
mA
150
°C
External VCC bias rail
BST to VCC
BST to SW
5
PGOOD
ISINK, ISRC
Sink/source current SYNCOUT
ISINK, ISRC
Sink/source current PGOOD
TJ
Operating junction temperature
(1)
MAX
VIN
Input voltage ILIM
Output
voltage
NOM
(1)
–1
–40
The Recommended Operating Conditions are conditions under which the device is intended to be functional. For specifications and
test conditions, see the Electrical Characteristics.
7.4 Thermal Information
LM5145-Q1
THERMAL
METRIC(1)
RGY (VQFN)
UNIT
20 PINS
RθJA
Junction-to-ambient thermal resistance
RθJC(top)
Junction-to-case (top) thermal resistance
RθJB
Junction-to-board thermal resistance
ψJT
ψJB
RθJC(bot)
(1)
36.8
°C/W
28
°C/W
11.8
°C/W
Junction-to-top characterization parameter
0.4
°C/W
Junction-to-board characterization parameter
11.7
°C/W
Junction-to-case (bottom) thermal resistance
2.1
°C/W
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics
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7.5 Electrical Characteristics
Typical values correspond to TJ = 25°C. Minimum and maximum limits apply over the –40°C to 150°C junction temperature
range unless otherwise stated. VVIN = 48 V, VEN/UVLO = 1.5 V, RRT = 25 kΩ unless otherwise stated. (1) (2)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
75
V
1.8
2.1
mA
INPUT SUPPLY
VIN
Operating input voltage range
IVCC ≤ 10 mA at VVIN = 5.5 V
IQ-RUN
Operating input current, not switching
VEN/UVLO = 1.5 V, VSS/TRK = 0 V
5.5
IQ-STBY
Standby input current
VEN/UVLO = 1 V
1.75
2
mA
IQ-SHDN
Shutdown input current
VEN/UVLO = 0 V, VVCC < 1 V
13.5
30
µA
7.5
7.7
V
VCC REGULATOR
VVCC
VCC regulation voltage
VSS/TRK = 0 V, 9 V ≤ VVIN ≤ 100 V, 0
mA ≤ IVCC ≤ 20 mA
VVCC-LDO
VIN to VCC dropout voltage
VVIN = 6 V, VSS/TRK = 0 V, IVCC = 20 mA
0.25
0.72
ISC-LDO
VCC short-circuit current
VSS/TRK = 0 V, VVCC = 0 V
40
50
70
mA
VVCC-UV
VCC undervoltage threshold
VVCC rising
4.8
4.93
5.2
V
VVCC-UVH
VCC undervoltage hysteresis
Rising threshold – falling threshold
VVCC-EXT
Minimum external bias voltage
Voltage required to disable VCC
regulator
IVCC
External VCC input current, not
switching
VSS/TRK = 0 V, VVCC = 13 V
7.3
0.26
V
V
8
V
2.3
mA
ENABLE AND INPUT UVLO
VSHDN
Shutdown to standby threshold
VEN/UVLO rising
VSHDN-HYS
Shutdown threshold hysteresis
EN/UVLO Rising threshold – falling
threshold
VEN
Standby to operating threshold
VEN/UVLO rising
IEN-HYS
Standby to operating hysteresis current
VEN/UVLO = 1.5 V
0.42
V
50
mV
1.164
1.2
1.236
V
9
10
11
µA
800
808
mV
0.1
µA
0.2
µA
ERROR AMPLIFIER
VREF
FB reference Voltage
FB connected to COMP
792
IFB-BIAS1
FB input bias current
VFB = 0.8 V, –40°C ≤ TJ ≤ 125°C
–0.1
IFB-BIAS2
FB input bias current
VFB = 0.8 V, –40℃ ≤ TJ ≤ 150℃
–0.2
VCOMP-OH
COMP output high voltage
VFB = 0 V, COMP sourcing 1 mA
VCOMP-OL
COMP output low voltage
COMP sinking 1 mA
AVOL
DC gain
94
dB
GBW
Unity gain bandwidth
6.5
MHz
5
V
0.3
V
SOFT-START and VOLTAGE TRACKING
ISS
SS/TRK capacitor charging current
VSS/TRK = 0 V
RSS
SS/TRK discharge FET resistance
VEN/UVLO = 1 V, VSS/TRK = 0.1 V
VSS-FB
SS/TRK to FB offset
VSS-CLAMP
SS/TRK clamp voltage
8.5
10
12
11
–15
VSS/TRK – VFB, VFB = 0.8 V
0
µA
Ω
15
115
mV
mV
POWER GOOD INDICATOR
8
PGUTH
FB upper threshold for PGOOD high to
low
% of VREF, VFB rising
106%
108%
110%
PGLTH
FB lower threshold for PGOOD high to
low
% of VREF, VFB falling
90%
92%
94%
PGHYS_U
PGOOD upper theshold hysteresis
% of VREF
PGHYS_L
PGOOD lower threshold hysteresis
% of VREF
TPG-RISE
PGOOD rising filter
FB to PGOOD rising edge
25%
µs
TPG-FALL
PGOOD falling filter
FB to PGOOD falling edge
25%
µs
VPG-OL
PGOOD low state output voltage
VFB = 0.9 V, IPGOOD = 2 mA
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3%
2%
150
mV
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Typical values correspond to TJ = 25°C. Minimum and maximum limits apply over the –40°C to 150°C junction temperature
range unless otherwise stated. VVIN = 48 V, VEN/UVLO = 1.5 V, RRT = 25 kΩ unless otherwise stated. (1) (2)
PARAMETER
IPG-OH
TEST CONDITIONS
PGOOD high state leakage current
VFB = 0.8 V, VPGOOD = 13 V
FSW1
Oscilator frequency – 1
RRT = 100 kΩ
FSW2
Oscillator frequency – 2
RRT = 25 kΩ
FSW3
Oscillator frequency – 3
RRT = 12.5 kΩ
MIN
TYP
MAX
UNIT
400
nA
OSCILLATOR
100
380
400
kHz
420
780
kHz
kHz
SYNCHRONIZATION INPUT AND OUTPUT
FSYNC
SYNCIN external clock frequency range % of nominal frequency set by RRT
VSYNC-IH
SYNCIN input logic high
VSYNC-IL
SYNCIN input logic low
RSYNC-IN
SYNCIN input resistance
VSYNCIN = 3 V
TSYNCI-PW
SYNCIN input minimum pulsewidth
Minimum high state or low state
duration
VSYNCO-OH
SYNCOUT high-state output voltage
ISYNCOUT = –1 mA (sourcing current)
VSYNCO-OL
SYNCOUT low-state output voltage
ISYNCOUT = 1 mA (sinking current)
TSYNCOUT
Delay from HO rising to SYNCOUT
leading edge
VSYNCIN = 0 V, TS = 1/FSW, FSW set by
RRT
TSYNCIN
Delay from SYNCIN rising to HO
leading edge
–20%
50%
2
V
0.8
20
V
kΩ
50
ns
3
V
0.4
V
TS/2 –
140
ns
50% to 50%
150
ns
GATE DRIVERS
RHO-UP
HO high state resistance, HO to BST
VBST – VSW = 7 V, IHO = –100 mA
1.5
Ω
RHO-DOWN
HO low state resistance, HO to SW
VBST – VSW = 7 V, IHO = 100 mA
0.9
Ω
RLO-UP
LO high state resistance, LO to VCC
VBST – VSW = 7 V, ILO = –100 mA
1.5
Ω
RLO-DOWN
LO low state resistance, LO to PGND
VBST – VSW = 7 V, ILO = 100 mA
0.9
Ω
IHOH, ILOH
HO, LO source current
VBST – VSW = 7 V, HO = SW, LO =
AGND
2.3
A
IHOL, ILOL
HO, LO sink current
VBST – VSW = 7 V, HO = BST, LO = VCC
3.5
A
BOOTSTRAP DIODE AND UNDERVOLTAGE THRESHOLD
VBST-FWD
Diode forward voltage, VCC to BST
VCC to BST, BST pin sourcing 20 mA
IQ-BST
BST to SW quiescent current, not
switching
VSS/TRK = 0 V, VSW = 48 V, VBST = 54 V
VBST-UV
BST to SW undervoltage detection
VBST-HYS
BST to SW undervoltage hysteresis
0.75
0.9
V
80
µA
VBST – VSW falling
3.4
V
VBST – VSW rising
0.42
V
PWM CONTROL
tON(min)
Minimum controllable on-time
VBST – VSW = 7 V, HO 50% to 50%
tOFF(min)
Minimum off-time
VBST – VSW = 7 V, HO 50% to 50%
DC100kHz
DC400kHz
Maximum duty cycle
VRAMP(min)
RAMP valley voltage (COMP at 0% duty
cycle)
kFF
PWM feedforward gain (VIN / VRAMP)
40
60
ns
140
200
ns
FSW = 100 kHz, 6 V ≤ VVIN ≤ 60 V
98
99
%
FSW = 400 kHz, 6 V ≤ VVIN ≤ 60 V
90
94
%
300
mV
15
V/V
6 V ≤ VVIN ≤ 100 V
OVER CURRENT PROTECT (OCP) – VALLEY CURRENT LIMITING
IRS
ILIM source current, RSENSE mode
Low voltage detected at ILIM
IRDSON
ILIM source current, RDS-ON mode
SW voltage detected at ILIM, TJ = 25°C
IRDSONTC
ILIM current tempco
RDS-ON mode
IRSTC
ILIM current tempco
RSENSE mode
VILIM-TH
ILIM comparator threshold at ILIM
90
180
100
110
200
220
4500
–2
µA
ppm/°C
0
–8
µA
ppm/°C
3.5
mV
SHORT CIRCUIT PROTECTION (SCP) – DUTY CYCLE CLAMP
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Typical values correspond to TJ = 25°C. Minimum and maximum limits apply over the –40°C to 150°C junction temperature
range unless otherwise stated. VVIN = 48 V, VEN/UVLO = 1.5 V, RRT = 25 kΩ unless otherwise stated. (1) (2)
PARAMETER
TEST CONDITIONS
VCLAMP-OS
Clamp offset voltage – no current
limiting
COMP to duty cycle clamp voltage
VCLAMP-MIN
Minimum clamp voltage
Clamp voltage with continuous current
limit
MIN
TYP
MAX
UNIT
0.2 +
VVIN/75
V
0.3 +
VVIN/150
V
HICCUP MODE FAULT PROTECTION
CHICC-DEL
Hiccup mode activation delay
Clock cycles with current limiting before
off-time activated
128
cycles
CHICCUP
Hiccup mode off time after activation
Clock cycles with no switching followed
by SS/TRK release
8192
cycles
0
mV
200
mV
DIODE EMULATION / DCM OPERATION
VZCD-SS
Zero-cross detect (ZCD) soft-start ramp
ZCD threshold measured at SW pin 50
cycles after first HO pulse
VZCD-DIS
Zero-cross detect disable threshold
ZCD threshold measured at SW pin
1000 cycles after first HO pulse
VDEM-TH
Diode emulation zero-cross threshold
Measured at SW with VSW rising
–5
0
5
mV
THERMAL SHUTDOWN
TSD
Thermal shutdown threshold
TSD-HYS
Thermal shutdown hysteresis
(1)
(2)
TJ rising
175
°C
20
°C
All minimum and maximum limits are specified by correlating the electrical characteristics to process and temperature variations and
applied statistical process control.
The junction temperature (TJ in ℃) is calculated from the ambient temperature (TA in ℃) and power dissipation (PD in Watts) as
follows: TJ = TA + (PD × RΘJA) where RΘJA (in ℃/W) is the package thermal impedance provided in Section 7.4.
7.6 Switching Characteristics
Typical values correspond to TJ = 25℃.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
THO-TR
TLO-TR
HO, LO rise times
VBST – VSW = 7 V, CLOAD = 1 nF, 20% to 80%
7
ns
THO -TF
TLO-TF
HO, LO fall times
VBST – VSW = 7 V, CLOAD = 1 nF, 20% to 80%
4
ns
THO-DT
HO turn-on dead timne
VBST – VSW = 7 V, LO off to HO on, 50% to
50%
14
ns
TLO-DT
LO turn-on dead timne
VBST – VSW = 7 V, HO off to LO on, 50% to
50%
14
ns
10
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7.7 Typical Characteristics
VVIN = 48 V, RRT = 25 kΩ, SYNCIN tied to VCC, EN/UVLO tied to VIN (unless otherwise noted).
100
100
95
95
85
80
75
VIN = 12V
VIN = 24V
VIN = 36V
VIN = 48V
VIN = 60V
VIN = 75V
70
65
Efficiency (%)
Efficiency (%)
90
90
85
75
60
70
0
2
4
6
8
Output Current (A)
VOUT = 5 V
See Figure 9-5
10
12
FSW = 300 kHz
RRT = 33.2 kΩ
0
160
0.806
140
Min On-Time, Min Off-Time (ns)
Feedback Voltage (V)
4
Output Current (A)
6
8
FSW = 400 kHz
RRT = 24.9 kΩ
Figure 7-2. Efficiency vs Load, CCM
0.808
0.804
0.802
0.8
0.798
0.796
0.794
0.792
-50
2
VOUT = 12 V
See Figure 9-16
Figure 7-1. Efficiency vs Load, CCM
120
100
80
60
40
20
tOFF(min)
-25
0
25
50
75
100
Junction Temperature (°C)
125
0
-50
150
Figure 7-3. FB Voltage vs Junction Temperature
-25
0
tON(min)
25
50
75
100
Junction Temperature (°C)
125
150
Figure 7-4. tON(min) and tOFF(min) vs Junction
Temperature
2.2
40°C
25°C
125°C
150°C
30
20
10
0
VIN Standby Quiescent Current (mA)
40
VIN Shutdown Quiescent Current ( PA)
VIN = 15V
VIN = 24V
VIN = 36V
VIN = 48V
VIN = 60V
VIN = 75V
80
2
1.8
1.6
40°C
25°C
150°C
1.4
0
20
40
60
Input Voltage (V)
VSW = 0 V
80
VEN/UVLO = 0 V
Figure 7-5. IQ-SHD vs Input Voltage
100
0
VSW = 0 V
20
40
60
Input Voltage (V)
80
100
VEN/UVLO = 1 V
Figure 7-6. IQ-STANDBY vs Input Voltage
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4
Switching (mA)
2
1.8
1.6
40°C
25°C
150°C
3.75
3.5
VIN Operating Current
VIN Operating Quiescent Current (mA)
2.2
3.25
3
2.75
40°C
0
20
40
60
Input Voltage (V)
VSW = 0 V
VEN/UVLO = VVIN
80
0
100
VSS/TRK = 0 V
0.5
300
ILIM Current Source (PA)
VIN Operating Quiescent Current (mA)
350
0.3
0.2
0.1
VCC = 8V
0
20
VSW = 0 V
40
60
Input Voltage (V)
VVCC = VBST = VILIM
80
40
60
Input Voltage (V)
200
150
100
0
-50
VFB = 0 V
RDS-ON Mode
RSENSE Mode
20
5
VCC UVLO Threshold (V)
5.2
10
5
-25
0
25
50
75
100
Junction Temperature (°C)
-25
0
25
50
75
100
Junction Temperature (°C)
125
150
VSW = 0 V
Figure 7-11. Deadtime vs Junction Temperature
150
4.8
4.6
4.4
HO to LO
LO to HO
0
-50
125
Figure 7-10. ILIM Current Source vs Junction
Temperature
25
15
100
250
100
Figure 7-9. VIN Quiescent Current with External
VCC Applied
80
HO, LO Open
50
0
12
150°C
Figure 7-8. IQ-OPERATING (Switching) vs Input
Voltage
0.6
0.4
20
VSW = 0 V
Figure 7-7. IQ-OPERATING (Nonswitching) vs Input
Voltage
Deadtime (ns)
25°C
2.5
1.4
Rising
Falling
4.2
-50
-25
0
25
50
75
100
Junction Temperature (°C)
125
150
Figure 7-12. VCC UVLO Thresholds vs Junction
Temperature
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98
PGOOD UVP Thresholds (V)
BST UVLO Threshold (V)
4
3.8
3.6
3.4
3.2
96
94
92
90
Rising
Falling
3
-50
-25
0
25
50
75
100
Junction Temperature (°C)
125
88
-50
150
Figure 7-13. BST UVLO Thresholds vs Junction
Temperature
110
1.3
108
1.25
106
104
-25
0
25
50
75
100
Junction Temperature (°C)
125
150
Figure 7-14. PGOOD UVP Thresholds vs Junction
Temperature
EN Threshold (V)
PGOOD OVP Thresholds (V)
Rising
Falling
102
1.2
1.15
1.1
Rising
Falling
100
-50
-25
0
25
50
75
100
Junction Temperature (°C)
125
Figure 7-15. PGOOD OVP Thresholds vs Junction
Temperature
0.5
1000
0.45
800
0.4
0.35
0.3
Rising
Falling
0.25
-50
-25
0
25
50
75
100
Junction Temperature (°C)
125
150
-25
0
25
50
75
100
Junction Temperature (°C)
125
150
Figure 7-16. EN/UVLO Threshold vs Junction
Temperature
Switching Frequency (kHz)
EN Standby Threshold (V)
1.05
-50
150
600
400
200
0
0
10
20
30
40
50
60
70
RT Resistance (k:)
80
90
100
VSW = 0 V
Figure 7-17. EN Standby Thresholds vs Junction
Temperature
Figure 7-18. Oscillator Frequency vs RT
Resistance
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1000
410
400
390
VIN = 6V
VIN = 48V
VIN = 100V
380
-50
-25
0
25
50
75
100
Junction Temperature (°C)
125
Switching Frequency (kHz)
Switching Frequency (kHz)
420
990
980
970
960
950
-50
150
VIN = 6V
VIN = 48V
VIN = 100V
-25
0
Figure 7-19. Oscillator Frequency vs Junction
Temperature
150
Figure 7-20. Oscillator Frequency vs Junction
Temperature
1.6
4
3.5
HO Gate Driver RDS(on) (:)
LO, HO Gate Driver Peak Current (A)
125
RRT = 10 kΩ
RRT = 25 kΩ
3
2.5
2
1.5
1.4
1.2
1
0.8
Source
Sink
High State
Low State
1
0.6
6
7
8
9
10
VCC Voltage (V)
11
12
13
Figure 7-21. Gate Driver Peak Current vs VCC
Voltage
6
7
8
9
10
VCC Voltage (V)
11
12
13
Figure 7-22. HO Driver Resistance vs VCC Voltage
1.6
8
7.5
1.4
VCC Voltage (V)
LO Gate Driver RDS(on) (:)
25
50
75
100
Junction Temperature (°C)
1.2
1
0.8
High State
Low State
0.6
7
6.5
6
5.5
40°C
25°C
150°C
5
6
7
8
9
10
VCC Voltage (V)
11
12
13
0
20
40
60
Input Voltage (V)
80
100
VSS/TRK = 0 V
Figure 7-23. LO Driver Resistance vs VCC Voltage
14
Figure 7-24. VCC Voltage vs Input Voltage
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8
7
40°C
25°C
125°C
150°C
7
6
5
VCC Voltage (V)
VCC Voltage (V)
6
4
3
2
5
4
3
2
1
1
0
0
25°C
40°C
0
10
20
30
40
VCC Current (mA)
50
0
60
10
20
30
40
VCC Current (mA)
VIN = 5.5 V
50
60
VIN = 12 V
Figure 7-25. VCC vs ICC Characteristic
Figure 7-26. VCC vs ICC Characteristic
1
10.6
10.4
0.9
Soft-Start Current (PA)
BST Diode Forward Voltage (V)
150°C
0.8
0.7
0.6
10.2
10
9.8
9.6
VCC = 8V
0.5
0
10
20
30
40
BST Diode Forward Current (mA)
50
Figure 7-27. BST Diode Forward Voltage vs Current
9.4
-50
-25
0
25
50
75
100
Junction Temperature (°C)
125
150
Figure 7-28. SS/TRK Current Source vs Junction
Temperature
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8 Detailed Description
8.1 Overview
The LM5145-Q1 is a 75-V synchronous buck controller with all of the functions necessary to implement a highefficiency step-down power supply. The output voltage range is from 0.8 V to 60 V. The voltage-mode control
architecture uses input feedforward for excellent line transient response over a wide VIN range. Voltage-mode
control supports the wide duty cycle range for high input voltage and low dropout applications as well as when
a high-voltage conversion ratio (for example, 10-to-1) is required. Current sensing for cycle-by-cycle current limit
can be implemented with either the low-side FET RDS(on) or a current sense resistor. The operating frequency
is programmable from 100 kHz to 1 MHz. The LM5145-Q1 drives external high-side and low-side NMOS power
switches with robust 7.5-V gate drivers suitable for standard threshold MOSFETs. Adaptive dead-time control
between the high-side and low-side drivers minimizes body diode conduction during switching transitions. An
external bias supply can be connected to the VCC pin to improve efficiency in high-voltage applications. A
user-selectable diode emulation feature enables DCM operation for improved efficiency and lower dissipation at
light-load conditions.
8.2 Functional Block Diagram
VIN
VCC
7.5 V LDO
REGULATOR
+
±
VCC
UVLO
7.5 V
VCC ENABLE
0.4 V
1.2 V
SHUTDOWN
+
±
EN/UVLO
BST
±
+
VVCC-UV
ENABLE
LOGIC
+
±
5 µs
FILTER
BST_UV
³1´
STANDBY
D
R
±
+
VSW +
VBST-UV
CL Q
kFF*VIN
RT
OSCILLATOR &
FEEDFORWARD
RAMP
GENERATOR
SYNCOUT
THERMAL
SHUTDOWN
HYSTERESIS
LEVEL
SHIFT
CLK
SYNCIN
RAMP
FPWM
PWM
COMPARATOR
PWM
LOGIC
VCC
0.3 V
DRIVER
+
COMP
HO
SW
ADAPTIVE
DEADTIME
DELAY
kFF*VIN + 0.3 V
PEAK
DETECT
FILTER
DRIVER
±
LO
PGND
ERROR
AMP
FB
±
115 mV
±
0.8 V
+
+
+
+
±
+
±
ZERO CROSS
DETECTION
CLAMP
SS/TRK
COMP
CLAMP
MODULATOR
STANDBY
HICCUP
COUNTERS
SUPERVISORY
COMPARATORS
±
RDS(on) or
Shunt Sensing
0.8 V + 8%
ILIM
LO
+
PGOOD
25 µs
delay
FB
OCP
LO
±
+
16
CLK
0.8 V - 8%
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CURRENT LIMIT
COMPARATOR
±
ILIM
+
AGND
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8.3 Feature Description
8.3.1 Input Range (VIN)
The LM5145-Q1 operational input voltage range is from 5.5 V to 75 V. The device is intended for step-down
conversions from 12-V, 24-V, 48-V, 60-V, and 72-V unregulated, semiregulated, and fully-regulated supply rails.
The application circuit in Figure 8-1 shows all the necessary components to implement an LM5145-Q1-based
wide-VIN step-down regulator using a single supply. The LM5145-Q1 uses an internal LDO subregulator to
provide a 7.5-V VCC bias rail for the gate drive and control circuits (assuming the input voltage is higher than 7.5
V plus the necessary subregulator dropout specification).
RUV2
RUV1
VOUT
VIN
20
1
RC2
RRT
RFB1
EN/UVLO
CBST
Q1
VIN
2
RT
3
SS/TRK
HO 18
4
COMP
SW 19
5
FB
BST 17
CC3
RC1
CC1
CSS
CC2
RFB2
SYNC
out
SYNC
oponal
LF
VOUT
NC 16
LM5145-Q1
6
AGND
7
SYNCOUT
8
SYNCIN
9
NC
Q2
EP 15
CIN
VCC 14
COUT
LO 13
PGOOD
ILIM
10
11
GND
PGND 12
CVCC
RPG
PG
RILIM
CILIM
Figure 8-1. Schematic Diagram for VIN Operating Range of 5.5 V to 75 V
In high-voltage applications, take extra care to ensure the VIN pin does not exceed the absolute maximum
voltage rating of 100 V during line or load transient events. Voltage ringing on the VIN pin that exceeds the
values in the Absolute Maximum Ratings can damage the IC. Use high-quality ceramic input capacitors to
minimize ringing. An RC filter from the input rail to the VIN pin (for example, 4.7 Ω and 0.1 µF) provides
supplementary filtering at the VIN pin.
8.3.2 Output Voltage Setpoint and Accuracy (FB)
The reference voltage at the FB pin is set at 0.8 V with a feedback system accuracy over the full junction
temperature range of ±1%. Junction temperature range for the device is –40°C to +150°C. While dependent on
switching frequency and load current requirements, the LM5145-Q1 is generally capable of providing an output
voltage in the range of 0.8 V to a maximum of 60 V or slightly less than VIN, whichever is lower. The DC output
voltage setpoint during normal operation is set by the feedback resistor network, RFB1 and RFB2, connected to
the output.
8.3.3 High-Voltage Bias Supply Regulator (VCC)
The LM5145-Q1 contains an internal high-voltage VCC regulator that provides a bias supply for the PWM
controller and its gate drivers for the external MOSFETs. The input pin (VIN) can be connected directly to an
input voltage source up to 75 V. The output of the VCC regulator is set to 7.5 V. However, when the input
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voltage is below the VCC setpoint level, the VCC output tracks VIN with a small voltage drop. Connect a ceramic
decoupling capacitor between 1 µF and 5 µF from VCC to AGND for stability.
The VCC regulator output has a current limit of 40 mA (minimum). At power up, the regulator sources current
into the capacitor connected to the VCC pin. When the VCC voltage exceeds its rising UVLO threshold of 4.93
V, the output is enabled (if EN/UVLO is above 1.2 V), and the soft-start sequence begins. The output remains
active until the VCC voltage falls below its falling UVLO threshold of 4.67 V (typical) or if EN/UVLO goes to a
standby or shutdown state.
Internal power dissipation of the VCC regulator can be minimized by connecting the output voltage or an
auxiliary bias supply rail (up to 13 V) to VCC using a diode DVCC as shown in Figure 8-2. A diode in series with
the input prevents reverse current flow from VCC to VIN if the input voltage falls below the external VCC rail.
Required if VIN < VCC(EXT)
LM5145-Q1
DVCC
DVIN
VIN
VCC 14
20 VIN
5.5 V to 75 V
CVIN
VCC-EXT
CVCC
0.1 F
8 V to 13 V
2.2 F
AGND
6
Figure 8-2. VCC Bias Supply Connection From VOUT or Auxiliary Supply
Note that a finite bias supply regulator dropout voltage exists and is manifested to a larger extent when driving
high gate charge (QG) power MOSFETs at elevated switching frequencies. For example, at VVIN = 6 V, the VCC
voltage is 5.8 V with a DC operating current, IVCC, of 20 mA. Such a low gate drive voltage can be insufficient
to fully enhance the power MOSFETs. At the very least, MOSFET on-state resistance, RDS(ON), can increase at
such low gate drive voltage.
Here are the main considerations when operating at input voltages below 7.5 V:
•
•
•
Increased MOSFET RDS(on) at lower VGS, leading to Increased conduction losses and reduced OCP setpoint
Increased switching losses given the slower switching times when operating at lower gate voltages
Restricted range of suitable power MOSFETs to choose from (MOSFETs with RDS(on) rated at VGS = 4.5 V
become mandatory)
8.3.4 Precision Enable (EN/UVLO)
The EN/UVLO input supports adjustable input undervoltage lockout (UVLO) with hysteresis programmed by
the resistor values for application specific power-up and power-down requirements. EN/UVLO connects to a
comparator-based input referenced to a 1.2-V bandgap voltage. An external logic signal can be used to drive the
EN/UVLO input to toggle the output ON and OFF and for system sequencing or protection. The simplest way
to enable the operation of the LM5145-Q1 is to connect EN/UVLO directly to VIN. This allows self start-up of
the LM5145-Q1 when VCC is within its valid operating range. However, many applications benefit from using a
resistor divider RUV1 and RUV2 as shown in Figure 8-3 to establish a precision UVLO level.
Use Equation 1 and Equation 2 to calculate the UVLO resistors given the required input turn-on and turn-off
voltages.
RUV1
RUV2
18
VIN(on)
VIN(off)
IHYS
RUV1 ˜
(1)
VEN
VIN(on)
VEN
(2)
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vcc
LM5145-Q1
VIN
10 A
RUV1
EN/UVLO
1
RUV2
1.2 V
Remote
shutdown
Enable
comparator
Figure 8-3. Programmable Input Voltage UVLO Turn-on and Turn-off
The LM5145-Q1 enters a low IQ shutdown mode when EN/UVLO is pulled below approximately 0.4 V. The
internal LDO regulator powers off and the internal bias supply rail collapses, shutting down the bias currents of
the LM5145-Q1. The LM5145-Q1 operates in standby mode when the EN/UVLO voltage is between the hard
shutdown and precision enable (standby) thresholds.
8.3.5 Power Good Monitor (PGOOD)
The LM5145-Q1 provides a PGOOD flag pin to indicate when the output voltage is within a regulation window.
Use the PGOOD signal as shown in Figure 8-4 for start-up sequencing of downstream converters, fault
protection, and output monitoring. PGOOD is an open-drain output that requires a pullup resistor to a DC supply
not greater than 13 V. The typical range of pullup resistance is 10 kΩ to 100 kΩ. If necessary, use a resistor
divider to decrease the voltage from a higher voltage pullup rail.
VIN(on) = 15 V
VIN(off) = 10 V
VOUT(MASTER) = 5 V
LM5145-Q1
RUV1
499 k
PGOOD 10
RFB1
20 k
1 EN/UVLO
RUV2
43.2 k
FB
5
VOUT(SLAVE) = 3.3 V
LM5145-Q1
RPG
20 k
0.8 V
PGOOD 10
1
EN/UVLO
FB 5
0.8 V
RFB4
6.34 k
RFB2
3.83 k
Regulator #1
Start-up based on
input voltage UVLO
RFB3
20 k
Regulator #2
Sequential start-up
based on PGOOD
Figure 8-4. Master-Slave Sequencing Implementation Using PGOOD and EN/UVLO
When the FB voltage exceeds 94% of the internal reference VREF, the internal PGOOD switch turns off and
PGOOD can be pulled high by the external pullup. If the FB voltage falls below 92% of VREF, the internal
PGOOD switch turns on, and PGOOD is pulled low to indicate that the output voltage is out of regulation.
Similarly, when the FB voltage exceeds 108% of VREF, the internal PGOOD switch turns on, pulling PGOOD low.
If the FB voltage subsequently falls below 105% of VREF, the PGOOD switch is turned off and PGOOD is pulled
high. PGOOD has a built-in deglitch delay of 25 µs.
8.3.6 Switching Frequency (RT, SYNCIN)
There are two options for setting the switching frequency, FSW, of the LM5145-Q1, thus providing a power supply
designer with a level of flexibility when choosing external components for various applications. To adjust the
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frequency, use a resistor from the RT pin to AGND, or synchronize the LM5145-Q1 to an external clock signal
through the SYNCIN pin.
8.3.6.1 Frequency Adjust
Adjust the free-running switching frequency by using a resistor from the RT pin to AGND. The switching
frequency range is from 100 kHz to 1 MHz. The frequency set resistance, RRT, is governed by Equation 3. E96
standard-value resistors for common switching frequencies are given in Table 8-1.
4
RRT ¬ªk: ¼º
10
FSW ¬ªkHz ¼º
(3)
Table 8-1. Frequency Set Resistors
SWITCHING FREQUENCY
(kHz)
FREQUENCY SET RESISTANCE
(kΩ)
100
100
200
49.9
250
40.2
300
33.2
400
24.9
500
20
750
13.3
1000
10
8.3.6.2 Clock Synchronization
Apply an external clock synchronization signal to the LM5145-Q1 to synchronize switching in both frequency and
phase. Requirements for the external clock SYNC signal are:
•
•
•
•
Clock frequency range: 100 kHz to 1 MHz
Clock frequency: –20% to +50% of the free-running frequency set by RRT
Clock maximum voltage amplitude: 13 V
Clock minimum pulse width: 50 ns
VSW 10 V/DIV
VSYNCIN
2 V/DIV
1 Ps/DIV
Figure 8-5. Typical 400-kHz SYNCIN and SW Voltage Waveforms
Figure 8-5 shows a clock signal at 400 kHz and the corresponding SW node waveform (VIN = 48 V, VOUT = 5 V,
free-running frequency = 280 kHz). The SW voltage waveform is synchronized with respect to the rising edge of
SYNCIN. The rising edge of the SW voltage is phase delayed relative to SYNCIN by approximately 100 ns.
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8.3.7 Configurable Soft Start (SS/TRK)
After the EN/UVLO pin exceeds its rising threshold of 1.2 V, the LM5145-Q1 begins charging the output to the
DC level dictated by the feedback resistor network. The LM5145-Q1 features an adjustable soft start (set by a
capacitor from the SS/TRK pin to GND) that determines the charging time of the output. A 10-µA current source
charges this soft-start capacitor. Soft start limits inrush current as a result of high output capacitance to avoid
an overcurrent condition. Stress on the input supply rail is also reduced. The soft-start time, tSS, for the output
voltage to ramp to its nominal level is set by Equation 4.
t SS
CSS ˜ VREF
ISS
(4)
where
•
•
•
CSS is the soft-start capacitance
VREF is the 0.8-V reference
ISS is the 10-µA current sourced from the SS/TRK pin
More simply, calculate CSS using Equation 5.
CSS ¬ªnF ¼º
12.5 ˜ t SS ¬ªms ¼º
(5)
The SS/TRK pin is internally clamped to VFB + 115 mV to allow a soft start recovery from an overload event.
The clamp circuit requires a soft-start capacitance greater than 2 nF for stability and has a current limit of
approximately 2 mA.
8.3.7.1 Tracking
The SS/TRK pin also doubles as a tracking pin when master-slave power-supply tracking is required. This
tracking is achieved by simply dividing down the output voltage of the master with a simple resistor network.
Coincident, ratiometric, and offset tracking modes are possible.
If an external voltage source is connected to the SS/TRK pin, the external soft-start capability of the LM5145-Q1
is effectively disabled. The regulated output voltage level is reached when the SS/TRK pin reaches the 0.8-V
reference voltage level. It is the responsibility of the system designer to determine if an external soft-start
capacitor is required to keep the device from entering current limit during a start-up event. Likewise, the system
designer must also be aware of how fast the input supply ramps if the tracking feature is enabled.
SS/TRK
160mV/DIV
94% VOUT
92% VOUT
VOUT 1V/DIV
PGOOD
2V/DIV
10 ms/DIV
Figure 8-6. Typical Output Voltage Tracking and PGOOD Waveforms
Figure 8-6 shows a triangular voltage signal directly driving SS/TRK and the corresponding output voltage
tracking response. Nominal output voltage here is 5 V, with oscilloscope channel scaling chosen such that the
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waveforms overlap during tracking. As expected, the PGOOD flag transitions at thresholds of 94% (rising) and
92% (falling) of the nominal output voltage setpoint.
Two practical tracking configurations, ratiometric and coincident, are shown in Figure 8-7. The most common
application is coincident tracking, used in core versus I/O voltage tracking in DSP and FPGA implementations.
Coincident tracking forces the master and slave channels to have the same output voltage ramp rate until the
slave output reaches its regulated setpoint. Conversely, ratiometric tracking sets the output voltage of the slave
to a fraction of the output voltage of the master during start-up.
VOUTMASTER = 3.3 V
Slave regulator #1
Ratiometric tracking
Slave regulator #2
Coincident tracking
VOUTSLAVE1 = 1.8 V
LM5145-Q1
LM5145-Q1
RTRK1
26.7 k
RFB1
12.5 k
3 SS/TRK
RTRK2
10 k
VOUTSLAVE2 = 1.2 V
FB
5
CSS1
RFB3
10 k
3
0.8 V
RFB2
10 k
2.2 nF
RTRK3
10 k
RTRK4
20 k
SS/TRK
FB
5
CSS2
0.8 V
RFB4
20 k
2.2 nF
SYNCIN
SYNCIN
8
8
SYNCOUT
from Master
Figure 8-7. Tracking Implementation with Master, Ratiometric Slave, and Coincident Slave Rails
For coincident tracking, connect the SS/TRK input of the slave regulator to a resistor divider from the output
voltage of the master that is the same as the divider used on the FB pin of the slave. In other words, simply
select RTRK3 = RFB3 and RTRK4 = RFB4 as shown in Figure 8-7. As the master voltage rises, the slave voltage
rises identically (aside from the 80-mV offset from SS/TRK to FB when VFB is below 0.8 V). Eventually, the slave
voltage reaches its regulation voltage, at which point the internal reference takes over the regulation while the
SS/TRK input continues to 115 mV above FB, and no longer controls the output voltage.
In all cases, to ensure that the output voltage accuracy is not compromised by the SS/TRK voltage being too
close to the 0.8-V reference voltage, the final value of the SS/TRK voltage of the slave should be at least 100
mV above FB.
8.3.8 Voltage-Mode Control (COMP)
The LM5145-Q1 incorporates a voltage-mode control loop implementation with input voltage feedforward to
eliminate the input voltage dependence of the PWM modulator gain. This configuration allows the controller to
maintain stability throughout the entire input voltage operating range and provides optimal response to input
voltage transient disturbances. The constant gain provided by the controller greatly simplifies loop compensation
design because the loop characteristics remain constant as the input voltage changes, unlike a buck converter
without voltage feedforward. An increase in input voltage is matched by a concomitant increase in ramp voltage
amplitude to maintain constant modulator gain. The input voltage feedforward gain, kFF, is 15, equivalent to the
input voltage divided by the ramp amplitude, VIN/VRAMP. See Section 9.1.3 for more detail.
8.3.9 Gate Drivers (LO, HO)
The LM5145-Q1 gate driver impedances are low enough to perform effectively in high output current applications
where large die-size or paralleled MOSFETs with correspondingly large gate charge, QG, are used. Measured at
VVCC = 7.5 V, the low-side driver of the LM5145-Q1 has a low impedance pulldown path of 0.9 Ω to minimize
the effect of dv/dt induced turn-on, particularly with low gate-threshold voltage MOSFETs. Similarly, the high-side
driver has 1.5-Ω and 0.9-Ω pullup and pulldown impedances, respectively, for faster switching transition times,
lower switching loss, and greater efficiency.
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The high-side gate driver works in conjunction with an integrated bootstrap diode and external bootstrap
capacitor, CBST. When the low-side MOSFET conducts, the SW voltage is approximately at 0 V and CBST is
charged from VCC through the integrated boot diode. Connect a 0.1-μF or larger ceramic capacitor close to the
BST and SW pins.
Furthermore, there is a proprietary adaptive dead-time control on both switching edges to prevent shoot-through
and cross-conduction, minimize body diode conduction time, and reduce body diode reverse recovery losses.
8.3.10 Current Sensing and Overcurrent Protection (ILIM)
The LM5145-Q1 implements a lossless current sense scheme designed to limit the inductor current during an
overload or short-circuit condition. Figure 8-8 portrays the popular current sense method using the on-state
resistance of the low-side MOSFET. Meanwhile, Figure 8-9 shows an alternative implementation with current
shunt resistor, RS. The LM5145-Q1 senses the inductor current during the PWM off-time (when LO is high).
VIN
VIN
Q1
Q1
LF
HO
HO
LF
VOUT
VOUT
SW
SW
RILIM
Q2
LO
ILIM
COUT
COUT
ILIM
Q2
RILIM
LO
GND
GND
Figure 8-8. MOSFET RDS(on) Current Sensing
RS
Figure 8-9. Shunt Resistor Current Sensing
The ILIM pin of the LM5145-Q1 sources a reference current that flows in an external resistor, designated RILIM,
to program of the current limit threshold. A current limit comparator on the ILIM pin prevents further SW pulses if
the ILIM pin voltage goes below GND. Figure 8-10 shows the implementation.
Resistor RILIM is tied to SW to use the RDS(on) of the low-side MOSFET as a sensing element (termed RDS(on)
mode). Alternatively, RILIM is tied to a shunt resistor connected at the source of the low-side MOSFET (termed
RSENSE mode). The LM5145-Q1 detects the appropriate mode at start-up and sets the source current amplitude
and temperature coefficient (TC) accordingly.
The ILIM current with RDS-ON sensing is 200 µA at 27°C junction temperature and incorporates a TC of +4500
ppm/°C to generally track the RDS(on) temperature variation of the low-side MOSFET. Conversely, the ILIM
current is a constant 100 µA in RSENSE mode. This controls the valley of the inductor current during a steadystate overload at the output. Depending on the chosen mode, select the resistance of RILIM using Equation 6.
RILIM
- IOUT 'IL 2
˜ RDS(on)Q2 , RDS(on) sensing
° I
° RDSON
®
° IOUT 'IL 2
˜ RS , shunt sensing
°
IRS
¯
(6)
where
•
•
•
•
ΔIL is the peak-to-peak inductor ripple current
RDS(on)Q2 is the on-state resistance of the low-side MOSFET
IRDSON is the ILIM pin current in RDS-ON mode
RS is the resistance of the current-sensing shunt element
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•
IRS is the ILIM pin current in RSENSE mode
Given the large voltage swings of ILIM in RDS(on) sensing mode, a capacitor designated CILIM connected from
ILIM to PGND is essential to the operation of the valley current limit circuit. Choose this capacitance such that
the time constant RILIM· CILIM is approximately 6 ns.
VIN
CLK
COMP
S
Q
R
Q
ValleyPWM
PWML
Error Amp
FB
PWM Comp
VREF
Q1
HO
IRAMP
S
Q
R
Q
Gate
Driver
+
+
PWM
Latch
VRAMP
VOUT
Q2
LO
ILIM
+
±
LF
SW
RILIM
COUT
IRDSON(TJ)
300 mV
CILIM
PWM Aux
COMP
Clamp
Modulator
+
ILIM
comparator
VCLAMP
+
PGND
GND
Figure 8-10. OCP Setpoint Defined by Current Source IRDSON and Resistor RILIM in RDS-ON Mode
Note that current sensing with a shunt component is typically implemented at lower output current levels
to provide accurate overcurrent protection. Burdened by the unavoidable efficiency penalty, PCB layout, and
additional cost implications, this configuration is not usually implemented in high-current applications (except
where OCP setpoint accuracy and stability over the operating temperature range are critical specifications).
8.3.11 OCP Duty Cycle Limiter
Short
Applied
CLAMP
COMP
Many
cycles
RAMP
300 mV
ILIM Threshold
Inductor Current
CLK
PWML
ValleyPWM
PWML terminated by
VRAMP > VCOMP
PWML terminated by
VRAMP > VCLAMP
Figure 8-11. OCP Duty Cycle Limiting Waveforms
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In addition to valley current limiting, the LM5145-Q1 uses a proprietary duty-cycle limiter circuit to reduce the
PWM on-time during an overcurrent condition. As shown in Figure 8-10, an auxiliary PWM comparator along
with a modulated CLAMP voltage limits how quickly the on-time increases in response to a large step in the
COMP voltage that typically occurs with a voltage-mode control loop architecture.
As depicted in Figure 8-11, the CLAMP voltage, VCLAMP, is normally regulated above the COMP voltage to
provide adequate headroom during a response to a load-on transient. If the COMP voltage rises quickly during
an overloaded or shorted output condition, the on-time pulse terminates, thereby limiting the on-time and peak
inductor current. Moreover, the CLAMP voltage is reduced if additional valley current limit events occur, further
reducing the average output current. If the overcurrent condition exists for 128 continuous clock cycles, a hiccup
event is triggered and SS is pulled low for 8192 clock cycles before a soft-start sequence is initiated.
8.4 Device Functional Modes
8.4.1 Shutdown Mode
The EN/UVLO pin provides ON / OFF control for the LM5145-Q1. When the EN/UVLO voltage is below 0.37 V
(typical), the device is in shutdown mode. Both the internal bias supply LDO and the switching regulator are off.
The quiescent current in shutdown mode drops to 13.5 μA (typical) at VIN = 48 V. The LM5145-Q1 also includes
undervoltage protection of the internal bias LDO. If the internal bias supply voltage is below its UVLO threshold
level, the switching regulator remains off.
8.4.2 Standby Mode
The internal bias supply LDO has a lower enable threshold than the switching regulator. When the EN/UVLO
voltage exceeds 0.42 V (typical) and is below the precision enable threshold (1.2 V typically), the internal LDO is
on and regulating. Switching action and output voltage regulation are disabled in standby mode.
8.4.3 Active Mode
The LM5145-Q1 is in active mode when the VCC voltage is above its rising UVLO threshold of 5 V and the
EN/UVLO voltage is above the precision EN threshold of 1.2 V. The simplest way to enable the LM5145-Q1 is
to tie EN/UVLO to VIN. This allows self start-up of the LM5145-Q1 when the input voltage exceeds the VCC
threshold plus the LDO dropout voltage from VIN to VCC.
8.4.4 Diode Emulation Mode
The LM5145-Q1 provides a diode emulation feature that can be enabled to prevent reverse (drain-to-source)
current flow in the low-side MOSFET. When configured for diode emulation, the low-side MOSFET is switched
off when reverse current flow is detected by sensing of the SW voltage using a zero-cross comparator. The
benefit of this configuration is lower power loss at no-load and light-load conditions, the disadvantage being
slower light-load transient response.
The diode emulation feature is configured with the SYNCIN pin. To enable diode emulation and thus achieve
discontinuous conduction mode (DCM) operation at light loads, connect the SYNCIN pin to AGND or leave
SYNCIN floating. If forced PWM (FPWM) continuous conduction mode (CCM) operation is desired, tie SYNCIN
to VCC either directly or using a pullup resistor. Note that diode emulation mode is automatically engaged to
prevent reverse current flow during a prebias start-up. A gradual change from DCM to CCM operation provides
monotonic start-up performance.
8.4.5 Thermal Shutdown
The LM5145-Q1 includes an internal junction temperature monitor. If the temperature exceeds 175°C (typical),
thermal shutdown occurs. When entering thermal shutdown, the device:
1. Turns off the high-side and low-side MOSFETs.
2. Pulls SS/TRK and PGOOD low.
3. Turns off the VCC regulator.
4. Initiates a soft-start sequence when the die temperature decreases by the thermal shutdown hysteresis of
20°C (typical).
This is a non-latching protection, and the device will cycle into and out of thermal shutdown if the fault persists.
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9 Application and Implementation
Note
Information in the following applications sections is not part of the TI component specification,
and TI does not warrant its accuracy or completeness. TI’s customers are responsible for
determining suitability of components for their purposes, as well as validating and testing their design
implementation to confirm system functionality.
9.1 Application Information
9.1.1 Design and Implementation
To expedite the process of designing of a LM5145-Q1-based regulator for a given application, use the LM5145Q1 Quickstart Calculator available as a free download, as well as numerous LM5145-Q1 reference designs
populated in TI Designs™ reference design library, or the designs provided in Section 9.2. The LM5145-Q1 is
also WEBENCH® Designer enabled.
9.1.2 Power Train Components
Comprehensive knowledge and understanding of the power train components are key to successfully completing
a synchronous buck regulator design.
9.1.2.1 Inductor
For most applications, choose an inductance such that the inductor ripple current, ΔIL, is between 30% and 40%
of the maximum DC output current at nominal input voltage. Choose the inductance using Equation 7 based on a
peak inductor current given by Equation 8.
LF
VOUT § VIN VOUT ·
˜¨
¸
VIN © 'IL ˜ FSW ¹
IL(peak)
IOUT
(7)
'IL
2
(8)
Check the inductor data sheet to ensure that the saturation current of the inductor is well above the peak
inductor current of a particular design. Ferrite designs have very low core loss and are preferred at high
switching frequencies, so design goals can then concentrate on copper loss and preventing saturation. Low
inductor core loss is evidenced by reduced no-load input current and higher light-load efficiency. However, ferrite
core materials exhibit a hard saturation characteristic and the inductance collapses abruptly when the saturation
current is exceeded. This results in an abrupt increase in inductor ripple current, higher output voltage ripple,
not to mention reduced efficiency and compromised reliability. Note that the saturation current of an inductor
generally decreases as its core temperature increases. Of course, accurate overcurrent protection is key to
avoiding inductor saturation.
9.1.2.2 Output Capacitors
Ordinarily, the output capacitor energy store of the regulator combined with the control loop response are
prescribed to maintain the integrity of the output voltage within the dynamic (transient) tolerance specifications.
The usual boundaries restricting the output capacitor in power management applications are driven by finite
available PCB area, component footprint and profile, and cost. The capacitor parasitics—equivalent series
resistance (ESR) and equivalent series inductance (ESL)—take greater precedence in shaping the load transient
response of the regulator as the load step amplitude and slew rate increase.
The output capacitor, COUT, filters the inductor ripple current and provides a reservoir of charge for step-load
transient events. Typically, ceramic capacitors provide extremely low ESR to reduce the output voltage ripple
and noise spikes, while tantalum and electrolytic capacitors provide a large bulk capacitance in a relatively
compact footprint for transient loading events.
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Based on the static specification of peak-to-peak output voltage ripple denoted by ΔVOUT, choose an output
capacitance that is larger than that given by Equation 9.
'IL
COUT t
8 ˜ FSW 'VOUT
2
RESR ˜ 'IL
2
(9)
Figure 9-1 conceptually illustrates the relevant current waveforms during both load step-up and step-down
transitions. As shown, the large-signal slew rate of the inductor current is limited as the inductor current ramps
to match the new load-current level following a load transient. This slew-rate limiting exacerbates the deficit
of charge in the output capacitor, which must be replenished as rapidly as possible during and after the load
step-up transient. Similarly, during and after a load step-down transient, the slew rate limiting of the inductor
current adds to the surplus of charge in the output capacitor that must be depleted as quickly as possible.
IOUT1
'IOUT
diL
dt
VOUT
LF
inductor current, iL(t)
'QC
IOUT2
diOUT
dt
load current,
iOUT(t)
'IOUT
tramp
inductor current, iL(t)
IOUT2
'QC
diL
dt
'IOUT
VIN
VOUT
LF
load current, iOUT(t)
IOUT1
tramp
Figure 9-1. Load Transient Response Representation Showing COUT Charge Surplus or Deficit
In a typical regulator application of 48-V input to low output voltage (for example, 5 V), the load-off transient
represents the worst case in terms of output voltage transient deviation. In that conversion ratio application, the
steady-state duty cycle is approximately 10% and the large-signal inductor current slew rate when the duty cycle
collapses to zero is approximately –VOUT/L. Compared to a load-on transient, the inductor current takes much
longer to transition to the required level. The surplus of charge in the output capacitor causes the output voltage
to significantly overshoot. In fact, to deplete this excess charge from the output capacitor as quickly as possible,
the inductor current must ramp below its nominal level following the load step. In this scenario, a large output
capacitance can be advantageously employed to absorb the excess charge and limit the voltage overshoot.
To meet the dynamic specification of output voltage overshoot during such a load-off transient (denoted as
ΔVOVERSHOOT with step reduction in output current given by ΔIOUT), the output capacitance should be larger than
LF ˜ 'IOUT
COUT t
VOUT
2
'VOVERSHOOT
2
VOUT
2
(10)
The ESR of a capacitor is provided in the manufacturer’s data sheet either explicitly as a specification or
implicitly in the impedance vs. frequency curve. Depending on type, size and construction, electrolytic capacitors
have significant ESR, 5 mΩ and above, and relatively large ESL, 5 nH to 20 nH. PCB traces contribute some
parasitic resistance and inductance as well. Ceramic output capacitors, on the other hand, have low ESR and
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ESL contributions at the switching frequency, and the capacitive impedance component dominates. However,
depending on package and voltage rating of the ceramic capacitor, the effective capacitance can drop quite
significantly with applied DC voltage and operating temperature.
Ignoring the ESR term in Equation 9 gives a quick estimation of the minimum ceramic capacitance necessary
to meet the output ripple specification. One to four 47-µF, 10-V, X7R capacitors in 1206 or 1210 footprint is
a common choice. Use Equation 10 to determine if additional capacitance is necessary to meet the load-off
transient overshoot specification.
A composite implementation of ceramic and electrolytic capacitors highlights the rationale for paralleling
capacitors of dissimilar chemistries yet complementary performance. The frequency response of each capacitor
is accretive in that each capacitor provides desirable performance over a certain portion of the frequency range.
While the ceramic provides excellent mid- and high-frequency decoupling characteristics with its low ESR and
ESL to minimize the switching frequency output ripple, the electrolytic device with its large bulk capacitance
provides low-frequency energy storage to cope with load transient demands.
9.1.2.3 Input Capacitors
Input capacitors are necessary to limit the input ripple voltage to the buck power stage due to switchingfrequency AC currents. TI recommends using X5R or X7R dielectric ceramic capacitors to provide low
impedance and high RMS current rating over a wide temperature range. To minimize the parasitic inductance in
the switching loop, position the input capacitors as close as possible to the drain of the high-side MOSFET and
the source of the low-side MOSFET. The input capacitor RMS current is given by Equation 11.
ICIN,rms
§
2
D ˜ ¨ IOUT ˜ 1 D
¨
©
2
'IL ·
¸
12 ¸
¹
(11)
The highest input capacitor RMS current occurs at D = 0.5, at which point the RMS current rating of the
capacitors should be greater than half the output current.
Ideally, the DC component of input current is provided by the input voltage source and the AC component by the
input filter capacitors. Neglecting inductor ripple current, the input capacitors source current of amplitude (IOUT −
IIN) during the D interval and sinks IIN during the 1−D interval. Thus, the input capacitors conduct a square-wave
current of peak-to-peak amplitude equal to the output current. It follows that the resultant capacitive component
of AC ripple voltage is a triangular waveform. Together with the ESR-related ripple component, the peak-to-peak
ripple voltage amplitude is given by Equation 12.
'VIN
IOUT ˜ D ˜ 1 D
FSW ˜ CIN
IOUT ˜ RESR
(12)
The input capacitance required for a particular load current, based on an input voltage ripple specification of
ΔVIN, is given by Equation 13.
CIN t
D ˜ 1 D ˜ IOUT
FSW ˜ 'VIN RESR ˜ IOUT
(13)
Low-ESR ceramic capacitors can be placed in parallel with higher valued bulk capacitance to provide optimized
input filtering for the regulator and damping to mitigate the effects of input parasitic inductance resonating with
high-Q ceramics. One bulk capacitor of sufficiently high current rating and two or three 2.2-μF 100-V X7R
ceramic decoupling capacitors are usually sufficient. Select the input bulk capacitor based on its ripple current
rating and operating temperature.
9.1.2.4 Power MOSFETs
The choice of power MOSFETs has significant impact on DC/DC regulator performance. A MOSFET with
low on-state resistance, RDS(on), reduces conduction loss, whereas low parasitic capacitances enable faster
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transition times and reduced switching loss. Normally, the lower the RDS(on) of a MOSFET, the higher the gate
charge and output charge (QG and QOSS respectively), and vice versa. As a result, the product RDS(on) × QG
is commonly specified as a MOSFET figure-of-merit. Low thermal resistance ensures that the MOSFET power
dissipation does not result in excessive MOSFET die temperature.
The main parameters affecting power MOSFET selection in a LM5145-Q1 application are as follows:
•
•
•
•
•
•
RDS(on) at VGS = 7.5 V
Drain-source voltage rating, BVDSS, typically 60 V, 80 V, or 100 V, depending on maximum input voltage
Gate charge parameters at VGS = 7.5 V
Output charge, QOSS, at the relevant input voltage
Body diode reverse recovery charge, QRR
Gate threshold voltage, VGS(th), derived from the Miller plateau evident in the QG versus VGS plot in the
MOSFET data sheet. With a Miller plateau voltage typically in the range of 2 V to 5 V, the 7.5-V gate drive
amplitude of the LM5145-Q1 provides an adequately-enhanced MOSFET when on and a margin against
Cdv/dt shoot-through when off.
The MOSFET-related power losses are summarized by the equations presented in Table 9-1, where suffixes 1
and 2 represent high-side and low-side MOSFET parameters, respectively. While the influence of inductor ripple
current is considered, second-order loss modes, such as those related to parasitic inductances and SW node
ringing, are not included. Consult the LM5145-Q1 Quickstart Calculator to assist with power loss calculations.
Table 9-1. Buck Regulator MOSFET Power Losses
POWER LOSS MODE
MOSFET conduction(2)
(3)
MOSFET switching
MOSFET gate drive(1)
HIGH-SIDE MOSFET
Pcond1
Psw1
§
2
D ˜ ¨ IOUT
¨
©
VIN ˜ FSW ª§
Ǭ IOUT
2
©
PGate1
'IL
2
Body diode reverse
recovery(5)
(1)
(2)
(3)
(4)
(5)
·
¸ ˜ RDS(on)1
12 ¸
¹
·
¸ ˜ tR
¹
'IL
2
§
¨ IOUT
©
Pcond2
PCoss
§
2
Dc ˜ ¨ IOUT
¨
©
· º
¸ ˜ tF »
¹ ¼
PGate2
FSW ˜ VIN ˜ Qoss2
N/A
VCC ˜ FSW ˜ QG2
Eoss1 Eoss2
PcondBD
PRR
2
'IL ·
¸ ˜ RDS(on)2
12 ¸
¹
Negligible
VCC ˜ FSW ˜ QG1
MOSFET output
charge(4)
Body diode conduction
LOW-SIDE MOSFET
2
'IL
ª§
VF ˜ FSW «¨ IOUT
©
'IL
2
·
§
¸ ˜ t dt1 ¨ IOUT
¹
©
'IL
2
º
·
¸ ˜ t dt2 »
¹
¼
VIN ˜ FSW ˜ QRR2
Gate drive loss is apportioned based on the internal gate resistance of the MOSFET, externally-added series gate resistance and the
relevant gate driver resistance of the LM5145-Q1.
MOSFET RDS(on) has a positive temperature coefficient of approximately 4500 ppm/°C. The MOSFET junction temperature, TJ, and its
rise over ambient temperature is dependent upon the device total power dissipation and its thermal impedance. When operating at or
near minimum input voltage, ensure that the MOSFET RDS(on) is rated at VGS = 4.5 V.
D' = 1–D is the duty cycle complement.
MOSFET output capacitances, Coss1 and Coss2, are highly non-linear with voltage. These capacitances are charged losslessly by the
inductor current at high-side MOSFET turn-off. During turn-on, however, a current flows from the input to charge Coss2 of the low-side
MOSFET. Eoss1, the energy of Coss1, is dissipated at turnon, but this is offset by the stored energy Eoss2 on Coss2.
MOSFET body diode reverse recovery charge, QRR, depends on many parameters, particularly forward current, current transition
speed, and temperature.
The high-side (control) MOSFET carries the inductor current during the PWM on-time (or D interval) and typically
incurs most of the switching losses. It is therefore imperative to choose a high-side MOSFET that balances
conduction and switching loss contributions. The total power dissipation in the high-side MOSFET is the sum of
the losses due to conduction, switching (voltage-current overlap), output charge, and typically two-thirds of the
net loss attributed to body diode reverse recovery.
The low-side (synchronous) MOSFET carries the inductor current when the high-side MOSFET is off (or 1–D
interval). The low-side MOSFET switching loss is negligible as it is switched at zero voltage – current just
commutates from the channel to the body diode or vice versa during the transition deadtimes. The LM5145-Q1,
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with its adaptive gate drive timing, minimizes body diode conduction losses when both MOSFETs are off. Such
losses scale directly with switching frequency.
In high step-down ratio applications, the low-side MOSFET carries the current for a large portion of the switching
period. Therefore, to attain high efficiency, it is critical to optimize the low-side MOSFET for low RDS(on). In cases
where the conduction loss is too high or the target RDS(on) is lower than available in a single MOSFET, connect
two low-side MOSFETs in parallel. The total power dissipation of the low-side MOSFET is the sum of the losses
due to channel conduction, body diode conduction, and typically one-third of the net loss attributed to body diode
reverse recovery. The LM5145-Q1 is well suited to drive TI's portfolio of NexFET™ power MOSFETs.
9.1.3 Control Loop Compensation
The poles and zeros inherent to the power stage and compensator are respectively illustrated by red and blue
dashed rings in the schematic embedded in Table 9-2. The compensation network typically employed with
voltage-mode control is a Type-III circuit with three poles and two zeros. One compensator pole is located at
the origin to realize high DC gain. The normal compensation strategy uses two compensator zeros to counteract
the LC double pole, one compensator pole located to nullify the output capacitor ESR zero, with the remaining
compensator pole located at one-half switching frequency to attenuate high frequency noise. The resistor divider
network to FB determines the desired output voltage. Note that the lower feedback resistor, RFB2, has no
impact on the control loop from an AC standpoint because the FB node is the input to an error amplifier and is
effectively at AC ground. Hence, the control loop is designed irrespective of output voltage level. The proviso
here is the necessary output capacitance derating with bias voltage and temperature.
Table 9-2. Buck Regulator Poles and Zeros
VIN
Power Stage
Q1
&L
D
Adaptive
Gate
Driver
&o
VOUT
&ESR
IOUT
RESR
LF
RDAMP
Q2
Modulator
COUT
RL
PWM Ramp
VRAMP
GND
Compensator
+
PWM
Comparator
Error
Amp
COMP
+
VREF
CC3 &p2 RC2
FB
CC1 &z1 RC1
RFB1
&z2
RFB2
&p1
CC2
POWER STAGE POLES
1
Zo
#
§ 1 RESR RL ·
LF ˜ COUT ¨
¸
© 1 RESR RDAMP ¹
1
LF ˜ COUT
POWER STAGE ZEROS
1
RESR ˜ COUT
ZESR
ZL
LF
RDAMP
COMPENSATOR POLES
Zp1
COMPENSATOR ZEROS
1
1
#
RC1 ˜ (CC1 CC2 ) RC1 ˜ CC2
Zp2
1
RC2 ˜ CC3
Zz1
Zz2
1
RC1 ˜ CC1
1
(RFB1 RC2 ) ˜ CC3
(1) (2)
(1)
(2)
RESR represents the ESR of the output capacitor COUT.
RDAMP = D · RDS(on)high-side + (1–D) · RDS(on) low-side + RDCR, shown as a lumped element in the schematic, represents the effective
series damping resistance.
The small-signal open-loop response of a buck regulator is the product of modulator, power train and
compensator transfer functions. The power stage transfer function can be represented as a complex pole pair
30
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associated with the output LC filter and a zero related to the ESR of the output capacitor. The DC (and low
frequency) gain of the modulator and power stage is VIN/VRAMP. The gain from COMP to the average voltage at
the input of the LC filter is held essentially constant by the PWM line feedforward feature of the LM5145-Q1 (15
V/V or 23.5 dB).
Complete expressions for small-signal frequency analysis are presented in Table 9-3. The transfer functions are
denoted in normalized form. While the loop gain is of primary importance, a regulator is not specified directly
by its loop gain but by its performance related characteristics, namely closed-loop output impedance and audio
susceptibility.
Table 9-3. Buck Regulator Small-Signal Analysis
TRANSFER FUNCTION
EXPRESSION
Open-loop transfer function
Tv (s)
Duty-cycle-to-output transfer function
Ö
vÖ comp (s) vÖ o (s)
d(s)
˜
˜
Ö
vÖ o (s)
d(s) vÖ comp (s)
Gvd (s)
Compensator transfer function(1)
Gc (s)
Modulator transfer function
FM
(1)
1
vÖ o (s)
Ö
vÖ in (s)
d(s)
0
Öi (s) 0
o
vÖ comp (s)
vÖ o (s)
Ö
d(s)
vÖ comp (s)
K mid
VIN
1
Gc (s) ˜ Gvd (s) ˜ FM
s
ZESR
2
s
s
QoZo
Zo
2
s
§ Zz1 · §
¨1 s ¸ ¨1 Z
©
¹©
z2
§
·§
s
s
¨1
¸¨ 1
¨ Zp1 ¸¨ Zp2
©
¹©
·
¸
¹
·
¸
¸
¹
1
VRAMP
Kmid = RC1/RFB1 is the mid-band gain of the compensator. By expressing one of the compensator zeros in inverted zero format, the
mid-band gain is denoted explicitly.
Figure 9-2 shows the open-loop response gain and phase. The poles and zeros of the system are marked with
x and o symbols, respectively, and a + symbol indicates the crossover frequency. When plotted on a log (dB)
scale, the open-loop gain is effectively the sum of the individual gain components from the modulator, power
stage, and compensator (see Figure 9-3). The open-loop response of the system is measured experimentally by
breaking the loop, injecting a variable-frequency oscillator signal, and recording the ensuing frequency response
using a network analyzer setup.
40
0
Loop
Gain
Complex
LC Double
Pole
Crossover
Frequency, fc
20
Loop
Gain
(dB)
Compensator
Poles
Compensator
Zeros
0
Loop
Phase
Loop
-90 Phase
(°)
NM
-135
-20
-40
1
-45
Output
Capacitor
ESR Zero
10
100
-180
1000
Frequency (kHz)
Figure 9-2. Typical Buck Regulator Loop Gain and Phase With Voltage-Mode Control
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If the pole located at ωp1 cancels the zero located at ωESR and the pole at ωp2 is located well above crossover,
the expression for the loop gain, Tv(s) in Table 9-3, can be manipulated to yield the simplified expression given in
Equation 14.
Tv (s)
RC1 ˜ CC3 ˜
2
VIN
˜
Zo
VRAMP
s
(14)
Essentially, a multi-order system is reduced to a single-order approximation by judicious choice of compensator
components. A simple solution for the crossover frequency (denoted as fc in Figure 9-2) with Type-III voltagemode compensation is derived as shown in Equation 15 and Equation 16.
Zc
K mid
2 S ˜ fc
Zo ˜ K mid ˜
fc 1
˜
fo kFF
VIN
VRAMP
(15)
RC1
RFB1
(16)
40
Modulator
Gain
Loop Gain
Compensator
Gain
20
Gain
(dB)
0
-20
Filter Gain
-40
1
10
fc 100
1000
Frequency (kHz)
Figure 9-3. Buck Regulator Constituent Gain Components
The loop crossover frequency is usually selected between one-tenth to one-fifth of switching frequency. Inserting
an appropriate crossover frequency into Equation 16 gives a target for the mid-band gain of the compensator,
Kmid. Given an initial value for RFB1, RFB2 is then selected based on the desired output voltage. Values for RC1,
RC2, CC1, CC2, and CC3 are calculated from the design expressions listed in Table 9-4, with the premise that the
compensator poles and zeros are set as follows: ωz1 = 0.5·ωo, ωz2 = ωo, ωp1 = ωSW/2, and ωp2 = ωESR.
Table 9-4. Compensation Component Selection
RESISTORS
RFB2
32
RFB1
VOUT VREF
CAPACITORS
CC1
1
RC1
K mid ˜ RFB1
CC2
RC2
1
Zp2 ˜ CC3
CC3
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1
Zz1 ˜ RC1
1
Zp1 ˜ RC1
1
Zz2 ˜ RFB1
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Referring to the bode plot in Figure 9-2, the phase margin, indicated as φM, is the difference between the loop
phase and –180° at crossover. A target of 50° to 70° for this parameter is considered ideal. Additional phase
boost is dialed in by locating the compensator zeros at a frequency lower than the LC double pole. This helps
mitigate the phase dip associated with the LC filter, particularly at light loads when the Q-factor is higher and
the phase dip becomes especially prominent. The ramification of low phase in the frequency domain is an
under-damped transient response in the time domain.
The power supply designer now has all the necessary expressions to optimally position the loop crossover
frequency while maintaining adequate phase margin over the required line, load and temperature operating
ranges. The LM5145-Q1 Quickstart Calculator is available to expedite these calculations and to adjust the bode
plot as needed.
9.1.4 EMI Filter Design
Switching regulators exhibit negative input impedance, which is lowest at the minimum input voltage. An
underdamped LC filter exhibits a high output impedance at the resonant frequency of the filter. For stability,
the filter output impedance must be less than the absolute value of the converter input impedance.
ZIN
VIN(min)
2
PIN
(17)
The EMI filter design steps are as follows:
•
•
•
Calculate the required attenuation of the EMI filter at the switching frequency, where CIN represents the
existing capacitance at the input of the switching converter.
Input filter inductor LIN is usually selected between 1 μH and 10 μH, but it can be lower to reduce losses in a
high current design.
Calculate input filter capacitor CF.
LIN
Q1
VIN
LF
CD
VOUT
CIN
CF
Q2
RD
COUT
GND
GND
Figure 9-4. Buck Regulator With π-Stage EMI Filter
By calculating the first harmonic current from the Fourier series of the input current waveform and multiplying it
by the input impedance (the impedance is defined by the existing input capacitor CIN), a formula is derived to
obtain the required attenuation as shown by Equation 18.
Attn
§ IL(PEAK)
1 ·
¸ VMAX
20log ¨ 2
˜ sin S ˜ DMAX ˜
¨ S ˜F ˜ C
1 9¸
SW
IN
©
¹
(18)
where
•
•
VMAX is the noise specification in dBμV from the applicable EMI standard, for example CISPR 25 Class 5
CIN is the existing input capacitance of the buck regulator
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•
•
DMAX is the maximum duty cycle
IPEAK is the peak inductor current
For filter design purposes, the current at the input can be modeled as a square-wave. Determine the EMI filter
capacitance CF from Equation 19.
CF
Attn
§
¨
1 10 40
¨
LIN ¨ 2S ˜ FSW
¨
©
·
¸
¸
¸
¸
¹
2
(19)
Adding an input filter to a switching regulator modifies the control-to-output transfer function. The output
impedance of the filter must be sufficiently small such that the input filter does not significantly affect the loop
gain of the buck converter. The impedance peaks at the filter resonant frequency. The resonant frequency of the
filter is given by Equation 20.
fres
1
2S ˜ LIN ˜ CF
(20)
The purpose of RD is to reduce the peak output impedance of the filter at the resonant frequency. Capacitor CD
blocks the DC component of the input voltage to avoid excessive power dissipation in RD. Capacitor CD must
have lower impedance than RD at the resonant frequency with a capacitance value greater than that of the input
capacitor CIN. This prevents CIN from interfering with the cutoff frequency of the main filter. Added damping is
needed when the output impedance of the filter is high at the resonant frequency (Q of filter formed by LIN and
CIN is too high). An electrolytic capacitor CD can be used for damping with a value given by Equation 21.
CD t 4 ˜ CIN
(21)
Select the damping resistor RD using Equation 22.
RD
34
LIN
CIN
(22)
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9.2 Typical Applications
For step-by-step design procedure, circuit schematics, bill of materials, PCB files, simulation and test results of
an LM5145-Q1-powered implementation, see TI Designs reference design library.
9.2.1 Design 1 – 12-A High-Efficiency Synchronous Buck DC/DC Regulator for Automotive Applications
Figure 9-5 shows the schematic diagram of a 5-V, 12-A buck regulator with a switching frequency of 300 kHz.
In this example, the target efficiencies are 94% and 92% at input voltages of 24 V and 48 V, respectively. The
input UVLO is set to turn on and off at 8 V and 7 V, respectively. The switching frequency is set by means
of a synchronization input signal at 300 kHz, and the free-running switching frequency (in the event that the
synchronization signal is removed) is set at 250 kHz by resistor RRT. In terms of control loop performance, the
target loop crossover frequency is 40 kHz with a phase margin greater than 50°. The output voltage soft-start
time is 6 ms.
RUV2
RUV1
17.8 kΩ
100 kΩ
VIN = 8 V to 75 V
CVIN
0.1 μF
VOUT
U1
RFB1
150 Ω
CC3
RC1
820 pF
CC1
7.5 kΩ 6.8 nF
CC2
CSS
EN/UVLO
VIN
2
RT
3
SS/TRK
HO 18
4
COMP
SW 19
5
FB
BST 17
Q1
47 nF
150 pF
RFB2
4.42 kΩ
CBST
0.1 F
40.2 kΩ
23.2 kΩ
20
1
RRT
RC2
SYNC Out
SYNC In
LF
3.3 H
VOUT = 5 V
NC 16
LM5145-Q1
6
AGND
7
SYNCOUT
Q2
EP 15
8
SYNCIN
9
NC
CIN
VCC 14
6
4.7 F
COUT
5
47 μF
LO 13
PGOOD
ILIM
10
11
PGND 12
GND
300 kHz
CVCC
2.2 μF
RPG
PGOOD 20 kΩ
CILIM
RILIM
499 Ω
10 pF
Figure 9-5. Application Circuit 1 With LM5145-Q1 48-V to 5-V, 12-A Buck Regulator at 300 kHz
Note
This and subsequent design examples are provided herein to showcase the LM5145-Q1 controller
in several different applications. Depending on the source impedance of the input supply bus, an
electrolytic capacitor may be required at the input to ensure stability, particularly at low input voltage
and high output current operating conditions. See Section 10 for more detail.
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9.2.1.1 Design Requirements
The intended input, output, and performance-related parameters pertinent to this design example are shown in
Table 9-5.
Table 9-5. Design Parameters
DESIGN PARAMETER
VALUE
Input voltage range (steady state)
8 V to 72 V
Input transient voltage (peak)
75 V
Output voltage and current
5 V, 12 A
Input voltage UVLO thresholds
8 V on, 7 V off
Switching frequency (SYNC in)
300 kHz
Output voltage regulation
±1%
Load transient peak voltage deviation
< 100 mV
9.2.1.2 Detailed Design Procedure
The design procedure for an LM5145-Q1 based regulator for a given application is streamlined by using the
LM5145-Q1 Quickstart Calculator available as a free download, or by availing of TI's WEBENCH® Power
Designer. Such tools are complemented by the availability of LM5145 and LM5146-Q1 evaluation module (EVM)
designs, numerous PSPICE models, as well as several LM5145-Q1 reference designs populated in the TI
Designs reference design library.
The selected buck converter powertrain components are cited in Table 9-6, and many of the components are
available from multiple vendors. The MOSFETs in particular are chosen for both lowest conduction and switching
power loss, as discussed in detail in Section 9.1.2.4.
The current limit setpoint in this design is set at 19 A based on the resistor RILIM and the 6-mΩ RDS(on) of the
low-side MOSFET (typical at TJ = 25°C and VGS = 7.5 V). This design uses a low-DCR, metal-powder inductor,
and all-ceramic output capacitor implementation.
Table 9-6. List of Materials for Application Circuit 1
REFERENCE
DESIGNATOR
CIN
COUT
QTY
6
5
SPECIFICATION
4.7 µF, 100 V, X7S, 1210, ceramic, AEC-Q200
47 µF, 6.3 V, X7R, 1210, ceramic, AEC-Q200
47 µF, 6.3 V, X7S, 1210, ceramic, AEC-Q200
3.3 µH, 6.25 mΩ, 19 A, 10.85 × 10.0 × 5.2 mm, AEC-Q200
LF
1
3.3 µH, 5.8 mΩ, 28.6 A, 10.5 × 10.0 × 6.5 mm, AEC-Q200
3.3 µH, 6.0 mΩ, 17 A, 10.9 × 10.0 × 6.0 mm, AEC-Q200
MANUFACTURER
PART NUMBER
TDK
CGA6M3X7S2A475K200
Murata
GCM32DC72A475KE02L
Taiyo Yuden
HMK325C7475MMHPE
Murata
GCM32ER70J476KE19L
Taiyo Yuden
JMK325B7476KMHTR
TDK
CGA6P1X7S0J476M
Cyntec
VCHA105D-3R3M
TDK
SPM10065VTT-3R3M-D
Panasonic
ETQP6M3R3YLC
Q1
1
100 V, 22 mΩ, MOSFET, SON 5 × 6, AEC-Q101
Onsemi
NVMFS6B25NL
Q2
1
100 V, 6 mΩ, MOSFET, SON 5 × 6, AEC-Q101
Onsemi
FDWS86068-F085
U1
1
Wide VIN synchronous buck controller, AEC-Q100
Texas Instruments
LM5145QRGYRQ1
9.2.1.2.1 Custom Design With WEBENCH® Tools
Click here to create a custom design using the LM5145-Q1 device with the WEBENCH® Power Designer.
1. Start by entering the input voltage (VIN), output voltage (VOUT), and output current (IOUT) requirements.
2. Optimize the design for key parameters such as efficiency, footprint, and cost using the optimizer dial.
3. Compare the generated design with other possible solutions from Texas Instruments.
36
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The WEBENCH Power Designer provides a customized schematic along with a list of materials with real-time
pricing and component availability.
In most cases, these actions are available:
• Run electrical simulations to see important waveforms and circuit performance
• Run thermal simulations to understand board thermal performance
• Export customized schematic and layout into popular CAD formats
• Print PDF reports for the design, and share the design with colleagues
Get more information about WEBENCH tools at www.ti.com/WEBENCH.
9.2.1.2.2 Custom Design With Excel Quickstart Tool
Select components based on the regulator specifications using the LM5145-Q1 Quickstart Calculator available
for download from the product folder.
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9.2.1.3 Application Curves
100
95
SW 10V/DIV
SYNCOUT 1V/DIV
Efficiency (%)
90
85
80
75
VIN = 12V
VIN = 24V
VIN = 36V
VIN = 48V
VIN = 60V
VIN = 75V
70
65
1 Ps/DIV
60
0
2
4
6
8
Output Current (A)
10
12
Figure 9-6. Efficiency and Power Loss vs IOUT and
VIN
VIN 10V/DIV
VIN = 48 V
IOUT = 6 A
Figure 9-7. SYNCOUT and SW Node Voltages
VOUT 1V/DIV
VOUT 1V/DIV
PGOOD 2V/DIV
IOUT 2A/DIV
IOUT 2A/DIV
PGOOD 2V/DIV
400 Ps/DIV
1 ms/DIV
VIN step to 48 V
0.8-Ω Load
Figure 9-8. Start-Up, Resistive Load
VIN 2V/DIV
VIN 48 V to 6 V
0.8-Ω Load
Figure 9-9. Shutdown Through UVLO
VOUT 200 mV/DIV
VOUT 1V/DIV
PGOOD 2V/DIV
EN 1V/DIV
IOUT 5A/DIV
40 Ps/DIV
1 ms/DIV
VIN = 48 V
0.8-Ω Load
Figure 9-10. ENABLE ON, Resistive Load
38
VIN = 48 V
Figure 9-11. Load Transient Response, 6 A to 12 A
to 6 A
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VOUT 50mV/DIV
VOUT 200 mV/DIV
IOUT 5A/DIV
VIN 20V/DIV
IOUT 5A/DIV
40 Ps/DIV
2 ms/DIV
VIN = 48 V
IOUT = 6 A
Figure 9-12. Load Transient Response, 0 A to 12 A
to 0 A
Figure 9-13. Line Transient Response, 12 V to 85 V
VOUT 50mV/DIV
SW 10V/DIV
VIN 20V/DIV
VOUT 50mV/DIV
IOUT 5A/DIV
1 Ps/DIV
20 ms/DIV
IOUT = 6 A
VIN = 48 V
Figure 9-14. Line Transient Response, 85 V to 12 V
IOUT = 0 A
Figure 9-15. SW Node and Output Ripple Voltages
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9.2.2 Design 2 – High Density, 12-V, 8-A Rail From 48-V Automotive Battery Power
Figure 9-16 shows the schematic diagram of a 400-kHz, 12-V output, 8-A synchronous buck regulator intended
for 48-V automotive battery applications.
RUV2
RUV1
9.31 kΩ
100 kΩ
VIN = 14 V to 75 V
RVIN
CVIN
VOUT
2.2 Ω
0.1 μF
U1
RFB1
24.9 kΩ
21 kΩ
CC3
RC1
1 nF
8.06 kΩ 4.7 nF
CC2
2.2 Ω
VIN
2
RT
3
SS/TRK
HO 18
4
COMP
SW 19
5
FB
NC 16
6
AGND
7
SYNCOUT
BST 17
47 nF
100 pF
LF
CBST
6.8 H
0.1 F
VOUT = 12 V
LM5145-Q1
RFB2
1.5 kΩ
EN/UVLO
RBST
Q1
CSS
CC1
20
1
RRT
RC2
100 Ω
EP 15
Q2
SYNC Out
SYNC In
8
SYNCIN
9
NC
CIN
VCC 14
5
2.2 F
COUT
5
22 μF
LO 13
PGOOD
ILIM
10
11
PGND 12
GND
D1
CVCC
PGOOD
RILIM
CILIM
optional
2.2 μF
619 Ω
10 pF
Figure 9-16. Application Circuit 2 With LM5145-Q1 48-V to 12-A Synchronous Buck Regulator at 400 kHz
9.2.2.1 Design Requirements
The required input, output, and performance parameters for this application example are shown in Table 9-7.
Table 9-7. Design Parameters
DESIGN PARAMETER
VALUE
Input voltage range (steady state)
14 V to 72 V
Input transient voltage (peak)
75 V
Output voltage and current
12 V, 8 A
Input UVLO thresholds
14 V on, 13 V off
Switching frequency
400 kHz
Output voltage regulation
±1%
Load transient peak voltage deviation, 4-A load step
< 120 mV
9.2.2.2 Detailed Design Procedure
A high power density, high-efficiency regulator solution uses automotive grade 100-V power MOSFETs in SON
5-mm × 6-mm packages, together with a low-DCR inductor and all-ceramic capacitor design. The design
occupies a footprint of 30 mm × 15 mm on a single-sided PCB. The overcurrent (OC) setpoint in this design is
set at 12 A based on the resistor RILIM and the 10-mΩ RDS(on) of the low-side MOSFET (typical at TJ = 25°C and
40
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VGS = 10 V). The 12-V output is connected to VCC through a diode, D1, to reduce IC bias power dissipation at
high input voltages.
The selected buck converter powertrain components are cited in Table 9-8, including power MOSFETs, buck
inductor, input and output capacitors, and ICs. Using the LM5145-Q1 Quickstart Calculator, compensation
components are selected based on a target loop crossover frequency of 40 kHz and phase margin greater than
55°. The output voltage soft-start time is 6 ms based on the selected soft-start capacitance, CSS, of 47 nF.
Table 9-8. List of Materials for Application Circuit 2
REFERENCE
DESIGNATOR
QTY
CIN
5
SPECIFICATION
2.2 µF, 100 V, X7R, 1210, ceramic, AEC-Q200
2.2 µF, 100 V, X7S, 1206, ceramic, AEC-Q200
COUT
5
22 µF, 25 V, X7R, 1210, ceramic, AEC-Q200
MANUFACTURER
PART NUMBER
TDK
CGA6N3X7R2A225K
Taiyo Yuden
HMK325B7225KM-P
Murata
GCM31CC72A225KE02
TDK
CGA6P3X7R1E226M
Murata
GCM32EC71E226KE36
Taiyo Yuden
TMK325B7226KMHT
6.8 µH, 12 mΩ, 13.3 A, 10.85 × 10.0 × 5.2 mm, AEC-Q200
Cyntec
VCHA105D-6R8MS6
6.8 µH, 13.3 mΩ, 21.4 A, 10.5 × 10.0 × 6.5 mm, AEC-Q200
TDK
SPM10065VT-6R8M-D
100 V, 22 mΩ, MOSFET, SON 5 × 6, AEC-Q101
Onsemi
NVMFS6B25NLT1G
100 V, 10 mΩ, MOSFET, SON 5 × 6, AEC-Q101
Onsemi
NVMFS6B14NLT1G
Texas Instruments
LM5145QRGYRQ1
LF
1
Q1
1
Q2
1
U1
1
Wide VIN synchronous buck controller, AEC-Q100
As shown in Figure 9-16, a 2.2-Ω resistor in series with CBST is used to slow the turn-on transition of the highside MOSFET, reducing the spike amplitude and ringing of the SW node voltage and minimizing the possibility of
Cdv/dt-induced shoot-through of the low-side MOSFET. If needed, place an RC snubber (for example, 2.2 Ω and
100 pF) close to the drain (SW node) and source (PGND) terminals of the low-side MOSFET to further attenuate
any SW node voltage overshoot and/or ringing. Please refer to the application note Reduce Buck Converter EMI
and Voltage Stress by Minimizing Inductive Parasitics for more detail.
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9.2.2.3 Application Curves
100
Efficiency (%)
95
SW 10V/DIV
90
85
VIN = 15V
VIN = 24V
VIN = 36V
VIN = 48V
VIN = 60V
VIN = 75V
80
75
1 Ps/DIV
70
0
2
4
Output Current (A)
6
8
VIN = 48 V
Figure 9-17. Efficiency vs IOUT and VIN
IOUT = 8 A
Figure 9-18. SW Node Voltages
VOUT 2V/DIV
VOUT 2V/DIV
VIN 10V/DIV
VIN 10V/DIV
IOUT 2A/DIV
IOUT 2A/DIV
PGOOD 5V/DIV
PGOOD 5V/DIV
1 ms/DIV
VIN step to 48 V
200 Ps/DIV
1.5-Ω Load
Figure 9-19. Start-Up, 8-A Resistive Load
1.5-Ω Load
Figure 9-20. Shutdown By Input UVLO, 8-A
Resistive Load
VOUT 2V/DIV
VOUT 2V/DIV
IOUT 2A/DIV
IOUT 2A/DIV
EN 2V/DIV
EN 2V/DIV
PGOOD 5V/DIV
PGOOD 5V/DIV
100 Ps/DIV
1 ms/DIV
VIN = 48 V
1.5-Ω Load
Figure 9-21. ENABLE ON, 10-A Resistive Load
42
VIN = 48 V
1.5-Ω Load
Figure 9-22. ENABLE OFF, 10-A Resistive Load
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VOUT 200 mV/DIV
VOUT 200 mV/DIV
IOUT 2A/DIV
IOUT 2A/DIV
100 Ps/DIV
100 Ps/DIV
VIN = 48 V
VIN = 48 V
Figure 9-23. Load Transient Response, 1 A to 8 A
to 1 A
Figure 9-24. Load Transient Response, 2 A to 8 A
to 2 A
VOUT 200 mV/DIV
VOUT 20 mV/DIV
IOUT 2A/DIV
1 Ps/DIV
100 Ps/DIV
VIN = 48 V
VIN = 48 V
Figure 9-25. Load Transient Response, 4 A to 8 A
to 4 A
IOUT = 8 A
Figure 9-26. Output Voltage Ripple
VOUT 20mV/DIV
VOUT 2V/DIV
EN 1V/DIV
PGOOD 5V/DIV
VIN 20V/DIV
1 ms/DIV
20 ms/DIV
IOUT = 4 A
VIN = 48 V
Figure 9-27. Repetitive Line Transients, 24 V to 75
V
IOUT = 0 A
Figure 9-28. Pre-Biased Start-Up
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SW 10V/DIV
SYNCOUT 2V/DIV
SW 10V/DIV
SYNCIN
1V/DIV
1 Ps/DIV
1 Ps/DIV
VIN = 48 V
FSW = 350 kHz
IOUT = 8 A
Figure 9-29. SW Node and SYNCIN Voltages
VIN = 48 V
IOUT = 8 A
Figure 9-30. SW Node and SYNCOUT Voltages
Margin
Margin
Start 150 kHz
VIN = 48 V
Stop 30 MHz
VOUT = 12 V
6-A resistive load
Figure 9-31. CISPR 25 Class 5 Conducted EMI, 150
kHz to 30 MHz
44
Start 30 MHz
VIN = 48 V
Stop 108 MHz
VOUT = 12 V
6-A resistive load
Figure 9-32. CISPR 25 Class 5 Conducted EMI, 30
MHz to 108 MHz
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10 Power Supply Recommendations
The LM5145-Q1 buck controller is designed to operate from a wide input voltage range from 5.5 V to 75 V. The
characteristics of the input supply must be compatible with the Absolute Maximum Ratings and Recommended
Operating Conditions. In addition, the input supply must be capable of delivering the required input current to the
fully-loaded regulator. Estimate the average input current with Equation 23.
IIN
VOUT ˜ IOUT
VIN ˜ K
(23)
where
•
η is the efficiency
If the converter is connected to an input supply through long wires or PCB traces with a large impedance,
take special care to achieve stable performance. The parasitic inductance and resistance of the input cables
may have an adverse affect on converter operation. The parasitic inductance in combination with the low-ESR
ceramic input capacitors form an underdamped resonant circuit. This circuit can cause overvoltage transients
at VIN each time the input supply is cycled ON and OFF. The parasitic resistance causes the input voltage to
dip during a load transient. If the regulator is operating close to the minimum input voltage, this dip can cause
false UVLO fault triggering and a system reset. The best way to solve such issues is to reduce the distance from
the input supply to the regulator and use an aluminum or tantalum input capacitor in parallel with the ceramics.
The moderate ESR of the electrolytic capacitors helps to damp the input resonant circuit and reduce any voltage
overshoots. A capacitance in the range of 10 µF to 47 µF is usually sufficient to provide input damping and helps
to hold the input voltage steady during large load transients.
An EMI input filter is often used in front of the regulator that, unless carefully designed, can lead to instability
as well as some of the effects mentioned above. The application report Simple Success with Conducted EMI
for DC-DC Converters (SNVA489) provides helpful suggestions when designing an input filter for any switching
regulator.
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11 Layout
11.1 Layout Guidelines
Proper PCB design and layout is important in a high-current, fast-switching circuits (with high current and voltage
slew rates) to assure appropriate device operation and design robustness. As expected, certain issues must be
considered before designing a PCB layout using the LM5145-Q1. The high-frequency power loop of the buck
converter power stage is denoted by #1 in the shaded area of Figure 11-1. The topological architecture of a buck
converter means that particularly high di/dt current flows in the components of loop 1, and it becomes mandatory
to reduce the parasitic inductance of this loop by minimizing its effective loop area. Also important is the gate
drive loops of the low-side and high-side MOSFETs, denoted by 2 and 3, respectively, in Figure 11-1.
VIN
LM5145-Q1
VCC 14
CIN
17
BST
CBST
High-side
gate driver
#1
High frequency
power loop
HO
Q1
18
LF
#2
19
14
SW
VOUT
VCC
CVCC
Low-side
gate driver
13
LO
PGND
Q2
COUT
#3
12
GND
Figure 11-1. DC-DC Regulator Ground System With Power Stage and Gate Drive Circuit Switching Loops
11.1.1 Power Stage Layout
1. Input capacitors, output capacitors, and MOSFETs are the constituent components of the power stage of a
buck regulator and are typically placed on the top side of the PCB (solder side). The benefits of convective
heat transfer are maximized because of leveraging any system-level airflow. In a two-sided PCB layout,
small-signal components are typically placed on the bottom side (component side). insert at least one inner
plane, connected to ground, to shield and isolate the small-signal traces from noisy power traces and lines.
2. The DC/DC converter has several high-current loops. Minimize the area of these loops in order to suppress
generated switching noise and parasitic loop inductance and optimize switching performance.
• Loop #1: The most important loop to minimize the area of is the path from the input capacitor or
capacitors through the high- and low-side MOSFETs, and back to the capacitor or capacitors through the
ground connection. Connect the input capacitor or capacitors negative terminal close to the source of the
low-side MOSFET (at ground). Similarly, connect the input capacitor or capacitors positive terminal close
to the drain of the high-side MOSFET (at VIN). Refer to loop #1 of Figure 11-1.
• Another loop, not as critical though as loop #1, is the path from the low-side MOSFET through the
inductor and output capacitor(s), and back to source of the low-side MOSFET through ground. Connect
the source of the low-side MOSFET and negative terminal of the output capacitor or capacitors at ground
as close as possible.
3. The PCB trace defined as SW node, which connects to the source of the high-side (control) MOSFET, the
drain of the low-side (synchronous) MOSFET and the high-voltage side of the inductor, must be short and
wide. However, the SW connection is a source of injected EMI and thus must not be too large.
4. Follow any layout considerations of the MOSFETs as recommended by the MOSFET manufacturer,
including pad geometry and solder paste stencil design.
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5. The SW pin connects to the switch node of the power conversion stage and acts as the return path for the
high-side gate driver. The parasitic inductance inherent to loop #1 in Figure 11-1 and the output capacitance
(COSS) of both power MOSFETs form a resonant circuit that induces high frequency (> 100 MHz) ringing
on the SW node. The voltage peak of this ringing, if not controlled, can be significantly higher than the
input voltage. Ensure that the peak ringing amplitude does not exceed the absolute maximum rating limit
for the SW pin. In many cases, a series resistor and capacitor snubber network connected from the SW
node to GND damps the ringing and decreases the peak amplitude. Provide provisions for snubber network
components in the PCB layout. If testing reveals that the ringing amplitude at the SW pin is excessive, then
include snubber components as needed.
11.1.2 Gate Drive Layout
The LM5145-Q1 high-side and low-side gate drivers incorporate short propagation delays, adaptive dead-time
control and low-impedance output stages capable of delivering large peak currents with very fast rise and
fall times to facilitate rapid turnon and turnoff transitions of the power MOSFETs. Very high di/dt can cause
unacceptable ringing if the trace lengths and impedances are not well controlled.
Minimization of stray or parasitic gate loop inductance is key to optimizing gate drive switching performance,
whether it be series gate inductance that resonates with MOSFET gate capacitance or common source
inductance (common to gate and power loops) that provides a negative feedback component opposing the
gate drive command, thereby increasing MOSFET switching times. The following loops are important:
• Loop 2: high-side MOSFET, Q1. During the high-side MOSFET turnon, high current flows from the bootstrap
(boot) capacitor through the gate driver and high-side MOSFET, and back to the negative terminal of the boot
capacitor through the SW connection. Conversely, to turn off the high-side MOSFET, high current flows from
the gate of the high-side MOSFET through the gate driver and SW, and back to the source of the high-side
MOSFET through the SW trace. Refer to loop #2 of Figure 11-1.
• Loop 3: low-side MOSFET, Q2. During the low-side MOSFET turn-on, high current flows from the VCC
decoupling capacitor through the gate driver and low-side MOSFET, and back to the negative terminal of the
capacitor through ground. Conversely, to turn off the low-side MOSFET, high current flows from the gate of
the low-side MOSFET through the gate driver and GND, and back to the source of the low-side MOSFET
through ground. Refer to loop #3 of Figure 11-1.
TI strongly recommends following circuit layout guidelines when designing with high-speed MOSFET gate drive
circuits.
1. Connections from gate driver outputs, HO and LO, to the respective gate of the high-side or low-side
MOSFET must be as short as possible to reduce series parasitic inductance. Use 0.65 mm (25 mils) or wider
traces. Use a via or vias, if necessary, of at least 0.5 mm (20 mils) diameter along these traces. Route HO
and SW gate traces as a differential pair from the LM5145-Q1 to the high-side MOSFET, taking advantage of
flux cancellation.
2. Minimize the current loop path from the VCC and BST pins through their respective capacitors as these
provide the high instantaneous current, up to 3.5 A, to charge the MOSFET gate capacitances. Specifically,
locate the bootstrap capacitor, CBST, close to the BST and SW pins of the LM5145-Q1 to minimize the area
of loop #2 associated with the high-side driver. Similarly, locate the VCC capacitor, CVCC, close to the VCC
and PGND pins of the LM5145-Q1 to minimize the area of loop #3 associated with the low-side driver.
3. Placing a 2-Ω to 10-Ω resistor in series with the boot capacitor, as shown in Figure 9-16, slows down the
high-side MOSFET turn-on transition, serving to reduce the voltage ringing and peak amplitude at the SW
node at the expense of increased MOSFET turnon power loss.
11.1.3 PWM Controller Layout
With the proviso to locate the controller as close as possible to the MOSFETs to minimize gate driver trace runs,
the components related to the analog and feedback signals, current limit setting, and temperature sense are
considered in the following:
1. Separate power and signal traces, and use a ground plane to provide noise shielding.
2. Place all sensitive analog traces and components such as COMP, FB, RT, ILIM, and SS/TRK away from
high-voltage switching nodes such as SW, HO, LO, or BST to avoid mutual coupling. Use an internal layer or
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layers as a ground plane or ground planes. Pay particular attention to shielding the feedback (FB) trace from
power traces and components.
3. The upper feedback resistor can be connected directly to the output voltage sense point at the load device or
the bulk capacitor at the converter side.
4. Connect the ILIM setting resistor from the drain of the low-side MOSFET to ILIM and make the connections
as close as possible to the LM5145-Q1. The trace from the ILIM pin to the resistor must avoid coupling to a
high-voltage switching net.
5. Minimize the loop area from the VCC and VIN pins through their respective decoupling capacitors to the
GND pin. Locate these capacitors as close as possible to the LM5145-Q1.
11.1.4 Thermal Design and Layout
The useful operating temperature range of a PWM controller with integrated gate drivers and bias supply LDO
regulator is greatly affected by:
•
•
•
•
Average gate drive current requirements of the power MOSFETs
Switching frequency
Operating input voltage (affecting bias regulator LDO voltage drop and hence its power dissipation)
Thermal characteristics of the package and operating environment
For a PWM controller to be useful over a particular temperature range, the package must allow for the efficient
removal of the heat produced while keeping the junction temperature within rated limits. The LM5145-Q1
controller is available in a small 3.5-mm × 4.5-mm 20-pin VQFN (RGY) PowerPAD™ package to cover a range
of application requirements. The thermal metrics of this package are summarized in Section 7.4. The application
report Semiconductor and IC Package Thermal Metrics provides detailed information regarding the thermal
information table.
The 20-pin VQFN package offers a means of removing heat from the semiconductor die through the exposed
thermal pad at the base of the package. While the exposed pad of the package is not directly connected to
any leads of the package, it is thermally connected to the substrate of the LM5145-Q1 device (ground). This
allows a significant improvement in heat sinking, and it becomes imperative that the PCB is designed with
thermal lands, thermal vias, and a ground plane to complete the heat removal subsystem. The exposed pad
of the LM5145-Q1 is soldered to the ground-connected copper land on the PCB directly underneath the device
package, reducing the thermal resistance to a very low value. Wide traces of the copper tying in the no-connect
pins of the LM5145-Q1 (pins 9 and 16) and connection to this thermal land helps to dissipate heat.
Numerous vias with a 0.3-mm diameter connected from the thermal land to the internal and solder-side ground
plane(s) are vital to help dissipation. In a multi-layer PCB design, a solid ground plane is typically placed on the
PCB layer below the power components. Not only does this provide a plane for the power stage currents to flow
but it also represents a thermally conductive path away from the heat generating devices.
The thermal characteristics of the MOSFETs also are significant. The drain pad of the high-side MOSFET is
normally connected to a VIN plane for heat sinking. The drain pad of the low-side MOSFET is tied to the SW
plane, but the SW plane area is purposely kept relatively small to mitigate EMI concerns.
11.1.5 Ground Plane Design
As mentioned previously, using one or more of the inner PCB layers as a solid ground plane is recommended.
A ground plane offers shielding for sensitive circuits and traces and also provides a quiet reference potential for
the control circuitry. Connect the PGND pin to the system ground plane using an array of vias under the exposed
pad. Also connect the PGND directly to the return terminals of the input and output capacitors. The PGND net
contains noise at the switching frequency and can bounce because of load current variations. The power traces
for PGND, VIN and SW can be restricted to one side of the ground plane. The other side of the ground plane
contains much less noise and is ideal for sensitive analog trace routes.
48
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11.2 Layout Example
Figure 11-2 shows an example PCB layout based on the LM5146-Q1-EVM12V design. The power component
connections are made on the top layer with wide, copper-filled polygon areas. The SW connection from the
power MOSFETs to the inductor is purposely kept at minimum area to reduce radiated EMI. A power ground
plane is placed on layer 2 with 6 mil (0.15 mm) spacing to the top layer, see Figure 11-3. As a result, the buck
regulator hot loop has a small effective area based on this tightly-coupled GND plane directly underneath the
MOSFETs.
The LM5145-Q1 controller is located close to the gate terminals of the MOSFETs such that the gate drive traces
are routed short and direct. Refer to the LM5146-Q1-EVM12V Evaluation Module User's Guide for more detail.
Use paralleled 0603 input capacitors close to
the FETs for VIN to PGND decoupling
Input
Capacitors
Output
Capacitor
VIN
High-side
MOSFET
S
PGND
G
ILIM
LO
Inductor
VCC
SW
FB
Low-side
MOSFET
S
Top Layer Copper
G
PGND
Output Capacitor
Legend
HO
SW
AGND
VOUT
Keep SW copper
area small
Place PGND vias close to the
source of the low-side FET
Locate controller close
to the power stage
Layer 2 GND Plane
Copper island
connected to
AGND pin
Top Solder
Figure 11-2. LM5145-Q1 Controller PCB Layout (Viewed From Top)
Tightly-coupled return path
minimizes power loop impedance
Q2
GND
SW
Q1
VIN
Cin1-4
GND
L1
0.15mm
L2
L3
0.3mm
vias
L4
Note
See the Improve High-current DC/DC Regulator Performance for Free with Optimized Power Stage
Layout application report for more detail.
Figure 11-3. PCB Stack-up Diagram With Low L1-L2 Intra-layer Spacing
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12 Device and Documentation Support
12.1 Device Support
12.1.1 Third-Party Products Disclaimer
TI'S PUBLICATION OF INFORMATION REGARDING THIRD-PARTY PRODUCTS OR SERVICES DOES NOT
CONSTITUTE AN ENDORSEMENT REGARDING THE SUITABILITY OF SUCH PRODUCTS OR SERVICES
OR A WARRANTY, REPRESENTATION OR ENDORSEMENT OF SUCH PRODUCTS OR SERVICES, EITHER
ALONE OR IN COMBINATION WITH ANY TI PRODUCT OR SERVICE.
12.1.2 Development Support
With an input operating voltage as low as 3.5 V and up to 100 V as specified in Table 12-1, the LM(2)514x-Q1
family of automotive synchronous buck controllers from TI provides flexibility, scalability and optimized solution
size for a range of applications. These controllers enable DC/DC solutions with high density, low EMI and
increased flexibility. Available EMI mitigation features include dual-random spread spectrum (DRSS) or triangular
spread spectrum (TRSS), split gate driver outputs for slew rate (SR) control, and integrated active EMI filtering
(AEF). All controllers are rated for a maximum operating junction temperature of 150°C, have AEC-Q100 grade
1 qualification, and are functional safety capable.
Table 12-1. Automotive Synchronous Buck DC/DC Controller Family
DC/DC
CONTROLLER
SINGLE or
DUAL
VIN RANGE
CONTROL METHOD
GATE DRIVE
VOLTAGE
SYNC OUTPUT
EMI MITIGATION
LM25148-Q1
Single
3.5 V to 42 V
Peak current mode
5V
180° phase shift
DRSS
LM25149-Q1
Single
3.5 V to 42 V
Peak current mode
5V
180° phase shift
AEF, DRSS
LM25141-Q1
Single
3.8 V to 42 V
Peak current mode
5V
N/A
SR control, TRSS
LM5141-Q1
Single
3.8 V to 65 V
Peak current mode
5V
N/A
SR control, TRSS
LM5143-Q1
Dual
3.5 V to 65 V
Peak current mode
5V
90° phase shift
SR control, TRSS
LM5145-Q1
Single
5.5 V to 75 V
Voltage mode
7.5 V
180° phase shift
N/A
LM5146-Q1
Single
5.5 V to 100 V
Voltage mode
7.5 V
180° phase shift
N/A
For development support see the following:
•
•
•
•
•
•
•
LM5145-Q1 quickstart calculator
LM5145-Q1 simulation models
For TI's reference design library, visit TI Designs
For TI's WEBENCH Design Environment, visit the WEBENCH® Design Center
To design a low-EMI power supply, review TI's comprehensive EMI Training Series
TI Reference Designs:
– 57W output synchronous buck converter for telecom reference design
– 10-A automotive pre-regulator reference design
– 10-A automotive pre-regulator reference design with extended input voltage range for trucks
– 20-A automotive pre-regulator reference design
– 20-A automotive pre-regulator reference design with extended input voltage range for trucks
Technical Articles:
– High-density PCB layout of DC/DC converters
– Synchronous buck controller solutions support wide VIN performance and flexibility
– How to use slew rate for EMI control
– How to reduce EMI and shrink power-supply size with an integrated active EMI filter
12.1.2.1 Custom Design With WEBENCH® Tools
Click here to create a custom design using the LM5145-Q1 device with the WEBENCH® Power Designer.
1. Start by entering the input voltage (VIN), output voltage (VOUT), and output current (IOUT) requirements.
2. Optimize the design for key parameters such as efficiency, footprint, and cost using the optimizer dial.
3. Compare the generated design with other possible solutions from Texas Instruments.
50
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The WEBENCH Power Designer provides a customized schematic along with a list of materials with real-time
pricing and component availability.
In most cases, these actions are available:
• Run electrical simulations to see important waveforms and circuit performance
• Run thermal simulations to understand board thermal performance
• Export customized schematic and layout into popular CAD formats
• Print PDF reports for the design, and share the design with colleagues
Get more information about WEBENCH tools at www.ti.com/WEBENCH.
12.2 Documentation Support
12.2.1 Related Documentation
For related documentation see the following:
•
•
•
•
•
•
•
LM5146-Q1 EVM User's Guide
LM5145 EVM User's Guide
LM5143-Q1 Synchronous Buck Controller EVM
LM5143-Q1 Synchronous Buck Controller High-Density 4-Phase Design
Reduce Buck Converter EMI and Voltage Stress by Minimizing Inductive Parasitics
AN-2162 Simple Success with Conducted EMI from DC-DC Converters
White Papers:
– Valuing Wide VIN, Low-EMI Synchronous Buck Circuits for Cost-Effective, Demanding Applications
– An Overview of Conducted EMI Specifications for Power Supplies
– An Overview of Radiated EMI Specifications for Power Supplies
12.2.1.1 PCB Layout Resources
•
•
•
•
Improve High-current DC/DC Regulator Performance for Free with Optimized Power Stage Layout
AN-1149 Layout Guidelines for Switching Power Supplies
Constructing Your Power Supply – Layout Considerations
Technical Articles:
– High-Density PCB Layout of DC-DC Converters
12.2.1.2 Thermal Design Resources
•
•
•
•
•
•
•
AN-2020 Thermal Design by Insight, Not Hindsight
AN-1520 A Guide to Board Layout for Best Thermal Resistance for Exposed Pad Packages
Semiconductor and IC Package Thermal Metrics
Thermal Design Made Simple with LM43603 and LM43602
PowerPAD™ Thermally Enhanced Package
PowerPAD Made Easy
Using New Thermal Metrics
12.3 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. Click on
Subscribe to updates to register and receive a weekly digest of any product information that has changed. For
change details, review the revision history included in any revised document.
12.4 Support Resources
TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straight
from the experts. Search existing answers or ask your own question to get the quick design help you need.
Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do
not necessarily reflect TI's views; see TI's Terms of Use.
Submit Document Feedback
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Product Folder Links: LM5145-Q1
51
LM5145-Q1
www.ti.com
SNVSBU9A – JUNE 2021 – REVISED JUNE 2021
12.5 Trademarks
NexFET™, PowerPAD™, and TI E2E™ are trademarks of Texas Instruments.
WEBENCH® is a registered trademark of Texas Instruments.
are registered trademarks of Texas Instruments.
All trademarks are the property of their respective owners.
12.6 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled
with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may
be more susceptible to damage because very small parametric changes could cause the device not to meet its published
specifications.
12.7 Glossary
TI Glossary
52
This glossary lists and explains terms, acronyms, and definitions.
Submit Document Feedback
Copyright © 2021 Texas Instruments Incorporated
Product Folder Links: LM5145-Q1
LM5145-Q1
www.ti.com
SNVSBU9A – JUNE 2021 – REVISED JUNE 2021
13 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
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Copyright © 2021 Texas Instruments Incorporated
Product Folder Links: LM5145-Q1
53
PACKAGE OPTION ADDENDUM
www.ti.com
23-Jun-2022
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
Samples
(4/5)
(6)
LM5145QRGYRQ1
ACTIVE
VQFN
RGY
20
3000
RoHS & Green
NIPDAU | SN
Level-2-260C-1 YEAR
-40 to 150
LM5145
B2Q
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of
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