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LM5166
SNVSA67B – DECEMBER 2016 – REVISED JUNE 2017
LM5166 3-V to 65-V Input, 500-mA Synchronous Buck Converter With Ultra-Low IQ
1 Features
3 Description
•
•
•
•
•
•
The LM5166 is a compact, easy-to-use, 3-V to 65-V,
ultra-low IQ synchronous buck converter with high
efficiency over wide input voltage and load current
ranges. With integrated high-side and low-side power
MOSFETs, up to 500 mA of output current can be
delivered at fixed output voltages of 3.3 V or 5 V, or
an adjustable output. The converter is designed to
simplify implementation while providing options to
optimize the performance for the target application.
Pulse frequency modulation (PFM) mode is selected
for optimal light-load efficiency or constant on-time
(COT) control for nearly constant operating
frequency. Both control schemes do not require loop
compensation while providing excellent line and load
transient response and short PWM on-time for large
step-down conversion ratios.
1
•
•
•
•
•
•
•
•
•
•
•
•
•
•
Wide Input Voltage Range of 3 V to 65 V
9.7-µA No-Load Quiescent Current
–40°C to 150°C Junction Temperature Range
Fixed (3.3-V, 5-V) or Adjustable VOUT Options
Meets EN55022 / CISPR 22 EMI Standards
Integrated 1-Ω PFET Buck Switch
– Supports 100% Duty Cycle for Low Dropout
Integrated 0.5-Ω NFET Synchronous Rectifier
– Eliminates External Schottky Diode
Programmable Peak Current Limit Supports:
– 500-mA, 300-mA, or 200-mA Loads
Selectable PFM or COT Mode Operation
1.223-V ±1.2% Internal Voltage Reference
Switching Frequency up to 600 kHz
900-µs Internal or Externally-Adjustable Soft Start
Diode Emulation and Pulse Skipping for UltraHigh Light-Load Efficiency
No Loop Compensation or Bootstrap Components
Precision Enable and Input UVLO With Hysteresis
Open-Drain Power Good Indicator
Thermal Shutdown Protection With Hysteresis
Pin-to-Pin Compatible With the LM5165
10-Pin, 3-mm × 3-mm VSON Package
Create a Custom Regulator Design Using
WEBENCH® Power Designer
The high-side P-channel MOSFET can operate at
100% duty cycle for lowest dropout voltage and does
not require a bootstrap capacitor for gate drive. Also,
the current limit setpoint is adjustable to optimize
inductor selection for a particular load current
requirement. Selectable and adjustable start-up
timing options include minimum delay (no soft start),
internally fixed (900 μs), and externally programmable
soft start using a capacitor. An open-drain PGOOD
indicator can be used for sequencing, fault reporting,
and output voltage monitoring. The LM5166 is
available in a 10-pin VSON package with 0.5-mm pin
pitch.
Device Information(1)
PART NUMBER
OUTPUT
2 Applications
LM5166
•
•
•
•
LM5166X
5-V fixed
LM5166Y
3.3-V fixed
Factory and Building Automation
Automotive and Battery-Powered Applications
High Voltage LDO Replacement
Low Power Bias Supplies
Typical COT Mode Application
LF
150 PH
VIN = 3 V...65 V
VIN
Typical COT Mode Application Efficiency
VOUT = 5 V
IOUT = 0.5 A
100
90
ILIM
VOUT
PGOOD
SS
HYS
RT
GND
RESR
0.5 :
COUT
47 PF
80
Efficiency (%)
EN
VSON (10)
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
SW
LM5166X
CIN
2.2 PF
PACKAGE
Adjustable
70
60
VIN = 8V
VIN = 12V
VIN = 24V
VIN = 36V
VIN = 65V
50
*VOUT tracks VIN if VIN < 5.5 V
RRT
40
30
0.01
Copyright © 2017, Texas Instruments Incorporated
0.1
1
10
Load (mA)
100
500
D001
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
LM5166
SNVSA67B – DECEMBER 2016 – REVISED JUNE 2017
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Table of Contents
1
2
3
4
5
6
7
Features ..................................................................
Applications ...........................................................
Description .............................................................
Revision History.....................................................
Pin Configuration and Functions .........................
Specifications.........................................................
1
1
1
2
3
4
6.1
6.2
6.3
6.4
6.5
6.6
6.7
4
4
4
4
5
6
7
Absolute Maximum Ratings ......................................
ESD Ratings..............................................................
Recommended Operating Conditions.......................
Thermal Information ..................................................
Electrical Characteristics...........................................
Switching Characteristics ..........................................
Typical Characteristics ..............................................
Detailed Description ............................................ 14
7.1 Overview ................................................................. 14
7.2 Functional Block Diagram ....................................... 14
7.3 Feature Description................................................. 15
7.4 Device Functional Modes........................................ 25
8
Applications and Implementation ...................... 26
8.1 Application Information............................................ 26
8.2 Typical Applications ................................................ 26
9 Power Supply Recommendations...................... 44
10 Layout................................................................... 44
10.1 Layout Guidelines ................................................. 44
10.2 Layout Example .................................................... 46
11 Device and Documentation Support ................. 47
11.1
11.2
11.3
11.4
11.5
11.6
11.7
Device Support......................................................
Documentation Support ........................................
Receiving Notification of Documentation Updates
Community Resources..........................................
Trademarks ...........................................................
Electrostatic Discharge Caution ............................
Glossary ................................................................
47
47
48
48
48
48
48
12 Mechanical, Packaging, and Orderable
Information ........................................................... 48
4 Revision History
Changes from Revision A (December 2016) to Revision B
Page
•
Updated data sheet text to the latest TI documentation and translations standards ............................................................ 1
•
Changed the language of WEBENCH list item; added additional content and links for WEBENCH in data sheet .............. 1
•
Added LM5166X and LM5166Y output versions to the data sheet........................................................................................ 1
•
Replaced the body size (NOM) column with output versions in the Device Information table............................................... 1
•
Changed the Typical COT Mode Application circuit to a fixed 5-V output ............................................................................. 1
•
Changed the EN absolute maximum voltage from (VVIN + 0.3 V) to 68 V ............................................................................ 4
•
Deleted note 5 under the Absolute Maximum Ratings table ................................................................................................. 4
•
Changed the EN max operating voltage from VVIN to 65 V ................................................................................................... 4
•
Removed note 2 under the Recommended Operating Conditions......................................................................................... 4
•
Changed the IFB maximum from: 100 nA to: 25 nA ............................................................................................................... 5
•
Added Figure 13 and Figure 14.............................................................................................................................................. 8
•
Modified the Functional Block Diagram graphic ................................................................................................................... 14
•
Changed RDSON1 to RDSON2 in Equation 3 ............................................................................................................................ 17
•
Updated Equation 12 ........................................................................................................................................................... 19
•
Added a link to TI Design TIDA-01395 to the Typical Applications section ......................................................................... 26
•
Changed Design 3 to a 3.3-V fixed output, LM5166Y.......................................................................................................... 35
•
Added a new part number to CIN ref description .................................................................................................................. 35
•
Added a new part number to LF ref description.................................................................................................................... 38
•
Added the Design 5: 12-V, 300-mA COT Converter Operating from 24-V or 48-V Input section to Typical Applications... 41
•
Changed the PCB Layout and PCB Layout Guidelines section names to Layout and Layout Guidelines .......................... 44
•
Added content to the Documentation Support section ......................................................................................................... 47
Changes from Original (December 2016) to Revision A
•
2
Page
Changed data sheet status from product preview to production data.................................................................................... 1
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SNVSA67B – DECEMBER 2016 – REVISED JUNE 2017
5 Pin Configuration and Functions
LM5166X and LM5166Y Fixed Output DRC Package
10-Pin VSON
Top View
LM5166 Adjustable Output DRC Package
10-Pin VSON
Top View
SW
1
10
GND
SW
1
10
GND
VIN
2
9
HYS
VIN
2
9
HYS
ILIM
3
8
VOUT
ILIM
3
8
FB
SS
4
7
EN
SS
4
7
EN
RT
5
6
PGOOD
RT
5
6
PGOOD
Pin Functions
PIN
NO.
NAME
I/O (1)
DESCRIPTION
1
SW
P
Switching node that is internally connected to the drain of the PFET buck switch (high side) and the
drain of the NFET synchronous rectifier (low side). Connect to the buck inductor.
2
VIN
P
Regulator supply input pin to high-side power MOSFET and internal bias rail LDO. Connect to input
supply and input filter capacitor CIN. The path from the VIN pin to the input capacitor must be as short as
possible.
3
ILIM
I
Programming pin for current limit. Connecting the appropriate resistance from the ILIM pin to GND
selects one of the three current limit options. The available current limit options are detailed in Table 3.
4
SS
I
Programming pin for the soft-start delay. If a 100-kΩ resistor is connected from the SS pin to GND, the
internal soft-start circuit is disabled and the FB comparator reference steps immediately from zero to full
value when the regulator is enabled by the EN input. If the SS pin is left open, the internal soft-start
circuit ramps the FB reference from zero to full value in 900 µs. If a capacitor is connected from the SS
pin to GND, the soft-start time can be set longer than 900 µs.
5
RT
I
Mode select and on-time programming pin for Constant On-Time control. Connect a resistor from the RT
pin to GND to program the on-time and hence switching frequency. Short RT to GND to select PFM
(pulse frequency modulation) operation.
6
PGOOD
O
Power Good output flag pin. PGOOD is connected to the drain of an NFET that holds the pin low when
either FB or VOUT is not in regulation. Use a 10-kΩ to 100-kΩ pullup resistor to system voltage rail or
VOUT (no higher than 12 V).
7
EN
I
Input pin of the precision enable / UVLO comparator. The regulator is enabled when the EN pin voltage
is greater than 1.22 V.
8
VOUT or FB
I
Feedback input to the voltage regulation loop for the LM5166 Adjustable Output version, or a VOUT pin
connects the internal feedback resistor divider to the regulator output voltage for the fixed 3.3-V or 5-V
options. The FB pin connects the internal feedback comparator to an external resistor divider for the
adjustable voltage option, and the reference for the FB pin comparator is 1.223 V.
9
HYS
O
Drain of internal NFET that is turned off when the EN input is greater than the EN pin threshold. External
resistors from HYS to EN and GND program the input UVLO threshold and hysteresis.
10
GND
G
Regulator ground return.
—
PAD
P
Connect to GND pin and system ground on PCB. Path to CIN must be as short as possible.
(1)
P = Power, G = Ground, I = Input, O = Output.
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SNVSA67B – DECEMBER 2016 – REVISED JUNE 2017
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6 Specifications
6.1 Absolute Maximum Ratings
Over the recommended operating junction temperature range of –40°C to 150°C (unless otherwise noted). (1) (2)
VIN, EN to GND
SW to GND
MIN
MAX
UNIT
–0.3
68
V
–0.7
VVIN + 0.3
20-ns transient
V
–3
PGOOD, VOUT (3) to GND
–0.3
HYS to GND
ILIM, SS, RT, FB (4) to GND
16
V
–0.3
7
V
–0.3
3.6
V
Maximum junction temperature, TJ
–40
150
°C
Storage temperature, Tstg
–55
150
°C
(1)
(2)
(3)
(4)
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
If Military/Aerospace specified devices are required, please contact the Texas Instruments Sales Office/Distributors for availability and
specifications.
Fixed output setting.
Adjustable output setting.
6.2 ESD Ratings
VALUE
V(ESD)
(1)
(2)
Human body model (HBM), per ANSI/ESDA/JEDEC JS-001
Electrostatic discharge
(1)
UNIT
±2000
Charged device model (CDM), per JEDEC specification JESD22-C101 (2)
V
±1000
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
6.3 Recommended Operating Conditions
Over the recommended operating junction temperature range of –40°C to 150°C (unless otherwise noted). (1)
MIN
Input voltages
NOM
MAX
VIN
3
65
EN
–0.3
65
PGOOD
–0.3
12
UNIT
V
HYS
–0.3
5.5
Output current
IOUT
0
500
mA
Temperature
Operating junction temperature
–40
150
°C
(1)
Operating Ratings are conditions under which the device is intended to be functional. For specifications and test conditions, see
Electrical Characteristics.
6.4 Thermal Information
LM5166
THERMAL METRIC (1)
DRC (VSON)
UNIT
10 PINS
RθJA
Junction-to-ambient thermal resistance
49.1
°C/W
RθJC(top)
Junction-to-case (top) thermal resistance
57.2
°C/W
RθJB
Junction-to-board thermal resistance
26.6
°C/W
ψJT
Junction-to-top characterization parameter
0.8
°C/W
ψJB
Junction-to-board characterization parameter
23.8
°C/W
RθJC(bot)
Junction-to-case (bottom) thermal resistance
4.8
°C/W
(1)
4
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
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SNVSA67B – DECEMBER 2016 – REVISED JUNE 2017
6.5 Electrical Characteristics
Typical values correspond to TJ = 25°C. Minimum and maximum limits are based on TJ = –40°C to +125°C. VIN = 12 V
(unless otherwise noted). (1) (2)
PARAMETER
TEST CONDITIONS
TYP
MAX
4
6
µA
VFB = 1.5 V, TJ = 25°C
9.7
15
µA
VIN DC supply current, no load
VFB = 1.5 V, VVIN = 65 V, TJ = 25°C
10
15
µA
IQ-ACTIVE-PFM
VIN DC supply current, active
PFM mode, RRT = 0 Ω, RSS = 100 kΩ
205
µA
IQ-ACTIVE-COT
VIN DC supply current, active
COT mode, RRT = RSS = 100 kΩ
320
µA
IQ-SD
VIN DC supply current,
shutdown
VEN = 0 V, TJ = 25°C
IQ-SLEEP
VIN DC supply current, no load
IQ-SLEEPVINMAX
MIN
UNIT
POWER SWITCHES
RDSON1
High-side MOSFET RDS(on)
ISW = –100 mA
0.93
Ω
RDSON2
Low-side MOSFET RDS(on)
ISW = 100 mA
0.48
Ω
CURRENT LIMITING
IHS_LIM1
IHS_LIM2
High-side peak current limit
threshold
See Table 3
IHS_LIM3
ILS_LIM1
ILS_LIM2
Low-side valley current limit
threshold
1125
1250
1375
675
750
825
440
500
560
415
See Table 3
mA
mA
315
REGULATION COMPARATOR
VVOUT5
VOUT 5-V DC setpoint
LM5166X
4.9
5.0
5.1
V
VVOUT3.3
VOUT 3.3-V DC setpoint
LM5166Y
3.23
3.3
3.37
V
IVOUT
VOUT pin input current
VFB1
Lower FB regulation threshold
(PFM and COT)
VVOUT = 5 V, LM5166X
7
VVOUT = 3.3 V, LM5166Y
µA
3.8
1.208
1.223
1.238
V
1.218
1.233
1.248
V
Adjustable VOUT version
VFB2
Upper FB regulation threshold
(PFM)
IFB
FB pin input bias current
VFB = 1 V
FBHYS-PFM
FB comparator PFM hysteresis
PFM mode
10
mV
FBHYS-COT
FB comparator dropout
hysteresis
COT mode
4
mV
FBLINE-REG
FB threshold variation over line
VVIN = 3 V to 65 V
0.005
%/V
VOUTLINE-REG
VOUT threshold variation over
line
LM5166X, VVIN = 6 V to 65 V
LM5166Y, VVIN = 4.5 V to 65 V
0.005
%/V
25
nA
POWER GOOD
UVTRISING
UVTFALLING
PGOOD comparator
VFB rising relative to VFB1 threshold
94%
VFB falling relative to VFB1 threshold
87%
RPGOOD
PGOOD on-resistance
VFB = 1 V
80
200
Ω
VINMIN-PGOOD
Minimum required VIN for valid
PGOOD
VVIN falling
IPGOOD = 0.1 mA, VPGOOD < 0.5 V
1.2
1.65
V
IPGOOD
PGOOD off-state leakage
VFB = 1.2 V, VPGOOD = 5.5 V
10
100
nA
2.60
2.75
2.95
V
ENABLE / UVLO
VIN-ON
Turnon threshold
VVIN rising
VIN-OFF
Turnoff threshold
VVIN falling
2.35
2.45
2.60
V
VEN-ON
EN turnon threshold
VEN rising
1.163
1.22
1.276
V
VEN-OFF
EN turnoff threshold
VEN falling
1.109
1.144
1.178
V
(1)
(2)
All hot and cold limits are specified by correlating the electrical characteristics to process and temperature variations and applying
statistical process control.
The junction temperature (TJ in °C) is calculated from the ambient temperature (TA in °C) and power dissipation (PD in Watts) as follows:
TJ = TA + (PD • θJA) where θJA (in °C/W) is the package thermal impedance provided in Thermal Information.
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Electrical Characteristics (continued)
Typical values correspond to TJ = 25°C. Minimum and maximum limits are based on TJ = –40°C to +125°C. VIN = 12 V
(unless otherwise noted).(1)(2)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
76
UNIT
VEN-HYS
EN hysteresis
VEN-SD
EN shutdown threshold
VEN falling
RHYS
HYS on-resistance
VEN = 1 V
80
200
Ω
IHYS
HYS off-state leakage
VEN = 1.5 V, VHYS = 5.5 V
10
100
nA
ISS
Soft-start charging current
VSS = 1 V
10
µA
TSS-INT
Soft-start rise time
SS floating
900
µs
0.3
mV
0.6
V
SOFT-START
THERMAL SHUTDOWN
TJ-SD
Thermal shutdown threshold
170
°C
TJ-SD-HYS
Thermal shutdown hysteresis
10
°C
6.6 Switching Characteristics
Over operating free-air temperature range (unless otherwise noted)
PARAMETER
TON-MIN
Minimum on-time
TON1
On-time
TON2
On-time
6
TEST CONDITIONS
MIN
TYP
MAX
UNIT
180
ns
16 kΩ from RT to GND
280
ns
75 kΩ from RT to GND
1150
ns
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6.7 Typical Characteristics
100
100
90
90
80
80
Efficiency (%)
Efficiency (%)
Unless otherwise specified, VIN = 12 V, VOUT = 5 V. Please refer to Typical Applications for circuit designs.
70
60
VIN = 8V
VIN = 12V
VIN = 24V
VIN = 36V
VIN = 65V
50
40
30
0.01
0.1
See schematic,
Figure 52
1
10
Load (mA)
LF = 150 µH
COUT = 47 µF
100
70
60
40
30
0.01
500
FSW(nom) = 100 kHz
RRT = 309 kΩ
See schematic,
Figure 63
1
10
Load (mA)
LF = 47 µH
COUT = 47 µF
100
500
D001
FSW(nom) = 200 kHz
RRT = 100 kΩ
Figure 2. Converter Efficiency: 3.3 V, 500 mA, COT
100
90
90
80
80
Efficiency (%)
100
70
60
50
70
60
50
VIN = 8V
VIN = 12V
VIN = 24V
VIN = 36V
40
30
0.01
0.1
See schematic,
Figure 70
1
Load (mA)
LF = 4.7 µH
COUT = 47 µF
10
100
VIN = 8V
VIN = 12V
VIN = 24V
VIN = 36V
40
30
0.01
300
0.1
1
10
Load (mA)
D001
FSW(nom) = 600 kHz
RRT = 0 Ω
See schematic,
Figure 77
Figure 3. Converter Efficiency: 3.3 V, 300 mA, PFM
LF = 22 µH
COUT = 200 µF
100
500
D001
FSW(nom) = 100 kHz
RRT = 0 Ω
Figure 4. Converter Efficiency: 5 V, 500 mA, PFM
3
1.24
Rising
Falling
2.9
1.22
2.8
EN Thresholds (V)
VINUVLO Thresholds (V)
0.1
D001
Figure 1. Converter Efficiency: 5 V, 500 mA, COT
Efficiency (%)
VIN = 8V
VIN = 12V
VIN = 24V
VIN = 36V
VIN = 65V
50
2.7
2.6
2.5
2.4
1.2
1.18
1.16
1.14
1.12
2.3
2.2
-50
-25
0
25
50
75
Temperature (qC)
100
125
150
Rising
Falling
1.1
-50
D001
Figure 5. Internal VIN UVLO Voltage vs Temperature
-25
0
25
50
75
Temperature (qC)
100
125
150
D002
Figure 6. Enable Threshold Voltage vs Temperature
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Typical Characteristics (continued)
Unless otherwise specified, VIN = 12 V, VOUT = 5 V. Please refer to Typical Applications for circuit designs.
12
16
14
10
Current (PA)
Current (PA)
12
10
8
8
6
6
4
4
Shutdown
Sleep
Shutdown
Sleep
2
-50
2
-25
0
25
50
75
Temperature (qC)
100
125
0
150
Figure 7. VIN Sleep and Shutdown Supply Current vs
Temperature
20
30
40
Input Voltage (V)
50
60
70
D001
D004
Figure 8. VIN Sleep and Shutdown Supply Current vs Input
Voltage
400
380
PFM
COT
360
PFM
COT
360
340
320
320
Current (PA)
Current (PA)
10
D003
280
240
300
280
260
240
220
200
200
160
-50
180
-25
0
25
50
75
Temperature (qC)
100
125
150
0
RRT = 100 kΩ
20
30
40
Input Voltage (V)
50
60
70
D006
RRT = 100 kΩ
Figure 9. VIN Active Mode Supply Current vs Temperature
Figure 10. VIN Active Mode Supply Current vs Input Voltage
600
1.25
VSW = 0 V
VSW = 65 V
PFM Rising
COT/PFM Falling
1.245
FB Regulation Thresholds (V)
500
SW Leakage Current (nA)
10
D005
400
300
200
100
1.24
1.235
1.23
1.225
1.22
1.215
1.21
0
-50
-25
0
25
50
75
Temperature (°C)
100
125
150
1.205
-50
D007
-25
0
25
50
75
Temperature (qC)
100
125
150
D008
VVIN = 65 V
Figure 11. SW Pin Leakage Current vs Temperature
8
Figure 12. Feedback Comparator Threshold Voltage vs
Temperature
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Typical Characteristics (continued)
Unless otherwise specified, VIN = 12 V, VOUT = 5 V. Please refer to Typical Applications for circuit designs.
5.08
PFM Rising
COT/PFM Falling
3.34
3.32
3.3
3.28
3.26
3.24
-50
-25
0
25
50
75
Temperature (qC)
100
125
VOUT Regulation Thresholds (V)
VOUT Regulation Thresholds (V)
3.36
5.02
5
4.98
4.96
4.94
-25
0
25
50
75
Temperature (qC)
100
150
Figure 14. VOUT Regulation Thresholds vs Temperature
1.5
98
FB Rising
FB Falling
1.25
VFB Threshold (V)
96
94
92
90
1
0.75
0.5
0.25
88
86
-50
0
-25
0
25
50
75
Temperature (qC)
100
125
0
150
0.25
0.5
D011
0.75
VSS (V)
1
1.25
1.5
D012
Figure 16. Feedback Voltage vs Soft-Start Voltage
Figure 15. PGOOD Thresholds vs Temperature
200
4000
RRT = 15.8 k:
RRT = 75 k:
3500
190
One Shot Time (ns)
VSS to VFB Clamp Offset (mV)
125
LM5166X
Figure 13. VOUT Regulation Thresholds vs Temperature
PGOOD Thresholds Relative to Falling FB Threshold (%)
5.04
4.92
-50
150
LM5166Y
PFM Rising
COT/PFM Falling
5.06
180
170
3000
2500
2000
1500
1000
160
500
150
-50
0
-25
0
25
50
75
Temperature (qC)
100
125
150
0
D014
Figure 17. Soft-Start to Feedback Clamp Offset vs
Temperature
10
20
30
40
Input Voltage (V)
50
60
70
D015
Figure 18. COT One-Shot Timer TON vs Input Voltage
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Typical Characteristics (continued)
Unless otherwise specified, VIN = 12 V, VOUT = 5 V. Please refer to Typical Applications for circuit designs.
1.75
2
50qC
25qC
150qC
1.8
1.5
RDSON (:)
RDSON (:)
1.6
1.25
1
1.4
1.2
1
0.8
0.75
0.6
0.5
-50
0.4
-25
0
25
50
75
Temperature (qC)
100
125
150
0
10
20
D016
Figure 19. High-Side MOSFET On-State Resistance vs
Temperature
30
40
Input Voltage (V)
50
60
D017
Figure 20. High-Side MOSFET On-State Resistance vs Input
Voltage
0.9
1.2
50qC
25qC
150qC
1.1
0.8
1
0.9
RDSON (:)
0.7
RDSON (:)
70
0.6
0.5
0.8
0.7
0.6
0.5
0.4
0.4
0.3
0.3
-50
0.2
-25
0
25
50
75
Temperature (qC)
100
125
150
0
10
20
D018
Figure 21. Low-Side MOSFET On-State Resistance vs
Temperature
30
40
Input Voltage (V)
50
60
70
D019
Figure 22. Low-Side MOSFET On-State Resistance vs Input
Voltage
1750
1375
1250
500 mA
750 mA
1250 mA
1500
Current Limit (mA)
Current Limit (mA)
1125
500 mA
750 mA
1250 mA
1000
875
750
1250
1000
750
625
500
500
375
-50
250
-25
0
25
50
75
Temperature (qC)
100
125
150
Figure 23. High-Side Peak Current Limit vs Temperature
10
0
D020
10
20
30
40
Input Voltage (V)
50
60
70
D021
Figure 24. High-Side Peak Current Limit vs Input Voltage
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Typical Characteristics (continued)
Unless otherwise specified, VIN = 12 V, VOUT = 5 V. Please refer to Typical Applications for circuit designs.
450
450
300 mA
400 mA
400
Current Limit (mA)
Current Limit (mA)
400
350
300
350
300
300 mA
400 mA
250
-50
250
-25
0
25
50
75
Temperature (qC)
100
125
150
0
150
40
125
30
20
10
-25
0
25
50
75
Temperature (qC)
100
125
150
D024
Figure 27. Zero-Cross Current Threshold vs Temperature
Time Scale: 20 ms/Div
CH1: VSW, 5 V/Div
20
CH2: VOUT, 50 mV/Div
CH4: IL, 200 mA/Div
Figure 29. No-Load Switching Waveforms, COT, Type 2
30
40
Input Voltage (V)
50
60
70
D023
Figure 26. Low-Side Valley Current Limit vs Input Voltage
50
Pull Down Resistance (:)
Zero Cross Threshold (mA)
Figure 25. Low-Side Valley Current Limit vs Temperature
0
-50
10
D022
100
75
50
25
-50
-25
0
25
50
75
Temperature (qC)
100
125
150
D025
Figure 28. PGOOD and HYS Pulldown RDS(on) vs
Temperature
Time Scale: 10 µs/Div
CH1: VSW, 5 V/Div
CH2: VOUT, 50 mV/Div
CH4: IL, 200 mA/Div
Figure 30. Full Load Switching Waveforms, COT, Type 2
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Typical Characteristics (continued)
Unless otherwise specified, VIN = 12 V, VOUT = 5 V. Please refer to Typical Applications for circuit designs.
Time Scale: 2 ms/Div
CH1: VIN, 2 V/Div
CH2: VOUT, 1 V/Div
CH4: IL, 200 mA/Div
Time Scale: 100 µs/Div
CH1: VSW, 4 V/Div
Figure 31. Full-Load Start-Up, COT, Type 2
Time Scale: 20 ms/Div
CH1: VSW, 5 V/Div
CH2: VOUT, 50 mV/Div
CH4: IL, 400 mA/Div
Figure 32. Short Circuit, COT, Type 2
Time Scale: 10 µs/Div
CH1: VSW, 5 V/Div
Time Scale: 20 µs/Div
CH1: VSW, 4 V/Div
CH2: VOUT, 1 V/Div
CH4: IL, 400 mA/Div
Figure 35. Full-Load Start-Up, PFM, ILIM = 750 mA
12
CH2: VOUT, 100 mV/Div
CH4: IL, 400 mA/Div
Figure 34. Full-Load Switching Waveforms
PFM Mode, ILIM = 750 mA
Figure 33. No-Load Switching Waveforms
PFM Mode, ILIM = 750 mA
Time Scale: 2 ms/Div
CH1: VIN, 2 V/Div
CH4: IL, 200 mA/Div
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Figure 36. Short Circuit, PFM, ILIM = 750 mA
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Typical Characteristics (continued)
Unless otherwise specified, VIN = 12 V, VOUT = 5 V. Please refer to Typical Applications for circuit designs.
Time Scale: 50 ms/Div
CH1: VSW, 5 V/Div
CH2: VOUT, 50 mV/Div
CH4: IL, 400 mA/Div
Time Scale: 20 µs/Div
CH1: VSW, 5 V/Div
Figure 37. No-Load Switching Waveforms
PFM Mode, ILIM = 1.25 A, Modulated
CH2: VOUT, 100 mV/Div
CH4: IL, 400 mA/Div
Figure 38. Full-Load Switching Waveforms
PFM Mode, ILIM = 1.25 A, Modulated
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7 Detailed Description
7.1 Overview
The LM5166 regulator is an easy-to-use synchronous buck DC-DC converter that operates from a supply voltage
ranging from 3 V to 65 V. The device is intended for step-down conversions from 5-V, 12-V, 24-V, and 48-V
unregulated, semi-regulated, and fully-regulated supply rails. With integrated high-side and low-side power
MOSFETs, the LM5166 delivers up to 500-mA DC load current with exceptional efficiency and ultra-low input
quiescent current in a very small solution size. Designed for simple implementation, a choice of operating modes
offers flexibility to optimize its usage according to the target application. Fixed-frequency, constant on-time (COT)
operation with discontinuous conduction mode (DCM) at light loads is ideal for low-noise, high current, fast
transient load requirements. Alternatively, pulse frequency modulation (PFM) mode, complemented by an
adjustable current limit, achieves ultra-high light-load efficiency performance. Control loop compensation is not
required with either operating mode, which reduces design time and external component count.
The LM5166 incorporates other features for comprehensive system requirements, including an open-drain Power
Good circuit for power-rail sequencing and fault reporting, internally-fixed or externally-adjustable soft start,
monotonic start-up into prebiased loads, precision enable with customizable hysteresis for programmable line
undervoltage lockout (UVLO), and thermal shutdown with automatic recovery. These features enable a flexible
and easy-to-use platform for a wide range of applications. The pin arrangement is designed for simple and
optimized PCB Layout, requiring only a few external components.
7.2 Functional Block Diagram
IN
VIN
LDO BIAS
REGULATOR
VDD
VDD UVLO
EN
HYS
THERMAL
SHUTDOWN
VIN UVLO
1.22V
1.144V
I-LIMIT
SELECT
ILIM
ENABLE
VIN
HI ILIM
DETECT
+
ON-TIME
ONE SHOT
VIN
SW
Control
Logic
ZC / LS ILIM
DETECT
HYSTERETIC
MODE
RT
OUT
ZC
VOUT/FB
+
R1(1)
FB
GND
VOLTAGE
REFERENCE
R2(1)
+
UV
ENABLE
SS
1.223V
REFERENCE
SOFT-START
PGOOD
s
1.150V
1.064V
Note:
(1) R1, R2 are implemented in the fixed output voltage versions only.
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7.3 Feature Description
7.3.1 Integrated Power MOSFETs
The LM5166 is a step-down buck converter with integrated high-side PMOS buck switch and low-side NMOS
synchronous switch. During the high-side MOSFET on-time, the SW voltage VSW swings up to approximately VIN,
and the inductor current increases with slope (VIN – VOUT)/LF. When the high-side MOSFET is turned off by the
control logic, the low-side MOSFET turns on after a fixed dead time. Inductor current flows through the low-side
MOSFET with slope –VOUT/LF. Duty cycle D is defined as TON/TSW, where TON is the high-side MOSFET
conduction time and TSW is the switching period.
7.3.2 Selectable PFM or COT Mode Converter Operation
Depending on how the RT pin is connected, the LM5166 operates in PFM or COT mode. With the RT pin tied to
GND, the device operates in PFM mode. An RRT resistor connected between the RT and GND pins enables COT
control and sets the desired switching frequency as defined by Equation 4. Figure 39 and Figure 40 show
converter schematics for PFM and COT modes of operation.
VIN
LF
VIN
VOUT
VIN
LM5166X
LM5166Y
EN
RUV1
VOUT
CIN
COUT
PGOOD
SW
RUV2
FB
PGOOD
SS
HYS
HYS
ILIM
RT
RFB1
LM5166
EN
CIN
SS
VOUT
LF
VIN
SW
ILIM
RHYS
COUT
CSS
RFB2
RILIM
RT
GND
(a)
GND
(b)
Figure 39. PFM Mode Converter Schematics: (a) Fixed Output Voltage of 5 V or 3.3 V, (b) Adjustable
Output Voltage With Programmable Soft Start, Current Limit, and UVLO
VIN
LF
VIN
LM5166X
LM5166Y
EN
VOUT
CIN
VOUT
VIN
PGOOD
SS
RUV1
SW
EN
FB
PGOOD
SS
CIN
RUV2
HYS
HYS
ILIM
RT
RRT
GND
RFB1
LM5166
RESR
COUT
VOUT
LF
VIN
SW
ILIM
RT
RHYS
RFB2
COUT
RILIM
RRT
(a)
CSS
RESR
GND
(b)
Figure 40. COT Mode Converter Schematics: (a) Fixed Output Voltage of 5 V or 3.3 V, (b) Adjustable
Output Voltage With Programmable Soft Start, Current Limit, and UVLO
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Feature Description (continued)
7.3.2.1 PFM Mode Operation
In PFM mode, the LM5166 behaves as a hysteretic voltage regulator operating in boundary conduction mode.
The output voltage is regulated between upper and lower threshold levels according to the PFM feedback
comparator hysteresis of 10 mV. Figure 41 shows the relevant output voltage and inductor current waveforms.
The LM5166 provides the required switching pulses to recharge the output capacitor to the upper threshold,
followed by a sleep period where most of the internal circuits are disabled. The load current is supported by the
output capacitor during this time, and the LM5166 current consumption reduces to 9.7 µA. The sleep period
duration depends on load current and output capacitance.
VIN
SW
Voltage
VOUT
VREF = 1.233V
10mV
FB
Voltage
(internal)
ILIM
Inductor
Current
IOUT2
IOUT1
t
ACTIVE
SLEEP
ACTIVE
SLEEP
ACTIVE
SLEEP ACTIVE
Figure 41. PFM Mode Output Voltage and Inductor Current Representative Waveforms
When operating in PFM mode at given input and output voltages, the chosen filter inductance dictates the PFM
pulse frequency as
FSW(PFM)
§
VOUT
VOUT ·
˜ ¨1
¸
LF ˜ IPK(PFM) ©
VIN ¹
where
•
IPK(PFM) is one of the programmable levels for peak current limit. See Adjustable Current Limit for more detail.
(1)
One of the supported ILIM settings enables a function that modulates the peak current threshold levels during
the first three switching cycles of each active period as illustrated in Figure 42. This function improves efficiency
under most application conditions at the expense of slightly degraded load transient response.
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Feature Description (continued)
VIN
SW
Voltage
VOUT
10mV
FB
Voltage
(internal)
VREF = 1.223V
1.25A
1.00A
0.75A
Inductor
Current
0.50A
IOUT2
IOUT1
t
ACTIVE
SLEEP
ACTIVE
SLEEP
ACTIVE
SLEEP ACTIVE
Figure 42. PFM Mode With Modulated ILIM, Output Voltage and Inductor Current Representative
Waveforms
As expected, the choice of mode and switching frequency represents a compromise between conversion
efficiency, quiescent current, and passive component size. Lower switching frequency implies reduced switching
losses (including gate charge losses, transition losses, and so forth) and higher overall efficiency. Higher
switching frequency, on the other hand, implies smaller LC output filter and hence, a more compact design.
Lower inductance also helps transient response and reduces the inductor DCR conduction loss. The ideal
switching frequency in a given application is a tradeoff and thus is determined on a case-by-case basis. It relates
to the input voltage, output voltage, most frequent load current level(s), external component choices, and circuit
size requirement. At light loads, the PFM converter has a relatively longer sleep time interval and thus operates
at lower input quiescent current levels.
7.3.2.2 COT Mode Operation
In COT mode, the LM5166-based converter turns on the high-side MOSFET with constant on-time that adapts to
VIN, as defined by Equation 2, to operate with nearly fixed switching frequency when in continuous conduction
mode (CCM). The high-side MOSFET turns on when the feedback voltage (VFB) falls below the reference
voltage. The regulator control loop maintains a constant output voltage by adjusting the PWM off-time as defined
with Equation 3. For stable operation, the feedback voltage must decrease monotonically in phase with the
inductor current during the off-time as explained in Ripple Generation Methods.
175 ˜ RRT [k @
t ON [ns]
VIN
(2)
tOFF
LF ˜ û,L(nom)
VOUT
(RDCR
RDSON2 ) ˜ IOUT
(3)
Diode emulation mode (DEM) prevents negative inductor current, and pulse skipping maintains high efficiency at
light load currents by decreasing the effective switching frequency. The COT-controlled LM5166 waveforms in
CCM and DEM are shown in Figure 43.
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Feature Description (continued)
VIN
SW
Voltage
Extended
On-Time
VOUT
FB
Voltage
(internal)
Inductor
Current
VREF
4 mV
DCM
Operation
IOUT2
CCM
Operation
IOUT1
SLEEP
ACTIVE
t
ACTIVE
SLEEP
Figure 43. COT Mode Feedback Voltage and Inductor Current Representative Waveforms
The required on-time adjust resistance for a particular frequency (in CCM) is given in Equation 4 and tabulated in
Table 1. The maximum programmable on-time is 15 µs.
RRT [k @
VOUT [V] 104
˜
FSW [kHz] 1.75
(4)
Table 1. On-Time Adjust Resistance (E96 EIA Values) for Various Switching
Frequencies and Output Voltages (1)
FSW (kHz)
(1)
18
RRT (kΩ)
VOUT = 1.8 V
VOUT = 3.3 V
VOUT = 5 V
VOUT = 12 V
100
102
187
287
681
200
51.1
95.3
143
340
300
34
63.4
95.3
226
400
25.5
47.5
71.5
169
500
20.5
37.4
57.6
137
600
16.9
31.6
47.5
115
For a more precise adjustment of the switching frequency consider Equation 2 and Equation 3. The
LM5166 Quickstart Calculatorl estimates and plots the switching frequency as a function of load
current.
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7.3.2.2.1 Ripple Generation Methods
In the Constant-On-Time (COT) control scheme, the on-time is terminated by a one-shot, and the off-time is
terminated by the feedback voltage (VFB) falling below the reference voltage (VFB1). Therefore, for stable
operation, the feedback voltage must decrease monotonically in phase with the inductor current during the offtime. Furthermore, this change in feedback voltage (VFB) during the off-time must be large enough to dominate
any noise present at the feedback node.
Table 2. Ripple Generation Methods
TYPE
SCHEMATIC
CALCULATION
VIN
LF
VIN
LM5166
CIN
RFB1
PGOOD
EN
Type 1
Lowest Cost
VOUT
SW
HYS
RESR
FB
COUT
RRT
RT
ILIM
SS
GND
RFB2
VIN
LM5166
CFF
EN
RFB1
PGOOD
RESR
FB
HYS
COUT
RT
ILIM
SS
GND
VIN
SW
RFB2
(6)
LF
VIN
RA
LM5166
EN
HYS
PGOOD
CB
20mV
'IL(nom)
(7)
VOUT
2 ˜ VIN ˜ FSW ˜ COUT
(8)
RESR t
RESR t
CFF t
RRT
Type 3 (1)
Lowest Ripple
RESR
SW
CIN
CIN
(5)
VOUT
t
2 ˜ VIN ˜ FSW ˜ COUT
VOUT
LF
VIN
Type 2
Reduced Ripple
20mV ˜ VOUT
VFB1 ˜ 'IL(nom)
RESR t
1
2S ˜ FSW ˜ (RFB1 || RFB2 ) (9)
VOUT
CA t
CA
FSW ˜ (RFB1 || RFB2 )
(10)
R A CA d
RFB1
COUT
FB
10
VIN-nom
VOUT ˜ TON
@VIN-nom
20mV
RT
ILIM
RFB2
RRT
SS
(1)
GND
(11)
CB t
TTR
Settling
3 ˜ RFB1
(12)
Lin, Min and others, "Frequency Domain Analysis of Fixed On-Time With Bottom Detection Control for Buck Converter," IEEE IECON
2010, pp. 481–485.
Table 2 presents three different methods for generating appropriate voltage ripple at the feedback node. Type 1
ripple generation method uses a single resistor, designated RESR, in series with the output capacitor. The
generated voltage ripple has two components:
• Capacitive ripple caused by the inductor ripple current charging and discharging the output capacitor.
• Resistive ripple caused by the inductor ripple current flowing in the output capacitor ESR and series
resistance RESR.
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The capacitive ripple component is out of phase with the inductor current. As a result, the capacitive ripple does
not decrease monotonically during the off-time. The resistive ripple component is in phase with the inductor
current and decreases monotonically during the off-time. The resistive ripple must exceed the capacitive ripple at
the output (VOUT) for stable operation. If this condition is not satisfied, unstable switching behavior is observed in
COT converters, with multiple on-time bursts in close succession followed by a long off-time. Equation 5 and
Equation 6 define the value of the RESR resistor that ensures the required amplitude and phase of the ripple at
the feedback node.
Type-2 ripple generation method uses a CFF capacitor in addition to the RESR resistor. As the output voltage
ripple is directly AC-coupled by CFF to the feedback node, the RESR value and ultimately the output voltage ripple
are reduced by a factor of VOUT / VFB1.
Type-3 ripple generation method uses an RC network consisting of RA and CA, and the switch node (SW) voltage
to generate a triangular ramp. This triangular ramp is then AC-coupled into the feedback node (FB) with
capacitor CB. Because this circuit does not use the output voltage ripple, it is suited for applications where low
output voltage ripple is critical. Application note AN-1481 Controlling Output Ripple & Achieving ESR
Independence in Constant On-Time Regulator Designs provides additional details on this topic.
7.3.2.2.2 COT Mode Light-Load Operation
Diode emulation mode (DEM) operation occurs when the low-side MOSFET switches off as the inductor valley
current reaches zero. Here, the load current is less than half of the peak-to-peak inductor current ripple in CCM.
Turning off the low-side MOSFET at zero current reduces switching loss, and preventing negative current
conduction reduces conduction loss. In DEM, the duration that both high-side and low-side MOSFETs remain off
progressively increases as load current decreases.
7.3.3 Low Dropout Operation and 100% Duty Cycle Mode
Using RDSON1 and RDSON2 for the high-side and low-side MOSFET on-state resistances, respectively, and RDCR
for the inductor DC resistance, the duty cycle in COT (CCM) or PFM mode is given by Equation 13.
D
VOUT
VIN
RDSON2
RDCR ˜ IOUT
RDSON1 RDSON2 ˜ IOUT
|
VOUT
VIN
(13)
The LM5166 provides a low input voltage to output voltage dropout by engaging the high-side MOSFET at 100%
duty cycle. In COT operation, the extended on-time mode seamlessly increases the duty cycle during low
dropout conditions or load-step transients. The buck switch on-time extends based on the requirement that the
FB voltage exceeds the internal 4-mV FB comparator hysteresis during any COT mode on-time. The on-time
(and duty cycle) are extended as needed at low input voltage conditions until the FB voltage reaches the upper
threshold. 100% duty cycle operation is eventually reached as the input voltage decreases to a level near the
output voltage setpoint. Very low dropout voltages can be achieved with 100% duty cycle and a low DCR
inductor.
Note that PFM mode operation provides a natural transition to 100% duty cycle if needed during low input
voltage conditions. If the input-to-output voltage difference is very low, the inductor current increases to a level
determined by the load and may not reach the peak current threshold required to turn off the buck switch.
Use Equation 14 to calculate the minimum input voltage to maintain output regulation at 100% duty cycle.
VIN(min) VOUT IOUT ˜ RDSON1 RDCR
(14)
7.3.4 Adjustable Output Voltage (FB)
Three voltage feedback settings are available. The fixed 3.3-V and 5-V versions include internal feedback
resistors that sense the output directly through the VOUT pin, and the adjustable voltage option senses the
output through an external resistor divider connected from the output to the FB pin.
The LM5166 voltage regulation loop regulates the output voltage by maintaining the FB voltage equal to the
internal reference voltage (VFB1). A resistor divider programs the ratio from output voltage VOUT to FB. For a
target VOUT setpoint, calculate RFB2 based on the selected RFB1 by Equation 15.
1.223V
RFB2
˜ RFB1
VOUT 1.223V
(15)
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RFB1 in the range of 100 kΩ to 1 MΩ is recommended for most applications. A larger RFB1 consumes less DC
current, which is necessary if light-load efficiency is critical. However, RFB1 larger than 1 MΩ is not recommended
as the feedback path becomes more susceptible to noise. Larger feedback resistances generally require more
careful feedback path PCB layout. It is important to route the feedback trace away from the noisy area of the
PCB. For more PCB layout recommendations, see Layout.
7.3.5 Adjustable Current Limit
The LM5166 protects the system from overload conditions using cycle-by-cycle current limiting of the peak
inductor current. The current sensed in the high-side MOSFET is compared to the current limit threshold set by
the ILIM pin (see Table 3). Current is sensed after a 120-ns leading-edge blanking time following the high-side
MOSFET turnon. The propagation delay of the current limit comparator is 80 ns, typical.
Table 3. Current Limit Thresholds
MODE OF
OPERATION
RILIM (kΩ)
TYPICAL IHS_LIM (mA)
TYPICAL ILS_LIM (mA)
IOUT(max) (mA)
0
750
415
500
≥ 100 (1)
500
315
300
COT Mode
PFM Mode
0
1250
N/A
500
24.9
1250 (2)
N/A
500
56.2
750
N/A
300
500
N/A
200
≥ 100
(1)
(2)
(1)
For this current limit threshold selection, the ILIM pin may also be left open instead of using a 100-kΩ
or greater resistor.
This ILIM setting enables a function that modulates the ILIM levels during the first three switching cycles
as illustrated in Figure 42.
Note that in PFM mode, the inductor current ramps from zero to the chosen peak threshold every switching
cycle. Consequently, the maximum output current is equal to half the peak inductor current. The output current
capability in COT mode is higher and equal to the peak current threshold minus one-half the inductor ripple
current. The ripple current is determined by the input and output voltages and the chosen inductance and
switching frequency.
7.3.6 Precision Enable (EN) and Hysteresis (HYS)
The precision EN input supports adjustable input undervoltage lockout (UVLO) with hysteresis programmed
independently through the HYS pin for application specific power-up and power-down requirements. EN connects
to the input of a comparator with 76-mV hysteresis. The reference input of the comparator is connected to a
1.22-V bandgap reference. An external logic signal can be used to drive EN input to toggle the output on and off
for system sequencing or protection. The simplest way to enable operation is to connect EN directly to VIN. This
allows self-start-up of the LM5166 when VIN is within its valid operating range.
VIN
RUV1
EN
EN
Comparator
7
RUV2
1.22V
1.144V
RHYS
HYS
9
Figure 44. Input Voltage UVLO Using EN and HYS
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However, many applications benefit from using a resistor divider RUV1 and RUV2 as shown in Figure 44 to
establish a precision UVLO level. Adding RHYS and the connection to the HYS pin increases the voltage
hysteresis as needed.
The input UVLO voltages are calculated using Equation 16 and Equation 17.
VIN(on)
VIN(off)
§
RUV1 ·
1.22V ˜ ¨ 1
¸
© RUV2 ¹
(16)
§
·
RUV1
1.144V ˜ ¨ 1
¸
© RUV2 RHYS ¹
(17)
The LM5166 enters a low IQ shutdown mode when EN is pulled below an NPN transistor base-emitter voltage
drop (approximately 0.6 V at room temperature). If EN is below this hard shutdown threshold, the internal LDO
regulator powers off and the internal bias supply rail collapses, turning off the bias currents of the LM5166.
7.3.7 Power Good (PGOOD)
The LM5166 has a built-in PGOOD flag to indicate whether the output voltage is within a regulation window. The
PGOOD signal can be used for start-up sequencing of downstream converters, as shown in Figure 45, or fault
protection. PGOOD is an open-drain output that requires a pullup resistor to a DC supply (12 V maximum).
Typical range of pullup resistance is 10 kΩ to 100 kΩ. If necessary, use a resistor divider to decrease the
PGOOD pin voltage from a higher pullup rail.
VIN(ON) = 4.5 V
VIN(OFF) = 4.1 V
RUV1
1M
7
EN
RUV2
374 k
7
PGOOD 6
9
RHYS
4.02 k
VOUTSLAVE = 1.5 V
VOUTMASTER = 2.5 V
HYS
FB
8
RFB1
105 k
EN
RPGOOD
100 k
PGOOD 6
9
1.223 V
HYS
FB
8
1.223 V
RFB4
100 k
RFB2
100 k
Regulator #1
Startup based on
Input Voltage UVLO
RFB3
22.4 k
Regulator #2
Sequential Startup
based on PGOOD
Figure 45. Master-Slave Sequencing Implementation Using PGOOD and EN
When the FB voltage exceeds 94% of the internal reference VFB1, the PGOOD switch turns off and PGOOD will
be pulled high. If the FB voltage falls below 87% of VFB1, the PGOOD switch turns on, and PGOOD pulls low to
indicate power bad. The rising edge of PGOOD has a built-in noise filter delay of 5 µs.
7.3.8 Configurable Soft Start (SS)
The LM5166 has a flexible and easy-to-use start-up control through the SS pin. A soft-start feature prevents
inrush current impacting the LM5166 and its supply when power is first applied. Soft start is achieved by slowly
ramping up the target regulation voltage when the device is enabled or powered up. Selectable and adjustable
soft-start timing options include minimum delay (no soft-start), 900-µs internally fixed soft-start, and an externallyadjustable soft start.
The simplest way to use the LM5166 is to leave the SS pin open circuit for a 900-µs soft-start time. The LM5166
will employ the internal soft-start control ramp and start-up to the regulated output voltage. In applications with a
large amount of output capacitors, higher VOUT, or other special requirements, extend the soft-start time by
connecting an external capacitor CSS from SS to GND. Longer soft-start time further reduces the supply current
needed to charge the output capacitors. An internal current source (ISS = 10 µA) charges CSS and generates a
ramp to control the ramp rate of the output voltage. For a desired soft-start time tSS, the CSS capacitance is:
22
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CSS ª¬nF º¼
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8.1˜ t SS ª¬ms º¼
(18)
CSS is discharged by an internal 80-Ω FET when VOUT is shutdown by EN, UVLO, or thermal shutdown.
It is desirable in some applications for the output voltage to reach its nominal setpoint in the shortest possible
time. Connecting a 100-kΩ resistor from SS to GND disables the soft-start circuit of the LM5166, and the
LM5166 operates in current limit during start-up to rapidly charge the output capacitance.
Diode emulation mode (DEM) of the LM5166 prevents negative inductor current enabling monotonic start-up
under prebiased output conditions. With a prebiased output voltage, the LM5166 waits until the soft-start ramp
allows regulation above the prebiased voltage and then follows the soft-start ramp to the regulation setpoint as
shown in Figure 46 and Figure 47.
Time Scale: 2 ms/Div
CH1: VEN, 1 V/Div
CH2: VOUT, 1 V/Div
CH4: IOUT, 200 mA/Div
Time Scale: 2 ms/Div
CH1: VEN, 5 V/Div
Figure 46. ENABLE On and Off; VOUT Prebiased to 1.8 V
Figure 52 Circuit, VIN = 24 V, No Load
CH2: VOUT, 1 V/Div
CH4: IOUT, 200 mA/Div
Figure 47. ENABLE On and Off; VOUT Prebiased to 1.8 V
Figure 52 Circuit, VIN = 24 V, 500 mA Load
7.3.9 Short-Circuit Operation
The LM5166 features a clamping circuit that clamps the SS voltage about 175 mV above the FB voltage (see
Figure 48 and Figure 49). The circuit is enabled in COT mode and only works when an external soft-start
capacitor is connected.
200
1.2
VSS to VFB Clamp Offset (mV)
1
VSS (V)
0.8
0.6
0.4
0.2
0
0
0.2
0.4
0.6
VFB (V)
0.8
1
190
180
170
160
150
-50
D013
Figure 48. Soft-Start (SS) Voltage vs Feedback (FB)
Voltage
-25
0
25
50
75
Temperature (qC)
100
125
150
D014
Figure 49. Soft-Start to Feedback Clamp Offset vs
Temperature
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In case of an overload event such as an output short circuit, the clamping circuit discharges the soft-start
capacitor. When the short is removed, the FB voltage quickly rises until it reaches the level of the SS pin. Then,
the recovery continues under the soft-start capacitor control. Figure 50 and Figure 51 show short-circuit entry
and recovery waveforms.
Time Scale: 1 ms/Div
CH2: VOUT, 2 V/Div
CH4: IL, 200 mA/Div
Time Scale: 1 ms/Div
CH2: VOUT, 2 V/Div
CH4: IL, 200 mA/Div
Figure 51. Short-Circuit Recovery
(Figure 52 Circuit)
Figure 50. Short-Circuit Entry
(Figure 52 Circuit)
7.3.10 Thermal Shutdown
Thermal shutdown is a built-in self protection to limit junction temperature and prevent damage related to
overheating. Thermal shutdown turns off the device when the junction temperature exceeds 170°C typically to
prevent further power dissipation and temperature rise. Junction temperature decreases during thermal
shutdown, and the LM5166 restarts when the junction temperature falls to 160°C.
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7.4 Device Functional Modes
7.4.1 Shutdown Mode
The EN pin provides ON / OFF control for the LM5166. When VEN is below 0.3 V, the device is in shutdown
mode. Both the internal LDO and the switching regulator are off. The quiescent current in shutdown mode drops
to 4 µA (typical) at VIN = 12 V. The LM5166 also includes undervoltage protection of the internal bias LDO. If the
internal bias supply voltage is below the UV threshold level, the switching regulator remains off.
7.4.2 Standby Mode
The internal bias LDO has a lower enable threshold than the switching regulator. When VEN is above 0.6 V and
below the precision enable threshold (1.22 V typically), the internal LDO is on and regulating. The precision
enable circuitry is turned on if the LDO output is above the bias rail UV threshold. The switching action and
output voltage regulation are disabled in the standby mode.
7.4.3 Active Mode – COT
The LM5166 is in active mode when VEN is above the precision enable threshold and the internal bias rail is
above its UV threshold level. In COT active mode, the LM5166 operates in one of three modes depending on the
load current:
1. CCM with fixed switching frequency when the load current is more than half of the peak-to-peak inductor
current ripple;
2. Pulse skipping and diode emulation mode when load current is less than half of the peak-to-peak inductor
current ripple of CCM operation;
3. Extended on-time mode when VIN is nearly equal to VOUT (dropout) and during load step transients.
7.4.4 Sleep Mode – COT
The LM5166 is in COT sleep mode when VEN and VIN are above their relevant threshold levels, FB has
exceeded its upper hysteresis level, and the output capacitor is sourcing the load current. In COT sleep mode,
the LM5166 operates with very low quiescent current (9.7 µA typical). There is a 2-µs wake-up delay from sleep
to active modes.
7.4.5 Active Mode – PFM
The LM5166 is in PFM active mode when VEN and VIN are above their relevant thresholds, FB has fallen below
the lower hysteresis level, and boundary conduction mode switching is recharging the output capacitor to the
upper hysteresis level.
7.4.6 Sleep Mode – PFM
The LM5166 is in PFM sleep mode when VEN and VIN are above their relevant threshold levels, FB has
exceeded the upper hysteresis level, and the output capacitor is sourcing the load current. In PFM sleep mode,
the LM5166 operates with very low quiescent current (9.7 µA typical). There is a 2-µs wake-up delay from sleep
to active modes.
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8 Applications and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
8.1 Application Information
The LM5166 only requires a few external components to convert from a wide range of supply voltages to a fixed
output voltage. To expedite and streamline the process of designing a LM5166-based converter, a
comprehensive LM5166 Quickstart Calculator is available for download to assist the designer with component
selection for a given application. WEBENCH® online software is also available to generate complete designs,
leveraging iterative design procedures and access to comprehensive component databases. The following
sections discuss the design procedure for both COT and PFM converters using specific circuit design examples.
The LM5166 integrates several optional features to meet system design requirements, including precision
enable, UVLO, programmable soft start, programmable switching frequency in COT mode, adjustable current
limit, and PGOOD indicator. Each application incorporates these features as needed for a more comprehensive
design. The application circuits detailed below show LM5166 configuration options suitable for several application
use cases. Please see the LM5166EVM-C50A and LM5166EVM-C33A EVM user's guides for more detail.
8.2 Typical Applications
For step-by-step design procedure, circuit schematics, bill of materials, PCB files, simulation and test results of
an LM5166-powered implementation, refer to 24-V AC Power Stage with Wide VIN Converter and Battery
Gauge for Smart Thermostat reference design.
8.2.1 Design 1: Wide VIN, Low IQ, High-Efficiency COT Converter Rated at 5 V, 500 mA
LF
150 PH
U1
VOUT = 5 V
SW
VIN
VIN = 6 V...65 V
IOUT = 0.5 A
LM5166
CIN
2.2 PF
EN
HYS
CSS
33 nF
PGOOD
CFF
100 pF
RFB1
309 k:
RESR
0.11 :
FB
SS
ILIM
RT
GND
RFB2
100 k:
COUT
47 PF
RRT
309 k:
Copyright © 2016, Texas Instruments Incorporated
Figure 52. Schematic for Design 1 With VIN(nom) = 24 V, VOUT = 5 V, IOUT(max) = 500 mA, FSW(nom) = 100 kHz
8.2.1.1 Design Requirements
The target efficiency is 90% for loads above 10 mA based on a nominal input voltage of 24 V and an output
voltage of 5 V. The required input voltage range is 6 V to 65 V. The LM5166 is chosen to deliver a 5-V output
voltage. The switching frequency is set at 100 kHz. The output voltage soft-start time is 4 ms. The required
components are listed in Table 4.
26
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Table 4. List of Components for Design 1 (1)
COUN
REF DES
T
(1)
DESCRIPTION
PART NUMBER
MFR
1
CIN
Capacitor, Ceramic, 2.2 μF, 100 V, X7R, 10%, 1210
GRM32ER72A225KA35L
Murata
1
COUT
Capacitor, Ceramic, 47 μF, 10 V, X7R, 10%, 1210
GRM32ER71A476KE15L
Murata
1
CSS
Capacitor, Ceramic, 33 nF, 16 V, X7R, 10%, 0402
Std
Std
1
CFF
Capacitor, Ceramic, 100 pF, 50 V, X7R, 10%, 0402
Std
Std
1
LF
Inductor, 150 µH, 0.240 Ω typ, 1.4 A Isat, 5 mm max
7447714151
Würth
Inductor, 150 µH, 0.285 Ω typ, 1.12 A Isat, 5.1 mm max
CDRH105RNP-151NC
Sumida
1
RRT
Resistor, Chip, 309 kΩ, 1/16W, 1%, 0402
Std
Std
1
RFB1
Resistor, Chip, 309 kΩ, 1/16W, 1%, 0402
Std
Std
1
RESR
Resistor, Chip, 0.11 Ω, 1/16W, 1%, 0402
Std
Std
1
RFB2
Resistor, Chip, 100 kΩ, 1/16W, 1%, 0402
Std
Std
1
U1
LM5166, Synchronous Buck Converter, VSON-10, ADJ
LM5166DRCR
TI
See Third-Party Products Disclaimer.
8.2.1.2 Detailed Design Procedure
8.2.1.2.1 Custom Design With WEBENCH® Tools
Click here to create a custom design using the LM5166 device with the WEBENCH® Power Designer.
1. Start by entering the input voltage (VIN), output voltage (VOUT), and output current (IOUT) requirements.
2. Optimize the design for key parameters such as efficiency, footprint, and cost using the optimizer dial.
3. Compare the generated design with other possible solutions from Texas Instruments.
The WEBENCH Power Designer provides a customized schematic along with a list of materials with real-time
pricing and component availability.
In most cases, these actions are available:
• Run electrical simulations to see important waveforms and circuit performance
• Run thermal simulations to understand board thermal performance
• Export customized schematic and layout into popular CAD formats
• Print PDF reports for the design, and share the design with colleagues
Get more information about WEBENCH tools at www.ti.com/WEBENCH.
8.2.1.2.2 Feedback Resistors – RFB1, RFB2
While the 5-V fixed output version of the LM5166 is suitable here, the adjustable version is chosen to provide the
user with the option to trim or margin the output voltage if needed. The feedback resistor divider network
comprises the upper feedback resistor RFB1 and lower feedback resistor RFB2. Select RFB1 of 309 kΩ to minimize
quiescent current and improve light-load efficiency in this application. With the desired output voltage setpoint of
5 V and VFB = 1.223 V, calculate the resistance of RFB2 using Equation 15 as 100.1 kΩ. Choose the closest
available standard value of 100 kΩ for RFB2. See Adjustable Output Voltage (FB) for more details.
8.2.1.2.3 Switching Frequency – RT
The switching frequency of a COT-configured LM5166 is set by the on-time programming resistor at the RT pin.
Using Equation 4, a standard 1% resistor of 309 kΩ gives a switching frequency of 92 kHz. Including the inductor
RDCR and RDSON2 in the calculation of tOFF (Equation 3) gives an adjusted FSW of 101 kHz at 500 mA. The
LM5166 Quickstart Calculator estimates and plots the switching frequency as a function of load current.
Note that at very low duty cycles, the minimum controllable on-time of the high-side MOSFET, TON(min), of 180 ns
may affect choice of switching frequency. In CCM, TON(min) limits the voltage conversion step-down ratio for a
given switching frequency. The minimum controllable duty cycle is given by Equation 19.
DMIN
TON(min) ˜ FSW
(19)
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Given a fixed TON(min), it follows that higher switching frequency implies a larger minimum controllable duty cycle.
Ultimately, the choice of switching frequency for a given output voltage affects the available input voltage range,
solution size, and efficiency. The maximum supply voltage for a given TON(min) before switching frequency
reduction occurs is given by Equation 20.
VOUT
VIN(max)
TON(min) ˜ FSW
(20)
8.2.1.2.4 Filter Inductance – LF
The inductor ripple current (assuming CCM operation) and peak inductor current are given respectively by
Equation 21 and Equation 22.
VOUT §
VOUT ·
˜ ¨1
¸
FSW ˜ LF ©
VIN ¹
'IL
IL(peak) IOUT(max)
2
'IL
(21)
(22)
For most applications, choose the inductance such that the inductor ripple current, ΔIL, is between 30% and 60%
of the rated load current at nominal input voltage. Calculate the inductance using Equation 23.
§
VOUT
VOUT ·
˜ ¨1
LF
¸
FSW ˜ 'IL(nom) ¨©
VIN(nom) ¸¹
(23)
Choosing a 150-μH inductor in this design results in 295-mA peak-to-peak ripple current at nominal input voltage
of 24 V, equivalent to 59% of the 500-mA rated load current. The peak inductor current at maximum input voltage
of 65 V is 675 mA, which is sufficiently below the LM5166 peak current limit of 750 mA.
Check the inductor datasheet to ensure that the inductor saturation current is well above the current limit setting
of a particular design. Ferrite designs have low core loss and are preferred at high switching frequencies, so
design goals can then concentrate on copper loss and preventing saturation. However, ferrite core materials
exhibit a hard saturation characteristic – the inductance collapses abruptly when the saturation current is
exceeded. This results in an abrupt increase in inductor ripple current, higher output voltage ripple, not to
mention reduced efficiency and compromised reliability. Note that inductor saturation current generally decreases
as the core temperature increases.
8.2.1.2.5 Output Capacitors – COUT
Select the output capacitor to limit the capacitive voltage ripple at the converter output. This is the sinusoidal
ripple voltage that arises from the triangular ripple current flowing in the capacitor. Select an output capacitance
using Equation 24 to limit the capacitive voltage ripple component to 0.5% of the output voltage.
'IL(nom)
COUT t
8 ˜ FSW ˜ û9OUT
(24)
Substituting ΔIL(nom) of 295 mA and ΔVOUT of 25 mV gives COUT greater than 16 μF. Mindful of the voltage
coefficient of ceramic capacitors, select a 47-μF, 10-V capacitor with a high-quality dielectric.
8.2.1.2.6 Ripple Generation Network – RESR, CFF
For this design, the Type 2 ripple generation method is selected as it offers a good balance between cost and
output voltage ripple. For other methods, see Ripple Generation Methods.
Select a series resistor, RESR, such that sufficient ripple in phase with the inductor current ripple appears at the
feedback node, FB, using Equation 7 and Equation 8. Select a feedforward capacitor, CFF, using Equation 9.
With ΔIL(nom) of 295 mA at the nominal input voltage of 24 V, the required RESR is 0.11 Ω. The required
feedforward capacitance, CFF, is 100 pF. Calculate the total output voltage ripple in CCM using Equation 25.
'VOUT
28
'IL(nom) ˜ RESR2
§
·
1
¨
¸
© 8 ˜ FSW ˜ COUT ¹
2
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8.2.1.2.7 Input Capacitor – CIN
An input capacitor is necessary to limit the input ripple voltage while providing switching-frequency AC current to
the buck power stage. To minimize the parasitic inductance in the switching loop, position the input capacitors as
close as possible to the VIN and GND pins of the LM5166. The input capacitors conduct a trapezoidal-wave
current of peak-to-peak amplitude equal to the output current. It follows that the resultant capacitive component
of AC ripple voltage is a triangular waveform. Together with the ESR-related ripple component, the peak-to-peak
input ripple voltage amplitude is given by Equation 26.
IOUT ˜ D ˜ 1 D
'VIN
IOUT ˜ RESR
FSW ˜ CIN
(26)
The input capacitance required for a particular load current, based on an input voltage ripple specification of
ΔVIN, is given by Equation 27.
CIN t
IOUT ˜ D ˜ 1 D
FSW ˜ 'VIN IOUT ˜ RESR
(27)
The recommended high-frequency input capacitance is 2.2 μF or higher and should be a high-quality ceramic
component with sufficient voltage rating. Based on the voltage coefficient of ceramic capacitors, choose a
voltage rating of twice the maximum input voltage. Additionally, some bulk capacitance is required if the LM5166
circuit is not located within approximately 5 cm from the input voltage source. This capacitor provides damping to
the resonance associated with parasitic inductance of the supply lines and high-Q ceramics.
8.2.1.2.8 Soft-Start Capacitor – CSS
Connect an external soft-start capacitor for a specific soft-start time. In this example, select a soft-start
capacitance of 33 nF based on Equation 18 to achieve a soft-start time of 4 ms.
8.2.1.2.9 Application Curves
Unless otherwise stated, application performance curves were taken at TA = 25°C.
5.1
100
5.08
90
5.06
5.04
VOUT (V)
Efficiency (%)
80
70
60
40
30
0.01
LF = 150 µH
COUT = 47 µF
0.1
1
10
Load (mA)
100
5
4.98
4.96
VIN = 8V
VIN = 12V
VIN = 24V
VIN = 36V
VIN = 65V
50
5.02
4.92
500
4.9
0.01
D001
FSW(nom) = 100 kHz
RRT = 309 kΩ
VIN = 8V
VIN = 12V
VIN = 24V
VIN = 36V
4.94
LF = 150 µH
COUT = 47 µF
Figure 53. Converter Efficiency
0.1
1
10
Load (mA)
100
500
D001
D001
FSW(nom) = 100 kHz
RRT = 309 kΩ
Figure 54. Converter Regulation
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Time Scale: 20 ms/Div
CH1: VSW, 5 V/Div
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CH2: VOUT, 50 mV/Div
CH4: IL, 200 mA/Div
Figure 55. No-Load Switching Waveforms, VIN = 24 V
Time Scale: 2 ms/Div
CH1: VIN, 3 V/Div
CH2: VOUT, 1 V/Div
CH4: IL, 200 mA/Div
Time Scale: 10 µs/Div
CH1: VSW, 5 V/Div
Figure 56. Full-Load Switching Waveforms, VIN = 24 V
Time Scale: 100 µs/Div
CH1: VSW, 4 V/Div
CH2: VOUT, 1 V/Div
CH4: IOUT, 200 mA/Div
Figure 59. ENABLE On and Off; VOUT Prebiased to 1.8 V
VIN = 24 V, No Load
30
CH4: IL, 200 mA/Div
Figure 58. Short Circuit, VIN = 24 V
Figure 57. Full-Load Start-Up, VIN = 24 V
Time Scale: 2 ms/Div
CH1: VEN, 1 V/Div
CH2: VOUT, 50 mV/Div
CH4: IL, 200 mA/Div
Time Scale: 2 ms/Div
CH1: VEN, 5 V/Div
CH2: VOUT, 1 V/Div
CH4: IOUT, 200 mA/Div
Figure 60. ENABLE On and Off; VOUT Prebiased to 1.8 V
VIN = 24 V, 500 mA Load
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Time Scale: 1 ms/Div
CH2: VOUT, 2 V/Div
CH4: IL, 200 mA/Div
Time Scale: 1 ms/Div
CH2: VOUT, 2 V/Div
CH4: IL, 200 mA/Div
Figure 62. Short-Circuit Recovery
Figure 61. Short-Circuit Entry
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8.2.2 Design 2: Wide VIN, Low IQ COT Converter Rated at 3.3 V, 500 mA
LF
47 PH
U1
LM5166
CIN
2.2 PF
EN
PGOOD
HYS
CSS
47 nF
VOUT = 3.3V
SW
VIN
VIN = 4.5 V...65 V
IOUT = 0.5 A
RFB1
169 k:
RESR
0.2 :
FB
SS
ILIM
RT
GND
COUT
47 PF
RFB2
100 k:
RRT
100 k:
Copyright © 2016, Texas Instruments Incorporated
Figure 63. Schematic for Design 2 With VIN(nom) = 12 V, VOUT = 3.3 V, IOUT(max) = 500 mA, FSW(nom) = 200 kHz
8.2.2.1 Design Requirements
The target efficiency is 85% for loads above 10 mA based on a nominal input voltage of 12 V and an output
voltage of 3.3 V. The required input voltage range is 4.5 V to 65 V. The LM5166 is chosen to deliver a 3.3-V
output voltage. The switching frequency is set at 200 kHz. The output voltage soft-start time is 4 ms. The
required components are listed in Table 5.
Table 5. List of Components for Design 2 (1)
COUN
REF DES
T
(1)
DESCRIPTION
PART NUMBER
MFR
1
CIN
Capacitor, Ceramic, 2.2 μF, 100 V, X7R, 10%, 1210
GRM32ER72A225KA35L
Murata
1
COUT
Capacitor, Ceramic, 47 μF, 10 V, X7R, 10%, 1210
GRM32ER71A476KE15L
Murata
1
CSS
Capacitor, Ceramic, 47 nF, 16 V, X7R, 10%, 0402
Std
Std
1
LF
Inductor, 47 µH, 0.245 Ω max, 1.2 A Isat, 3.5 mm max
LPS6235-473MR
Coilcraft
Inductor, 47 µH, 0.315 Ω typ, 1.3 A Isat, 2.8 mm max
74404063470
Würth
1
RRT
Resistor, Chip, 100 kΩ, 1/16W, 1%, 0402
Std
Std
1
RFB1
Resistor, Chip, 169 kΩ, 1/16W, 1%, 0402
Std
Std
1
RESR
Resistor, Chip, 0.2 Ω, 1/16W, 1%, 0402
Std
Std
1
RFB2
Resistor, Chip, 100 kΩ, 1/16W, 1%, 0402
Std
Std
1
U1
LM5166, Synchronous Buck Converter, VSON-10, ADJ
LM5166DRCR
TI
See Third-Party Products Disclaimer.
8.2.2.2 Detailed Design Procedure
8.2.2.2.1 Feedback Resistors – RFB1, RFB2
The output voltage of the LM5166 is externally adjustable using a resistor divider network. The divider network
comprises the upper feedback resistor RFB1 and lower feedback resistor RFB2. Select RFB1 of 169 kΩ to minimize
quiescent current and improve light-load efficiency in this application. With the desired output voltage setpoint of
3.3 V and VFB = 1.223 V, calculate the resistance of RFB2 using Equation 15 as 100.1 kΩ. Choose the closest
available standard value of 100 kΩ for RFB2. See Adjustable Output Voltage (FB) for more detail.
32
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8.2.2.2.2 Switching Frequency – RT
The switching frequency of a COT-configured LM5166 is set by the on-time programming resistor at the RT pin.
Using Equation 4, a standard 1% resistor of 100 kΩ gives a switching frequency of 190 kHz. Including the
inductor RDCR and RDSON2 in the calculation of tOFF (Equation 3) gives an adjusted FSW of 215 kHz at 500 mA.
The LM5166 Quick-Start Design Tool estimates and plots the switching frequency as a function of load current.
Note that at very low duty cycles, the minimum controllable on-time of the high-side MOSFET, TON(min), of 180 ns
may affect choice of switching frequency. In CCM, TON(min) limits the voltage conversion step-down ratio for a
given switching frequency. The minimum controllable duty cycle is given by Equation 19.
Given a fixed TON(min), it follows that higher switching frequency implies a larger minimum controllable duty cycle.
Ultimately, the choice of switching frequency for a given output voltage affects the available input voltage range,
solution size, and efficiency. The maximum supply voltage for a given TON(min) before switching frequency
reduction occurs is given by Equation 20.
8.2.2.2.3 Filter Inductance – LF
The inductor ripple current (assuming CCM operation) and peak inductor current are given respectively by
Equation 21 and Equation 22. For most applications, choose an inductance such that the inductor ripple current,
ΔIL, is between 30% and 60% of the rated load current at nominal input voltage. Calculate the inductance using
Equation 23.
Choosing a 47-μH inductor in this design results in 275-mA peak-to-peak ripple current at nominal input voltage
of 12 V, equivalent to 55% of the 500-mA rated load current. The peak inductor current at maximum input voltage
of 65 V is 694 mA, which is sufficiently below the LM5166 peak current limit of 750 mA.
8.2.2.2.4 Output Capacitors – COUT
Select the output capacitor to limit the capacitive voltage ripple at the converter output. This is the sinusoidal
ripple voltage that arises from the triangular ripple current flowing in the capacitor. Select an output capacitance
using Equation 24 to limit the capacitive voltage ripple component to 0.5% of the output voltage.
Substituting ΔIL(nom) of 275 mA and ΔVOUT of 25 mV gives COUT greater than 11 μF. Mindful of the voltage
coefficient of ceramic capacitors, select a 47-μF, 10-V capacitor with a high-quality dielectric.
8.2.2.2.5 Ripple Generation Network – RESR
For this design, the Type 1 ripple generation method is selected as it only requires a single external component.
For other schemes, see Ripple Generation Methods.
Select a series resistor, RESR, using Equation 5 and Equation 6 such that sufficient ripple in phase with the SW
node voltage appears at the feedback node, FB. With ΔIL(nom) of 275 mA at the nominal input voltage of 12 V, the
required RESR is 0.2 Ω. Calculate the total output voltage ripple in CCM using Equation 25.
8.2.2.2.6 Input Capacitor – CIN
An input capacitor is necessary to limit the input ripple voltage while providing switching-frequency AC current to
the buck power stage. To minimize the parasitic inductance in the switching loop, position the input capacitors as
close as possible to the VIN and GND pins of the LM5166. The input capacitors conduct a trapezoidal-wave
current of peak-to-peak amplitude equal to the output current. It follows that the resultant capacitive component
of AC ripple voltage is a triangular waveform. Together with the ESR-related ripple component, the peak-to-peak
input ripple voltage amplitude is given by Equation 26. The input capacitance required for a particular load
current, based on an input voltage ripple specification of ΔVIN, is given by Equation 27.
The recommended high-frequency capacitance is 2.2 μF or higher and should be a high-quality ceramic with
sufficient voltage rating. Based on the voltage coefficient of ceramic capacitors, choose a voltage rating of twice
the maximum input voltage. Additionally, some bulk capacitance is required if the LM5166 circuit is not located
within approximately 5 cm from the input voltage source. This capacitor provides damping to the resonance
associated with parasitic inductance of the supply lines and high-Q ceramics.
8.2.2.2.7 Soft-Start Capacitor – CSS
Connect an external soft-start capacitor for a specific soft-start time. In this example, select a soft-start
capacitance of 47 nF based on Equation 18 to achieve a soft-start time of 6 ms.
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8.2.2.2.8 Application Curves
Unless otherwise stated, application curves were taken at TA = 25°C.
3.4
100
3.38
90
3.36
3.34
VOUT (V)
Efficiency (%)
80
70
60
40
30
0.01
0.1
1
10
Load (mA)
LF = 47 µH
COUT = 47 µF
100
3.3
3.28
3.26
VIN = 8V
VIN = 12V
VIN = 24V
VIN = 36V
VIN = 65V
50
3.32
3.22
500
3.2
0.01
100
500
D001
FSW(nom) = 200 kHz
RRT = 100 kΩ
Figure 65. Converter Regulation
CH2: VOUT, 50 mV/Div
CH4: IL, 200 mA/Div
Time Scale: 5 µs/Div
CH1: VSW, 5 V/Div
CH2: VOUT, 1 V/Div
CH4: IL, 200 mA/Div
CH2: VOUT, 50 mV/Div
CH4: IL, 200 mA/Div
Figure 67. Full-Load Switching Waveforms
Figure 66. No-Load Switching Waveforms
Time Scale: 100 µs/Div
CH1: VSW, 4 V/Div
CH4: IL, 200 mA/Div
Figure 69. Short Circuit
Figure 68. Full-Load Start-Up
34
1
10
Load (mA)
LF = 47 µH
COUT = 47 µF
Figure 64. Converter Efficiency
Time Scale: 2 ms/Div
CH1: VIN, 2 V/Div
0.1
D001
FSW(nom) = 200 kHz
RRT = 100 kΩ
Time Scale: 20 ms/Div
CH1: VSW, 5 V/Div
VIN = 8V
VIN = 12V
VIN = 24V
VIN = 36V
VIN = 65V
3.24
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8.2.3 Design 3: High-Density PFM Converter Rated at 3.3 V, 0.3 A
LF
4.7 PH
U1
VIN = 4.5 V...36 V
CIN
VIN
SW
EN
VOUT
4.7 PF
VOUT = 3.3 V
IOUT = 0.3 A
COUT
47 PF
LM5166Y
PGOOD
SS
HYS
ILIM
RT
GND
RILIM
56.2 k:
Copyright © 2017, Texas Instruments Incorporated
Figure 70. Schematic for Design 3 With VIN(nom) = 24 V, VOUT = 3.3 V, IOUT(max) = 0.3 A, FSW(nom) = 600 kHz
8.2.3.1 Design Requirements
The target efficiency is 75% for loads above 10 mA based on a nominal input voltage of 24 V, an output voltage
of 3.3 V, with the emphasis on small solution size. The required input voltage range is 4.5 V to 36 V. The
LM5166 has an internally-set soft-start time of 900 µs and an adjustable peak current limit threshold. The
required components are listed in Table 6.
Table 6. List of Components for Design 3 (1)
COUN REF
T
DES
(1)
DESCRIPTION
PART NUMBER
MFR
GRM31CR71H475MA12L
Murata
885012208094
Würth
1
CIN
Capacitor, Ceramic, 4.7 μF, 50 V, X7R, 10%, 1206
1
COUT
Capacitor, Ceramic, 47 μF, 6.3 V, X5R, 10%, 1206
GRM31CR60J476KE19
Murata
Inductor, 4.7 µH, 0.18 Ω typ, 2.2 A Isat, 1.2 mm max
TFM252012ALMA4R7TMAA
TDK
Inductor, 4.7 µH, 0.3 Ω typ, 2.1 A Isat, 1.2 mm max
Würth
Würth
1
LF
1
RILIM
Resistor, Chip, 56.2 kΩ, 1/16W, 1%, 0402
Std
Std
1
U1
LM5166Y, Synchronous Buck Converter, VSON-10, 3.3-V Fixed
LM5166YDRCR
TI
See Third-Party Products Disclaimer.
8.2.3.2 Detailed Design Procedure
8.2.3.2.1 Peak Current Limit Setting – RILIM
Install a 56.2-kΩ resistor from ILIM to GND to select a 750-mA peak current limit threshold setting to meet the
rated output current of 300 mA in PFM. See Adjustable Current Limit for more detail.
8.2.3.2.2 Switching Frequency – LF
Tie RT to GND to select PFM mode of operation. The inductor, input voltage, output voltage and peak current
determine the pulse switching frequency of a PFM-configured LM5166. For a given input voltage, output voltage
and peak current, the inductance of LF sets the switching frequency when the output is in regulation. Use
Equation 28 to select an inductance of 4.7 μH based on the target PFM converter switching frequency of 600
kHz at 24-V input.
LF
§
VOUT
VOUT ·
˜ ¨1
¸
FSW(PFM) ˜ IPK(PFM) ©
VIN ¹
(28)
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IPK(PFM) in this example is the peak current limit setting of 750 mA plus the inductor current overshoot resulting
from the 80-ns peak current comparator delay, tILIM_delay. An additional constraint on the inductance is the 180-ns
minimum on-time of the high-side MOSFET. Therefore, to keep the inductor current well controlled, choose an
inductance that is larger than LF(min) using Equation 29 where VIN(max) is the maximum input supply voltage for the
application, tILIM_delay is 80 ns, tON(min) is 180 ns, the maximum current limit threshold, ILIM(max), is 825 mA, and the
maximum allowed peak inductor current, IL(max), is 1.6 A.
LF(min)
§ VIN(max) ˜ tON(min) VIN(max) ˜ tILIM_delay
Max ¨
,
¨
IL(max)
IL(max) ILIM(max)
©
·
¸
¸
¹
(29)
Choose an inductor with saturation current rating above the peak current limit setting, and allow for derating of
the saturation current at the highest expected operating temperature.
8.2.3.2.3 Output Capacitors – COUT
The output capacitor, COUT, filters the inductor’s ripple current and stores energy to meet the load current
requirement when the LM5166 is in sleep mode. The output ripple has a base component of amplitude VOUT/123
related to the typical feedback comparator hysteresis in PFM. The wake-up time from sleep to active mode adds
a ripple voltage component that is a function of the output current. Approximate the total output ripple by
Equation 30.
§ IPK(PFM)
· 1 V
VOUT
'VOUT ¨¨
IOUT ¸¸ ˜
2
C
123
©
¹ OUT
(30)
Also, the output capacitance must be large enough to accept the energy stored in the inductor without a large
deviation in output voltage. Setting this voltage change equal to 1% of the output voltage results in a COUT
requirement defined with Equation 31.
§ IPK(PFM) ·
COUT t 50 ˜ LF ˜ ¨¨
¸¸
© VOUT ¹
2
(31)
In general, select the capacitance of COUT to limit the output voltage ripple at full load current, ensuring that it is
rated for worst-case RMS ripple current given by IRMS = IPK(PFM)/2. In this design example, select a 47-μF, 6.3-V
capacitor with a high-quality dielectric.
8.2.3.2.4 Input Capacitor – CIN
The input capacitor, CIN, filters the triangular current waveform of the high-side MOSFET (see Figure 89). To
prevent large ripple voltage, use a low-ESR ceramic input capacitor sized for the worst-case RMS ripple current
given by IRMS = IOUT/2. In this design example, choose a 2.2-μF, 50-V ceramic input capacitor with a high-quality
dielectric.
36
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8.2.3.2.5 Application Curves
Unless otherwise stated, application curves were taken at TA = 25°C.
3.4
100
3.38
90
3.36
3.34
VOUT (V)
Efficiency (%)
80
70
60
3.3
3.28
3.26
50
VIN = 8V
VIN = 12V
VIN = 24V
VIN = 36V
40
30
0.01
3.32
0.1
LF = 4.7 µH
COUT = 47 µF
1
Load (mA)
10
100
3.22
300
3.2
0.01
LF = 4.7 µH
COUT = 47 µF
Figure 71. Converter Efficiency
1
Load (mA)
10
100
300
D001
FSW(nom) = 600 kHz
RRT = 0 Ω
Figure 72. Converter Regulation
CH2: VOUT, 50 mV/Div
CH4: IL, 400 mA/Div
Figure 73. No-Load Switching Waveforms, VIN = 24 V
Time Scale: 2 ms/Div
CH1: VIN, 4 V/Div
0.1
D001
FSW(nom) = 600 kHz
RRT = 0 Ω
Time Scale: 20 ms/Div
CH1: VSW, 10 V/Div
VIN = 8V
VIN = 12V
VIN = 24V
VIN = 36V
3.24
CH2: VOUT, 1 V/Div
CH4: IL, 400 mA/Div
Time Scale: 10 µs/Div
CH1: VSW, 10 V/Div
CH2: VOUT, 50 mV/Div
CH4: IL, 400 mA/Div
Figure 74. Full-Load Switching Waveforms, VIN = 24 V
Time Scale: 20 µs/Div
CH1: VSW, 6 V/Div
Figure 75. Full-Load Start-Up, VIN = 24 V
CH4: IL, 400 mA/Div
Figure 76. Short Circuit, VIN = 24 V
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8.2.4 Design 4: Wide VIN, Low IQ PFM Converter Rated at 5 V, 500 mA
LF
22 PH
U1
VIN
VIN = 6 V...42 V
IOUT = 0.5 A
LM5166
CIN
4.7 PF
VOUT = 5 V
SW
EN
PGOOD
SS
FB
HYS
ILIM
RT
GND
RFB1
309 k:
COUT
2 x 100 PF
RFB2
100 k:
RILIM
24.9 k:
Copyright © 2016, Texas Instruments Incorporated
Figure 77. Schematic for Design 4 With VIN(nom) = 12 V, VOUT = 5 V, IOUT(max) = 500 mA, FSW(nom) = 100 kHz
8.2.4.1 Design Requirements
The target efficiency is 85% for loads above 1 mA based on a nominal input voltage of 12 V, an output voltage of
5 V. The required input voltage range is 6 V to 42 V. The LM5166 has an internally-set soft-start time of 900 µs
and an adjustable peak current limit threshold. The required components are listed in Table 7.
Table 7. List of Components for Design 4 (1)
COUN
REF DES
T
(1)
DESCRIPTION
PART NUMBER
MFR
GRM31CR71H475MA12L
Murata
C3216X7R1H475M160AC
TDK
1
CIN
Capacitor, Ceramic, 4.7 μF, 50 V, X7R, 20%, 1206
2
COUT
Capacitor, Ceramic, 100 μF, 10 V, X5R, 10%, 1210
GRM32ER61A107ME20K
Murata
Inductor, 22 µH, 0.145 Ω max, 1.7 A Isat, 3.5 mm max
LPS6235-223MR
Coilcraft
1
LF
Inductor, 22 µH, 0.2 Ω max, 2.3 A Isat, 3 mm max
CMLB063T-220MS
Cyntec
1
RILIM
Resistor, Chip, 24.9 kΩ, 1/16W, 1%, 0402
Std
Std
1
RFB1
Resistor, Chip, 309 kΩ, 1/16W, 1%, 0402
Std
Std
1
RFB2
Resistor, Chip, 100 kΩ, 1/16W, 1%, 0402
Std
Std
1
U1
LM5166, Synchronous Buck Converter, VSON-10, ADJ
LM5166DRCR
TI
See Third-Party Products Disclaimer.
8.2.4.2 Detailed Design Procedure
8.2.4.2.1 Feedback Resistors – RFB1, RFB2
The output voltage of the LM5166 is externally adjustable using a resistor divider network. The divider network
comprises the upper feedback resistor RFB1 and lower feedback resistor RFB2. Select RFB1 of 309 kΩ to minimize
quiescent current and improve light-load efficiency in this application. With the desired output voltage setpoint of
5 V and VFB = 1.223 V, calculate the resistance of RFB2 using Equation 15 as 99.5 kΩ. Choose the closest
available standard value of 100 kΩ for RFB2. See Adjustable Output Voltage (FB) for more detail.
8.2.4.2.2 Peak Current Limit Setting – RILIM
Install a 24.9-kΩ resistor from ILIM to GND to select a 1.25-A peak current limit threshold setting with modulated
ILIM function to meet the rated output current of 500 mA and the efficiency target. See Adjustable Current Limit
for more detail.
38
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8.2.4.2.3 Switching Frequency – LF
Tie RT to GND to select PFM mode of operation. The inductor, input voltage, output voltage and peak current
determine the pulse switching frequency of a PFM-configured LM5166. For a given input voltage, output voltage
and peak current, the inductance of LF sets the switching frequency when the output is in regulation. Use
Equation 28 to select an inductance of 22 μH based on the target PFM converter switching frequency of 100 kHz
at 12-V input.
IPK(PFM) in this example is the peak current limit setting of 1.25 A plus the inductor current overshoot resulting
from the 80-ns peak current comparator delay. An additional constraint on the inductance is the 180-ns minimum
on-time of the high-side MOSFET. Therefore, to keep the inductor current well controlled, choose an inductance
that is larger than LF(min) using Equation 29.
Choose an inductor with saturation current rating above the peak current limit setting, and allow for derating of
the saturation current at the highest expected operating temperature.
8.2.4.2.4 Output Capacitors – COUT
The output capacitor, COUT, filters the ripple current of the inductor and stores energy to meet the load current
requirement when the LM5166 is in sleep mode. The output ripple has a base component of amplitude VOUT/123
related to the typical feedback comparator hysteresis in PFM. The wake-up time from sleep to active mode adds
a ripple voltage component that is a function of the output current. Approximate the total output ripple by
Equation 30.
Also, the output capacitance must be large enough to accept the energy stored in the inductor without a large
deviation in output voltage. Setting this voltage change equal to 1% of the output voltage results in a COUT
requirement defined with Equation 31.
In general, select the capacitance of COUT to limit the output voltage ripple at full load current, ensuring that it is
rated for worst-case RMS ripple current given by IRMS = IPK(PFM)/2. In this design example, select two 100-μF, 10V capacitors with a high-quality dielectric.
8.2.4.2.5 Input Capacitor – CIN
The input capacitor, CIN, filters the triangular current waveform of the high-side MOSFET (see Figure 89). To
prevent large ripple voltage, use a low-ESR ceramic input capacitor sized for the worst-case RMS ripple current
given by IRMS = IOUT/2. In this design example, choose a 4.7-μF, 50-V ceramic input capacitor with a high-quality
dielectric.
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8.2.4.3 Application Curves
Unless otherwise stated, application curves were taken at TA = 25°C.
5.1
100
5.08
90
5.06
5.04
VOUT (V)
Efficiency (%)
80
70
60
5.02
5
4.98
4.96
50
VIN = 8V
VIN = 12V
VIN = 24V
VIN = 36V
40
30
0.01
0.1
1
10
Load (mA)
LF = 22 µH
COUT = 200 µF
100
4.92
500
4.9
0.01
LF = 22 µH
COUT = 200 µF
Figure 78. Converter Efficiency
CH2: VOUT, 50 mV/Div
CH4: IL, 0.4 A/Div
CH2: VOUT, 1 V/Div
CH4: IL, 0.4 A/Div
100
500
D001
FSW(nom) = 100 kHz
RRT = 0 Ω
Time Scale: 20 µs/Div
CH1: VSW, 5 V/Div
CH2: VOUT, 100 mV/Div
CH4: IL, 0.4 A/Div
Figure 81. Full-Load Switching Waveforms
Time Scale: 50 µs/Div
CH1: VSW, 4 V/Div
CH4: IL, 0.4 A/Div
Figure 83. Short Circuit
Figure 82. Full-Load Start-Up
40
1
10
Load (mA)
Figure 79. Converter Regulation
Figure 80. No-Load Switching Waveforms
Time Scale: 2 ms/Div
CH1: VIN, 2 V/Div
0.1
D001
FSW(nom) = 100 kHz
RRT = 0 Ω
Time Scale: 50 ms/Div
CH1: VSW, 5 V/Div
VIN = 8V
VIN = 12V
VIN = 24V
VIN = 36V
4.94
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8.2.5 Design 5: 12-V, 300-mA COT Converter Operating From 24-V or 48-V Input
The schematic diagram of 12-V, 300-mA COT converter is given in Figure 84.
LF
100 H
U1
VIN = 24 V...65 V
VIN
RUV1
LM5166
10 M:
CIN
4.7 F
649 k:
PGOOD
FB
HYS
SS
RHYS
ILIM
14 k:
CA
CB
2.2 nF
100 pF
RA
402 k:
EN
RUV2
VOUT = 12 V
IOUT = 0.3 A
SW
RT
RFB1
1 M:
COUT
10 F
RFB2
CSS
113 k:
47 nF
GND
RRT
169 k:
Copyright © 2017, Texas Instruments Incorporated
Figure 84. Schematic for Design 5 With VOUT = 12 V, IOUT(max) = 300 mA, FSW(nom) = 400 kHz
8.2.5.1 Design Requirements
The full-load efficiency specifications are 93% and 89% based on input voltages of 24 V and 48 V, respectively,
and an output voltage setpoint of 12 V. The input voltage range is 24 V to 65 V, with UVLO turnon and turnoff at
20 V and 18 V, respectively. The output voltage setpoint is established by feedback resistors, RFB1 and RFB2. The
required components are listed in Table 8.
Table 8. List of Components for Design 5 (1)
REF DES
QTY
CIN
1
COUT
1
SPECIFICATION
VENDOR
PART NUMBER
4.7 µF, 100 V, X7S, 1210
Murata
GRM31CR71H475MA12L
4.7 µF, 80 V, X7R, 1210
Murata
GRM32ER71K475KE14L
Murata
GRM31CR71E106MA12L
TDK
C3216X7R1E106M
Würth
885012208069
10 µF, 25 V, X7R, 1206
LF
1
100 µH ±20%, 0.54 A, 375 mΩ maximum DCR, 6 × 6 × 3.5 mm
Coilcraft
LPS6235-104MRC
RA
1
402 kΩ, 1%, 0402
Std
Std
RFB1
1
1 MΩ, 1%, 0402
Std
Std
RFB2
1
113 kΩ, 1%, 0402
Std
Std
RUV1
1
10 MΩ, 1%, 0603
Std
Std
RUV2
1
649 kΩ, 1%, 0402
Std
Std
RHYS
1
14 kΩ, 1%, 0402
Std
Std
RRT
1
169 kΩ, 1%, 0402
Std
Std
CA
1
2.2 nF, 25 V, X7R, 0402
Std
Std
CB
1
100 pF, 50 V, NP0, 0402
Std
Std
CSS
1
47 nF, 16 V, X7R, 0402
Std
Std
U1
1
LM5166 Synchronous Buck Converter, VSON-10, 3 mm × 3 mm
TI
LM5166DRCR
(1)
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8.2.5.2 Detailed Design Procedure
The component selection procedure for this design is quite similar to that of COT designs 1 and 2.
8.2.5.2.1 Peak Current Limit Setting – RILIM
Leave the ILIM pin open circuit to select the 500-mA peak current limit setting for a rated output current of 300
mA. See Table 3.
8.2.5.2.2 Switching Frequency – RRT
Using Equation 4, select a standard 1% resistor value of 169 kΩ to set a switching frequency of 400 kHz.
8.2.5.2.3 Inductor – LF
Choosing a 100-μH inductor in this design results in 150-mA peak-to-peak ripple current at an input voltage of 24
V, equivalent to 50% of the 300-mA rated load current. A larger ripple current design results in improved lightload efficiency. The peak inductor current at maximum input voltage of 65 V is 424 mA, which is sufficiently
below the LM5166 peak current limit of 500 mA. Select an inductor with saturation current rating well above the
peak current limit setting, and allow for derating of the saturation current at the highest expected operating
temperature.
8.2.5.2.4 Input and Output Capacitors – CIN, COUT
Choose a 4.7-µF, 80-V or 100-V ceramic input capacitor with 1210 footprint. Such a capacitor is typically
available in X7S or X7R dielectric. Based on Equation 24, select a 10-µF, 25-V ceramic output capacitor with
X7R dielectric and 1206 footprint.
8.2.5.2.5 Feedback Resistors – RFB1, RFB2
Select RFB1 of 1 MΩ to minimize quiescent current and improve light-load efficiency in this application. With the
desired output voltage setpoint of 12 V and VFB = 1.223 V, calculate the resistance of RFB2 using Equation 15 as
113.5 kΩ. Choose the closest available standard value of 113 kΩ for RFB2. See Adjustable Output Voltage (FB)
for more detail.
8.2.5.2.6 Ripple Generation Network – RA, CA, CB
Select the ripple injection circuit components RA and CA values using Equation 10 and Equation 11. Choose
capacitor CB using Equation 12 based on a target transient response settling time of 300 µs.
8.2.5.2.7 Undervoltage Lockout Setpoint – RUV1, RUV2, RHYS
Adjust the undervoltage lockout (UVLO) using an externally-connected resistor divider network of RUV1, RUV2, and
RHYS. The UVLO has two thresholds, one for power up when the input voltage is rising and one for power down
or brownouts when the input voltage is falling. The EN rising threshold for the LM5166 is 1.22 V.
Rearranging Equation 16 and Equation 17, the expressions to calculate RUV2 and RHYS are as follows:
VEN(on)
RUV2
˜ RUV1
VIN(on) VEN(on)
RHYS
VEN(off)
VIN(off)
VEN(off)
(32)
˜ RUV1 RUV2
(33)
Choose RUV1 as 10 MΩ to minimize input quiescent current. Given the desired input voltage UVLO thresholds of
20 V and 18 V, calculate the resistance of RUV2 and RHYS as 649 kΩ and 14 kΩ, respectively. See Precision
Enable (EN) and Hysteresis (HYS) for more detail.
8.2.5.2.8 Soft Start – CSS
Install a 47-nF capacitor from SS to GND for a soft-start time of 6 ms.
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8.2.5.3 Application Curves
Unless otherwise stated, application curves were taken at TA = 25°C.
100
VOUT 20 mV/DIV
90
Efficiency (%)
80
70
60
50
VIN = 24V
VIN = 36V
VIN = 48V
VIN = 65V
40
30
0.1
1
10
Load (mA)
100
300
IOUT 100 mA/DIV
200 Ps/DIV
Time Scale: 200 µs/Div
CH3: VOUT, 20 mV/Div
CH4: IOUT, 0.1 A/Div
Figure 86. Load Transient Waveforms, 100 mA to 300 mA
Figure 85. Converter Efficiency
VOUT 2 V/DIV
VOUT 2 V/DIV
VIN 10 V/DIV
IOUT 100 mA/DIV
2 ms/DIV
Time Scale: 2 ms/Div
CH2: VIN, 10 V/Div
CH3: VOUT, 2 V/Div
CH4: IOUT, 0.1 A/Div
VIN 10 V/DIV
IOUT 100 mA/DIV
Time Scale: 2 ms/Div
CH2: VIN, 10 V/Div
2 ms/DIV
CH3: VOUT, 2 V/Div
CH4: IL, 0.1 A/Div
Figure 88. Shutdowm Waveforms
Figure 87. Start-up Waveforms
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9 Power Supply Recommendations
The LM5166 is designed to operate from an input voltage supply range between 3 V and 65 V. This input supply
should be able to withstand the maximum input current and maintain a voltage above 3 V. Ensure that the
impedance of the input supply rail is low enough that an input current transient does not cause a high enough
drop at the LM5166 supply voltage to create a false UVLO fault triggering and system reset. If the input supply is
placed more than a few inches from the LM5166 converter, additional bulk capacitance may be required in
addition to the ceramic bypass capacitors. A 10-μF electrolytic capacitor is a typical choice for this function,
whereby the capacitor ESR provides a level of damping against input filter resonances. A typical ESR of 0.5 Ω
provides enough damping for most input circuit configurations.
10 Layout
The performance of any switching converter depends as much upon PCB layout as it does the component
selection. The following guidelines are provided to assist with designing a PCB with the best power conversion
performance, thermal performance, and minimized generation of unwanted EMI.
10.1 Layout Guidelines
PCB layout is a critical portion of good power supply design. There are several paths that conduct high slew-rate
currents or voltages that can interact with stray inductance or parasitic capacitance to generate noise and EMI or
degrade the power supply performance.
1. To help eliminate these problems, bypass the VIN pin to GND with a low-ESR ceramic bypass capacitor with
a high-quality dielectric. Place CIN as close as possible to the LM5166 VIN and GND pins. Grounding for
both the input and output capacitors should consist of localized top-side planes that connect to the GND pin
and GND PAD.
2. Minimize the loop area formed by the input capacitor connections to the VIN and GND pins.
3. Locate the inductor close to the SW pin. Minimize the area of the SW trace or plane to prevent excessive
capacitive coupling.
4. Tie the GND pin directly to the power pad under the device and to a heat-sinking PCB ground plane.
5. Use a ground plane in one of the middle layers as noise shielding and heat dissipation path.
6. Have a single-point ground connection to the plane. Route the ground connections for the feedback, softstart, and enable components to the ground plane. This prevents any switched or load currents from flowing
in analog ground traces. If not properly handled, poor grounding results in degraded load regulation or erratic
output voltage ripple behavior.
7. Make VIN, VOUT and ground bus connections as wide as possible. This reduces any voltage drops on the
input or output paths of the converter and maximizes efficiency.
8. Minimize trace length to the FB pin. Place both feedback resistors, RFB1 and RFB2, close to the FB pin. Place
CFF (if needed) directly in parallel with RFB1. If output setpoint accuracy at the load is important, connect the
VOUT sense at the load. Route the VOUT sense path away from noisy nodes and preferably through a layer on
the other side of a shielding layer.
9. The RT pin is sensitive to noise. Thus, locate the RRT resistor as close as possible to the device and route
with minimal lengths of trace. The parasitic capacitance from RT to GND must not exceed 20 pF.
10. Provide adequate heat sinking for the LM5166 to keep the junction temperature below 150°C. For operation
at full rated load, the top-side ground plane is an important heat-dissipating area. Use an array of heatsinking vias to connect the exposed pad to the PCB ground plane. If the PCB has multiple copper layers,
these thermal vias must also be connected to inner layer heat-spreading ground planes.
10.1.1 Compact PCB Layout for EMI Reduction
Radiated EMI generated by high di/dt components relates to pulsing currents in switching converters. The larger
area covered by the path of a pulsing current, the more electromagnetic emission is generated. The key to
minimizing radiated EMI is to identify the pulsing current path and minimize the area of that path.
The critical switching loop of the buck converter power stage in terms of EMI is denoted in Figure 89. The
topological architecture of a buck converter means that a particularly high di/dt current path exists in the loop
comprising the input capacitor and the integrated MOSFETs of the LM5166, and it becomes mandatory to reduce
the parasitic inductance of this loop by minimizing the effective loop area.
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Layout Guidelines (continued)
VIN
VIN
2
CIN
LM5166
High-side
PMOS
gate driver
High
di/dt
loop
Q1
LF
1
Low-side
NMOS
gate driver
SW
VOUT
COUT
Q2
10
GND
GND
Figure 89. DC-DC Buck Converter With Power Stage Circuit Switching Loops
The input capacitor provides the primary path for the high di/dt components of the high-side MOSFET's current.
Placing a ceramic capacitor as close as possible to the VIN and GND pins is the key to EMI reduction. Keep the
trace connecting SW to the inductor as short as possible and just wide enough to carry the load current without
excessive heating. Use short, thick traces or copper pours (shapes) for current conduction path to minimize
parasitic resistance. Place the output capacitor close to the VOUT side of the inductor, and connect the capacitor's
return terminal to the GND pin and exposed PAD of the LM5166.
10.1.2 Feedback Resistors
For the adjustable output voltage version of the LM5166, reduce noise sensitivity of the output voltage feedback
path by placing the resistor divider close to the FB pin, rather than close to the load. This reduces the trace
length of FB signal and noise coupling. The FB pin is the input to the feedback comparator, and as such is a high
impedance node sensitive to noise. The output node is a low impedance node, so the trace from VOUT to the
resistor divider can be long if a short path is not available.
Route the voltage sense trace from the load to the feedback resistor divider, keeping away from the SW node,
the inductor and VIN to avoid contaminating the feedback signal with switch noise, while also minimizing the trace
length. This is most important when high feedback resistances, greater than 100 kΩ, are used to set the output
voltage. Also, route the voltage sense trace on a different layer from the inductor, SW node and VIN, such that
there is a ground plane that separates the feedback trace from the inductor and SW node copper polygon. This
provides further shielding for the voltage feedback path from switching noise sources
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10.2 Layout Example
Figure 90 shows an example layout for the PCB top layer of a 4-layer board with essential components placed
on the top side. The bottom layer features optional Type 3 ripple generation components (RA and CA), and RUV1,
RUV2, and RHYS resistors.
LF
Vias to Type 3 Ripple
Generation Network
(Optional)
VIN
connection
CIN
VOUT
connection
COUT
Place ceramic
input cap close
to VIN and GND
RFB2
RFB1
RESR
CFF
RILIM
Place SS cap
close to pin
CSS
CB
RRT
GND
connection
Thermal vias under
LM5166 PAD
Place FB resistors very
close to FB & GND pins
Figure 90. LM5166 Single-Sided PCB Layout Example
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11 Device and Documentation Support
11.1 Device Support
11.1.1 Third-Party Products Disclaimer
TI'S PUBLICATION OF INFORMATION REGARDING THIRD-PARTY PRODUCTS OR SERVICES DOES NOT
CONSTITUTE AN ENDORSEMENT REGARDING THE SUITABILITY OF SUCH PRODUCTS OR SERVICES
OR A WARRANTY, REPRESENTATION OR ENDORSEMENT OF SUCH PRODUCTS OR SERVICES, EITHER
ALONE OR IN COMBINATION WITH ANY TI PRODUCT OR SERVICE.
11.1.2 Development Support
• LM5166 Quickstart Calculator
• LM5166 Simulation Models
• For TI's Reference Design Library, visit TIDesigns
• For TI's WEBENCH Design Environment, visit the WEBENCH® Design Center
11.1.3 Custom Design With WEBENCH® Tools
Click here to create a custom design using the LM5166 device with the WEBENCH® Power Designer.
1. Start by entering the input voltage (VIN), output voltage (VOUT), and output current (IOUT) requirements.
2. Optimize the design for key parameters such as efficiency, footprint, and cost using the optimizer dial.
3. Compare the generated design with other possible solutions from Texas Instruments.
The WEBENCH Power Designer provides a customized schematic along with a list of materials with real-time
pricing and component availability.
In most cases, these actions are available:
• Run electrical simulations to see important waveforms and circuit performance
• Run thermal simulations to understand board thermal performance
• Export customized schematic and layout into popular CAD formats
• Print PDF reports for the design, and share the design with colleagues
Get more information about WEBENCH tools at www.ti.com/WEBENCH.
11.2 Documentation Support
11.2.1 Related Documentation
For related documentation see the following:
• LM5166EVM-C50A EVM User's Guide (SNVU485)
• LM5166EVM-C33A EVM User's Guide (SNVU544)
• Low-IQ Synchronous Buck Converter Enables Intelligent Field-sensor Applications (SLYT671)
• Low EMI Buck Converter Powers a Multivariable Sensor Transmitter with BLE Connectivity (SLYT693)
• Selecting an Ideal Ripple Generation Network for Your COT Buck Converter (SNVA776)
• TI Designs:
– TIDA-01487 Isolated CAN Flexible Data(FD) Rate Repeater Reference Design (TIDUDB5)
– TIDA-01437 RGB Signal Light with IO-Link Interface Reference Design (TIDUD35)
– TIDA-01395 24-V AC Power Stage with Wide VIN Converter and Battery Gauge for Smart Thermostat
(TIDUCW0)
– TIDA-01386 Ultrasonic Distance Sensor with IO-Link Reference Design (TIDUDB2)
– TIDA-01358 24-V AC Power Stage with Wide VIN Converter and Battery Backup for Smart Thermostat
(TIDUCE1)
– TIPD215 Less than 1 W, Quad-Channel, Analog Output Module with Adaptive Power Management
Reference Design (TIDUCV5)
– TIDA-00666 Field Transmitter with Bluetooth® Low Energy Connectivity Powered from 4 to 20-mA Current
Loop (TIDUC27)
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Documentation Support (continued)
•
•
•
•
•
•
Industrial Strength Blogs:
– Powering Smart Sensor Transmitters in Industrial Applications
– Industrial Strength Design – Part 1
– Trends in Building Automation: Predictive Maintenance
– Trends in Building Automation: Connected Sensors for User Comfort
White Papers:
– Valuing Wide VIN, Low-EMI Synchronous Buck Circuits for Cost-Effective, Demanding Applications
(SLYY104)
AN-2162: Simple Success with Conducted EMI from DC-DC Converters (SNVA489)
Automotive Cranking Simulator User's Guide (SLVU984)
Using New Thermal Metrics (SBVA025)
Semiconductor and IC Package Thermal Metrics (SPRA953)
11.3 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper
right corner, click on Alert me to register and receive a weekly digest of any product information that has
changed. For change details, review the revision history included in any revised document.
11.4 Community Resources
The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.
11.5 Trademarks
E2E is a trademark of Texas Instruments.
WEBENCH is a registered trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
11.6 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
11.7 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
12 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this datasheet, refer to the left-hand navigation.
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PACKAGE OPTION ADDENDUM
www.ti.com
22-Nov-2022
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
Samples
(4/5)
(6)
LM5166DRCR
ACTIVE
VSON
DRC
10
3000
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 150
5166
Samples
LM5166DRCT
ACTIVE
VSON
DRC
10
250
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 150
5166
Samples
LM5166XDRCR
ACTIVE
VSON
DRC
10
3000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 150
5166X
Samples
LM5166XDRCT
ACTIVE
VSON
DRC
10
250
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 150
5166X
Samples
LM5166YDRCR
ACTIVE
VSON
DRC
10
3000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 150
5166Y
Samples
LM5166YDRCT
ACTIVE
VSON
DRC
10
250
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 150
5166Y
Samples
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of
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