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LM556
SNAS549A – MARCH 2000 – REVISED OCTOBER 2015
LM556 Dual Timer
1 Features
3 Description
•
•
•
•
•
•
•
•
•
The LM556 dual-timing circuit is a highly-stable
controller capable of producing accurate time delays
or oscillation. The LM556 device is a dual-timing
version of the LM555 device. Timing is provided by
an external resistor and capacitor for each timing
function. The two timers operate independently of
each other, sharing only VCC and ground. The circuits
may be triggered and reset on falling waveforms. The
output structures may sink or source 200 mA.
1
Direct Replacement for SE556/NE556
Timing From Microseconds Through Hours
Operates in Both Astable and Monostable Modes
Replaces Two 555 Timers
Adjustable Duty Cycle
Output Can Source or Sink 200 mA
Output and Supply TTL-Compatible
Temperature Stability Better Than 0.005% per °C
Normally On and Normally Off Output
2 Applications
•
•
•
•
•
•
•
Precision Timing
Pulse Generation
Sequential Timing
Time Delay Generation
Pulse Width Modulation
Pulse Position Modulation
Linear Ramp Generator
Device Information(1)
PART NUMBER
LM556
PACKAGE
BODY SIZE (NOM)
SOIC (14)
3.91 mm × 8.65 mm
PDIP (14)
6.35 mm × 19.177 mm
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
Schematic Diagram
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
LM556
SNAS549A – MARCH 2000 – REVISED OCTOBER 2015
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Table of Contents
1
2
3
4
5
6
7
Features ..................................................................
Applications ...........................................................
Description .............................................................
Revision History.....................................................
Pin Configuration and Functions .........................
Specifications.........................................................
1
1
1
2
3
4
6.1
6.2
6.3
6.4
6.5
6.6
4
4
4
4
5
6
Absolute Maximum Ratings ......................................
ESD Ratings..............................................................
Recommended Operating Conditions.......................
Thermal Information ..................................................
Electrical Characteristics...........................................
Typical Characteristics ..............................................
Detailed Description .............................................. 8
7.1 Overview ................................................................... 8
7.2 Functional Block Diagram ......................................... 8
7.3 Feature Description................................................... 8
7.4 Device Functional Modes.......................................... 8
8
Application and Implementation ........................ 10
8.1 Application Information............................................ 10
8.2 Typical Application ................................................. 10
9 Power Supply Recommendations...................... 12
10 Layout................................................................... 12
10.1 Layout Guidelines ................................................. 12
10.2 Layout Example .................................................... 12
11 Device and Documentation Support ................. 13
11.1
11.2
11.3
11.4
11.5
Documentation Support ........................................
Community Resources..........................................
Trademarks ...........................................................
Electrostatic Discharge Caution ............................
Glossary ................................................................
13
13
13
13
13
12 Mechanical, Packaging, and Orderable
Information ........................................................... 13
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Original (March 2000) to Revision A
Page
•
Added ESD Ratings table, Feature Description section, Device Functional Modes, Application and Implementation
section, Power Supply Recommendations section, Layout section, Device and Documentation Support section, and
Mechanical, Packaging, and Orderable Information section. ................................................................................................ 1
•
Deleted the VCC = 5 V and ISINK = 8 mA test condition row for the Output voltage drop parameter in the Electrical
Characteristics table ............................................................................................................................................................... 5
2
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5 Pin Configuration and Functions
D or NFF Package
14-Pin SOIC or PDIP
Top View
DISCHARGE
1
14
VCC
THRESHOLD
2
13
DISCHARGE
CTRL VOLTAGE
3
12
THRESHOLD
RESET
4
11
CTRL VOLTAGE
OUTPUT
5
10
RESET
TRIGGER
6
9
OUTPUT
GND
7
8
TRIGGER
Pin Functions
PIN
NAME
NO.
I/O
DESCRIPTION
CONTROL
VOLTAGE
(Timer 0)
3
I
Controls the threshold and trigger levels. It determines the pulse width of the output
waveform. An external voltage applied to this pin can also be used to modulate the output
waveform.
CONTROL
VOLTAGE
(Timer 1)
11
I
Controls the threshold and trigger levels. It determines the pulse width of the output
waveform. An external voltage applied to this pin can also be used to modulate the output
waveform.
DISCHARGE
(Timer 0)
1
I
Open collector output which discharges a capacitor between intervals (in phase with output).
It toggles the output from high to low when voltage reaches 2/3 of supply voltage.
DISCHARGE
(Timer 1)
13
I
Open collector output which discharges a capacitor between intervals (in phase with output).
It toggles the output from high to low when voltage reaches 2/3 of supply voltage.
GND
7
O
Ground reference voltage
OUTPUT
(Timer 0)
5
O
Output driven waveform
OUTPUT
(Timer 1)
9
O
Output driven waveform
RESET
(Timer 0)
4
I
Negative pulse applied to this pin to disable or reset the timer. When not used for reset
purposes, it should be connected to Vcc to avoid false triggering.
RESET
(Timer 1)
10
I
Negative pulse applied to this pin to disable or reset the timer. When not used for reset
purposes, it should be connected to Vcc to avoid false triggering.
THRESHOLD
(Timer 0)
2
I
Compares the voltage applied to the terminal with a reference voltage of 2/3 VCC. The
amplitude of voltage applied to this terminal is responsible for the set state of the flip-flop.
TRIGGER
(Timer 0)
6
I
Responsible for transition of the flip-flop from set to reset. The output of the timer depends
on the amplitude of the external trigger pulse applied to this pin.
THRESHOLD
(Timer 1)
12
I
Compares the voltage applied to the terminal with a reference voltage of 2/3 VCC. The
amplitude of voltage applied to this terminal is responsible for the set state of the flip-flop.
TRIGGER
(Timer 1)
8
I
Responsible for transition of the flip-flop from set to reset. The output of the timer depends
on the amplitude of the external trigger pulse applied to this pin.
VCC
14
I
Supply voltage with respect to GND
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6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted) (1) (2)
MIN
Supply voltage
Power dissipation (3)
(2)
(3)
V
410
LM556CN
1620
0
mW
70
°C
PDIP package soldering (10 seconds)
260
SOIC package vapor phase (60 seconds)
215
SOIC package infrared (15 seconds)
220
Storage temperature, Tstg
(1)
UNIT
18
LM556CM
Operating temperature, LM556C
Soldering information
MAX
–65
°C
150
°C
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/ Distributors for availability
and specifications.
For operating at elevated temperatures the device must be derated based on a 150°C maximum junction temperature and a thermal
resistance of 77°C/W (Plastic Dip), and 110°C/W (SO-14 Narrow).
6.2 ESD Ratings
V(ESD)
(1)
Electrostatic discharge
Human body model (HBM), per ANSI/ESDA/JEDEC JS-001
(1)
VALUE
UNIT
±500
V
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
6.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
VCC
Supply voltage
TA
Operating temperature
MIN
MAX
UNIT
4.5
16
V
0
70
°C
6.4 Thermal Information
LM556
THERMAL METRIC (1)
D (SOIC)
NFF (PDIP)
UNIT
14 PINS
14 PINS
RθJA
Junction-to-ambient thermal resistance
85.3
48.0
°C/W
RθJC(top)
Junction-to-case (top) thermal resistance
45.8
34.9
°C/W
RθJB
Junction-to-board thermal resistance
39.6
27.9
°C/W
ψJT
Junction-to-top characterization parameter
11.7
19.3
°C/W
ψJB
Junction-to-board characterization parameter
39.4
27.8
°C/W
RθJC(bot)
Junction-to-case (bottom) thermal resistance
—
—
°C/W
(1)
4
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report, SPRA953.
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6.5 Electrical Characteristics
TA = 25°C, VCC = 5 V to 15 V, unless otherwise specified
PARAMETER
TEST CONDITIONS
Supply voltage
MIN
Supply current (each timer section)
VCC = 5 V, RL = ¥
VCC = 15 V, RL = ¥ (low state) (1)
Initial accuracy
Timing error,
monostable
Drift with temperature
Accuracy over temperature
Accuracy over temperature
6
10
14
0.30
5
5.5
VCC = 5 V
1.25
1.67
2
0.2
1
0.5
1
0.1
0.6
mA
0.1
µA
250
nA
0.03
VTH = 11.2 V
VCC = 15 V
VCC = 5 V
9
10
11
2.6
3.33
4
1
100
VCC = 15 V, I = 15 mA
180
300
VCC = 4.5 V, I = 4.5 mA
80
200
ISINK = 10 mA
0.1
0.25
ISINK = 50 mA
0.4
0.75
ISINK = 100 mA
2
2.75
ISINK = 200 mA
2.5
VCC = 15 V
VCC = 5 V, ISINK = 5 mA
0.25
ISOURCE = 200 mA, VCC = 15 V
12.5
ISOURCE = 100 mA, VCC = 15 V
VCC = 5 V
12.75
2.75
Fall time of output
100
0.1%
See
(5)
Drift with supply voltage
(1)
(2)
(3)
(4)
(5)
µA
V
V
nA
mV
V
0.35
V
3.3
100
Initial timing accuracy
V
13.3
Rise time of output
Timing drift with temperature
%/V
4.5
Pin 1, 13 leakage output high
Matching
characteristics
ppm/°C
VCC = 15 V
VTH = V-control (3)
Output voltage drop (high)
%/V
3%
Reset current
Output voltage drop (low)
ppm/°C
150
RA, RB = 1 k to 100 kΩ,
C = 0.1 μF (2)
0.4
Pin 1, 13 sat output low (4)
mA
0.1
Reset voltage
Control voltage level and threshold voltage
V
2.25%
Trigger current
Threshold current
3
1.5%
Drift with supply
Trigger voltage
UNIT
16
50
RA = 1 k to 100 kΩ,
C = 0.1 μF (2)
Initial accuracy
Drift with temperature
MAX
0.75%
Drift with supply
Timing error,
astable
TYP
4.5
ns
ns
2%
±10
0.2
ppm/°C
0.5
%/V
Supply current when output high typically 1 mA less at VCC = 5 V.
Tested at VCC = 5 V and VCC = 15 V.
This will determine the maximum value of RA + RB for 15-V operation. The maximum total (RA + RB) is 20 MΩ.
No protection against excessive pin 1, 13 current is necessary providing the package dissipation rating will not be exceeded.
Matching characteristics refer to the difference between performance characteristics of each timer section.
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6.6 Typical Characteristics
DS007852-4
6
Figure 1. Minimum Pulse Width Required for Triggering
Figure 2. Supply Current vs Supply Voltage (Each Section)
Figure 3. High Output Voltage vs Output Source Current
Figure 4. Low Output Voltage vs Output Sink Current
Figure 5. Low Output Voltage vs Output Sink Current
Figure 6. Low Output Voltage vs Output Sink Current
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Typical Characteristics (continued)
DS007852-10
Figure 7. Output Propagation Delay vs Voltage Level of
Trigger Pulse
Figure 8. Output Propagation Delay vs Voltage Level of
Trigger Pulse
Figure 9. Discharge Transistor (Pin 1, 13) Voltage vs Sink
Current
Figure 10. Discharge Transistor (Pin 1, 13) Voltage vs Sink
Current
DS007852-12
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7 Detailed Description
7.1 Overview
The LM556 dual-timing circuit is a highly stable device for generating accurate time delays or oscillations. The
two timers operate independently from one another, only sharing VCC and ground. For each individual timer,
additional terminals are provided for triggering or resetting. In the monostable mode of operation, the time is
precisely controlled by one external resistor and capacitor. For astable mode operation as an oscillator, the free
running frequency and duty cycle are accurately controlled with two external resistors and one capacitor. The
circuit may be triggered and reset on falling waveforms and the output circuit can source or sink up to 200 mA.
7.2 Functional Block Diagram
7.3 Feature Description
7.3.1 Operating Characteristics
The LM556 is specified for operation from 4.5 V to 16 V. Many of the specifications apply from 0⁰C to 70⁰C.
Parameters that can exhibit significant variance with regard to operating voltage or temperature are presented
Electrical Characteristics section and in and Typical Characteristics.
7.3.2 Timing from Microseconds Through Hours
The LM556 has the ability to have timing parameters from the microseconds range to hours. The time delay of
the system can be determined by the time constant of the R and C values used for either the monostable or
astable configuration. A nomograph is available for easy determination of R and C values for various time delays.
7.4 Device Functional Modes
The LM556 can operate in both astable and monostable mode depending on the application requirements.
7.4.1 Monostable Mode
The LM556 timer acts as a one-shot pulse generator. The pulse begins when the LM556 timer receives a signal
at the trigger input that falls below 1/3 of the voltage supply. The width of the output pulse is determined by the
time constant of an RC network. The output pulse ends when the voltage on the capacitor equals 2/3 of the
supply voltage. The output pulse width can be extended or shortened depending on the application by adjusting
the R and C values. More details are given in the LM555 datasheet (SNAS548).
8
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Device Functional Modes (continued)
Figure 11. Monostable
7.4.2 Astable (Free-Running) Mode
The LM556 timer can operate as an oscillator and puts out a continuous stream of rectangular pulses having a
specified frequency. The frequency of the pulse stream depends on the values of RA, RB, and C. Again, more
details are given in the LM555 datasheet (SNAS548).
Figure 12. Astable
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8 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
8.1 Application Information
The LM556 timer can be used in various configurations. A typical application for the LM556 timer in astable
mode is to drive an audio device (such as a beeper) to provide a pulsed sound. This simple application can be
modified to fit any application requirement.
8.2 Typical Application
R2A
4
2
Vin
0.01 µF
10 µF
R1A
1
LM556
5
6
3
10
13
12
9
8
11
14
7
Vout
0.01 µF
R1B
0.01 µF
100 µF
R2B
Figure 13. Typical Application
8.2.1 Design Requirements
The main design requirements for this application require setting one of the timers (Timer A in this case) to the
same resonant frequency as the piezo transducer which can be set by choosing R1A, R2A, and CA with
Equation 1:
1.44
fo =
((R1A + 2R2 A )C )
(1)
The other design choice is to decide how often and long to produce the bleeping sound. This can be set by
choosing R1B and R2B of Timer B (acts as the reset button for Timer A) with Equation 2:
R2B
D=
R1B + R2B
(2)
Other useful design equations like Equation 3 and Equation 4 are given below where th represents the time it
takes to charge the capacitor of each individual timer and tl represents the time it takes to discharge the
capacitor.
10
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Typical Application (continued)
th = 0.693(R1 +R2 )C
where
•
th represents the time it takes to charge the capacitor of each individual timer
(3)
tl = 0.693R2C
where
•
tl represents the time it takes to discharge the capacitor.
(4)
8.2.2 Detailed Design Procedure
Given that the resonant frequency of the piezo transducer is about 3 kHz, by choosing R1, C and using
Equation 1, R2 can be determined to be 23.5 kΩ.
In order to have the sound be audible for half the period, the duty cycle for the triggering timer should be 50%.
However, this is difficult to achieve because the recommended minimum value for R1 is 1 kΩ. Therefore, a duty
cycle of 49% was chosen for this application. By choosing R1 to be 1 kΩ and using Equation 2, R2 is found to be
24.5 kΩ.
8.2.3 Application Curve
Output Waveform
VCC
0V
Capacitor Voltage Waveform
VCC
2/3 VCC
1/3 VCC
0V
tl
th
TS
Figure 14. Capacitor Voltage and Output Waveforms in Astable Mode
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9 Power Supply Recommendations
The LM556 requires a voltage supply within 4.5 V to 16 V. Adequate power supply bypassing is necessary to
protect associated circuitry. The minimum recommended capacitor value is 0.1 µF in parallel with a 1-µF
electrolytic capacitor. Place the bypass capacitors as close as possible to the LM556 and minimize the trace
length
CAUTION
Supply voltages larger than 18 V can permanently damage the device; see the
Absolute Maximum Ratings table.
10 Layout
10.1 Layout Guidelines
Standard PCB rules apply to routing the LM556. The parallel combination of a 0.1-µF capacitor and a 1-µF
electrolytic capacitor should be as close as possible to the LM556. The capacitor used for the time delay should
also be placed as close as possible to the discharge pin. A ground plane on the bottom layer can be used to
provide better noise immunity and signal integrity.
10.2 Layout Example
2
GND
1: DIS_A
14: VCC
2: THR_A
13: DIS_B
3: CVOLT_A
12: THR_B
4: OUT_B
11: CVOLT_B
5: OUT_A
10: RST_B
6: THR_A
9: OUT_B
7: GND
8: THR_B
1
VCC
Figure 15. Layout Example
12
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11 Device and Documentation Support
11.1 Documentation Support
11.1.1 Related Documentation
For related documentation, see the following:
LM555 Timer, SNAS548
11.2 Community Resources
The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.
11.3 Trademarks
E2E is a trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
11.4 Electrostatic Discharge Caution
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
11.5 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
12 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
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PACKAGE OPTION ADDENDUM
www.ti.com
27-Jul-2016
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
Lead/Ball Finish
MSL Peak Temp
(2)
(6)
(3)
Op Temp (°C)
Device Marking
(4/5)
LM556 MD8
ACTIVE
DIESALE
Y
0
324
Green (RoHS
& no Sb/Br)
Call TI
Level-1-NA-UNLIM
-55 to 125
LM556 MWC
ACTIVE
WAFERSALE
YS
0
1
Green (RoHS
& no Sb/Br)
Call TI
Level-1-NA-UNLIM
-40 to 85
LM556CM
LIFEBUY
SOIC
D
14
55
TBD
Call TI
Call TI
0 to 70
LM556CM
LM556CM/NOPB
ACTIVE
SOIC
D
14
55
Green (RoHS
& no Sb/Br)
CU SN
Level-1-260C-UNLIM
0 to 70
LM556CM
LM556CMX/NOPB
ACTIVE
SOIC
D
14
2500
Green (RoHS
& no Sb/Br)
CU SN
Level-1-260C-UNLIM
0 to 70
LM556CM
LM556CN/NOPB
ACTIVE
PDIP
NFF
14
25
Green (RoHS
& no Sb/Br)
CU SN
Level-1-NA-UNLIM
0 to 70
LM556CN
NE556V
OBSOLETE
PDIP
NFF
14
TBD
Call TI
Call TI
0 to 70
LM556CN
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
Addendum-Page 1
Samples
PACKAGE OPTION ADDENDUM
www.ti.com
27-Jul-2016
(6)
Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
28-Oct-2015
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
LM556CMX/NOPB
Package Package Pins
Type Drawing
SOIC
D
14
SPQ
Reel
Reel
A0
Diameter Width (mm)
(mm) W1 (mm)
2500
330.0
16.4
Pack Materials-Page 1
6.5
B0
(mm)
K0
(mm)
P1
(mm)
9.35
2.3
8.0
W
Pin1
(mm) Quadrant
16.0
Q1
PACKAGE MATERIALS INFORMATION
www.ti.com
28-Oct-2015
*All dimensions are nominal
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
LM556CMX/NOPB
SOIC
D
14
2500
367.0
367.0
35.0
Pack Materials-Page 2
MECHANICAL DATA
NFF0014A
N0014A
N14A (Rev G)
www.ti.com
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