LM567, LM567C
ZHCSP37F – MAY 1999 – REVISED JANUARY 2022
LM567x 语音解码器
1 特性
•
•
•
•
•
•
•
频率范围为 20:1（可通过外部电阻器调整）
具有 100mA 灌电流能力的逻辑兼容输出
带宽在 0 至 14% 之间可调
有效抑制带外信号和噪声
抗虚假信号干扰
中心频率高度稳定
中心频率在 0.01Hz 至
500kHz 之间可调
2 应用
•
•
•
•
•
•
•
按键音解码
精密振荡器
频率监测和控制
宽带 FSK 调制
超声波控制
载波电流遥控
通信寻呼解码器
3 说明
LM567 和 LM567C 为通用型语音解码器，设计用于在
通带内有输入信号时，将饱和晶体管的开关接地。电路
包含由压控振荡器驱动的 I 和 Q 检测器，该振荡器决
定了解码器的中心频率。外部元件用于独立设定中心频
率、带宽和输出延迟。
器件信息(1)
器件型号
LM567C
(1)
封装
封装尺寸（标称值）
SOIC (8)
4.90mm × 3.91mm
PDIP (8)
9.81mm × 6.35mm
如需了解所有可用封装，请见数据表末尾的可订购产品附录。
简化版图表
本文档旨在为方便起见，提供有关 TI 产品中文版本的信息，以确认产品的概要。有关适用的官方英文版本的最新信息，请访问
www.ti.com，其内容始终优先。TI 不保证翻译的准确性和有效性。在实际设计之前，请务必参考最新版本的英文版本。
English Data Sheet: SNOSBQ4
LM567, LM567C
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ZHCSP37F – MAY 1999 – REVISED JANUARY 2022
Table of Contents
1 特性................................................................................... 1
2 应用................................................................................... 1
3 说明................................................................................... 1
4 Revision History.............................................................. 2
5 Device Comparison......................................................... 3
6 Pin Configuration and Functions...................................3
7 Specifications.................................................................. 4
7.1 Absolute Maximum Ratings........................................ 4
7.2 Recommended Operating Conditions.........................4
7.3 Thermal Information....................................................4
7.4 Electrical Characteristics.............................................5
7.5 Typical Characteristics................................................ 6
8 Parameter Measurement Information............................ 8
9 Detailed Description........................................................8
9.1 Overview..................................................................... 8
9.2 Functional Block Diagram........................................... 8
9.3 Feature Description.....................................................9
9.4 Device Functional Modes..........................................10
10 Application and Implementation................................ 12
10.1 Application Information........................................... 12
10.2 Typical Applications................................................ 12
11 Power Supply Recommendations..............................18
12 Layout...........................................................................18
12.1 Layout Guidelines................................................... 18
12.2 Layout Example...................................................... 18
13 Device and Documentation Support..........................19
13.1 接收文档更新通知................................................... 19
13.2 支持资源..................................................................19
13.3 Trademarks............................................................. 19
13.4 Electrostatic Discharge Caution..............................19
13.5 术语表..................................................................... 19
14 Mechanical, Packaging, and Orderable
Information.................................................................... 19
4 Revision History
注：以前版本的页码可能与当前版本的页码不同
Changes from Revision E (October 2014) to Revision F (January 2022)
Page
• Changed the pin number of 5 and 6 in the Pin Functions table..........................................................................3
• Changed 方程式 1 ............................................................................................................................................. 9
• Changed 方程式 2 ........................................................................................................................................... 13
Changes from Revision D (March 2013) to Revision E (October 2014)
Page
• 添加了引脚配置和功能 部分、特性说明 部分、器件功能模式、应用和实施 部分、电源相关建议 部分、布局 部
分、器件和文档支持 部分以及机械、封装和可订购信息 部分............................................................................ 1
Changes from Revision C (March 2013) to Revision D (March 2013)
Page
• Changed layout of National Data Sheet to TI format.......................................................................................... 9
2
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5 Device Comparison
表 5-1. Device Comparison
DEVICE NAME
LM567, LM567C
LMC567
DESCRIPTION
General Purpose Tone Decoder
Same as LM567C, but lower power supply current consumption and double oscillator frequency
6 Pin Configuration and Functions
图 6-1. 8-Pin PDIP (P) and SOIC (D) Package Top View
表 6-1. Pin Functions
PIN
NAME
NO.
TYPE
DESCRIPTION
GND
7
P
Circuit ground.
IN
3
I
Device input.
LF_CAP
2
I
Loop filter capacitor pin (LPF of the PLL).
OUT
8
O
Device output.
OF_CAP
1
I
Output filter capacitor pin.
T_CAP
6
I
Timing capacitor connection pin.
T_RES
5
I
Timing resistor connection pin.
VCC
4
P
Voltage supply pin.
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7 Specifications
7.1 Absolute Maximum Ratings
See (1) (2)
MIN
MAX
UNIT
9
V
1100
mW
15
V
V3
−10
V
V3
V4 + 0.5
V
Supply Voltage Pin
Power
Dissipation(1)
V8
LM567CM, LM567CN
PDIP Package
Operating Temperature Range
SOIC Package
70
°C
Soldering (10 s)
0
260
°C
Vapor Phase (60 s)
215
°C
Infrared (15 s)
220
°C
150
°C
−65
Storage temperature range, Tstg
(1)
(2)
Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Recommended Operating Conditions
indicate conditions for which the device is functional, but do not ensure specific performance limits. Electrical Characteristics state DC
and AC electrical specifications under particular test conditions which ensure specific performance limits. This assumes that the device
is within the Recommended Operating Conditions. Specifications are not ensured for parameters where no limit is given, however, the
typical value is a good indication of device performance.
See http://www.ti.com for other methods of soldering surface mount devices.
7.2 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
MIN
MAX
UNIT
VCC
Supply Voltage
3.5
8.5
V
VIN
Input Voltage Level
–8.5
8.5
V
TA
Operating Temperature Range
–20
120
°C
7.3 Thermal Information
LM567C
THERMAL
METRIC(1)
D (SOIC)
P (PDIP)
UNIT
8 PINS
RθJA
Junction-to-ambient thermal resistance
107.5
53.0
RθJC(top)
Junction-to-case (top) thermal resistance
54.6
42.3
RθJB
Junction-to-board thermal resistance
47.5
30.2
ψJT
Junction-to-top characterization parameter
10.0
19.6
ψJB
Junction-to-board characterization parameter
47.0
30.1
(1)
4
°C/W
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report, (SPRA953).
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7.4 Electrical Characteristics
AC Test Circuit, TA = 25°C, V+ = 5 V
PARAMETER
TEST CONDITIONS
Power Supply Voltage Range
LM567
LM567C/LM567CM
UNIT
MIN
TYP
MAX
MIN
TYP
MAX
4.75
5.0
9.0
4.75
5.0
9.0
V
Power Supply Current Quiescent
RL = 20k
6
8
7
10
mA
Power Supply Current Activated
RL = 20k
11
13
12
15
mA
25
mVrms
Input Resistance
18
Smallest Detectable Input Voltage
IL = 100 mA, fi = fo
Largest No Output Input Voltage
IC = 100 mA, fi = fo
20
10
Largest Simultaneous Outband Signal to
Inband Signal Ratio
Minimum Input Signal to Wideband Noise
Ratio
Bn = 140 kHz
Largest Detection Bandwidth
12
Largest Detection Bandwidth Skew
Largest Detection Bandwidth Variation with
Temperature
Largest Detection Bandwidth Variation with
Supply Voltage
20
15
25
15
20
10
Highest Center Frequency
mVrms
6
6
dB
−6
−6
dB
14
16
1
2
±1
100
10
35 ± 60
35 ± 140
Center Frequency Shift with Supply Voltage 4.75 V – 6.75 V
4.75 V – 9 V
0.5
14
18
% of fo
2
3
% of fo
±0.1
±2
500
Center Frequency Stability (4.75 – 5.75 V) 0 < TA < 70
−55 < TA < +125
Fastest ON-OFF Cycling Rate
kΩ
15
±0.1
4.75 – 6.75 V
20
±1
100
1.0
2.0
fo/20
%/°C
±5
%V
500
kHz
35 ± 60
35 ± 140
ppm/°C
ppm/°C
0.4
2.0
2.0
%/V
%/V
fo/20
Output Leakage Current
V8 = 15 V
0.01
25
0.01
25
µA
Output Saturation Voltage
ei = 25 mV, I8 = 30 mA
ei = 25 mV, I8 = 100 mA
0.2
0.6
0.4
1.0
0.2
0.6
0.4
1.0
V
Output Fall Time
30
30
ns
Output Rise Time
150
150
ns
(1)
The maximum junction temperature of the LM567 and LM567C is 150°C. For operating at elevated temperatures, devices in the DIP
package must be derated based on a thermal resistance of 110°C/W, junction to ambient. For the SOIC package, the device must be
derated based on a thermal resistance of 160°C/W, junction to ambient.
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7.5 Typical Characteristics
6
图 7-1. Typical Frequency Drift
图 7-2. Typical Bandwidth Variation
图 7-3. Typical Frequency Drift
图 7-4. Typical Frequency Drift
图 7-5. Bandwidth vs Input Signal Amplitude
图 7-6. Largest Detection Bandwidth
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7.5 Typical Characteristics (continued)
图 7-7. Detection Bandwidth as a Function of C2 and C3
图 7-8. Typical Supply Current vs Supply Voltage
图 7-9. Greatest Number of Cycles Before Output
图 7-10. Typical Output Voltage vs Temperature
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8 Parameter Measurement Information
All parameters are measured according to the conditions described in the Specifications section.
9 Detailed Description
9.1 Overview
The LM567C is a general purpose tone decoder. The circuit consists of I and Q detectors driven by a voltage
controlled oscillator which determines the center frequency of the decoder. This device is designed to provide a
transistor switch to ground output when the input signal frequency matches the center frequency pass band.
Center frequency is set by an external timing circuit composed by a capacitor and a resistor. Bandwidth and
output delay are set by external capacitors.
9.2 Functional Block Diagram
8
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9.3 Feature Description
9.3.1 Center Frequency
The center frequency of the LM567 tone decoder is equal to the free running frequency of the voltage controlled
oscillator. In order to set this frequency, external components should be placed externally. The component
values are given by:
fo ≃ 1 / (1.1 × R1 × C1)
(1)
where
• R1 = Timing Resistor
• C1 = Timing Capacitor
9.3.2 Output Filter
To eliminate undesired signals that could trigger the output stage, a post detection filter is featured in the
LM567C. This filter consists of an internal resistor (4.7K-Ω) and an external capacitor. Although typically external
capacitor value is not critical, it is recommended to be at least twice the value of the loop filter capacitor. If the
output filter capacitor value is too large, the turn-on and turn off-time of the output will present a delay until the
voltage across this capacitor reaches the threshold level.
9.3.3 Loop Filter
The phase locked loop (PLL) included in the LM567 has a pin for connecting the low pass loop filter capacitor.
The selection of the capacitor for the filter depends on the desired bandwidth. The device bandwidth selection is
different according to the input voltage level. Refer to the Operation With Vi < 200m – VRMS section and the
Operation With Vi > 200m – VRMS section for more information about the loop filter capacitor selection.
9.3.4 Logic Output
The LM567 is designed to provide a transistor switch to ground output when the input signal frequency matches
the center frequency pass band. The logic output is an open collector power transistor that requires an external
load resistor that is used to regulate the output current level.
9.3.5 Die Characteristics
图 9-1. Die Layout (C - Step)
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表 9-1. Die and Wafer Characteristics
Fabrication Attributes
General Die Information
Physical Die Identification
LM567C
Bond Pad Opening Size (min)
91µm x 91µm
Die Step
C
Bond Pad Metalization
0.5% COPPER_BAL.
ALUMINUM
Passivation
VOM NITRIDE
Wafer Diameter
Physical Attributes
150mm
Back Side Metal
BARE BACK
Dise Size (Drawn)
1600µm x 1626µm
63.0mils x 64.0mils
Back Side Connection
Floating
Thickness
406µm Nominal
Min Pitch
198µm Nominal
Special Assembly Requirements:
Note: Actual die size is rounded to the nearest micron.
Die Bond Pad Coordinate Locations (C - Step)
(Referenced to die center, coordinates in µm) NC = No Connection, N.U. = Not Used
SIGNAL NAME
X/Y COORDINATES
PAD# NUMBER
X
PAD SIZE
Y
X
Y
OUTPUT FILTER
1
-673
686
91
x
91
LOOP FILTER
2
-673
-419
91
x
91
INPUT
3
-673
-686
91
x
91
V+
4
-356
-686
91
x
91
TIMING RES
5
673
-122
91
x
91
TIMING CAP
6
673
76
91
x
91
GND
7
178
686
117
x
91
OUTPUT
8
-318
679
117
x
104
9.4 Device Functional Modes
9.4.1 Operation With Vi < 200m – VRMS
When the input signal is below a threshold voltage, typically 200m-VRMS, the bandwidth of the detection band
should be calculated 方程式 2.
where
• Vi = Input voltage (volts rms), Vi ≤ 200mV
• C2 = Capacitance at Pin 2(μF)
10
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9.4.2 Operation With Vi > 200m – VRMS
For input voltages greater than 200m-VRMS, the bandwidth depends directly from the loop filter capacitance and
free running frequency product. Bandwidth is represented as a percentage of the free running frequency, and
according to the product of f0∙C2, it can have a variation from 2 to 14%. 表 9-2 shows the approximate values
for bandwidth in function of the product result.
表 9-2. Detection Bandwidth in Function of fo × C2
fo × C2 (kHzµF)
Bandwidth (% of fo)
62
2
16
4
7.3
6
4.1
8
2.6
10
1.8
12
1.3
14
< 1.3
14
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10 Application and Implementation
备注
以下应用部分中的信息不属于 TI 器件规格的范围，TI 不担保其准确性和完整性。TI 的客 户应负责确定
器件是否适用于其应用。客户应验证并测试其设计，以确保系统功能。
10.1 Application Information
The LM567 tone decoder is a device capable of detecting if an input signal is inside a selectable range of
detection. The device has an open collector transistor output, so an external resistor is required to achieve
proper logic levels. When the input signal is inside the detection band, the device output will go to a LOW state.
The internal VCO free running frequency establishes the detection band central frequency. An external RC filter
is required to set this frequency. The bandwidth in which the device will detect the desired frequency depends on
the capacitance of loop filter terminal. Typically a 1µF capacitor is connected to this pin. The device detection
band has a different behavior for low and high input voltage levels. Refer to the Operation With Vi < 200m –
VRMS section and the Operation With Vi > 200m – VRMS section for more information.
10.2 Typical Applications
10.2.1 Touch-Tone Decoder
Component values (typ) R1
6.8 to 15k R2
4.7k R3
20k C1
0.10 mfd C2
1.0 mfd 6V C3
2.2 mfd 6V C4
250 mfd 6V
图 10-1. Touch-Tone Decoder
12
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10.2.1.1 Design Requirements
PARAMETERS
VALUES
Supply Voltage Range
3.5 V to 8.5 V
Input Voltage Range
20 mVRMS to VCC + 0.5
Input Frequency
1 Hz to 500 kHz
Output Current
Max. 15 mA
10.2.1.2 Detailed Design Procedure
10.2.1.2.1 Timing Components
To calculate the timing components for an approximated desired central detection frequency (f0), the timing
capacitor value (C1) should be stated in order to calculate the timing resistor value (R1). Typically for most
applications, a 0.1-µF capacitor is used.
fo = 1 / (1.1 × R1 × C1)
(2)
10.2.1.2.2 Bandwidth
Detection bandwidth is represented as a percentage of f0. It can be selected based on the input voltage levels
(Vi). For Vi < 200 mVRMS,
(3)
For Vi > 200 mVRMS, refer to 表 9-2 or 图 7-5.
10.2.1.2.3 Output Filter
The output filter selection is made considering the capacitor value to be at least twice the Loop filter capacitor.
C3 ≥ 2C2
(4)
10.2.1.3 Application Curve
IN (PIN 3)
OUT (PIN 8)
图 10-2. Frequency Detection
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10.2.2 Oscillator with Quadrature Output
Connect Pin 3 to 2.8V to Invert Output
图 10-3. Oscillator with Quadrature Output
10.2.2.1 Design Requirements
Refer to the previous Design Requirements section.
10.2.2.2 Detailed Design Procedure
Refer to the previous Detailed Design Procedure section.
10.2.2.3 Application Curve
OUT 1 (PIN 3)
OUT 2 (PIN 8)
图 10-4. Quadrature Output
14
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10.2.3 Oscillator with Double Frequency Output
图 10-5. Oscillator with Double Frequency Output
10.2.3.1 Design Requirements
Refer to the previous Design Requirements section.
10.2.3.2 Detailed Design Procedure
Refer to the previous Detailed Design Procedure section.
10.2.3.3 Application Curve
OUT 1 (PIN 5)
OUT 2 (PIN 8)
图 10-6. Double Frequency Output
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10.2.4 Precision Oscillator Drive 100-mA Loads
图 10-7. Precision Oscillator Drive 100-mA Loads
10.2.4.1 Design Requirements
Refer to the previous Design Requirements section.
10.2.4.2 Detailed Design Procedure
Refer to the previous Detailed Design Procedure section.
10.2.4.3 Application Curve
OUT (PIN 8)
图 10-8. Output for 100-mA Load
16
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10.2.5 AC Test Circuit
fi = 100 kHz + 5 V
*Note: Adjust for fo = 100 kHz.
10.2.5.1 Design Requirements
Refer to the previous Design Requirements section.
10.2.5.2 Detailed Design Procedure
Refer to the previous Detailed Design Procedure section.
10.2.5.3 Application Curve
Refer to the previous Application Curve section.
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11 Power Supply Recommendations
The LM567C is designed to operate with a power supply up to 9 V. It is recommended to have a well regulated
power supply. As the operating frequency of the device could be very high for some applications, the decoupling
of power supply becomes critical, so is required to place a proper decoupling capacitor as close as possible to
VCC pin.
12 Layout
12.1 Layout Guidelines
The VCC pin of the LM567 should be decoupled to ground plane as the device can work with high switching
speeds. The decoupling capacitor should be placed as close as possible to the device. Traces length for the
timing and external filter components should be kept at minimum in order to avoid any possible interference from
other close traces.
12.2 Layout Example
图 12-1. LM567 Layout Example
18
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13 Device and Documentation Support
13.1 接收文档更新通知
要接收文档更新通知，请导航至 ti.com 上的器件产品文件夹。点击订阅更新 进行注册，即可每周接收产品信息更
改摘要。有关更改的详细信息，请查看任何已修订文档中包含的修订历史记录。
13.2 支持资源
TI E2E™ 支持论坛是工程师的重要参考资料，可直接从专家获得快速、经过验证的解答和设计帮助。搜索现有解
答或提出自己的问题可获得所需的快速设计帮助。
链接的内容由各个贡献者“按原样”提供。这些内容并不构成 TI 技术规范，并且不一定反映 TI 的观点；请参阅
TI 的《使用条款》。
13.3 Trademarks
TI E2E™ is a trademark of Texas Instruments.
所有商标均为其各自所有者的财产。
13.4 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled
with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may
be more susceptible to damage because very small parametric changes could cause the device not to meet its published
specifications.
13.5 术语表
TI 术语表
本术语表列出并解释了术语、首字母缩略词和定义。
14 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
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PACKAGE OPTION ADDENDUM
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PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
(4/5)
(6)
LM567CM/NOPB
ACTIVE
SOIC
D
8
95
RoHS & Green
SN
Level-1-260C-UNLIM
0 to 70
LM
567CM
LM567CMX/NOPB
ACTIVE
SOIC
D
8
2500
RoHS & Green
SN
Level-1-260C-UNLIM
0 to 70
LM
567CM
LM567CN/NOPB
ACTIVE
PDIP
P
8
40
RoHS & Green
NIPDAU
Level-1-NA-UNLIM
0 to 70
LM
567CN
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of
