LM62435-Q1
SNVSBP3B – MAY 2020 – REVISED JUNE 2021
LM62435-Q1 Automotive 3-V to 36-V, 3.5-A, Low EMI Synchronous Step-Down
Converter
1 Features
3 Description
•
The LM62435-Q1 is an automotive-focused,
high-performance, DC-DC synchronous step-down
converter. With integrated high-side and low-side
MOSFETs, up to 3.5 A of output current is delivered
over a wide input range of 3.0 V to 36 V; 42 V
tolerance supports load dump for durations of 400ms.
The LM62435-Q1 implements soft recovery from
dropout eliminating overshoot on the output.
•
•
•
•
•
AEC-Q100 qualified for automotive applications
– Temperature grade 1: –40°C to +150°C, TJ
Functional Safety-Capable
– Documentation available to aid functional safety
system design
Optimized for ultra low EMI requirements
– Hotrod™ package and parallel input path
minimize switch node ringing
– Spread spectrum reduces peak emissions
– Adjustable SW node rise time
– Pin selectable FPWM mode for constant
frequency at light loads
Designed for automotive applications
– Supports 42-V automotive load dump
– ±1% total output regulation accuracy
– VOUT adjustable from 1 V to 95% of VIN, with
factory options for 5-V and 3.3-V fixed output
voltage
High efficiency power conversion at all loads
– 7-µA no load current at 13.5 VIN, 3.3 VOUT
– 83% PFM efficiency at 1-mA, 13.5 VIN, 5 VOUT
– External bias option for improved efficiency
Suitable for scalable power supplies
– Pin compatible with:
• LM62440-Q1 (36 V, 4 A, fixed fSW)
• LM61460-Q1 (36 V, 6 A, adjustable fSW)
The LM62435-Q1 is specifically designed for minimal
EMI. The device incorporates pseudo-random spread
spectrum, adjustable SW node rise time, low-EMI
VQFN-HR package featuring low switch node ringing,
and optimized pinout for ease of use. The switching
frequency can be synchronized between 200 kHz
and 2.2 MHz to avoid noise sensitive frequency
bands. In addition the frequency can be selected
for improved efficiency at low operating frequency or
smaller solution size at high operating frequency.
Auto-mode enables frequency foldback when
operating at light loads, allowing an unloaded current
consumption of only 7 µA (typical) and high light
load efficiency. Seamless transition between PWM
and PFM modes, along with very low MOSFET
ON resistances and an external bias input, ensures
exceptional efficiency across the entire load range.
Device Information
2 Applications
•
Automotive infotainment and cluster: head unit,
media hub, USB charge, display
Automotive ADAS and body electronics
LM62435-Q1
(1)
PACKAGE(1)
VQFN-HR (14)
BODY SIZE (NOM)
4.00 mm × 3.50 mm
For all available packages, see the orderable addendum at
the end of the data sheet.
100
95
90
Efficiency (%)
•
PART NUMBER
85
80
75
70
VIN = 8 V
VIN = 13.5 V
VIN = 24 V
65
YELLOW: PEAK
BLUE: AVERAGE
60
0.001
0.01 0.02 0.05 0.1 0.2
Load Current (A)
0.5
1
2 3 45
SNVS
Efficiency VOUT = 5 V, FSW = 2200 kHz
Conducted EMI: VOUT = 5 V, fSW = 2100 kHz
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
LM62435-Q1
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SNVSBP3B – MAY 2020 – REVISED JUNE 2021
Table of Contents
1 Features............................................................................1
2 Applications..................................................................... 1
3 Description.......................................................................1
4 Revision History.............................................................. 2
5 Device Comparison Table...............................................3
6 Pin Configuration and Functions...................................4
7 Specifications.................................................................. 5
7.1 Absolute Maximum Ratings ....................................... 5
7.2 ESD Ratings .............................................................. 5
7.3 Recommended Operating Conditions ........................5
7.4 Thermal Information ...................................................6
7.5 Electrical Characteristics ............................................6
7.6 Timing Characteristics ................................................9
7.7 Systems Characteristics .......................................... 10
7.8 Typical Characteristics.............................................. 11
8 Detailed Description......................................................13
8.1 Overview................................................................... 13
8.2 Functional Block Diagram......................................... 14
8.3 Feature Description...................................................15
8.4 Device Functional Modes..........................................24
9 Application and Implementation.................................. 31
9.1 Application Information............................................. 31
9.2 Typical Application.................................................... 31
10 Power Supply Recommendations..............................43
11 Layout........................................................................... 44
11.1 Layout Guidelines................................................... 44
11.2 Layout Example...................................................... 46
12 Device and Documentation Support..........................47
12.1 Documentation Support.......................................... 47
12.2 Receiving Notification of Documentation Updates..47
12.3 Support Resources................................................. 47
12.4 Trademarks............................................................. 47
12.5 Electrostatic Discharge Caution..............................47
12.6 Glossary..................................................................47
13 Mechanical, Packaging, and Orderable
Information.................................................................... 47
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision A (April 2021) to Revision B (June 2021)
Page
• Added EVM thermal resistance.......................................................................................................................... 6
Changes from Revision * (May 2020) to Revision A (April 2021)
Page
• Updated the numbering format for tables, figures and cross-references throughout the document. .................1
• Changed RθJA from 59 to 58.7............................................................................................................................6
• Changed θJC(top) from 19 to 26.1.........................................................................................................................6
2
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5 Device Comparison Table
DEVICE
LM62435-Q1
ORDERABLE PART
NUMBER
REFERENCE PART
NUMBER
LM62435APPQRJRRQ1
LM62435APP-Q1
LM62435BPPQRJRRQ1
LM62435BPP-Q1
LM62435CPPQRJRRQ1
LM62435CPP-Q1
LIGHT LOAD
MODE
SPREAD
SPECTRUM
OUTPUT
VOLTAGE
SWITCHING
FREQUENCY
Pin Selectable Pin Selectable
Adjustable
2.1 MHz
Pin Selectable Pin Selectable
3.3 V
2.1 MHz
Pin Selectable Pin Selectable
5V
2.1 MHz
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SNVSBP3B – MAY 2020 – REVISED JUNE 2021
CBOOT
RBOOT
VIN2
13
12
1
5
11
PGND2
10
SW
9
8
PGOOD
VIN1
4
7
FB
EN
2
3
6
VCC
AGND
MODE/
SYNC
BIAS
14
6 Pin Configuration and Functions
PGND1
Figure 6-1. RJR Package 14-Pin VQFN-HR Top View
Table 6-1. Pin Functions
PIN
NAME
4
NO.
I/O
DESCRIPTION
BIAS
1
P
Input to internal LDO. Connect to output voltage point to improve efficiency. Connect an optional
high quality 0.1-µF to 1-µF capacitor from this pin to ground for improved noise immunity. If output
voltage is above 12 V, connect this pin to ground.
VCC
2
O
Internal LDO output. Used as supply to internal control circuits. Do not connect to any external
loads. Connect a high-quality 1-µF capacitor from this pin to AGND.
AGND
3
G
Analog ground for internal circuitry. Feedback and VCC are measured with respect to this pin.
Must connect AGND to both PGND1 and PGND2 on PCB.
FB
4
I
Output voltage feedback input to the internal control loop. Connect to output voltage sense point
for fixed 3.3 V or 5 V output voltage factory options. Connect to feedback divider tap point for
adjustable output voltage. Do not float or connect to ground.
PGOOD
5
O
Open-drain power-good status output. Pull this pin up to a suitable voltage supply through a
current limiting resistor. High = power OK, low = fault. PGOOD output goes low when EN = low,
VIN > 1 V.
MODE/SYNC
6
I
This pin controls the mode of operation of the LM62435-Q1. Modes include Auto Mode
(automatic PFM / PWM operation), FPWM, and synchronization to an external clock. When
synchronized, the clock triggers on rising edge of an external clock. Also, spread spectrum
operation is controlled by this pin. See Section 8.3.2. Do not float this pin.
EN
7
I
Precision enable input. High = on, Low = off. Can be connected to VIN. Precision enable allows
the pin to be used as an adjustable UVLO. See Section 9.
VIN1
8
P
Input supply to the converter. Connect a high-quality bypass capacitor or capacitors from this pin
to PGND1. Low impedance connection must be provided to VIN2.
PGND1
9
G
Power ground to internal low-side MOSFET. Connect to system ground. Low impedance
connection must be provided to PGND2. Connect a high-quality bypass capacitor or capacitors
from this pin to VIN1.
SW
10
O
Switch node of the converter. Connect to output inductor.
PGND2
11
G
Power ground to internal low-side MOSFET. Connect to system ground. Low impedance
connection must be provided to PGND1. Connect a high-quality bypass capacitor or capacitors
from this pin to VIN2.
VIN2
12
P
Input supply to the converter. Connect a high-quality bypass capacitor or capacitors from this pin
to PGND2. Low impedance connection must be provided to VIN1.
RBOOT
13
I/O
Connect to CBOOT through a resistor. This resistance must be between 0 Ω and open and
determines SW node rise time.
CBOOT
14
I/O
High-side driver upper supply rail. Connect a 100-nF capacitor between SW pin and CBOOT. An
internal diode connects to VCC and allows CBOOT to charge while SW node is low.
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7 Specifications
7.1 Absolute Maximum Ratings
Over the recommended operating junction temperature range of -40℃ to +150℃ (unless otherwise noted)(1)
Input Voltage
PARAMETER
MIN
VIN1, VIN2 to AGND, PGND
-0.3
42
V
RBOOT to SW
-0.3
5.5
V
CBOOT to SW
-0.3
5.5
V
BIAS to AGND, PGND
-0.3
16
V
EN to AGND, PGND
-0.3
42
V
SYNC/MODE to AGND, PGND
-0.3 lower of 42 & VIN+5
V
FB to AGND, PGND
-0.3
16
V
0
20
V
PGOOD to AGND, PGND
PGND to
Output Voltage
AGND(3)
MAX
UNIT
-1
2
V
SW to AGND, PGND(2)
-0.3
VIN+0.3
V
VCC to AGND, PGND
-0.3
5.5
V
10
mA
Current
PGOOD sink current(4)
TJ
Junction temperature
-40
150
°C
Tstg
Storage temperature
-40
150
°C
(1)
(2)
(3)
(4)
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress
ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under
Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device
reliability.
A voltage of 2 V below GND and 2 V above VIN can appear on this pin for ≤ 200 ns with a duty cycle of ≤ 0.01%.
This specification applies to voltage durations of 100 ns or less. The maximum D.C. voltage should not exceed ± 0.3 V.
Do not exceed pin’s voltage rating.
7.2 ESD Ratings
VALUE
V(ESD)
(1)
Electrostatic discharge
Human body model (HBM), per AEC
Device HBM Classification Level 2
Q100-002(1)
UNIT
±2000
V
Charged device model (CDM), per AEC Q100-011
Device CDM Classification Level C5
±750
AEC Q100-002 indicates that HBM stressing shall be in accordance with the ANSI/ESDA/JEDEC JS-001 specification.
7.3 Recommended Operating Conditions
Over the recommended operating junction temperature range of -40°C to 150°C (unless otherwise noted) (1)
MIN
Input voltage
Input voltage range after start-up
Output voltage
Output voltage range for adjustable version
Frequency
Free running frequency
Sync frequency
Synchronization frequency range
Load current
Output DC current range (3)
Temperature
Operating junction temperature TJ range
(1)
(2)
(3)
NOM
3
(2)
MAX
36
1
0.95 * VIN
2.1
UNIT
V
V
MHz
200
2200
0
3.5
kHz
A
–40
150
°C
Recommended operating conditions indicate conditions for which the device is intended to be functional, but do not ensure specific
performance limits. For ensured specifications, see Electrical Characteristics table.
Under no conditions should the output voltage be allowed to fall below zero volts.
Maximum continuous DC current may be derated when operating with high switching frequency and/or high ambient temperature. See
Application section for details.
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7.4 Thermal Information
The value of RθJA given in this table is only valid for comparison with other packages and cannot be used for design
purposes. These values were calculated in accordance with JESD 51-7, and simulated on a 4-layer JEDEC board. They do
not represent the performance obtained in an actual application. For example, with a 4-layer PCB, a RΘJA = 25℃/W can be
achieved. For design information see Maximum Ambient Temperature versus Output Current.
LM62435-Q1
THERMAL METRIC (1) (2)
RJR (QFN)
UNIT
14 PINS
RθJA
Junction-to-ambient thermal resistance (LM61460-Q1 EVM)
25
°C/W
RθJA
RθJC(top)
Junction-to-ambient thermal resistance (JESD 51-7)
58.7
°C/W
Junction-to-case (top) thermal resistance
26.1
°C/W
RθJB
Junction-to-board thermal resistance
19.2
°C/W
ΨJT
Junction-to-top characterization parameter
1.4
°C/W
ΨJB
Junction-to-board characterization parameter
19
°C/W
RθJC(bot)
Junction-to-case (bottom) thermal resistance
-
°C/W
(1)
(2)
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
The value of RθJA given in this table is only valid for comparison with other packages and cannot be used for design purposes.
These values were calculated in accordance with JESD 51-7, and simulated on a 4-layer JEDEC board. They do not represent the
performance obtained in an actual application.
7.5 Electrical Characteristics
Limits apply over the recommended operating junction temperature range of -40°C to +150°C, unless otherwise stated.
Minimum and Maximum limits are specified through test, design or statistical correlation. Typical values represent the most
likely parametric norm at TJ = 25°C, and are provided for reference purposes only. Unless otherwise stated the following
conditions apply: VIN = 13.5 V. VIN1 shorted to VIN2 = VIN. VOUT is converter output voltage.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNI
T
SUPPLY VOLTAGE AND CURRENT
Needed to start up
VIN_OPERATE
Input operating voltage(2)
VIN_OPERATE_H
Hysteresis(2)
IQ_VIN
Operating quiescent current (not
switching)(3)
VFB = +5%, VBIAS = 5 V
ISD
Shutdown quiescent current;
measured at VIN pin
EN = 0 V, TJ = 25℃
Once operating
3.95
V
3.0
1
V
9
18
µA
0.6
6
µA
ENABLE
VEN
Enable input threshold voltage rising
VEN-ACC
Enable input threshold voltage rising deviation from typical
-5
VEN-HYST
Enable threshold hysteresis as
percentage of VEN (TYP)
24
VEN-WAKE
Enable wake-up threshold
IEN
Enable pin input current
1.263
28
0.4
V
5
%
32
%
V
VIN = EN = 13.5 V
2.3
VBIAS > 3.4 V, CCM Operation(2)
3.3
VBIAS = 3.1 V, Non-switching
3.1
nA
LDO - VCC
6
VCC
Internal VCC voltage
VCC_UVLO
Internal VCC input under voltage
lock-out
VCC rising under voltage threshold
3.6
V
VCC_UVLO_HYST
Internal VCC input under voltage
lock-out
Hysteresis below VCC_UVLO
1.1
V
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Limits apply over the recommended operating junction temperature range of -40°C to +150°C, unless otherwise stated.
Minimum and Maximum limits are specified through test, design or statistical correlation. Typical values represent the most
likely parametric norm at TJ = 25°C, and are provided for reference purposes only. Unless otherwise stated the following
conditions apply: VIN = 13.5 V. VIN1 shorted to VIN2 = VIN. VOUT is converter output voltage.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNI
T
FEEDBACK
VFB_acc
Initial reference voltage accuracy
VIN = 3.3 V to 36 V, FPWM Mode
-1
VOUT_acc
Reference voltage accuracy for
Fixed 3.3-V VOUT trim option
VIN = 13.5 V, FPWM Mode
3.2587
VOUT_acc
Reference voltage accuracy for
Fixed 5-V VOUT trim option
VIN = 13.5 V, FPWM Mode
4.9375
RFB
Resistance from FB to AGND
IFB
Input current from FB to AGND
5-V Option
1
%
3.3
3.3413
V
5
5.0625
V
1.85
3.3-V Option
2.1
Adjustable versions only, FB = 1 V
10
MΩ
nA
OSCILLATOR
fADJ
Minimum adjustable frequency by
SYNC
0.18
0.2
0.22 MHz
Adjustable frequency by SYNC
0.36
0.4
0.44 MHz
Maximum adjustable frequency
by SYNC
1.98
2.2
2.42 MHz
1.9
2.1
2.3 MHz
VIN = 13.5 V, Center frequency with
or without spread spectrum, PWM
operation
fSW
Switching frequency
fS SS
Frequency span of spread spectrum
operation - largest deviation from
Spread spectrum active
center frequency
fPSS
Spread spectrum pattern
frequency(2)
Spread spectrum active, fSW = 2.1
MHz
IMODE/SYNC
MODE/SYNC pin leakage current
after startup
VIN = 13.5 V, VSYNC/MODE = 3.3 V
1
VIN = 13.5 V, VSYNC/MODE = 5.5 V
1
VMODE_L
MODE/SYNC input voltage low
VMODE_H
MODE/SYNC input voltage high
VSYNCD_HYST
MODE/SYNC input voltage
hysteresis
VMODE_H2
Spread spectrum on if MODE/SYNC
voltage is below this voltage and
Level dependent operation
above VMODE_H
VMODE_H3
Spread spectrum off if MODE/SYNC
Level dependent operation
is above this voltage
RMODE_H
MODE/SYNC attached resistance
indicating Spread Spectrum off
Level dependent operation
RMODE_L
MODE/SYNC attached resistance
indicating Spread Spectrum on
Level dependent operation
RDS(ON)_HS
Power switch on-resistance
High side MOSFET RDS(ON)
41
82 mΩ
RDS(ON)_LS
Power switch on-resistance
Low side MOSFET RDS(ON)
21
45 mΩ
VBOOT_UVLO
Voltage on CBOOT pin compared
to SW which will turn off high-side
switch
2
%
1.5
Hz
MODE/SYNC PIN
nA
0.4
V
1.6
V
0.155
1
V
2.5
V
4.9
30
V
kΩ
6
kΩ
MOSFETS
2.1
V
CURRENT LIMITS
IL-HS
High side switch current limit(1)
IL-LS
Low side switch current limit
Duty cycle approaches 0%
6
7
8.1
A
3.7
4.8
5.4
A
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Limits apply over the recommended operating junction temperature range of -40°C to +150°C, unless otherwise stated.
Minimum and Maximum limits are specified through test, design or statistical correlation. Typical values represent the most
likely parametric norm at TJ = 25°C, and are provided for reference purposes only. Unless otherwise stated the following
conditions apply: VIN = 13.5 V. VIN1 shorted to VIN2 = VIN. VOUT is converter output voltage.
PARAMETER
TEST CONDITIONS
IL-ZC
Zero-cross current
limit. Positive current direction is
out of SW pin
Auto Mode, static measurement
IL-NEG
Negative current limit FPWM and
SYNC Modes. Positive current
direction is out of SW pin.
IPK_MIN_0
MIN
TYP
MAX
UNI
T
0.25
A
FPWM operation
-2
A
Minimum peak command in Auto
Mode / device current rating
Pulse duration < 100 ns
25
%
IPK_MIN_100
Minimum peak command in Auto
Mode / device current rating
Pulse duration > 1 µs
12.5
%
VHICCUP
Ratio of FB voltage to in-regulation
FB voltage
Not during soft start
40
%
PGDOV
PGOOD upper threshold - rising
% of VOUT setting
105
107
110
%
PGDU V
PGOOD lower threshold - falling
% of VOUT setting
92
94
96.5
%
PGDHYST
PGOOD upper threshold (rising &
falling)
% of VOUT setting
VIN(PGD_VALID)
Input voltage for proper
PGOOD function
POWER GOOD
VPGD(LOW)
1.3
%
1.0
Low level PGOOD function output
voltage
RPGD
RDS(ON) of PGOOD output
IOV
Pull down current at the SW node
under over voltage condition
V
46 µA pullup to PGOOD pin, VIN =
1.0 V, EN = 0 V
0.4
1 mA pullup to PGOOD pin, VIN =
13.5 V, EN = 0 V
0.4
2 mA pullup to PGOOD pin, VIN =
13.5 V, EN = 3.3 V
0.4
V
1 mA pullup to PGOOD pin, EN = 0
V
17
40
Ω
1 mA pullup to PGOOD, EN = 3.3 V
40
90
Ω
0.5
mA
THERMAL SHUTDOWN
TSD_R
TSD_HYST
(1)
(2)
(3)
8
Thermal shutdown rising threshold(2)
Thermal shutdown
hysteresis(2)
158
168
180
10
℃
℃
High side current limit is function of duty factor. High side current limit is highest at small duty factor and less at higher duty factors.
Parameter specified by design, statistical analysis and production testing of correlated parameters.
IQ_VIN = IQ + IBIAS × (VOUT / VIN)
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7.6 Timing Characteristics
Limits apply over the recommended operating junction temperature range of -40°C to +150°C, unless otherwise stated.
Minimum and Maximum limits are specified through test, design or statistical correlation. Typical values represent the most
likely parametric norm at TJ = 25°C, and are provided for reference purposes only. Unless otherwise stated the following
conditions apply: VIN = 13.5 V.
Parameter
Test Condition
MIN
TYP
MAX
55
70
UNI
T
SWITCH NODE
VIN = 20 V, IOUT = 2 A, RBOOT short
to CBOOT
tON_MIN
Minimum HS switch on time
tON_MAX
Maximum HS switch on time
tOFF_MIN
Minimum LS switch on time
VIN = 4.0 V, IOUT = 1 A, RBOOT
short to CBOOT
tSS
Time from first SW pulse to Vref at
90%, of set point.
VIN ≥ 4.2 V
tSS2
Time from first SW pulse to release
of FPWM lockout if output not in
regulation
VIN ≥ 4.2 V
tW
Short circuit wait time ("Hiccup" time)
ns
9
μs
65
85
ns
2
3
4
ms
4.5
6.5
8.5
ms
40
ms
0.7
ms
ENABLE
tEN
Turn-on delay(1)
CVCC = 1 µF, time from EN high to
first SW pulse if output starts at 0 V
tB
Blanking of EN after rising or falling
edges
Low level is 0.6 V.
4
9
µs
SYNC
tPULSE_H
High duration needed to be
recognized as a pulse
100
ns
tPULSE_L
Low duration needed to be
recognized as a pulse
100
ns
tMODE
Time at one level needed to indicate
FPWM or Auto Mode
16.5
µs
tSYNC
High or low signal duration in a valid
synchronization signal
CLOCK
Time needed for clock to lock to a
valid synchronization signal in sync
cycles(1)
tMEAS
SYNC/MODE pin duration of
resistance test upon entering Auto
Mode
8
2048
level dependent SYNC/MODE pin
operation
µs
cycle
25
µs
POWER GOOD
tPGDFLT(rise)
Delay time to PGOOD high signal
tPGDFLT(fall)
Glitch filter time constant for
PGOOD function
(1)
1.5
2
2.5
ms
24
µs
Parameter specified using design, statistical analysis and production testing of correlated parameters; not tested in production.
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7.7 Systems Characteristics
The following values are specified by design provided that the component values in the typical application circuit are
used. Limits apply over the junction temperature range of -40°C to +150°C, unless otherwise noted. Minimum and Maximum
limits are derived using test, design or statistical correlation. Typical values represent the most likely parametric norm at TJ
= 25°C, and are provided for reference purposes only. Unless otherwise stated the following conditions apply: VIN = 13.5
V. VIN1 shorted to VIN2 = VIN. VOUT is output setting. These parameters are not tested in production.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNI
T
EFFICIENCY
ƞ5V_2p1MHz
ƞ5V_400kHz
Typical 2.1 MHz efficiency
Typical 400 kHz efficiency
VOUT = 5 V, IOUT = 3.5 A, RBOOT = 0
Ω
93
VOUT = 5 V, IOUT = 100 µA, RBOOT = 0
Ω
73
VOUT = 5 V, IOUT = 3.5 A, RBOOT = 0
Ω
95
VOUT = 5 V, IOUT = 100 µA, RBOOT = 0
Ω
76
%
%
RANGE OF OPERATION
VVIN_MIN1
VIN for full functionality at reduced
load, after start-up.
VOUT set to 3.3 V
3.0
V
VVIN_MIN2
VIN for full functionality at 100% of
maximum rated load, after start-up.
VOUT set to 3.3 V
3.95
V
IQ-VIN
Operating quiescent
VOUT = 3.3 V, IOUT = 0 A, Auto mode,
RFBT=1 MΩ
current(1)
7
µA
VOUT = 5 V, IOUT = 0 A, Auto mode,
RFBT=1 MΩ
VOUT5
Output voltage for 5V factory option
VOUT3
Output voltage for 3.3V factory
option
DMAX
Maximum switch duty cycle
10
VIN = 5.8 V to 36 V, IOUT = 3.5A
4.9
5
5.1
V
Auto mode, VIN = 5.5V to 36 V,
IOUT = 100 µA to 100 mA
4.9
5.05
5.125
V
VIN = 3.9 V to 36 V, IOUT = 3.5 A
3.24
3.3
3.35
V
VIN= 3.9 V to 36 V, IOUT = 100 µA to
100 mA
3.24
3.33
3.38
V
fSW =1.85 MHz
While in frequency fold back
87
98
%
%
RBOOT
tRISE
(1)
10
SW node rise time
RBOOT = 0 Ω, IOUT = 2 A (10% to
80%)
RBOOT = 100 Ω, IOUT = 2 A (10% to
80%)
2.15
ns
2.7
ns
See detailed description for the meaning of this specification and how it can be calculated.
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7.8 Typical Characteristics
Unless otherwise specified, VIN = 13.5 V and fSW = kHz.
16
4000
3500
Shutdown Current (nA)
Quiescent Current (µA)
14
12
10
8
6
4
-50
3000
2500
2000
1500
1000
0
-25
0
25
50
75
Temperature (°C)
100
125
0
150
5
10
SNVS
15
20
25
Input Voltage (V)
30
35
40
SNVS
VEN = 0 V
VBIAS = 5 V
Figure 7-2. Shutdown Supply Current
Figure 7-1. Non-Switching Input Supply Current
1.01
9
1.006
8
7
1.002
Current (A)
Voltage (V)
-40C
25C
150C
500
0.998
6
5
0.994
4
0.99
-50
-25
0
25
50
75
Temperature (°C)
100
125
snvs
0
25
50
75
Temperature (°C)
100
125
150
SNVS
70
FREQ = 200 kHz
FREQ = 400 kHz
FREQ = 2.2 MHz
60
RDS-ON (m-Ohm)
Frequency (kHz)
-25
Figure 7-4. LM62435-Q1 High-side and Low-side
Current Limits
Figure 7-3. Feedback Voltage
3500
3250
3000
2750
2500
2250
2000
1750
1500
1250
1000
750
500
250
0
-50
3
-50
150
HS
LS
50
40
30
20
-25
0
25
50
75
Temperature (°C)
100
125
150
10
-50
HS Switch
LS Switch
-25
SNVS
Figure 7-5. Switching Frequency Set by SYNC
0
25
50
75
Temperature (°C)
100
125
150
SNVS
Figure 7-6. High-side and Low-side Switches
RDS_ON
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1.4
1.3
1.2
1.1
1
0.9
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0
-50
115
110
VEN Rising
VEN Falling
VEN_WAKE Rising
VEN_WAKE Falling
-25
0
25
50
75
Temperature (°C)
100
125
105
100
95
90
OV Tripping
OV Recovery
UV Recovery
UV Tripping
85
150
80
-50
-25
snvs
Figure 7-7. Enable Thresholds
12
PGOOD Threshold (%)
Enable Threshold (V)
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0
25
50
75
Temperature (°C)
100
125
150
SNVS
Figure 7-8. PGOOD Thresholds
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8 Detailed Description
8.1 Overview
The LM62435-Q1 is a wide input, synchronous peak-current mode buck regulator designed for a wide variety of
automotive applications. The regulator can operate over a wide range of switching frequencies including sub-AM
band at 400 kHz and above the AM band at 2.1 MHz. This device operates over a wide range of conversion
ratios. If minimum on-time or minimum off-time does not support the desired conversion ratio, the frequency is
reduced automatically, allowing output voltage regulation to be maintained during input voltage transients with a
high operating-frequency setting.
The LM62435-Q1 has been designed for low EMI and is optimized for both above and below AM band operation:
•
•
•
•
•
Meets CISPR25 class 5 standard
Hotrod™ package minimizes switch node ringing
Parallel input path minimizes parasitic inductance
Spread spectrum reduces peak emissions
Adjustable SW node rise time
These features together can eliminate shielding and other expensive EMI mitigation measures.
This device is designed to minimize end-product cost and size while operating in demanding automotive
environments. Operation at 2.1 MHz allows for the use of small passive components. State-of-the-art current
limit function allows the use of the inductors that are optimized for 3.5-A regulators. In addition, this device has
low unloaded current consumption, which is desirable for off-battery, always on applications. The low shutdown
current and high maximum operating voltage also allow for the elimination of an external load switch and input
transient protection. To further reduce system cost, an advanced PGOOD output is provided, which can often
eliminate the use of an external reset or supervisory device.
The LM62435-Q1 devices are AEC-Q100-qualified and have electrical characteristics ensured up to a maximum
junction temperature of 150°C.
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8.2 Functional Block Diagram
VCC
MODE
/SYNC
MODE/
SYNC
Detect
Clock
Sync
VCC
Oscillator
BIAS
VCC UVLO
Slope
compensation
LDO
Over
Temperature
detect
FPWM/Auto
Frequency Foldback
RBOOT
System enable
Enable
EN
VIN
OTP
CBOOT
HS Current
sense
Error
amplifier
±
Comp Node
Output
low
System enable
FB
+
+
±
VIN
OTP
Hiccup active
Soft start
circuit and
bandgap
VCC UVLO
AGND
VIN2
Clock
High and
low limiting
circuit
+
VIN1
+
HS
±
Current
Limit
SW
Drivers and
logic
LS
Current
Limit
±
+
Voltage Reference
±
FPWM/Auto
PGOOD
PGOOD
Logic with
filter and
release delay
LS
Current
Min
PGND1
+
PGND2
Vout UV/OV
LS Current
sense
System enable
14
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8.3 Feature Description
8.3.1 EN Uses for Enable and VIN UVLO
Start-up and shutdown are controlled by the EN input and VIN UVLO. For the device to remain in shutdown
mode, apply a voltage below VEN_WAKE (0.4 V) to the EN pin. In shutdown mode, the quiescent current drops to
0.6 µA (typical). At a voltage above VEN_WAKE and below VEN, VCC is active and the SW node is inactive. Once
the EN voltage is above VEN, the chip begins to switch normally, provided the input voltage is above 3 V.
The EN pin cannot be left floating. The simplest way to enable the operation is to connect the EN pin to VIN,
allowing self-start-up of the LM62435-Q1 when VIN drives the internal VCC above its UVLO level. However,
many applications benefit from the employment of an enable divider network as shown in Figure 8-1, which
establishes a precision input undervoltage lockout (UVLO). This can be used for sequencing, preventing retriggering of the device when used with long input cables, or reducing the occurrence of deep discharge of
a battery power source. Note that the precision enable threshold, VEN, has a 5% tolerance. Hysteresis must
be enough to prevent re-triggering. External logic output of another IC can also be used to drive the EN pin,
allowing system power sequencing.
VIN
RENT
EN
RENB
AGND
Figure 8-1. VIN UVLO Using the EN pin
Resistor values can be calculated using Equation 1. See Section 9.2.2.11 for additional information.
RENB = RENT Â
VEN
VON Å 9EN
(1)
where
•
VON is the desired typical start-up input voltage for the circuit being designed
8.3.2 MODE/SYNC Pin Operation
The LM62435-Q1 features selectable operating modes through the MODE/SYNC input pin. The LM62435-Q1
can operate in one of three selectable modes:
• Auto Mode: Pulse frequency modulation (PFM) operation is enabled during light load and diode emulation
prevents reverse current through the inductor. See Section 8.4.3.2 for more details.
• FPWM Mode: In FPWM mode, diode emulation is disabled, allowing current to flow backwards through the
inductor. This allows operation at full frequency even without load current. See Section 8.4.3.3 for more
details.
• SYNC Mode: The LM62435-Q1 clock locks to an external signal applied to the MODE/SYNC pin. As long
as output voltage can be regulated at full frequency and is not limited by minimum off-time or minimum
on-time, clock frequency is matched to the frequency of the signal applied to the MODE/SYNC pin. While the
LM62435-Q1 is in SYNC mode, it operates as though in FPWM mode: diode emulation is disabled allowing
the frequency applied to the MODE/SYNC pin to be matched without a load.
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In addition, the MODE/SYNC pin can be used to activate or deactivate the spread spectrum feature of the
LM624-Q1. The MODE/SYNC pin can be configured in two ways: level dependent MODE/SYNC control (see
Section 8.3.2.1) or pulse dependent MODE/SYNC pin control (see Section 8.3.2.2).
8.3.2.1 Level-Dependent MODE/SYNC Pin Control
If only a single mode is used, the part can be configured using level-dependent control. Note that the LMQ6235Q1 cannot be synchronized to an external clock signal in level-dependent mode. Table 8-1 shows a summary of
level-dependent mode selection settings. The level-dependent mode selection setting registers after tMODE. The
level-dependent mode summary is also depicted in Figure 8-2.
Table 8-1. Level-Dependent Mode Selection Settings
MODE/SYNC INPUT
MODE
GND
Auto Mode with Spread Spectrum
VCC OR > VMODE_H AND < VMODE_H2
FPWM Mode with Spread Spectrum
VIN OR > VMODE_H3
FPWM Mode without Spread Spectrum
Above VMODE_H3, operational mode is
FPWM with no spread spectrum
VMODE_H3
Above VMODE_H, FPWM
Mode operation
VMODE_H2
Between VMODE_H and VMODE_H2,
operational mode is FPWM with
spread spectrum
VMODE_H
VMODE_L/VMODE_H controlled transitions
have VSYNCD_HYST hysteresis
Below VMODE_L, Auto
Mode operation
VMODE_L
GND
Figure 8-2. Level-Dependent Mode Selection Settings
Note that during dropout operation, the input voltage is close to VCC. Since this condition is typically seen while
operating in dropout, frequency is typically folded back and spread spectrum is deactivated. When VIN increases
and the device is no longer in frequency foldback, spread spectrum is reactivated. When the input voltage is
between 3 V to 3.7 V and the LMQ6235-Q1 is not in dropout operation, the spread spectrum operation is not
guaranteed.
One purpose of level-dependent MODE/SYNC pin control is to dynamically change between FPWM and Auto
Mode. To ensure the resistance from MODE/SYNC to ground is < RSYNC_L, it is recommended to use 6 kΩ to
ground. The MODE/SYNC pin can then be toggled between FPWM and Auto Mode as shown in Table 8-1.
If Auto Mode without spread spectrum operation is desired, tie the MODE/SYNC pin to ground through a 100-kΩ
resistor. Auto Mode without spread spectrum is a fixed option, and the mode cannot be changed dynamically.
8.3.2.2 Pulse-Dependent MODE/SYNC Pin Control
Most systems that require more than a single mode of operation from the LM62345-Q1 are controlled by digital
circuitry such as a microprocessor. These systems can generate dynamic signals easily but have difficulty
generating multi-level signals. Pulse-Dependent MODE/SYNC pin control is useful with these systems.
To initiate Pulse-Dependent MODE/SYNC pin control, a valid sync signal must be applied. Upon completion
of the fourth pulse in a valid synchronization pulse train, the SYNC mode pin operates in Pulse-Dependent
MODE/SYNC control mode, shown in Figure 8-3 and Figure 8-4. The only way to return to Level-Dependent
MODE/SYNC control is to restart the LM62345-Q1.
16
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FPWM Mode
< tSYNC
< tSYNC
Pulse 1
Pulse 2
SYNC/MODE enters Pulse
Dependent mode, Spread
spectrum turns on, and part
will synchronize clock if
pulse train continues to
pulse number 2048.
< tSYNC
< tSYNC
Pulse 3
Pulse 4
VMODE_H
VMODE_L
> tPULSE_L
> tPULSE_H
> tPULSE_L
> tPULSE_L
> tPULSE_H
> tPULSE_H
> tPULSE_L
< tSYNC
< tSYNC
< tSYNC
> tPULSE_L
> tPULSE_H
< tSYNC
Figure 8-3. Transition from FPWM Mode to Pulse-Dependent Control
< tSYNC
SYNC/MODE enters Pulse
Dependent mode, Spread
spectrum turns on, and part
will synchronize clock if
pulse train continues to
pulse number 2048.
< tSYNC
< tSYNC
Pulse 2
Pulse 1
Pulse 4
Pulse 3
VMODE_H
VMODE_L
Auto Mode
> tPULSE_H
> tPULSE_H
> tPULSE_L
< tSYNC
> tPULSE_L
> tPULSE_H
> tPULSE_L
< tSYNC
< tSYNC
> tPULSE_H
> tPULSE_L
< tSYNC
Figure 8-4. Transition from Auto Mode to Pulse-Dependent Control
Once Pulse Dependent MODE/SYNC control has been initiated, Table 8-2 shows a summary of the pulse
dependent mode selection settings.
Table 8-2. Pulse-Dependent Mode Selection Settings
MODE/SYNC INPUT
MODE
> VMODE_H
FPWM with Spread Spectrum
< VMODE_L
Auto Mode with Spread Spectrum
Synchronization Clock
SYNC Mode without Spread Spectrum
> VMODE_H AND Double Pulse (Figure 8-6)
FPWM without Spread Spectrum
< VMODE_L AND Double Pulse (Figure 8-7)
Auto Mode without Spread Spectrum
Figure 8-5 shows the transition between AUTO Mode and FPWM Mode while in Pulse-Dependent MODE/SYNC
control. The LMQ6240-Q1 transitions to a new mode of operation after the time, tMODE.
Transition to new mode of operation
starts, spread spectrum turns on
> tMODE
FPWM Mode
VMODE_H
VMODE_L
Auto Mode
Figure 8-5. Transition from Auto Mode and FPWM Mode
Two positive going pulses can be used to turn off spread spectrum in Auto and FPWM modes. The two positive
pulses must be consistent with the characteristics of a valid sync signal. The following four diagrams, Figure 8-6
through Figure 8-9, show the only waveforms that result in spread spectrum being turned off. Refer to Section
7.5 for more information about the timing specifications.
tMODE
< tSYNC
MODE
< tSYNC
Pulse 1
FPWM Mode
Spread spectrum turns off
Pulse 2
VMODE_H
VMODE_L
> tPULSE_L
> tPULSE_H
tSYNC
>>tPULSE_L
>>tPULSE_H
tSYNC
> tPULSE_L
Now FPWM Mode, Spread Spectrum off
< tSYNC
SYNC
< tMODE
< tSYNC
Figure 8-6. Spread Spectrum Disabled in FPWM Mode
< tSYNC
tMODE
Pulse 2
Pulse 1
Spread spectrum turns off
VMODE_H
VMODE_L
Auto Mode
> tPULSE_H
> tPULSE_L
> tPULSE_H
Now Auto Mode, Spread Spectrum off
tPULSE_H
> tPULSE_L
>>tPULSE_L
tSYNC
< tMODE
SYNC
Now Auto Mode, Spread Spectrum off
> tPULSE_H
< tSYNC
Figure 8-8. Spread Spectrum Disabled in Transition from FPWM Mode to Auto Mode
< tSYNC
< tSYNC
tMODE
Spread spectrum turns off,
now in FPWM mode
Pulse 2
Pulse 1
VMODE_H
VMODE_L
> tPULSE_L
> tPULSE_H
Auto Mode
< tSYNC
> tPULSE_H
Now FPWM Mode, Spread Spectrum off
> tPULSE_L
< tSYNC
Figure 8-9. Spread Spectrum Disabled in Transition from Auto Mode to FPWM Mode
To enter the SYNC Mode, the valid synchronization signal must be present for 2048 cycles.
If MODE/SYNC voltage becomes constant longer than tMODE, the LM62345-Q1 enters either Auto mode or
FPWM mode. At this time, spread spectrum is turned on and MODE/SYNC operates in Pulse-Dependent mode.
tMODE
Now Auto Mode, Spread Spectrum on
VMODE_H
VMODE_L
> tPULSE_H
> tPULSE_L
< tSYNC
Figure 8-10. Transition from SYNC Mode to Auto Mode
tMODE
< tSYNC
Now FPWM Mode, Spread Spectrum on
VMODE_H
VMODE_L
> tPULSE_H
> tPULSE_L
> tPULSE_L
< tSYNC
Figure 8-11. Transition from SYNC Mode to FPWM Mode
8.3.2.3 Clock Locking
Once a valid synchronization signal is detected, a clock locking procedure is initiated. The LM62435-Q1 receives
this signal over the MODE/SYNC pin. After approximately 2048 pulses, the clock frequency completes a smooth
transition to the frequency of the synchronization signal without output variation. Note that while the frequency is
adjusted suddenly, phase is maintained so the clock cycle that lies between operation at the default frequency
and at the synchronization frequency is of intermediate length. This eliminates very long or very short pulses.
Once frequency is adjusted, phase is adjusted over a few tens of cycles so that rising synchronization edges
correspond to rising SW node pulses.
Pulse 1
Pulse 2
Pulse 3
Pulse
~2048
Pulse 4
Pulse
~2049
Pulse
~2050
Pulse
~2051
VSYNCDH
VSYNCDL
Synchronization
signal
Spread Spectrum is on between pulse 1 and
approximately pulse 2048, there is no change to
operating frequency
SW Node
On approximately pulse 2048, spread
spectrum turns off
Also clock frequency matches the
synchronization signal and phase
locking begins
Phase lock achieved, Rising edges
align to within approximately 45 ns,
no spread spectrum
VIN
GND
Pulses four and synchronization signal is detected. After the pulse, approximately 2048 ready to synchronize and frequency is adjusted
using a glitch free technique. Later, phase is locked.
Figure 8-12. Synchronization Process
18
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Also note that the LM62435-Q1 turns on spread spectrum after the first edge in the synchronization pulse. See
the MODE/SYNC pin description in the Section 6. Upon adjustment of frequency on the approximate 2048th
pulse, spread spectrum is turned off. Finally, if the part runs at reduced frequency due to low or high input
voltage or during current limit, frequency lock does not occur until the condition causing low frequency operation
has been removed.
8.3.3 PGOOD Output Operation
The PGOOD function is implemented to replace a discrete reset device, reducing BOM count and cost. The
PGOOD pin voltage goes low when the feedback voltage is outside of the specified PGOOD thresholds (see
Figure 7-8). This can occur in current limit and thermal shutdown, as well as while disabled and during normal
start-up. A glitch filter prevents false flag operation for short excursions of the output voltage, such as during line
and load transients. Output voltage excursions that are shorter than tPGDFLT_FALL do not trip the power-good flag.
Power-good operation can be best understood by referring to Figure 8-13.
The power-good output consists of an open-drain NMOS, requiring an external pullup resistor to a suitable logic
supply or VOUT. When EN is pulled low, the flag output is also forced low. With EN low, power good remains valid
as long as the input voltage is ≥ 1 V (typical).
Input
Voltage
Output
Voltage
Input Voltage
tPGDFLT(fall)
tPGDFLT(rise)
tPGDFLT(rise)
VPGD_HYST
tPGDFLT(fall)
tPGDFLT(fall)
tPGDFLT(fall)
VPGD_UV (falling)
VIN_OPERATE (rising)
VIN_OPERATE (falling)
VIN(PGD_VALID)
GND
< 18 V
PGOOD
PGOOD may
not be valid if
input is below
VIN(PGD_VALID)
Small glitches
do not cause
PGOOD to
signal a fault
Small glitches do not
reset tPGDFLT(rise) timer
Startup
delay
PGOOD may not
be valid if input is
below VIN(PGD_VALID)
Figure 8-13. PGOOD Timing Diagram (Excludes OV Events)
Table 8-3. Conditions That Cause PGOOD to Signal a Fault (Pull Low)
(1)
FAULT CONDITION INITIATED
FAULT CONDITION ENDS (AFTER WHICH tPGDFLT(rise) MUST PASS
BEFORE PGOOD OUTPUT IS RELEASED)(1)
VOUT < VOUT-target × PGDUV AND t > tPGDFLT(fall)
Output voltage in regulation:
VOUT-target × (PGDUV + PGDHYST) < VOUT < VOUT-target × (PGDOV PGDHYST) (See Figure 7-8)
VOUT > VOUT-target × PGDOV AND t > tPGDFLT(fall)
Output voltage in regulation
TJ > TSD_R
TJ < TSD_F AND output voltage in regulation
EN < VEN Falling
EN > VEN Rising AND output voltage in regulation
VCC < VCC_UVLO - VCC_UVLO_HYST
VCC > VCC_UVLO AND output voltage in regulation
As an additional operational check, PGOOD remains low during soft start, defined as until the lesser of either full output voltage
reached or tSS2 has passed since initiation.
8.3.4 Internal LDO, VCC UVLO, and BIAS Input
The VCC pin is the output of the internal LDO used to supply the control circuits of the LM62435-Q1. The
nominal output is 3 V to 3.3 V. The BIAS pin is the input to the internal LDO. This input can be connected to
VOUT to provide the lowest possible input supply current. If the BIAS voltage is less than 3.1 V, VIN1 and VIN2
directly powers the internal LDO.
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To prevent unsafe operation, VCC has a UVLO that prevents switching if the internal voltage is too low. See
VCC_UVLO and VCC_UVLO_HYST in Section 7.5. Note that these UVLO values and the dropout of the LDO are used
to derive minimum VIN_OPERATE and VIN_OPERATE_H values.
8.3.5 Bootstrap Voltage and VCBOOT-UVLO (CBOOT Pin)
The driver of the High-Side (HS) switch requires bias higher than VIN. The capacitor, CBOOT, connected
between CBOOT and SW, works as a charge pump to boost voltage on the CBOOT pin to SW + VCC. A boot
diode is integrated on the LM62435-Q1 die to minimize external component count. It is recommended that a
100-nF capacitor rated for 10 V or higher is used. The VBOOT_UVLO threshold (2.1 V typ.) is designed to maintain
proper HS switch operation. If the CBOOT capacitor voltage drops below VBOOT_UVLO, then the device initiates a
charging sequence, turning on the low-side switch before attempting to turn on the HS switch.
8.3.6 Adjustable SW Node Slew Rate
To allow optimization of EMI with respect to efficiency, the LM62435-Q1 is designed to allow a resistor to select
the strength of the driver of the high-side FET during turn on. See Figure 8-14. The current drawn through the
RBOOT pin (the dotted loop) is magnified and drawn through from CBOOT (the dashed line). This current is
used to turn on the high-side power MOSEFT.
VIN
VCC
CBOOT
HS
Driver
HS FET
RBOOT
SW
LS FET
Figure 8-14. Simplified Circuit Showing How RBOOT Functions
With RBOOT short circuited to CBOOT, rise time is very fast. As a result, SW node harmonics do not "roll off"
until above 150 MHz. A boot resistor of 100 Ω corresponds to approximately 2.7-ns SW node rise, and this
100-Ω boot resistor virtually eliminates SW node overshoot. The slower rise time allows energy in SW node
harmonics to roll off near 100 MHz under most conditions. Rolling off harmonics eliminates the need for shielding
and common mode chokes in many applications. Note that rise time increases with increasing input voltage.
Noise due to stored charge is also greatly reduced with higher RBOOT resistance. Switching with slower slew
rate also decreases the efficiency.
8.3.7 Spread Spectrum
Spread spectrum is pin-controlled. The purpose of spread spectrum is to eliminate peak emissions at specific
frequencies by spreading these emissions across a wider range of frequencies rather than apart with fixed
frequency operation. In most systems containing the LM62435-Q1, low frequency-conducted emissions from the
first few harmonics of the switching frequency can be easily filtered. A more difficult design criterion is reduction
of emissions at higher harmonics that fall in the FM band. These harmonics often couple to the environment
through electric fields around the switch node and inductor. The LM62435-Q1 uses a ±2% spread of frequencies
which can spread energy smoothly across the FM and TV bands but is small enough to limit subharmonic
emissions below the device switching frequency. Peak emissions at the switching frequency of the part are only
reduced slightly, by less than 1 dB, while peaks in the FM band are typically reduced by more than 6 dB.
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The LM62435-Q1 uses a cycle-to-cycle frequency hopping method based on a linear feedback shift register
(LFSR). This intelligent pseudo-random generator limits cycle-to-cycle frequency changes to limit output ripple.
The pseudo-random pattern repeats at less than 1.5 Hz, which is below the audio band.
The spread spectrum is only available while the clock of the LM62435-Q1 devices are free running at their
natural frequency. Any of the following conditions overrides spread spectrum, turning it off:
•
•
•
•
The clock is slowed during dropout.
The clock is slowed at light load in auto mode. In FPWM mode, spread spectrum is active even if there is no
load.
At a high input voltage/low output voltage ratio when the device operates at minimum on-time, the internal
clock is slowed, disabling spread spectrum. See Section 7.6.
The clock is synchronized with an external clock.
8.3.8 Soft Start and Recovery From Dropout
The LM62435-Q1 uses a reference-based soft start that prevents output voltage overshoots and large inrush
currents during start-up. Soft start is triggered by any of the following conditions:
•
•
•
•
Power is applied to the VIN pin of the IC, releasing UVLO.
EN is used to turn on the device.
Recovery from a hiccup waiting period
Recovery from shutdown due to overtemperature protection
Once soft start is triggered, the IC takes the following actions:
•
•
The reference used by the IC to regulate output voltage is slowly ramped. The net result is that output voltage
takes tSS to reach 90% of its desired value.
Operating mode is set to auto, activating diode emulation. This allows start-up without pulling output low if
there is a voltage already present on output.
These actions together provide start-up with limited inrush currents and also allow the use of larger output
capacitors and higher loading conditions that cause current to border on current limit during start-up without
triggering hiccup. See Soft-Start Operation.
EN and Output Voltages
tEN
V
tSS
If selected, FPWM
is enabled after
regulation but no
later than tSS2
VEN
VOUT Set
Point
VOUT
90% of
VOUT Set
Point
0V
tSS2
Time
t
Triggering event
tEN
EN and Output Voltages
Triggering event
V
tSS
If selected, FPWM
is enabled after
regulation but no
later than tSS2
VEN
VOUT Set
Point
VOUT
90% of
VOUT Set
Point
0V
tSS2
Time
t
Soft start works with both output voltages starting from 0 V on the left curves, or if there is already voltage on the output, as shown on
right. In either case, output voltage must reach within 10% of the desired value tSS after soft start is initiated. During soft start, FPWM
and hiccup are disabled. Both hiccup and FPWM are enabled once output reaches regulation or tSS2, whichever happens first.
Figure 8-15. Soft-Start Operation
Any time the output voltage falls more than a few percent, the output voltage ramps up slowly. This condition is
called recovery from dropout and differs from soft start in three important ways:
•
The reference voltage is set to approximately 1% above what is needed to achieve the existing output
voltage.
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•
•
Hiccup is allowed if output voltage is less than 0.4 times its set point. Note that during dropout regulation
itself, hiccup is inhibited.
FPWM mode is allowed during recovery from dropout. If the output voltage were to suddenly be pulled up by
an external supply, the LM62435-Q1 can pull down on the output.
Despite being called recovery from dropout, this feature is active whenever output voltage drops to a few percent
lower than the set point. This primarily occurs under the following conditions:
•
•
Dropout: When there is insufficient input voltage for the desired output voltage to be generated
Overcurrent: When there is an overcurrent event that is not severe enough to trigger hiccup
V
Input and Output
Voltage
VIN
Slope
the same
as during
soft start
VOUT
VOUT Set
Point
t
Time
Whether output voltage falls due to high load or low input voltage, once the condition that causes output to fall below its set point
is removed, the output climbs at the same speed as during start-up. Even though hiccup does not trigger due to dropout, it can, in
principle, be triggered during recovery if output voltage is below 0.4 times the output set point for more than 128 clock cycles.
Figure 8-16. Recovery From Dropout
8.3.9 Output Voltage Setting
A feedback resistor divider network between the output voltage and the FB pin is used to set output voltage
level. See Figure 8-17.
VOUT
RFBT
FB
RFBB
AGND
Figure 8-17. Setting Output Voltage of Adjustable Versions
Adjustable versions of the LM62435-Q1 use a 1-V reference voltage for the feedback (FB) pin. The FB pin
voltage is regulated by the internal controller to be the same as the reference voltage. The output voltage level
is then set by the ratio of the resistor divider. Equation 3 can be used to determine RFBB for a desired output
voltage and a given RFBT. Usually RFBT is between 10 kΩ and 1 MΩ. 100 kΩ is recommended for RFBT for
improved noise immunity compared to 1 MΩ and reduced current consumption compared to lower resistance
values.
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RFBT
VOUT Å 1
(2)
In addition, a feedforward capacitor, CFF, connected in parallel with RFBT can be required to optimize the
transient response.
8.3.10 Overcurrent and Short Circuit Protection
The LM62435-Q1 is protected from overcurrent conditions with cycle-by-cycle current limiting on both the highside and the low-side MOSFETs.
High-side MOSFET overcurrent protection is implemented by the nature of the peak-current mode control. The
HS switch current is sensed when the HS is turned on after a short blanking time. Every switching cycle,
the HS switch current is compared to either the minimum of a fixed current set point or the output of the
voltage regulation loop minus slope compensation. Because the voltage loop has a maximum value and slope
compensation increases with duty cycle, HS current limit decreases with increased duty cycle when duty cycle is
above 35%.
When the LS switch is turned on, the switch current is also sensed and monitored. Like the high-side device, the
low-side device turns off as commanded by the voltage control loop and low-side current limit. If the LS switch
current is higher than ILS_Limit at the end of a switching cycle, the switching cycle is extended until the LS current
reduces below the limit. The LS switch is turned off once the LS current falls below its limit, and the HS switch is
turned on again as long as at least one clock period has passed since the last time the HS device has turned on.
SW Voltage
VSW
VIN
tON < tON_MAX
0
t
Inductor Current
Typically, tSW > Clock setting
iL
IL-HS
IOUT
IL-LS
0
t
Figure 8-18. Current Limit Waveforms
Since the current waveform assumes values between IL-HS and IL-LS, the maximum output current is very close
to the average of these two values. Hysteretic control is used and current does not increase as output voltage
approaches zero.
The LM62435-Q1 employs hiccup overcurrent protection if there is an extreme overload, and the following
conditions are met for 128 consecutive switching cycles:
•
•
•
Output voltage is below approximately 0.4 times the output voltage set point.
Greater than tSS2 has passed since soft start has started; see Section 8.3.8.
The part is not operating in dropout, which is defined as having minimum off-time controlled duty cycle.
In hiccup mode, the device shuts itself down and attempts to soft start after tW. Hiccup mode helps reduce the
device power dissipation under severe overcurrent conditions and short circuits. See Figure 8-19.
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Once the overload is removed, the device recovers as though in soft start; see Figure 8-20.
VOUT
(5 V/DIV)
VOUT
(5 V/DIV)
VSW
(5 V/DIV)
VSW
(5 V/DIV)
IL
(2 A/DIV)
IL
(2 A/DIV)
Time (10 ms/DIV)
Time (1.6 ms/DIV)
Figure 8-19. Inductor Current Bursts During
Hiccup
Figure 8-20. Short Circuit Recovery
8.3.11 Thermal Shutdown
Thermal shutdown prevents the device from extreme junction temperatures by turning off the internal switches
when the IC junction temperature exceeds 165°C (typical). Thermal shutdown does not trigger below 158°C.
After thermal shutdown occurs, hysteresis prevents the device from switching until the junction temperature
drops to approximately 155°C. When the junction temperature falls below 155°C (typical), the LM62435-Q1
attempts to soft start.
While the LM62435-Q1 is shut down due to high junction temperature, power continues to be provided to VCC.
To prevent overheating due to a short circuit applied to VCC, the LDO that provides power for VCC has reduced
current limit while the part is disabled due to high junction temperature. The VCC current limit is reduced to a few
milliamperes during thermal shutdown.
8.3.12 Input Supply Current
The LM62435-Q1 is designed to have very low input supply current when regulating light loads. This is achieved
by powering much of the internal circuitry from the output. The BIAS pin is the input to the LDO that powers the
majority of the control circuits. By connecting the BIAS input pin to the output of the regulator, a small amount of
current is drawn from the output. This current is reduced at the input by the ratio of VOUT / VIN.
IQ _ VIN
SW
§ 1 ·
§ Output Voltage ·
IEN IQ _ VIN u ¨
¸ Idiv u ¨
¸
© Keff ¹
© Input Voltage u Keff ¹
(3)
where
•
•
•
•
•
IQ_VIN is the current consumed by the operating (switching) buck converter while unloaded.
IQ is the current drawn from the VIN terminal. See IQ in Section 7.5.
IEN is current drawn by the EN terminal. Include this current if EN is connected to VIN. See IEN in Section 7.5.
Note that this current drops to a very low value if connected to a voltage less than 5 V.
Idiv is the current drawn by the feedback voltage divider used to set output voltage.
ηeff is the light-load efficiency of the buck converter with IQ_VIN removed from the input current of the buck
converter. ηeff = 0.8 is a conservative value that can be used under normal operating conditions.
8.4 Device Functional Modes
8.4.1 Shutdown Mode
The EN pin provides electrical ON and OFF control of the device. When the EN pin voltage is below 0.4 V, both
the converter and the internal LDO have no output voltage and the part is in shutdown mode. In shutdown mode,
the quiescent current drops to typically 0.6 µA.
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8.4.2 Standby Mode
The internal LDO has a lower EN threshold than the output of the converter. When the EN pin voltage is above
1.1 V (maximum) and below the precision enable threshold for the output voltage, the internal LDO regulates the
VCC voltage at 3.3 V typical. The precision enable circuitry is ON once VCC is above its UVLO. The internal
power MOSFETs of the SW node remain off unless the voltage on EN pin goes above its precision enable
threshold. The LM62435-Q1 also employs UVLO protection. If the VCC voltage is below its UVLO level, the
output of the converter is turned off.
8.4.3 Active Mode
The LM61435-Q1 is in active mode whenever the EN pin is above VEN, VIN is high enough to satisfy
VIN_OPERATE, and no other fault conditions are present. The simplest way to enable the operation is to connect
the EN pin to VIN, which allows self start-up when the applied input voltage exceeds the minimum VIN_OPERATE.
In active mode, depending on the load current, input voltage, and output voltage, the LM62435-Q1 is in one of
five modes:
•
•
•
•
•
Continuous conduction mode (CCM) with fixed switching frequency when load current is above half of the
inductor current ripple.
Auto Mode - Light Load Operation: PFM when switching frequency is decreased at very light load.
FPWM Mode - Light Load Operation: Discontinuous conduction mode (DCM) when the load current is lower
than half of the inductor current ripple.
Minimum on-time: At high input voltage and low output voltages, the switching frequency is reduced to
maintain regulation.
Dropout mode: When switching frequency is reduced to minimize voltage dropout.
8.4.3.1 CCM Mode
The following operating description of the LM62435-Q1 refers to Section 8.2 and to the waveforms in Figure
8-21. In CCM, the LM62435-Q1 supplies a regulated output voltage by turning on the internal high-side (HS) and
low-side (LS) NMOS switches with varying duty cycle (D). During the HS switch on-time, the SW pin voltage,
VSW, swings up to approximately VIN, and the inductor current, iL, increases with a linear slope. The HS switch
is turned off by the control logic. During the HS switch off-time, tOFF, the LS switch is turned on. Inductor current
discharges through the LS switch, which forces the VSW to swing below ground by the voltage drop across the
LS switch. The converter loop adjusts the duty cycle to maintain a constant output voltage. D is defined by the
on-time of the HS switch over the switching period:
D = TON / TSW
(4)
In an ideal buck converter where losses are ignored, D is proportional to the output voltage and inversely
proportional to the input voltage:
D = VOUT / VIN
(5)
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SW Voltage
VSW
D=
VIN
tON
VOUT
§
tSW
VIN
tOFF
tON
0
- IOUTÂ5DSLS
t
tSW
Inductor Current
iL
ILPK
IOUT
Iripple
0
t
Figure 8-21. SW Voltage and Inductor Current Waveforms in Continuous Conduction Mode (CCM)
8.4.3.2 Auto Mode - Light Load Operation
The LM62435-Q1 can have two behaviors while lightly loaded. One behavior, called auto mode operation, allows
for seamless transition between normal current mode operation while heavily loaded and highly efficient light
load operation. The other behavior, called FPWM Mode, maintains full frequency even when unloaded. Which
mode the LM62435-Q1 operates in depends on the configuration of the MODE/SYNC pin. See Table 8-1. When
using the LM62435-Q1, light load behavior is selected using the MODE/SYNC pin. Note that all parts operate in
FPWM mode when synchronizing frequency to an external signal.
In auto mode, light load operation is employed in the LM62435-Q1. Light load operation employs two techniques
to improve efficiency:
•
•
Diode emulation, which allows DCM operation
Frequency reduction
Note that while these two features operate together to create excellent light load behavior, they operate
independently of each other.
8.4.3.2.1 Diode Emulation
Diode emulation prevents reverse current through the inductor which requires a lower frequency needed to
regulate given a fixed peak inductor current. Diode emulation also limits ripple current as frequency is reduced.
With a fixed peak current, as output current is reduced to zero, frequency must be reduced to near zero to
maintain regulation.
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VOUT
tON
<
VIN
tSW
D=
VSW
SW Voltage
VIN
tON
tOFF
tHIGHZ
0
t
tSW
Inductor Current
iL
ILPK
IOUT
0
t
In auto mode, the low-side device is turned off once SW node current is near zero. As a result, once output current is less than half of
what inductor ripple would be in CCM, the part operates in DCM which is equivalent to the statement that diode emulation is active.
Figure 8-22. PFM Operation
The device has a minimum peak inductor current setting while in auto mode.Once current is reduced to a low
value with fixed input voltage, on-time is constant. Regulation is then achieved by adjusting frequency. This
mode of operation is called PFM mode regulation.
8.4.3.2.2 Frequency Reduction
The LM62435-Q1 reduces frequency whenever output voltage is high. This function is enabled whenever Comp,
an internal signal, is low and there is an offset between the regulation set point of FB and the voltage applied
to FB. The net effect is that there is larger output impedance while lightly loaded in auto mode than in normal
operation. Output voltage must be approximately 1% high when the part is completely unloaded.
Output Voltage
VOUT
Current
Limit
1% Above
Set point
VOUT Set
Point
0
Output Current
IOUT
In auto mode, once output current drops below approximately 1/10th the rated current of the part, output resistance increases so that
output voltage is 1% high while the buck is completely unloaded.
Figure 8-23. Steady State Output Voltage versus Output Current in Auto Mode
In PFM operation, a small DC positive offset is required on the output voltage to activate the PFM detector. The
lower the frequency in PFM, the more DC offset is needed on VOUT. If the DC offset on VOUT is not acceptable, a
dummy load at VOUT or FPWM Mode can be used to reduce or eliminate this offset.
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8.4.3.3 FPWM Mode - Light Load Operation
In FPWM Mode, frequency is maintained while lightly loaded. To maintain frequency, a limited reverse current is
allowed to flow through the inductor. Reverse current is limited by reverse current limit circuitry, see Section 7.5
for reverse current limit values.
VSW
D=
SW Voltage
VIN
tON
VOUT
§
tSW
VIN
tOFF
tON
0
t
Inductor Current
tSW
iL
ILPK
IOUT
0
Iripple
t
In FPWM mode, Continuous Conduction (CCM) is possible even if IOUT is less than half of Iripple.
Figure 8-24. FPWM Mode Operation
Transitions between auto mode and FPWM mode can be commanded during operation if you are using the
LM62435-Q1. These transitions are gradual, taking tens of clock cycles, allowing minimal disruption of output
voltage during transitions. If the load is heavy enough to operate in CCM, since operation is identical in FPWM
and Auto mode, no change in behavior is visible until the next time the circuit is lightly loaded.
For all devices, in FPWM mode, frequency reduction is still available if output voltage is high enough to
command minimum on-time even while lightly loaded, allowing good behavior during faults which involve output
being pulled up.
8.4.3.4 Minimum On-time (High Input Voltage) Operation
The LM62435-Q1 continues to regulate output voltage even if the input-to-output voltage ratio requires an
on-time less than the minimum on-time of the chip with a given clock setting. This is accomplished using valley
current control. At all times, the compensation circuit dictates both a maximum peak inductor current and a
maximum valley inductor current. If for any reason, valley current is exceeded, the clock cycle is extended until
valley current falls below that determined by the compensation circuit. If the converter is not operating in current
limit, the maximum valley current is set above the peak inductor current, preventing valley control from being
used unless there is a failure to regulate using peak current only. If the input-to-output voltage ratio is too high,
even though current exceeds the peak value dictated by compensation, the high-side device cannot be turned
off quickly enough to regulate output voltage. As a result, the compensation circuit reduces both peak and valley
current. Once a low enough current is selected by the compensation circuit, valley current matches that being
commanded by the compensation circuit. Under these conditions, the low-side device is kept on and the next
clock cycle is prevented from starting until inductor current drops below the desired valley current. Since on-time
is fixed at its minimum value, this type of operation resembles that of a device using a Constant On-Time (COT)
control scheme; see Valley Current Mode Operation.
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SW Voltage
VSW
D=
VIN
tON
VOUT
§
tSW
VIN
tON = tON_MIN
tOFF
0
- IOUTÂ5DSLS
t
Inductor Current
tSW > Clock setting
iL
IOUT
Iripple
ILVLY
t
0
In valley control mode, minimum inductor current is regulated, not peak inductor current.
Figure 8-25. Valley Current Mode Operation
8.4.3.5 Dropout
Dropout operation is defined as any input-to-output voltage ratio that requires frequency to drop to achieve the
required duty cycle. At a given clock frequency, duty cycle is limited by minimum off-time. Once this limit is
reached, if clock frequency were maintained, output voltage would fall. Instead of allowing the output voltage
to drop, the LM62435-Q1 extends on-time past the end of the clock cycle until needed peak inductor current
is achieved. The clock is allowed to start a new cycle once peak inductor current is achieved or once a
pre-determined maximum on-time, tON_MAX, of approximately 9 µs passes. As a result, once the needed duty
cycle cannot be achieved at the selected clock frequency due to the existence of a minimum off-time, frequency
drops to maintain regulation. If input voltage is low enough so that output voltage cannot be regulated even with
an on-time of tON_MAX, output voltage drops to slightly below the input voltage, VDROP1. For additional information
on recovery from dropout, reference Recovery From Dropout.
Output Voltage
iL
VDROP1
Output
Setting
0
Switching Frequency
VDROP2 if
frequency =
1.85 MHz
Input
Voltage
Output
Voltage
Input Voltage
VIN
iL
Frequency
Setting
~100kHz
0
IOUT
Input Voltage
VIN
Output voltage and frequency versus input voltage: If there is little difference between input voltage and output voltage setting, the IC
reduces frequency to maintain regulation. If input voltage is too low to provide the desired output voltage at approximately 110 kHz,
input voltage tracks output voltage.
Figure 8-26. Frequency and Output Voltage in Dropout
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SW Voltage
VSW
VIN
D=
tON
VOUT
§
tSW
VIN
tOFF = tOFF_MIN
tON < tON_MAX
0
- IOUTÂ5DSLS
t
Inductor Current
tSW > Clock setting
iL
ILPK
IOUT
0
Iripple
t
Switching waveforms while in dropout. Inductor current takes longer than a normal clock to reach the desired peak value. As a result,
frequency drops. This frequency drop is limited by tON_MAX.
Figure 8-27. Dropout Waveforms
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9 Application and Implementation
Note
Information in the following applications sections is not part of the TI component specification,
and TI does not warrant its accuracy or completeness. TI’s customers are responsible for
determining suitability of components for their purposes, as well as validating and testing their design
implementation to confirm system functionality.
9.1 Application Information
The LM62435-Q1 step-down DC-to-DC converter is typically used to convert a higher DC voltage to a lower
DC voltage with a maximum output current of 3.5 A. The following design procedure can be used to select
components for the LM62435-Q1.
9.2 Typical Application
Figure 9-1 shows a typical application circuit for the LM62435-Q1. This device is designed to function with a wide
range of external components and system parameters. However, the internal compensation is optimized for a
certain range of external inductance and output capacitance. As a quick start guide, provides typical component
values for some of the common configurations.
5 V to 36 V input
CIN_HF1
VIN1
VIN2
PGND1
CIN_HF2
CIN-BLK
PGND2
PGOOD
EN
RPG
BIAS
Output
L1
SW
CBT
MODE/SYNC
COUT
RFF
CBOOT
RFBT
VCC
CFF
RBOOT
CVCC
AGND
FB
RFBB
Figure 9-1. Example Application Circuit
9.2.1 Design Requirements
Table 9-1 provides the parameters for the detailed design procedure example:
Table 9-1. Detailed Design Parameters
DESIGN PARAMETER
EXAMPLE VALUE
Input voltage
13.5 V (5 V to 36 V)
Input voltage for constant fSW
8 V to 18 V
Output voltage
5V
Maximum output current
0 A to 3.5 A
Switching frequency
2.1 MHz
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Table 9-2. Typical External Component Values
fSW
(kHz)
VOUT (V)
L1 (µH)
COUT (RATED)
RFBT
(kΩ)
RFBB
(kΩ)
CBOOT
(µF)
RBOOT
(Ω)
2100
3.3
1.5
3 × 22 µF ceramic
100
43.2
0.1
0
400
3.3
8.2
4 × 22 µF ceramic
100
43.2
0.1
0
2100
5
1.5
2 × 22 µF ceramic
100
24.9
0.1
400
5
8.2
3 × 22 µF ceramic
100
24.9
0.1
CVCC
(µF)
CFF (pF)
RFF (kΩ)
1
10
1
1
4.7
1
0
1
22
1
0
1
22
1
9.2.2 Detailed Design Procedure
The following design procedure applies to Figure 9-1 and Table 9-1.
9.2.2.1 Choosing the Switching Frequency
The choice of switching frequency is a compromise between conversion efficiency and overall solution size.
Lower switching frequency implies reduced switching losses and usually results in higher system efficiency.
However, higher switching frequency allows for the use of smaller inductors and output capacitors, hence, a
more compact design.
When choosing operating frequency, the most important consideration is thermal limitations. This constraint
typically dominates frequency selection. See Maximum Ambient Temperature versus Output Current for circuits
running at 400 kHz and Maximum Ambient Temperature versus Output Current for circuits running at 2.1 MHz.
These curves show how much output current can be supported at a given ambient temperature given these
switching frequencies. Note that power dissipation is layout-dependent so while these curves are a good starting
point, thermal resistance in any design will be different from the estimates used to generate Maximum Ambient
Temperature versus Output Current and Maximum Ambient Temperature versus Output Current. The maximum
temperature ratings are based on a 100-mm x 80-mm, 4-layer EVM PCB design, LM61460EVM.
130
135
125
Ambient Temperature (°C)
Ambient Temperature (°C)
125
120
115
110
105
100
95
VIN = 13.5 V
VIN = 16 V
VIN = 24 V
90
115
105
95
85
VIN = 13.5 V
VIN = 16 V
VIN = 24 V
75
85
65
3
3.1
fSW = 400 kHz
3.2
3.3
Output Current (A)
PCB RθJA = 25°C/W
3.4
3.5
2
2.25
snvs
VOUT = 5 V
fSW = 2100 kHz
2.5
2.75
3
Output Current (A)
PCB RθJA = 25°C/W
3.25
3.5
snvs
VOUT = 5 V
Figure 9-2. Maximum Ambient Temperature versus Figure 9-3. Maximum Ambient Temperature versus
Output Current
Output Current
Two other considerations are what maximum and minimum input voltage the part must maintain its frequency
setting. Since the LM62435-Q1 adjusts its frequency under conditions in which regulation would normally be
prevented by minimum on-time or minimum off time, these constraints are only important for input voltages
requiring constant frequency operation.
If foldback is undesirable at high input voltage, then use Equation 6:
fSW G
32
VOUT
VIN(MAX2) Â WON_MIN(MAX)
(6)
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If foldback at low input voltage is a concern, use Equation 7:
fSW ”
VINeff(MIN2) ± VOUT
VINeff(MIN2) Â WOFF_MIN(MAX)
(7)
where:
•
VINeff(MIN2) = VIN(MIN2) ± IOUT(MAX) Â (RDS(ON)_HS(MAX) + DCR(MAX))
•
•
•
DCR(MAX) = maximum DCR of the inductor
tOFF_MIN(MAX) = see Section 7.5
RDS(ON)_HS(MAX) = see Section 7.5
The fourth constraint is the rated frequency range of the IC. See fADJ in Section 7.5. All previously stated
constraints (thermal, VIN(MAX2), VIN(MIN2), and device-specified frequency range) must be considered when
selecting frequency.
Many applications require that the AM band can be avoided. These applications tend to operate at either 400
kHz below the AM band or 2.1 MHz above the AM band. In this example, 400 kHz is chosen.
9.2.2.2 Setting the Output Voltage
The adjustable output voltage device variant of LM62435-Q1 is externally adjustable using a resistor divider
network. The range of recommended output voltage is found in Section 7.3. The divider network is comprised of
RFBT and RFBB, and closes the loop between the output voltage and the converter. The converter regulates the
output voltage by holding the voltage on the FB pin equal to the internal reference voltage, VREF. The resistance
of the divider is a compromise between excessive noise pickup and excessive loading of the output. Smaller
values of resistance reduce noise sensitivity but also reduce the light load efficiency. The recommended value
for RFBT is 100 kΩ with a maximum value of 1 MΩ. If 1 MΩ is selected for RFBT, then a feedforward capacitor
must be used across this resistor to provide adequate loop phase margin (see Section 9.2.2.10). Once RFBT is
selected, Equation 2 is used to select RFBB. VREF is nominally 1 V. For this 5-V example, RFBT = 100 kΩ and
RFBB = 24.9 kΩ are chosen.
For the fixed output voltage versions, FB is connected directly to the output voltage node, preferably, near the
top of the output capacitor. If the feedback point is located further away from the output capacitors (that is,
remote sensing), then a small 100-nF capacitor can be needed at the sensing point.
9.2.2.3 Inductor Selection
The parameters for selecting the inductor are the inductance and saturation current. The inductance is based
on the desired peak-to-peak ripple current and is normally chosen to be in the range of 20% to 40% of
the maximum output current. Experience shows that the best value for inductor ripple current is 30% of the
maximum load current for systems with a fixed input voltage and 25% for systems with a variable input voltage
such as the 12 volt battery in a car. Note that when selecting the ripple current for applications with much smaller
maximum load than the maximum available from the device, the maximum device current must still be used.
Equation 8 can be used to determine the value of inductance. The constant K is the percentage of inductor
current ripple. For this example, K = 0.25 was chosen and an inductance of approximately 2.3 µH was found.
The next standard value of 1.5 μH was selected.
L=
VIN Å 9OUT
VOUT
Â
fSW Â . Â ,OUT(MAX)
VIN
(8)
The saturation current rating of the inductor must be at least as large as the high-side switch current limit, IL-HS
(see Section 7.5). This ensures that the inductor does not saturate even during a short circuit on the output.
When the inductor core material saturates, the inductance falls to a very low value, causing the inductor current
to rise very rapidly. Although the valley current limit, IL-LS, is designed to reduce the risk of current run-away,
a saturated inductor can cause the current to rise to high values very rapidly. This can lead to component
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damage; do not allow the inductor to saturate. Inductors with a ferrite core material have very hard saturation
characteristics, but usually have lower core losses than powdered iron cores. Powdered iron cores exhibit a soft
saturation, allowing some relaxation in the current rating of the inductor. However, they have more core losses at
frequencies typically above 1 MHz. In any case, the inductor saturation current must not be less than the device
high-side current limit, IL-HS (see Section 7.5). To avoid subharmonic oscillation, the inductance value must not
be less than that given in Equation 9. The maximum inductance is limited by the minimum current ripple required
for the current mode control to perform correctly. As a rule-of-thumb, the minimum inductor ripple current must
be no less than about 10% of the device maximum rated current under nominal conditions.
/ • 0.5 Â
VOUT
fSW
(9)
Equation 9 assumes that this design must operate with input voltage near or in dropout. If minimum operating
voltage for this design is high enough to limit duty factor to below 40%, Equation 8 can be used in place of
Equation 9.
Note that choosing an inductor that is larger than the minimum inductance calculated using Equation 8 and
Equation 9 results in less output capacitance being needed to limit output ripple but more output capacitance
being needed to manage large load transients. See Section 9.2.2.4.
9.2.2.4 Output Capacitor Selection
The value of the output capacitor and its ESR determine the output voltage ripple and load transient
performance. The output capacitor is usually determined by the load transient requirements rather than the
output voltage ripple. Table 9-3 can be used to find the output capacitor and CFF selection for a few common
applications. Note that a 1-kΩ RFF can be used in series with CFF to further improve noise performance. In this
example, improved transient performance is desired giving 2 x 47-µF ceramic as the output capacitor and 22 pF
as CFF.
Table 9-3. Recommended Output Ceramic Capacitors and CFF Values
3.3-V OUTPUT
5-V OUTPUT
FREQUENCY
TRANSIENT
PERFORMANCE
CERAMIC OUTPUT CAPACITANCE
CFF
CERAMIC OUTPUT CAPACITANCE
CFF
2.1 MHz
Minimum
3 x 22 µF
10 pF
2 x 22 µF
22 pF
2.1 MHz
Better Transient
2 x 47 µF
33 pF
3 x 22 µF
33 pF
400 kHz
Minimum
4 x 22 µF
4.7 pF
3 x 22 µF
10 pF
400 kHz
Better Transient
5 x 22 µF
33 pF
33 pF
To minimize ceramic capacitance, a low-ESR electrolytic capacitor can be used in parallel with minimal ceramic
capacitance. As a starting point for designing with an output electrolytic capacitor, Table 9-4 shows the
recommended output ceramic capacitance CFF values when using an electrolytic capacitor.
Table 9-4. Recommended Electrolytic and Ceramic Capacitor and CFF Values
FREQUENCY
TRANSIENT
PERFORMANCE
400 kHz
400 kHz
3.3-V OUTPUT
5-V OUTPUT
COUT
CFF
COUT
CFF
Minimum
2 x 22 µF ceramic + 1 x 470 µF, 100-mΩ electrolytic
10 pF
2 x 22 µF ceramic + 1 x 470 µF, 100-mΩ
electrolytic
10 pF
Better Transient
4 x 22 µF ceramic + 2 x 280 µF,100-mΩ electrolytic
33 pF
3 x 22 µF ceramic + 1 x 560 µF, 100-mΩ
electrolytic
22 pF
Most ceramic capacitors deliver far less capacitance than the rating of the capacitor indicates. Be sure to check
any capacitor selected for initial accuracy, temperature derating, and voltage derating. Table 9-3 and Table 9-4
have been generated assuming typical derating for 16-V, X7R, automotive grade capacitors. If lower voltage,
non-automotive grade, or lower temperature rated capacitors are used, more capacitors than listed are likely to
be needed.
9.2.2.5 Input Capacitor Selection
The ceramic input capacitors provide a low impedance source to the converter in addition to supplying the
ripple current and isolating switching noise from other circuits. A minimum of 10 μF of ceramic capacitance
34
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is required on the input of the device. This must be rated for at least the maximum input voltage that the
application requires; preferably twice the maximum input voltage. This capacitance can be increased to help
reduce input voltage ripple and maintain the input voltage during load transients. In addition, a small case
size 100-nF ceramic capacitor must be used at each input/ground pin pair, VIN1/PGND1 and VIN2/PGND2,
immediately adjacent to the converter. This provides a high-frequency bypass for the control circuits internal
to the device. These capacitors also suppress SW node ringing, which reduces the maximum voltage present
on the SW node and EMI. The two 100 nF must also be rated at 50 V with an X7R or better dielectric. The
VQFN-HR (RJR) package provides two input voltage pins and two power ground pins on opposite sides of the
package. This allows the input capacitors to be split, and placed optimally with respect to the internal power
MOSFETs, thus improving the effectiveness of the input bypassing. In this example, two 4.7-μF and two 100-nF
ceramic capacitors are used, one at each VIN/PGND location. A single 10-μF can also be used on one side of
the package.
Many times, it is desirable and necessary to use an electrolytic capacitor on the input in parallel with the
ceramics. This is especially true if long leads or traces are used to connect the input supply to the converter.
The moderate ESR of this capacitor can help damp any ringing on the input supply caused by the long power
leads. The use of this additional capacitor also helps with momentary voltage dips caused by input supplies with
unusually high impedance.
Most of the input switching current passes through the ceramic input capacitors. The approximate worst case
RMS value of this current can be calculated from Equation 10 and must be checked against the manufacturers'
maximum ratings.
IRMS §
IOUT
2
(10)
9.2.2.6 BOOT Capacitor
The LM62435-Q1 requires a bootstrap capacitor connected between the CBOOT pin and the SW pin. This
capacitor stores energy that is used to supply the gate drivers for the high-side power MOSFET. A high-quality
(X7R) ceramic capacitor of 100 nF and at least 10 V is required.
9.2.2.7 BOOT Resistor
A BOOT resistor can be connected between the CBOOT and RBOOT pins. Unless EMI for the application
being designed is critical, these two pins can be shorted. A 100-Ω resistor between these pins eliminates
overshoot. Even with 0 Ω, overshoot and ringing are minimal, less than 2 V if input capacitors are placed
correctly. A boot resistor of 100 Ω, which corresponds to approximately 2.7-ns SW node rise time and decreases
efficiency by approximately 0.5% at 2 MHz. To maximize efficiency, 0 Ω is chosen for this example. Under
most circumstances, selecting an RBOOT resistor value above 100 Ω is undesirable since the resulting small
improvement in EMI is not enough to justify further decreased efficiency.
9.2.2.8 VCC
The VCC pin is the output of the internal LDO used to supply the control circuits of the converter. This output
requires a 1-μF, 16-V ceramic capacitor connected from VCC to AGND for proper operation. In general, avoid
loading this output with any external circuitry. However, this output can be used to supply the pullup for the
power-good function (see Section 8.3.3). A pullup resistor with a value of 100 kΩ is a good choice in this case.
Note, VCC remains high when VEN_WAKE< EN < VEN. The nominal output voltage on VCC is 3.3 V. Do not short
this output to ground or any other external voltage.
9.2.2.9 BIAS
Because VOUT = 5 V in this design, the BIAS pin is tied to VOUT to reduce LDO power loss. The output voltage
is supplying the LDO current instead of the input voltage. The power saving is ILDO × (VIN – VOUT). The power
saving is more significant when VIN >> VOUT and with higher frequency operation. To prevent VOUT noise and
transients from coupling to BIAS, a series resistor, 1 Ω to 10 Ω, can be added between VOUT and BIAS. A
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bypass capacitor with a value of 1 μF or higher can be added close to the BIAS pin to filter noise. Note the
maximum allowed voltage on the BIAS pin is 16 V.
9.2.2.10 CFF and RFF Selection
A feedforward capacitor, Cff, is used to improve phase margin and transient response of circuits which have
output capacitors with low ESR. Since this capacitor can conduct noise from the output of the circuit directly
to the FB node of the IC, a 1-kΩ resistor, Rff, can be placed in series with Cff. If the ESR zero of the output
capacitor is below 200 kHz, no Cff must be used.
If output voltage is less than 2.5 V, Cff has little effect, so it can be omitted. If output voltage is greater than 14 V,
Cff must not be used since it introduces too much gain at higher frequencies.
9.2.2.11 External UVLO
In some cases, an input UVLO level different than that provided internal to the device is needed. This can
be accomplished by using the circuit shown in Figure 9-4. The input voltage at which the device turns on is
designated VON while the turnoff voltage is VOFF. First, a value for RENB is chosen in the range of 10 kΩ to 100
kΩ, then Equation 12 is used to calculate RENT and VOFF. RENB is typically set based on how much current this
voltage divider must consume. RENB can be calculated using Equation 11.
RENB =
VEN Â 9IN
IDIVIDER Â 9ON
(11)
VIN
RENT
EN
RENB
AGND
Figure 9-4. UVLO Using EN
RENT =
VON
Å 1 Â 5ENB
VEN
VOFF = VON Â (1 Å 9EN-HYST)
(12)
where
•
•
•
36
VON = VIN turnon voltage
VOFF = VIN turnoff voltage
IDIVIDER = voltage divider current
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9.2.3 Application Curves
100
100
95
90
80
70
Efficiency (%)
Efficiency (%)
90
85
80
75
60
50
40
30
70
VIN = 8 V
VIN = 12 V
VIN = 13.5 V
VIN = 24 V
65
60
0.001
VIN = 8 V
VIN = 12 V
VIN = 13.5 V
VIN = 24 V
20
10
0
0.005
0.02 0.05 0.1 0.2
Output Current (A)
VOUT = 3.3 V
FSW = 2100 kHz
0.5
1
2 34
0
AUTO Mode
VOUT = 3.3 V
Figure 9-5. LM62435-Q1 Efficiency
100
100
95
90
FSW = 2100 kHz
3
4
LM61
FPWM Mode
80
70
Efficiency (%)
Efficiency (%)
2
Output Current (A)
Figure 9-6. LM62435-Q1 Efficiency
90
85
80
75
60
50
40
30
70
VIN = 8 V
VIN = 12 V
VIN = 13.5 V
VIN = 24 V
65
60
0.001
VIN = 8 V
VIN = 12 V
VIN = 13.5 V
VIN = 24 V
20
10
0
0.005
0.02 0.05 0.1 0.2
Output Current (A)
VOUT = 5 V
FSW = 2100 kHz
0.5
1
2 34
0
1
LM61
AUTO Mode
VOUT = 5 V
Figure 9-7. LM62435-Q1 Efficiency
2
Output Current (A)
FSW = 2100 kHz
3
4
LM61
FPWM Mode
Figure 9-8. LM62435-Q1 Efficiency
3.37
3.37
VIN = 8 V
VIN = 12 V
VIN = 13.5 V
VIN = 24 V
VIN = 8 V
VIN = 12 V
VIN = 13.5 V
VIN = 24 V
3.35
Output Voltage (V)
3.35
Output Voltage (V)
1
LM61
3.33
3.33
3.31
3.31
3.29
3.29
0
VOUT = 3.3 V
1
2
Output Current (A)
FSW = 2100 kHz
3
4
0
LM61
Auto Mode
Figure 9-9. LM62435-Q1 Load and Line Regulation
VOUT = 3.3 V
1
2
Output Current (A)
FSW = 2100 kHz
3
4
LM61
FPWM Mode
Figure 9-10. LM62435-Q1 Load and Line Regulation
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5.11
5.11
5.09
5.09
5.07
5.07
Output Voltage (V)
Output Voltage (V)
9.2.3 Application Curves (continued)
5.05
5.03
5.01
4.99
5.03
5.01
4.99
VIN = 8 V
VIN = 12 V
VIN = 13.5 V
VIN = 24 V
4.97
5.05
VIN = 8 V
VIN = 12 V
VIN = 13.5 V
VIN = 24 V
4.97
4.95
4.95
0
1
2
Output Current (A)
VOUT = 5V
FSW = 2100 kHz
3
4
0
1
2
Output Current (A)
LM61
Auto Mode
VOUT = 5V
Figure 9-11. LM62435-Q1 Load and Line Regulation
FSW = 2100 kHz
3
4
LM61
FPWM Mode
Figure 9-12. LM62435-Q1 Load and Line Regulation
6
3.5
5.5
Ouput Voltage (V)
Output Voltage (V)
3.25
3
5
4.5
4
2.75
3.5
IOUT = 0.01 A
IOUT = 3 A
2.5
3
3.25
VOUT = 3.3 V
3.5
3.75
4
4.25
Input Voltage (V)
FSW = 2100 kHz
4.5
4.75
IOUT = 0.01 A
IOUT = 3 A
3
5
4
4.2
AUTO Mode
VOUT = 5 V
4.6
2.5E+6
2.5E+6
2.25E+6
2.25E+6
2E+6
1.75E+6
1.5E+6
1.25E+6
1E+6
7.5E+5
5E+5
2.5E+5
4.8
5
5.2 5.4
Input Voltage (V)
FSW = 2100 kHz
5.6
5.8
6
SNVS
AUTO Mode
Figure 9-14. LM62435-Q1 Dropout Curve
Switching Frequency (Hz)
Switching Frequency (Hz)
Figure 9-13. LM62435-Q1 Dropout Curve
2E+6
1.75E+6
1.5E+6
1.25E+6
1E+6
7.5E+5
5E+5
2.5E+5
IOUT = 3 A
0
IOUT = 3 A
0
3
VOUT = 3.3 V
3.5
4
Input Voltage (V)
FSW = 2100 kHz
4.5
5
5
SNVS
AUTO Mode
Figure 9-15. LM62435-Q1 Frequency Dropout Curve
38
4.4
SNVS
VOUT = 5 V
5.5
6
Input Voltage (V)
FSW = 2100 kHz
6.5
7
SNVS
AUTO Mode
Figure 9-16. LM62435-Q1 Frequency Dropout Curve
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9.2.3 Application Curves (continued)
Time (400ns/DIV)
VOUT = 5 V
FSW = 2100 kHz
IOUT = 100 mA
VIN = 13.5 V
AUTO Mode
Figure 9-17. LM62435-Q1 Switching Waveform and VOUT Ripple
VOUT = 5 V
FSW = 2100 kHz
IOUT = 3.5 A
VIN = 13.5 V
AUTO Mode
Figure 9-18. LM62435-Q1 Switching Waveform and VOUT Ripple
VOUT
(2 V/DIV)
IINDUCTOR
(1 A/DIV)
VPG
(5 V/DIV)
VEN
(5 V/DIV)
Time (1 ms/DIV)
VOUT = 3.3 V
FSW = 2100 kHz
IOUT = 3.25 A
VIN = 13.5 V
FPWM Mode
VOUT = 5 V
FSW = 2100 kHz
IOUT = 2.5 A to Short
VIN = 13.5 V
Circuit
Figure 9-19. LM62435-Q1 Start-up with 3.25 A
Figure 9-20. LM62435-Q1 Short Circuit Protection
VOUT
(5 V/DIV)
VOUT
(5 V/DIV)
VSW
(5 V/DIV)
VSW
(5 V/DIV)
IL
(2 A/DIV)
IL
(2 A/DIV)
Time (1.6 ms/DIV)
VOUT = 5 V
FSW = 2100 kHz
IOUT = Short Circuit to 2.5 A
FPWM Mode
Time (20 ms/DIV)
FPWM Mode
VOUT = 5 V
FSW = 2100 kHz
VIN = 13.5 V
IOUT = Short Circuit
VIN = 13.5 V
Figure 9-21. LM62435-Q1 Short Circuit Recovery
FPWM Mode
Figure 9-22. LM62435-Q1 Short Circuit Performance
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9.2.3 Application Curves (continued)
VOUT = 3.3 V
FSW = 2100 kHz
AUTO Mode
VOUT = 5 V
FSW = 2100 kHz
AUTO Mode
IOUT = 1.5 A to 3.5 A to 1.5
VIN = 13.5 V
TR = TF = 2µs
IOUT = 1.5 A to 3.5 A to 1.5
VIN = 13.5 V
TR = TF = 2µs
A
A
Figure 9-23. LM62435-Q1 Load Transient
VOUT = 5 V
FSW = 400 kHz
IOUT = 5 A*
Figure 9-24. LM62435-Q1 Load Transient
VOUT = 5 V
*Tested on 6 A Variant
Figure 9-25. Conducted EMI versus CISPR25 Limits (Yellow:
Peak Signal, Blue: Average Signal)
VOUT = 5 V
FSW = 400 kHz
FSW = 400 kHz
IOUT = 5 A
Frequency Tested: 30 MHz to 108 MHz
Frequency Tested: 150 kHz to 30 MHz
Figure 9-26. Conducted EMI versus CISPR25 Limits (Yellow:
Peak Signal, Blue: Average Signal)
IOUT = 5 A
Frequency Tested: 150 kHz to 30 MHz
Figure 9-27. Radiated EMI Rod versus CISPR25 Limits
VOUT = 5 V
FSW = 400 kHz
IOUT = 5 A
Frequency Tested: 30 MHz to 300 MHz
Figure 9-28. Radiated EMI Bicon Vertical versus CISPR25 Limits
40
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9.2.3 Application Curves (continued)
VOUT = 5 V
FSW = 400 kHz
IOUT = 5 A
VOUT = 5 V
Frequency Tested: 30 MHz to 300 MHz
FSW = 400 kHz
IOUT = 5 A
Frequency Tested: 300 MHz to 1 GHz
Figure 9-29. Radiated EMI Bicon Horizontal versus CISPR25
Limits
Figure 9-30. Radiated EMI Log Vertical versus CISPR25 Limits
744316220
L=2.2µH
VIN
IN+
IN-
GND
CF5=2.2uF
CF6=2.2uF
VOUT = 5 V
FSW = 400 kHz
IOUT = 5 A
Frequency Tested: 300 MHz to 1 GHz
Figure 9-31. Radiated EMI Log Horizontal versus CISPR25
Limits
FSW = 2100 kHz
VOUT = 5 V
FSW = 400 kHz
CF3=2.2uF
CF4= 2.2uF
CF1=470nF
CF2=470nF
Note: Measurements taken with
LM61460EVM with 6 A variant
Figure 9-32. Recommended Input EMI Filter
IOUT = 5 A*
Frequency Tested: 150 kHz to 30 MHz
*Tested on 6 A Variant
FSW = 2100 kHz
Figure 9-33. Conducted EMI versus CISPR25 Limits (Yellow:
Peak Signal, Blue: Average Signal)
VOUT = 5 V
IOUT = 5 A
Frequency Tested: 30 MHz to 108 MHz
Figure 9-34. Conducted EMI versus CISPR25 Limits (Yellow:
Peak Signal, Blue: Average Signal)
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9.2.3 Application Curves (continued)
74438356010
L=1µH
VIN
IN+
IN-
GND
CF5=2.2uF
CF6=2.2uF
CF3=2.2uF
CF4= 2.2uF
CF1=470nF
CF2=470nF
Note: All EMI measurements taken with 6 A Variant
FSW = 2100 kHz
Figure 9-35. Recommended Input EMI Filter
Table 9-5. BOM for Typical Application Curves
42
VOUT
FREQUENCY
RFBB
RT
COUT
CIN + CHF
L
CFF
3.3 V
2100 kHz
43.2 kΩ
6.04 kΩ
3 x 22 µF
2 x 4.7 µF + 2 x 100 nF
1.5 µH (MAPI 4020HT)
22 pF
5V
2100 kHz
24.9 kΩ
6.04 kΩ
2 x 22 µF
2 x 4.7 µF + 2 x 100 nF
1.5 µH (MAPI 4020HT)
22 pF
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10 Power Supply Recommendations
The characteristics of the input supply must be compatible with Absolute Maximum Ratings and Recommended
Operating Conditions in this data sheet. In addition, the input supply must be capable of delivering the required
input current to the loaded converter. The average input current can be estimated with Equation 13.
IIN =
VOUT Â ,OUT
VIN Â
(13)
where
•
η is the efficiency
If the converter is connected to the input supply through long wires or PCB traces, special care is required to
achieve good performance. The parasitic inductance and resistance of the input cables can have an adverse
effect on the operation of the converter. The parasitic inductance, in combination with the low-ESR, ceramic
input capacitors, can form an under-damped resonant circuit, resulting in overvoltage transients at the input to
the converter or tripping UVLO. The parasitic resistance can cause the voltage at the VIN pin to dip whenever
a load transient is applied to the output. If the application is operating close to the minimum input voltage, this
dip can cause the converter to momentarily shutdown and reset. The best way to solve these kind of issues is to
reduce the distance from the input supply to the converter and use an aluminum input capacitor in parallel with
the ceramics. The moderate ESR of this type of capacitor helps damp the input resonant circuit and reduce any
overshoot or undershoot at the input. A value in the range of 20 µF to 100 µF is usually sufficient to provide input
damping and help hold the input voltage steady during large load transients.
In some cases, a transient voltage suppressor (TVS) is used on the input of converters. One class of this
device has a snap-back characteristic (thyristor type). The use of a device with this type of characteristic is not
recommended. When the TVS fires, the clamping voltage falls to a very low value. If this voltage is less than
the output voltage of the converter, the output capacitors discharge through the device back to the input. This
uncontrolled current flow can damage the TVS and cause large input transients.
The input voltage must not be allowed to fall below the output voltage. In this scenario, such as a shorted input
test, the output capacitors discharge through the internal parasitic diode found between the VIN and SW pins of
the device. During this condition, the current can become uncontrolled, possibly causing damage to the device. If
this scenario is considered likely, then a Schottky diode between the input supply and the output must be used.
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11 Layout
11.1 Layout Guidelines
The PCB layout of any DC-DC converter is critical to the optimal performance of the design. Bad PCB layout can
disrupt the operation of an otherwise good schematic design. Even if the converter regulates correctly, bad PCB
layout can mean the difference between a robust design and one that cannot be mass produced. Furthermore,
the EMI performance of the converter is dependent on the PCB layout, to a great extent. In a buck converter, the
most critical PCB feature is the loop formed by the input capacitor or capacitors and power ground, as shown in
Figure 11-1. This loop carries large transient currents that can cause large transient voltages when reacting with
the trace inductance. These unwanted transient voltages disrupt the proper operation of the converter. Because
of this, the traces in this loop must be wide and short, and the loop area as small as possible to reduce the
parasitic inductance. Figure 11-2 shows a recommended layout for the critical components for the circuit of the
device.
•
•
•
•
•
•
•
•
44
Place the input capacitor or capacitors as close as possible input pin pairs: VIN1 to PGND1 and VIN2
to PGND2. Each pair of pins are adjacent, simplifying the input capacitor placement. With the VQFN-HR
package, there are two VIN/PGND pairs on either side of the package. This provides for a symmetrical layout
and helps minimize switching noise and EMI generation. Use a wide VIN plane on a lower layer to connect
both of the VIN pairs together to the input supply.
Place bypass capacitor for VCC close to the VCC pin and AGND pins: This capacitor must routed with short,
wide traces to the VCC and AGND pins.
Use wide traces for the CBOOT capacitor: Place the CBOOT capacitor as close to the device with short, wide
traces to the CBOOT and SW pins. It is important to route the SW connection under the device through the
gap between VIN2 and RBOOT pins, reducing exposed SW node area. If an RBOOT resistor is used, place
as close as possible to CBOOT and RBOOT pins. If high efficiency is desired, RBOOT and CBOOT pins can
be shorted. This short must be placed as close as possible to RBOOT and CBOOT pins as possible.
Place the feedback divider as close as possible to the FB pin of the device: Place RFBB, RFBT, and CFF, if
used, physically close to the device. The connections to FB and AGND through RFBB must be short and close
to those pins on the device. The connection to VOUT can be somewhat longer. However, this latter trace must
not be routed near any noise source (such as the SW node) that can capacitively couple into the feedback
path of the converter. For fixed output variants, the FB pin must be directly routed to the output of the device.
Layer of the PCB beneath the top layer with the IC must be a ground plane: This plane acts as a noise shield
and a heat dissipation path. Using the layer directly next to the IC reduces the inclosed area in the input
circulating current in the input loop, reducing inductance.
Provide wide paths for VIN, VOUT, and GND: These paths must be wide and direct as possible to reduce any
voltage drops on the input or output paths of the converter and maximizes efficiency.
Provide enough PCB area for proper heat sinking: Enough copper area must be used to ensure a low RθJA,
commensurate with the maximum load current and ambient temperature. Make the top and bottom PCB
layers with two-ounce copper and no less than one ounce. If the PCB design uses multiple copper layers
(recommended), thermal vias can also be connected to the inner layer heat-spreading ground planes. Note
that the package of this device dissipates heat through all pins. Wide traces must be used for all pins except
where noise considerations dictate minimization of area.
Keep switch area small: Keep the copper area connecting the SW pin to the inductor as short and wide as
possible. At the same time, the total area of this node must be minimized to help reduce radiated EMI.
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VIN1
VIN2
HS
FET
CIN_HF1
CIN_HF2
SW
LS
FET
PGND1
PGND2
Figure 11-1. Input Current Loop
11.1.1 Ground and Thermal Considerations
As mentioned above, TI recommends using one of the middle layers as a solid ground plane. A ground plane
provides shielding for sensitive circuits and traces. It also provides a quiet reference potential for the control
circuitry. The AGND and PGND pins must be connected to the ground planes using vias next to the bypass
capacitors. PGND pins are connected directly to the source of the low-side MOSFET switch, and also connected
directly to the grounds of the input and output capacitors. The PGND net contains noise at the switching
frequency and can bounce due to load variations. The PGND trace, as well as the VIN and SW traces, must be
constrained to one side of the ground planes. The other side of the ground plane contains much less noise and
must be used for sensitive routes.
TI recommends providing adequate device heat sinking by using vias near ground and VIN to connect to the
system ground plane or VIN strap, both of which dissipate heat. Use as much copper as possible, for system
ground plane, on the top and bottom layers for the best heat dissipation. Use a four-layer board with the copper
thickness for the four layers, starting from the top as: 2 oz / 1 oz / 1 oz / 2 oz. A four-layer board with enough
copper thickness and proper layout, provides low current conduction impedance, proper shielding, and lower
thermal resistance.
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11.2 Layout Example
GND POUR
VIAS to BIAS
VIA to Feedback
divider
VOUT
COUT2
COUT1
GND POUR
GND POUR
INDUCTOR
Inductor
CIN_HF2
CIN2
CIN_HF1
11
10
12
CIN1
9
8
VIN
7
6
13
14
CBOOT
1
2 3 4
VIN
5
RBOOT
VOUT
IC
REN
CVCC
RMODE
RFBB
CFF
GND POUR
RFBT
GND POUR
RFF
VOUT
INNER GND PLANE ± LAYER 2
Top Trace/Pour
VIA to Signal Layer
Inner GDN Plane
VIA to GND
Figure 11-2. Layout Example
46
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12 Device and Documentation Support
12.1 Documentation Support
12.1.1 Related Documentation
For related documentation see the following:
• Texas Instruments, LM61460-Q1 EVM User's Guide
• Texas Instruments, 30 W Power for Automotive Dual USB Type-C Charge Port Reference Design
• Texas Instruments, EMI Filter Components and Their Nonidealities for Automotive DC/DC Regulators
Technical Brief
• Texas Instruments, AN-2020 Thermal Design by Insight, Not Hindsight Application Report
• Texas InstrumentsOptimizing the Layout for the TPS54424/TPS54824 HotRod QFN Package for Thermal
Performance Application Report
• Texas Instruments, AN-2162 Simple Success With Conducted EMI From DC-DC Converters Application
Report
• Texas Instruments, Practical Thermal Design With DC/DC Power Modules Application Report
12.2 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. Click on
Subscribe to updates to register and receive a weekly digest of any product information that has changed. For
change details, review the revision history included in any revised document.
12.3 Support Resources
TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straight
from the experts. Search existing answers or ask your own question to get the quick design help you need.
Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do
not necessarily reflect TI's views; see TI's Terms of Use.
12.4 Trademarks
Hotrod™ and TI E2E™ are trademarks of Texas Instruments.
All trademarks are the property of their respective owners.
12.5 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled
with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may
be more susceptible to damage because very small parametric changes could cause the device not to meet its published
specifications.
12.6 Glossary
TI Glossary
This glossary lists and explains terms, acronyms, and definitions.
13 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
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PACKAGE OPTION ADDENDUM
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14-Jun-2021
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
(4/5)
(6)
LM62435APPQRJRRQ1
ACTIVE
VQFN-HR
RJR
14
3000
RoHS & Green
SN
Level-2-260C-1 YEAR
-40 to 150
62435Q
APP
LM62435BPPQRJRRQ1
ACTIVE
VQFN-HR
RJR
14
3000
RoHS & Green
SN
Level-2-260C-1 YEAR
-40 to 150
62435Q
BPP
LM62435CPPQRJRRQ1
ACTIVE
VQFN-HR
RJR
14
3000
RoHS & Green
SN
Level-2-260C-1 YEAR
-40 to 150
62435Q
CPP
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of