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LM7372
SNOS926F – MAY 1999 – REVISED SEPTEMBER 2014
LM7372 High Speed, High Output Current, Dual Operational Amplifier
1 Features
3 Description
The LM7372 is a high speed dual voltage feedback
amplifier with the slewing characteristic of current
feedback amplifiers. However, it can be used in all
traditional voltage feedback amplifier configurations.
−80 dBc Highest Harmonic Distortion @1 MHz,
2VPP
Very High Slew Rate: 3000 V/µs
Wide Gain Bandwidth Product: 120 MHz
−3 dB Frequency @ AV = +2: 200 MHz
Low Supply Current: 13 mA (both amplifiers)
High Open Loop Gain: 85 dB
High Output Current: 150 mA
Differential Gain and Phase: 0.01%, 0.02°
•
1
•
•
•
•
•
•
•
The LM7372 is stable for gains as low as +2 or −1. It
provides a very high slew rate at 3000 V/µs and a
wide gain bandwidth product of 120 MHz, while
consuming only 6.5 mA/per amplifier of supply
current. It is ideal for video and high speed signal
processing applications such as xDSL and pulse
amplifiers. With 150 mA output current, the LM7372
can be used for video distribution, as a transformer
driver or as a laser diode driver.
2 Applications
•
•
•
•
•
•
HDSL and ADSL Drivers
Multimedia Broadcast Systems
Professional Video Cameras
CATV/Fiber Optics Signal Processing
Pulse Amplifiers and Peak Detectors
HDTV Amplifiers
Operation on ±15 V power supplies allows for large
signal swings and provides greater dynamic range
and signal-to-noise ratio. The LM7372 offers high
SFDR and low THD, ideal for ADC/DAC systems. In
addition, the LM7372 is specified for ±5 V operation
for portable applications.
The LM7372 is built on TI's Advance VIP™ III
(Vertically integrated PNP) complementary bipolar
process.
Device Information(1)
PART NUMBER
PACKAGE
BODY SIZE (NOM)
LM7372
DDA (8)
4.90 mm × 3.91 mm
LM7372
D (16)
9.90 mm × 3.91 mm
(1) For all available packages, see the orderable addendum at
the end of the datasheet.
Harmonic Distortion vs Frequency
Single Supply Application (16-Pin SOIC)
-50
VCC
5
+ VIN
VCC
4
14
C6
0.1uF
+
1/2
LM7372
-
3
R9
50
R3
5.1k
R1
10.2k
C7
20uF
1:1
R5
2k
R6
2k
+
C3
47uF
R7
2k
R4
5.1k
C2
0.1uF
- VIN
100
R2
10.2k
12
11
Twisted
Pair Line
R8
50
HARMONIC DISTORTION (dBc)
VS = ±12V
+
C1
0.1uF
AV = 2
VO = 2VP-P
-70
HD2
RL = 100
HD3
-90
-110
1/2
LM7372
+
13
6
100k
1M
10M
FREQUENCY (Hz)
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
LM7372
SNOS926F – MAY 1999 – REVISED SEPTEMBER 2014
www.ti.com
Table of Contents
1
2
3
4
5
6
Features ..................................................................
Applications ...........................................................
Description .............................................................
Revision History.....................................................
Pin Configuration and Functions .........................
Specifications.........................................................
1
1
1
2
3
4
6.1
6.2
6.3
6.4
6.5
6.6
6.7
6.8
6.9
4
4
4
4
5
6
6
7
8
Absolute Maximum Ratings ......................................
Handling Ratings.......................................................
Recommended Operating Conditions (1) ...................
Thermal Information ..................................................
±15V DC Electrical Characteristics ..........................
±15V AC Electrical Characteristics ..........................
±5V DC Electrical Characteristics ............................
±5V AC Electrical Characteristics ............................
Typical Performance Characteristics ........................
7
Detailed Description ............................................ 12
8
Application and Implementation ........................ 13
7.1 Functional Block Diagram ....................................... 12
8.1 Application Information............................................ 13
8.2 Typical Application .................................................. 13
8.3 Application Details................................................... 14
9 Power Supply Recommendations...................... 20
10 Layout................................................................... 21
10.1 Layout Guidelines ................................................. 21
11 Device and Documentation Support ................. 21
11.1 Trademarks ........................................................... 21
11.2 Electrostatic Discharge Caution ............................ 21
11.3 Glossary ................................................................ 21
12 Mechanical, Packaging, and Orderable
Information ........................................................... 21
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision E (March 2013) to Revision F
Page
•
Changed data sheet structure and organization. Added, updated, or renamed the following sections: Device
Information Table, Pin Configuration and Functions, Application and Implementation; Device and Documentation
Support; Mechanical, Packaging, and Ordering Information.................................................................................................. 1
•
Changed "Junction Temperature Range" to "Operating Temperature Range" ...................................................................... 4
•
Deleted TJ = 25°C for Electrical Characteristics tables .......................................................................................................... 5
Changes from Revision D (March 2013) to Revision E
•
2
Page
Changed layout of National Data Sheet to TI format ........................................................................................................... 21
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SNOS926F – MAY 1999 – REVISED SEPTEMBER 2014
5 Pin Configuration and Functions
NOTE
For SO PowerPAD package the exposed pad should be tied either to V− or left electrically
floating. Die attach material is conductive and is internally tied to V−.
* Heatsink Pins. (1)
Package DDA
8-Pin SO PowerPAD
Top View
1
Package D
16-Pin SOIC
Top View
+
8
*
V
OUT A
16
1
NC 2
*
15 NC
A
-
2
+
OUT A 3
7
OUT B
-IN A
14 V+
A
-
+
13 OUT B
-IN A 4
+IN A
3
+
12 -IN B
+IN A 5
6
-IN B
B
B
V- 6
-
+
NC 7
4
-
V
5
-
11 +IN B
10 NC
+IN B
*
9
8
*
Pin Functions
PIN
NAME
NUMBER
I/O
DESCRIPTION
DDA
D
*
––
1,8,9,16
––
-IN A
2
4
I
ChA Inverting Input
+IN A
3
5
I
ChA Non-inverting Input
-IN B
6
12
I
ChB Inverting Input
+IN B
5
11
I
ChB Non-inverting Input
NC
––
2, 7, 10, 15
––
No Connection
OUT A
1
3
O
Output A
OUT B
7
13
O
Output B
Heatsink Pin
-
V
4
6
I
Negative Supply
V+
8
14
I
Positive Supply
(1)
The maximum power dissipation is a function of T(JMAX), RθJA, and TA. The maximum allowable power dissipation at any ambient
temperature is PD = (T(JMAX) – TA)/RθJA. All numbers apply for packages soldered directly into a PC board. The value for RθJA is
106°C/W for the 16-Pin SOIC package. With a total area of 4sq. in of 1oz CU connected to pins 1,6,8,9 & 16, RθJA for the 16-Pin SOIC
is decreased to 70°C/W. 8-Pin SO PowerPAD package RθJA is with 2 in2 heatsink (top and bottom layer each) and 1 oz. copper (see
Table 2 and Application and Implementation )
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LM7372
SNOS926F – MAY 1999 – REVISED SEPTEMBER 2014
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6 Specifications
6.1 Absolute Maximum Ratings (1) (2) (3)
over operating free-air temperature range (unless otherwise noted)
PARAMETER
MIN
MAX
UNIT
36
V
±10
V
Suppy Voltage (V+−V−)
Differential Input Voltage (VS = ±15V)
Output Short Circuit to Ground (2)
Continuous
Infrared or Convection Reflow (20 sec.)
Soldering Information
Wave Soldering Lead Temperature (10 sec.)
Input Voltage
Maximum Junction Temperature (4)
(1)
(2)
(3)
(4)
235
°C
260
°C
V− to V+
V
150
°C
Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for
which the device is intended to be functional, but specific performance is not ensured. For ensured specifications and the test
conditions, see the Electrical Characteristics.
Applies to both single-supply and split-supply operation. Continuous short circuit operation at elevated ambient temperature can result in
exceeding the maximum allowed junction temperature of 150°C.
If Military/Aerospace specified devices are required, please contact the Texas Instruments Sales Office/ Distributors for availability and
specifications.
The maximum power dissipation is a function of T(JMAX), RθJA, and TA. The maximum allowable power dissipation at any ambient
temperature is PD = (T(JMAX) – TA)/RθJA. All numbers apply for packages soldered directly into a PC board. The value for RθJA is
106°C/W for the 16-Pin SOIC package. With a total area of 4sq. in of 1oz CU connected to pins 1,6,8,9 & 16, RθJA for the 16-Pin SOIC
is decreased to 70°C/W. 8-Pin SO PowerPAD package RθJA is with 2 in2 heatsink (top and bottom layer each) and 1 oz. copper (see
Table 2 and Application and Implementation )
6.2 Handling Ratings
MIN
Tstg
V(ESD)
(1)
(2)
(3)
−65
Storage temperature range
Electrostatic discharge (1)
MAX
UNIT
150
°C
Human body model (HBM), per ANSI/ESDA/JEDEC JS-001, all
pins (2)
1500
Charged device model (CDM), per JEDEC specification
JESD22-C101, all pins (3)
200
V
For testing purposes, ESD was applied using human body model, 1.5kΩ in series with 100pF. Machine model, 0Ω in series with 200pF.
JEDEC document JEP155 states that 1500-V HBM allows safe manufacturing with a standard ESD control process.
JEDEC document JEP157 states that 200-V CDM allows safe manufacturing with a standard ESD control process.
6.3 Recommended Operating Conditions (1)
over operating free-air temperature range (unless otherwise noted)
Supply Voltage
Operating Temperature Range
(1)
MIN
MAX
9
36
UNIT
V
−40
85
°C
Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for
which the device is intended to be functional, but specific performance is not ensured. For ensured specifications and the test
conditions, see the Electrical Characteristics.
6.4 Thermal Information
THERMAL METRIC (1)
RθJA
(1)
(2)
4
Junction-to-ambient thermal resistance
DDA
8 PINS
106
D
(2)
16 PINS (2)
47
UNIT
°C/W
For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.
The maximum power dissipation is a function of T(JMAX), RθJA, and TA. The maximum allowable power dissipation at any ambient
temperature is PD = (T(JMAX) – TA)/RθJA. All numbers apply for packages soldered directly into a PC board. The value for RθJA is
106°C/W for the 16-Pin SOIC package. With a total area of 4sq. in of 1oz CU connected to pins 1,6,8,9 & 16, RθJA for the 16-Pin SOIC
is decreased to 70°C/W. 8-Pin SO PowerPAD package RθJA is with 2 in2 heatsink (top and bottom layer each) and 1 oz. copper (see
Table 2 and Application and Implementation )
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6.5
SNOS926F – MAY 1999 – REVISED SEPTEMBER 2014
±15V DC Electrical Characteristics
Unless otherwise specified, all limits ensured for VCM = 0V and RL = 1kΩ. Boldface apply at the temperature extremes.
PARAMETER
TEST CONDITIONS
MIN (1)
TYP (2)
MAX (1)
2.0
8.0
10.0
VOS
Input Offset Voltage
TC VOS
Input Offset Voltage Average Drift
IB
Input Bias Current
IOS
Input Offset Current
RIN
Input Resistance
RO
Open Loop Output Resistance
CMRR
Common Mode Rejection Ratio
VCM = ±10V
75
70
93
PSRR
Power Supply Rejection Ratio
VS = ±15V to ±5V
75
70
90
VCM
Input Common-Mode Voltage Range
CMRR > 60dB
AV
VO
Large Signal Voltage Gain
(3)
Output Swing
12
IS
(1)
(2)
(3)
µV/°C
2.7
10
12
µA
0.1
4.0
6.0
µA
40
MΩ
Differential Mode
3.3
MΩ
Ω
15
75
70
85
RL = 100Ω
70
66
81
13
12.7
13.4
−13
−12.7
−13.3
11.8
11.4
12.4
−11.2
−10.8
−11.9
RL = 1kΩ
dB
dB
±13
RL = 1kΩ
IOUT = 150mA
Output Short Circuit Current
mV
Common Mode
IOUT = − 150mA
ISC
UNIT
V
dB
dB
V
V
V
V
Sourcing
260
mA
Sinking
250
mA
Supply Current (both Amps)
13
17
19
mA
All limits are specified by testing or statistical analysis.
Typical values represent the most likely parametic norm.
Large signal voltage gain is the total output swing divided by the input signal required to produce that swing. For VS = ±15V, VOUT = ±
10V. For VS = ±5V, VOUT = ±2V
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LM7372
SNOS926F – MAY 1999 – REVISED SEPTEMBER 2014
6.6
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±15V AC Electrical Characteristics
Unless otherwise specified, all limits ensured for VCM = 0V and RL = 1kΩ. Boldface apply at the temperature extremes.
PARAMETER
SR
Slew Rate
TEST CONDITIONS
(3)
MIN (1)
TYP (2)
AV = +2, VIN 13VP-P
3000
AV = +2, VIN 10VP-P
2000
Unity Bandwidth Product
MAX (1)
UNIT
V/µs
120
MHz
220
MHz
AVOL = 6dB
70
deg
AV = −1, AO = ±5V,
RL = 500Ω
50
AV = −2, VIN = ±5V,
RL = 500Ω
6.0
−3dB Frequency
AV = +2
φm
Phase Margin
tS
Settling Time (0.1%)
tP
Propagation Delay
AD
Differential Gain (4)
φD
Differential Phase (4)
hd2
Second Harmonic Distortion
FIN = 1MHz, AV = +2
hd3
IMD
ns
ns
0.01%
0.02
deg
VOUT = 2VP-P, RL = 100Ω
−80
dBc
VOUT = 16.8VP-P, RL = 100Ω
−73
dBc
Third Harmonic Distortion
FIN = 1MHz, AV = +2
VOUT = 2VP-P, RL = 100Ω
−91
dBc
VOUT = 16.8VP-P, RL = 100Ω
−67
dBc
Intermodulation Distortion
Fin 1 = 75kHz,
Fin 2 = 85kHz
VOUT = 16.8VP-P, RL = 100Ω
−87
dBc
en
Input-Referred Voltage Noise
f = 10kHz
14
nV/√Hz
in
Input-Referred Current Noise
f = 10kHz
1.5
pA/√Hz
(1)
(2)
(3)
(4)
All limits are specified by testing or statistical analysis.
Typical values represent the most likely parametic norm.
Slew Rate is the average of the rising and falling slew rates.
Differential gain and phase are measured with AV = +2, VIN = 1VPP at 3.58 MHz and output is 150Ω terminated.
6.7
±5V DC Electrical Characteristics
Unless otherwise specified, all limits ensured for VCM = 0V and RL = 1kΩ. Boldface apply at the temperature extremes.
PARAMETER
VOS
Input Offset Voltage
TC VOS
Input Offset Voltage Average Drift
IB
Input Bias Current
IOS
Input Offset Current
RIN
Input Resistance
TEST CONDITIONS
MIN (1)
TYP (2)
MAX (1)
2.2
8.0
10.0
12
µV/°C
10
12
µA
0.1
4
6
µA
Common Mode
40
MΩ
Differential Mode
3.3
MΩ
15
Ω
Open Loop Output Resistance
CMRR
Common Mode Rejection Ratio
VCM = ±2.5V
70
65
90
PSRR
Power Supply Rejection Ratio
VS = ±15V to ±5V
75
70
90
VCM
Input Common-Mode Voltage Range
CMRR > 60dB
AV
Large Signal Voltage Gain (3)
RL = 1kΩ
70
65
78
RL = 100Ω
64
60
72
6
mV
3.3
RO
(1)
(2)
(3)
UNIT
±3
dB
dB
V
dB
dB
All limits are specified by testing or statistical analysis.
Typical values represent the most likely parametic norm.
Large signal voltage gain is the total output swing divided by the input signal required to produce that swing. For VS = ±15V, VOUT = ±
10V. For VS = ±5V, VOUT = ±2V
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±5V DC Electrical Characteristics (continued)
Unless otherwise specified, all limits ensured for VCM = 0V and RL = 1kΩ. Boldface apply at the temperature extremes.
PARAMETER
VO
TEST CONDITIONS
Output Swing
RL = 1kΩ
IOUT = − 80mA
IOUT = 80mA
ISC
IS
6.8
Output Short Circuit Current
MIN (1)
TYP (2)
3.2
3.0
3.4
−3.2
−3.0
−3.4
2.5
2.2
2.8
−2.5
−2.2
−2.7
Sourcing
150
Sinking
150
Supply Current (both Amps)
12.4
MAX (1)
UNIT
V
V
V
V
mA
mA
16
18
mA
±5V AC Electrical Characteristics
Unless otherwise specified, all limits ensured for VCM = 0V and RL = 1kΩ. Boldface apply at the temperature extremes.
PARAMETER
SR
Slew Rate
(3)
TEST CONDITIONS
AV = +2, VIN 3VP-P
Unity Bandwidth Product
−3dB Frequency
AV = +2
MIN (1)
TYP (2)
MAX (1)
UNIT
700
V/µs
100
MHz
125
MHz
70
deg
φm
Phase Margin
tS
Settling Time (0.1%)
AV = −1, VO = ±1V, RL = 500Ω
70
ns
tP
Propagation Delay
AV = +2, VIN = ±1V, RL = 500Ω
7
ns
AD
Differential Gain (4)
φD
Differential Phase (4)
hd2
Second Harmonic Distortion
FIN = 1MHz, AV = +2
VOUT = 2VP-P, RL = 100Ω
−84
hd3
Third Harmonic Distortion
FIN = 1MHz, AV = +2
VOUT = 2VP-P, RL = 100Ω
−94
en
Input-Referred Voltage Noise
f = 10kHz
14
nV/√Hz
in
Input-Referred Current Noise
f = 10kHz
1.8
pA/√Hz
(1)
(2)
(3)
(4)
0.02%
0.03
deg
dBc
dBc
All limits are specified by testing or statistical analysis.
Typical values represent the most likely parametic norm.
Slew Rate is the average of the rising and falling slew rates.
Differential gain and phase are measured with AV = +2, VIN = 1VPP at 3.58 MHz and output is 150Ω terminated.
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6.9 Typical Performance Characteristics
-50
-30
VS = ±12V
AV = 2
HARMONIC DISTORTION (dBc)
HARMONIC DISTORTION (dBc)
VS = ±12V
VO = 2VP-P
-70
HD2
RL = 100
HD3
-90
-110
AV = 2
-50
RL = 100
HD2
-70
-90
-110
1M
100k
10M
1M
100k
FREQUENCY (Hz)
Figure 2. Harmonic Distortion vs Frequency
-30
-30
VS = ±12V
VS = ±12V
HARMONIC DISTORTION (dBc)
HARMONIC DISTORTION (dBc)
AV = 8
VO = 2VP-P
-50
HD2
RL = 100
-70
HD3
-90
HD3
AV = 8
VO = 16.8VP-P
-50
RL = 100
HD2
-70
-90
-110
1M
100k
100M
1M
100k
FREQUENCY (Hz)
10M
FREQUENCY (Hz)
Figure 3. Harmonic Distortion vs Frequency
Figure 4. Harmonic Distortion vs Frequency
-50
-40
VS = ±12V
VS = ±12V
AV = 8
AV = 8
RL = 100
f = 1MHz
RL = 100
f = 100kHz
-70
DISTORTION (dBc)
DISTORTION (dBc)
10M
FREQUENCY (Hz)
Figure 1. Harmonic Distortion vs Frequency
HD2
-90
HD3
-110
-60
HD2
-80
HD3
-100
1
10
20
1
OUTPUT VOLTAGE (VP-P)
10
20
OUTPUT VOLTAGE (VP-P)
Figure 5. Harmonic Distortion vs
8
HD3
VO = 16.8VP-P
Figure 6. Harmonic Distortion vs Output Level
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Typical Performance Characteristics (continued)
-50
VS = ±12V
VS = ±12V
AV = 2
AV = 2
RL = 100
f = 100kHZ
-80
DISTORTION (dBc)
DISTORTION (dBc)
-60
HD2
-100
RL = 100
f = 1MHZ
-70
HD2
-90
HD3
HD3
-110
-120
1
10
1
20
10
OUTPUT VOLTAGE (VP-P)
OUTPUT VOLTAGE (VP-P)
Figure 7. Harmonic Distortion vs Output Level
Figure 8. Harmonic Distortion vs Output Level
-40
-60
VS = ±12V
VS = ±12v
AV = 2
AV = 2
VO = 2VP-P
f = 100kHz
-80
-60
DISTORTION (dBc)
DISTORTION (dBc)
20
HD2
-100
VO = 2VP-P
f = 1MHz
-80
HD2
HD3
-100
HD3
-120
-120
10
100
1000
10
1000
LOAD RESISTANCE (:)
LOAD RESISTANCE (:)
Figure 9. Harmonic Distortion vs Load Resistance
-40
100
Figure 10. Harmonic Distortion vs Load Resistance
-40
VS = ±12V
VS = ±12V
AV = 8
-80
HD2
-100
VO = 2VP-P
f = 100kHz
-60
DISTORTION (dBc)
DISTORTION (dBc)
AV = 8
VO = 2VP-P
f = 1MHz
-60
-80
HD2
-100
HD3
HD3
-120
-120
10
100
1000
10
LOAD RESISTANCE (:)
100
1000
LOAD RESISTANCE (:)
Figure 11. Harmonic Distortion vs Load Resistance
Figure 12. Harmonic Distortion vs Load Resistance
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Typical Performance Characteristics (continued)
2
2
VS = ±12V
1
1
RL = 100
0
NORMALIZED GAIN (dB)
NORMALIZED GAIN (dB)
0
GAIN = +2
-1
-2
GAIN = +8
-3
-4
-1
GAIN = +2
-2
GAIN = +8
-3
-4
-5
-5
-6
-6
VS = ±15V
RL = 100
1
10
100
1
1000
10
100
1000
FREQUENCY (MHz)
FREQUENCY (MHz)
Figure 13. Frequency Response
Figure 14. Frequency Response
2
VS = ±5V
VS = ±12V
RL = 100
AV = 2
OUTPUT VOLTAGE (100mV/div)
1
NORMALIZED GAIN (dB)
0
-1
GAIN = +2
-2
GAIN = +8
-3
-4
RL = 100
-5
-6
1
10
100
1000
TIME (100ns/div)
FREQUENCY (MHz)
Figure 16. Small Signal Pulse Response
Figure 15. Frequency Response
100
AV = 2
90
RL = 100
80
TJA (°C/W)
OUTPUT VOLTAGE (2V/div)
VS = ±12V
70
0.5 oz
60
1.0 oz
50
2.0 oz
40
30
20
0
TIME (100ns/div)
1.0
1.5
2.0
2.5
2
COPPER AREA (in )
Figure 17. Large Signal Pulse Response
10
0.5
Figure 18. Thermal Performance of 8ld-SO PowerPAD
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Typical Performance Characteristics (continued)
-50
3
VS = ±5V
VS = ±15V
2.5
VO = 2VP-P
-70
INPUT BIAS CURRENT (µA)
HARMONIC DISTORTION (dBc)
AV = 2
RL = 100
HD2
-90
HD3
2
1.5
1
0.5
0
-40
-110
100k
1M
10M
25
85
125
TEMPERATURE (°C)
FREQUENCY (Hz)
Figure 20. Input Bias Current (µA) vs Temperature
Figure 19. Harmonic Distortion vs Frequency
20
VS = ±15V
OUTPUT VOLTAGE (V)
POSITIVE OUTPUT
10
0
NEGATIVE OUTPUT
-10
-20
-200
-100
0
100
200
OUTPUT CURRENT (mA)
Figure 21. Output Voltage vs Output Current
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7 Detailed Description
7.1 Functional Block Diagram
M1
Q1
Q4
RE
IN
-
V
-
IN
+
OUTPUT
BUFFER
+
A
V
Q3
Q2
M2
Figure 22. Simplified Schematic Diagram
12
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LM7372
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8 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
8.1 Application Information
The LM7372 is a high speed dual operational amplifier with a very high slew rate and very low distortion. Like
many other op amps, it is used in conventional voltage feedback amplifier applications, and has a class AB
output stage in order to deliver high currents to low impedance loads. However, it draws a low quiescent supply
current in most situations since the supply current increases when necessary to keep up with large output swing
and/or high frequency (see High Frequency/Large Signal Swing Considerations). For most op amps in typical
applications, this topology means that internal power dissipation is rarely an issue, even with the trend to smaller
surface mount packages. However, TI has designed the LM7372 for applications where there are significant
levels of power dissipation, and a way to effectively remove the internal heat generated by this power dissipation
is needed in order to maintain the semiconductor junction temperature at acceptable levels. This is particularly
important in environments with elevated ambient temperatures.
8.2 Typical Application
V+
+
0.1uF
3
+ VIN
2
5.1k
0.1uF
8
20uF
+
1/2
LM7372
-
1
50
1:1
2k
Twisted
Pair Line
2k
100
2k
50
6
0.1uF
5
- VIN
1/2
LM7372
+
7
4
5.1k
V0.1uF
+
20uF
Figure 23. Split Supply Application (SO PowerPAD)
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Typical Application (continued)
VCC
+
C1
0.1uF
5
+ VIN
VCC
4
14
C6
0.1uF
+
1/2
LM7372
-
3
R9
50
R3
5.1k
R1
10.2k
C7
20uF
1:1
R5
2k
Twisted
Pair Line
R6
2k
+
C3
47uF
100
R7
2k
R2
10.2k
R4
5.1k
12
C2
0.1uF
11
- VIN
R8
50
1/2
LM7372
+
13
6
Figure 24. Single Supply Application (16-Pin SOIC)
8.3 Application Details
Several factors contribute to power dissipation and consequently higher semiconductor junction temperatures.
Understanding these factors is necessary if the LM7372 is to perform to the desired specifications. Since
different applications will have different dissipation levels and since there are various possible compromises
between the ways these factors will contribute to the total junction temperature, this section will examine the
typical application shown in Figure 24 as an example, and offer solutions when encountering excessive junction
temperatures.
There are two major contributors to the internal power dissipation. The first is the product of the supply voltage
and the LM7372 quiescent current when no signal is being delivered to the external load, and the second is the
additional power dissipated while delivering power to the external load. For low frequency (
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