LM74610-DQEVM

LM74610-DQEVM User's Guide Literature Number: SNVU488 October 2015 Contents 1 2 3 Introduction ......................................................................................................................... 4 Setup .................................................................................................................................. 4 2.1 Input/Output Connector Description ................................................................................... 4 2.2 Board Setup ............................................................................................................... 6 Operation ............................................................................................................................ 7 3.1 Reverse Polarity Protection ............................................................................................. 7 3.2 Output Voltage ............................................................................................................ 9 4 5 6 ................................................................................................ 10 3.4 Power Supply Consideration .......................................................................................... 13 Board Layout ..................................................................................................................... 14 Schematic ......................................................................................................................... 16 Bill of Materials .................................................................................................................. 18 2 Table of Contents 3.3 ORing Application Test SNVU488 – October 2015 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated www.ti.com List of Figures ........................................................................ 5 .......................................................................................................... 6 Response to Reverse Polarity 12V to -20V .............................................................................. 7 Response to Start Up Reverse Polarity ................................................................................... 8 Periodic Body Diode Voltage Drop at the Output........................................................................ 9 The LM74610-DQEVM Output Voltage Waveform .................................................................... 10 OR-ing Application Output Voltage Waveform ......................................................................... 11 ORing Application for One DC Input and One Dynamic Pulse ....................................................... 12 LM74610-Q1 OR-ing Waveform.......................................................................................... 13 Top Assembly Layer ....................................................................................................... 14 Bottom Layer ................................................................................................................ 15 LM74610-DQ EVM Schematic............................................................................................ 16 1 LM74610-Q1 Typical OR-ing Application Circuit 2 LM74610-DQ EVM 3 4 5 6 7 8 9 10 11 12 List of Tables 1 Device and Package Configurations ...................................................................................... 4 2 LM74610-DQ EVM Bill of Materials for Configuration ................................................................. 18 SNVU488 – October 2015 Submit Documentation Feedback List of Figures Copyright © 2015, Texas Instruments Incorporated 3 Introduction 1 www.ti.com Introduction The Texas Instruments LM74610-DQ Evaluation Module helps designers evaluate the operation and performance of the LM74610-Q1 Reverse Polarity Protection Smart Diode Controller in an OR-ing configuration. In this design scheme two LM74610-Q1 ICs are combined with MOSFETs and used with redundant N+1 power supplies arrangements as replacement for schottky diodes in an OR-ing device as shown in Figure 1 . This EVM demonstrates how an N-channel power MOSFET can emulate a very low forward voltage diode with zero Iq and low reverse leakage current. For more information on the LM74610-Q1 functional and electrical characteristics, see the LM74610-Q1 Reverse Polarity Protection Smart Diode Controller Data Sheet (LM74610-Q1). The EVM contains two LM74610-Q1 Smart Diode Controllers devices(See Table 1). For single channel LM74610-Q1 performance evaluation, use LM74610-SQEVM (LM74610-SQEVM). Table 1. Device and Package Configurations 2 CONVERTER IC PACKAGE U1 LM74610-Q1 VSSOP-8 U2 LM74610-Q1 VSSOP-8 Setup This section describes the jumpers and connectors on the EVM as well and how to properly connect, set up and use the LM74610EVM. Ensure the power supply is turned off while making connections on the board. 2.1 Input/Output Connector Description • • • • • 4 VBAT_1 is the power input connector to the positive rail of the input power supply. VBAT_2 is the second power input connector to the positive rail of the input power supply. GND is the ground connector. VOUT is the power output connector to the positive side of the load. TEST POINTS are also available at VBAT_1, VBAT_2, GND, VOUT, DRV_1/ DRV_2 (MOSFET Gate Voltage), and VCAP_1/ VCAP_2 (charge pump capacitors). List of Tables SNVU488 – October 2015 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated Setup www.ti.com + PS1 Gate Drive Anode ± Pull Down LM74610-Q1 Cathode CLOAD VCAPH RLOAD VCAPL Vcap + PS2 Gate Drive Anode ± Pull Down LM74610-Q1 VCAPH Cathode VCAPL Vcap Figure 1. LM74610-Q1 Typical OR-ing Application Circuit SNVU488 – October 2015 Submit Documentation Feedback List of Tables Copyright © 2015, Texas Instruments Incorporated 5 Setup 2.2 www.ti.com Board Setup Before applying power to the LM74610-DQ EVM, all external connections should be verified. External power supplies should be turned off and connected with proper polarity to the VBAT_1 and GND connectors. An electronic or resistive load must be connected at the output. The LM74610-Q1 will not initiate the charge pump operation if a closed loop system is in standby mode or the drain current is smaller than 1mA (typical). The tests outlined in this document has 3A constant load current and 12V input supply voltage at (VBAT_1). VBAT_2 can be used as a secondary input when using LM74610-DQEVM as an OR-ing device. Make sure that the external power supply source for the input voltage is capable of providing enough current to the output load so that the output voltage can be obtained. Once all connections to the LM74610EVM are verified, power can be applied to VBAT_1. The EVM will then begin to operate. Figure 2. LM74610-DQ EVM 6 List of Tables SNVU488 – October 2015 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated Operation www.ti.com 3 Operation 3.1 Reverse Polarity Protection A dynamic voltage pulse from +12V to -20V is applied at the VBAT_1 input of the LM74610-DQEVM. Figure 3 shows when the input voltage (yellow) drops down to -20V, the output voltage (blue) does not go negative, and therefore, the load is protected from dynamic reverse pulses at the input. The LM74610-Q1 reacts the negative voltage surge within 2 μ sec and shuts down the MOSFET by pulling the gate voltage to zero (green). The output slowly decays due to the large output capacitors and increased time constant. VIN (10 V/DIV, 12 V to -20 V) VOUT (10 V/DIV, 12 V to 0 V) Gate Drive (10 V/DIV) Time (100 µs/DIV) Figure 3. Response to Reverse Polarity 12V to -20V SNVU488 – October 2015 Submit Documentation Feedback List of Tables Copyright © 2015, Texas Instruments Incorporated 7 Operation www.ti.com A -12V source is connected to the VBAT_1 input of the LM74610-DQEVM. Figure 4 shows that the Output voltage will stay at a constant 0V in this situation. This test simulates the event of connecting a 12V battery in the reverse direction, and therefore, protects the load from negative voltages. Figure 4. Response to Start Up Reverse Polarity Note: the leakage current is 60uA (typ). This means that if you apply a voltage on the output you will see some voltage on input and this voltage will collapse if you draw more current than the leakage current. The same applies for a reverse voltage applied on the input. 8 List of Tables SNVU488 – October 2015 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated Operation www.ti.com 3.2 Output Voltage When power is initially applied, the load current (ID) will flow through the body diode of the MOSFET. This current will produce a forward voltage drop (Vf) across the MOSFET body diode. This voltage is used to charge up the charge pump capacitor Vcap. This periodic voltage drop will be equal to the MOSFET body diode forward voltage drop and occurs for about 25.6msec as shown in Figure 5. Figure 5. Periodic Body Diode Voltage Drop at the Output During the rest of the period of conduction, the LM74610-Q1 will drive the gate of the MOSFET. When the MOSFET is ON, it provides a low resistive path for the drain current to flow and minimizes the power dissipation associated with forward conduction. The power losses during the MOSFET ON state depend primarily on the RDSON of the selected MOSFET and load current. The LM74610-Q1 operation keeps the MOSFET ON at approximately 98% as shown in Figure 6, leading to very little overall power dissipation when compared to a typical diode. SNVU488 – October 2015 Submit Documentation Feedback List of Tables Copyright © 2015, Texas Instruments Incorporated 9 Operation www.ti.com Figure 6. The LM74610-DQEVM Output Voltage Waveform 3.3 ORing Application Test When using LM74610-DQEVM as an OR-ing device, if the input supplies operate at slightly different voltages, the voltage at the common load point should follow the higher voltage. The LM74610-Q1 prevents reverse current flow from the common load point to the lower voltage supply rail. This test uses 15V and 12V at the inputs (VBAT_1 and VBAT_2). As shown in Figure 7, the voltage source at Input 1 is turned off for a period of time and the output (VOUT) equals the voltage from Input 2. When the voltage source at Input 1 is turned on again, the output equals the voltage from Input 1 because of its larger voltage. 10 List of Tables SNVU488 – October 2015 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated Operation www.ti.com Figure 7. OR-ing Application Output Voltage Waveform SNVU488 – October 2015 Submit Documentation Feedback List of Tables Copyright © 2015, Texas Instruments Incorporated 11 Operation www.ti.com A dynamic voltage pulse from +14V to -37V is applied at the input (VBAT_1) of the EVM. A 10V source is connected to the second input (VBAT_2) of the EVM. Figure 8 shows that the VOUT voltage equals 10V when VBAT_1 equals -37V and does not go negative. Therefore, the load is protected from dynamic reverse pulses at the input. Figure 8. ORing Application for One DC Input and One Dynamic Pulse If one of the power supplies fails in LM74610-Q1 OR-ing controller application, the output remains uninterrupted. This behavior is similar to diode OR-ing.Figure 9 12 List of Tables SNVU488 – October 2015 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated Operation www.ti.com VOUT (5 V/DIV, 12 V) VIN 1 (5 V/DIV, 12 V) VIN 2 (5 V/DIV, 12 V to 0 V) Time (1 s/DIV) Figure 9. LM74610-Q1 OR-ing Waveform 3.4 Power Supply Consideration While testing the LM74610-DQEVM OR-ing solution, it is important to use low impedance power supply which allows current sinking. If the power supply does not allow current sinking, it would prevent the current flow in the reverse direction in the event of reverse polarity. The MOSFET gate won't get pulled down immediately due to the absence of reverse current flow. SNVU488 – October 2015 Submit Documentation Feedback List of Tables Copyright © 2015, Texas Instruments Incorporated 13 Board Layout 4 www.ti.com Board Layout Figure 10. Top Assembly Layer 14 List of Tables SNVU488 – October 2015 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated Board Layout www.ti.com Figure 11. Bottom Layer SNVU488 – October 2015 Submit Documentation Feedback List of Tables Copyright © 2015, Texas Instruments Incorporated 15 Schematic 5 www.ti.com Schematic Figure 12. LM74610-DQ EVM Schematic 16 List of Tables SNVU488 – October 2015 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated Schematic www.ti.com Note:The TVS+ and TVS- are not required for the LM74610-Q1. However, they are typically used to clamp the positive and negative voltage surges respectively. The output capacitors are recommended to protect the immediate output voltage collapse as a result of line disturbance. SNVU488 – October 2015 Submit Documentation Feedback List of Tables Copyright © 2015, Texas Instruments Incorporated 17 Bill of Materials 6 www.ti.com Bill of Materials Table 2. LM74610-DQ EVM Bill of Materials for Configuration COUNT DRV_1, DRV_2, P1, P2, P3, P4 3 TP3, VIN_1, VIN_2 C6 2 DESCRIPTION MFR PART NUMBER NONE NONE Test Point, Miniature, SMT Keystone 5015 CAP, AL, 1000 µF, 50 V, +/- 20%, 0.073 ohm, SMD Panasonic EEV-FK1H102M D1_1, D2_1 Diode, TVS, Uni, 28 V, 600 W, SMB Diodes Inc. SMBJ28A-13-F 2 D1_2, D2_2 Diode, TVS, Uni, 14 V, 600 W, SMB Diodes Inc. SMBJ14A-13-F 2 FET1_A, FET2_A MOSFET, N-CH, 40 V, 75 A, PowerPAK_SO-8L VishaySiliconix SQJ422EP-T1-GE3 2 TP2, TP4 Test Point, Multipurpose, Black, TH Keystone 5011 2 U1, U2 Smart Diode Controller, DGK0008A Texas Instruments LM74610QDGKRQ1 C7 CAP, AL, 68 µF, 50 V, +/- 20%, 0.6 ohm, SMD Nippon Chemi-Con EMVY500ADA680MHA0G 2 GND, J4 Standard Banana Jack, Insulated, Black Keystone 6092 3 J3, VBAT_1, VBAT_2 Standard Banana Jack, Insulated, Red Keystone 6091 4 C3, C4, C5, C23 CAP, CERM, 4.7 µF, 50 V, +/- 10%, X7R, 1210 MuRata GRM32ER71H475KA88L 2 C1, C21 CAP, CERM, 100 pF, 50 V, +/- 5%, C0G/NP0, 0805 AVX 08055A101JAT2A 2 C2, C22 CAP, CERM, 1 µF, 50 V, +/- 10%, X7R, 0805 TDK C2012X7R1H105K125AB 2 VCAP_1, VCAP_2 CAP, CERM, 2.2 µF, 50 V, +/- 10%, X5R, 0805 TDK C2012X5R1H225K125AB DNS DNS 18 REF DES 6 List of Tables SNVU488 – October 2015 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated STANDARD TERMS AND CONDITIONS FOR EVALUATION MODULES 1. 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