LM8342
www.ti.com
SNOSAM0B – NOVEMBER 2005 – REVISED MARCH 2013
LM8342 Programmable TFT VCOM Calibrator with Non-Volatile Memory
Check for Samples: LM8342
FEATURES
DESCRIPTION
1
•
2
•
•
•
•
•
•
The LM8342 is an integrated combination of a nonvolatile register (7 bits EEPROM) and a DAC
controlled current source. Using the LM8342, the
VCOM calibration procedure is simplified by elimination
of the potentiometer adjustment task. This adjustment
task is currently performed at the factory using a
trimmer adjustment tool and visual inspection.
2
I C Compatible Programmable DAC to Set the
Output Current
Ensured Monotonic DAC
Non-Volatile Memory to Hold the Setting
EEPROM in System Programmable
No External Programming Voltage Required
Maximum Interface Bus Speed is 400 kHz
SON-10 Package
The VCOM adjustment can be done electronically in
production, using the I2C compatible interface. The
factory operator can physically view the screen headon (frontal viewing) when performing this step, easing
manufacturing especially for large TFT panels.
APPLICATIONS
•
•
•
TFT Panel Factory Calibration
Digital Potentiometer
Programmable Current Sink
The VCOM level is typically at half AVDD (determined
by R1 and R2) and is buffered by the actual VCOM
driver. By controlling the level of IOUT, the VCOM level
can be tuned. The current level at the output of the
LM8342 is a fraction (1/128 to 128/128) of a
maximum current which is set by RSET and an analog
reference (AVDD). The actual fraction is determined
by the 7-bit DAC. As a result, the output current of
the LM8342 has a good temperature stability yielding
a very stable VCOM adjustment. Controlling the DAC
setting of the LM8342 is done via its I2C compatible
interface. The actual DAC setting is stored in a
volatile register. Using a “Write to EE” command the
data can be stored permanently in the embedded
EEPROM. At power on of the device, the EEPROM
data is copied to the volatile register, setting the DAC.
At any time, the data in the EEPROM can be
changed again via the I2C compatible interface.
Typical Application
15 k:
2
I C INTERFACE
VDD
15 k:
15 k:
7
8
2
VDD
AVDD
R1
+
-
OUT
SDA
1
SCL
IOUT
VCOM
R2
LM8342
9
CONTROLLER
AVDD
6
3
SCL-S
SET
WPN
10
RSET
WPP
4
GND
5
1
2
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
All trademarks are the property of their respective owners.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2005–2013, Texas Instruments Incorporated
LM8342
SNOSAM0B – NOVEMBER 2005 – REVISED MARCH 2013
www.ti.com
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
Absolute Maximum Ratings (1)
Human Body Model
ESD Tolerance (2)
SCL, SDA Pins
All Other Pins
Machine Model
Supply and Reference Voltage
250V
VDD
5V
AVDD
20V
−65°C to +150°C
Storage Temperature Range
Junction Temperature
(3)
+150°C
Soldering Information
(1)
(2)
(3)
4 kV
2.5 kV
Infrared or Convection (20 sec.)
235°C
Wave Soldering (10 sec.)
260°C
Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for
which the device is intended to be functional, but specific performance is not ensured. For specified specifications and test conditions,
see the Electrical Characteristics tables.
Human Body Model is 1.5 kΩ in series with 100 pF. Machine Model is 0Ω in series with 200 pF.
The maximum power dissipation is a function of TJ(MAX), θJA and TA. The maximum allowable power dissipation at any ambient
temperature is PD = (TJ(MAX) — TA)/ θJA. All numbers apply for packages soldered directly onto a PC board.
Operating Ratings (1)
Operating Temperature Range (2)
−40°C to 85°C
Digital Supply (VDD) (3)
2.25V to 3.6V
Digital Supply (VDD) @ Programming
Analog Reference (AVDD)
2.6V to 3.6V
(3)
4.5V to 18V
Package Thermal Resistance θJA (4)
(1)
(2)
(3)
(4)
2
52°C/W
Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for
which the device is intended to be functional, but specific performance is not ensured. For specified specifications and test conditions,
see the Electrical Characteristics tables.
Programming temperature range 0°C to 70°C .
When AVDD is in the voltage range of 4.5V to 13V, the supply voltage VDD can be in 2.25V to 3.6V range. When AVDD is in the voltage
range from 13V to 18V, the supply voltage VDD is limited to the 2.6V to 3.6V range
The maximum power dissipation is a function of TJ(MAX), θJA and TA. The maximum allowable power dissipation at any ambient
temperature is PD = (TJ(MAX) — TA)/ θJA. All numbers apply for packages soldered directly onto a PC board.
Submit Documentation Feedback
Copyright © 2005–2013, Texas Instruments Incorporated
Product Folder Links: LM8342
LM8342
www.ti.com
SNOSAM0B – NOVEMBER 2005 – REVISED MARCH 2013
Electrical Characteristics
Unless otherwise specified, all limits are specified for TJ = 25°C, VDD = 3V, AVDD = 15V, VOUT = 1/2 AVDD and RSET = 10 kΩ.
Boldface limits apply at the temperature extremes. (1)
Symbol
Parameter
Conditions
Min (2)
Typ (3)
Max (2)
Units
Supply and Reference Current
IDD
Supply Current
40
62
μA
AIDD
Analog Reference Current
8
13
μA
Control and Programming
Low Voltage
SCL, SDA
0.3 * VDD
High Voltage
0.7 * VDD
Input Current
Frequency
WPP/WPN Low Level
WPP/WPN High Level
RON
1
μA
400
kHz
0.3 * VDD
V
0.7 * VDD
VIH = 3.0V (4)
WPN Input Current
V
100
SCL to SCL-S Switch Resistance
SDA/SCL Input Capacitance
SCL-S Input Capacitance
Programming Time
See
µA
150
Ω
5
pF
3
pF
No Supply, VSDA,
VSCL = 3.6V
SDA/SCL/SCL-S load current
1
(5)
IDD @ Programming
Programming Cycles
1000
Reading Cycles
10000
V
μA
200
300
ms
10
18
mA
Output
Output Settling Time
95% of Final Value
Start-Up Time
VOUT
Adjustability
Zero Scale Error
AVDD = 10V,
VOUT = 5V
(2)
(3)
(4)
(5)
AVDD
V
Bits
−1
1
−1
1.5
LSB
Full Scale Error
−4
4
Full Scale Range
5
100
μA
−1
1
LSB
Voltage Drift VRSET
(1)
μs
7
Differential Non-Linearity
Output Current
μs
30
VRSET
+ 0.5V
Output Voltage
IOUT
10
Electrical Table values apply only for factory testing conditions at the temperature indicated. Factory testing conditions result in very
limited self-heating of the device such that TJ = TA. No assurance of parametric performance is indicated in the electrical tables under
conditions of internal self-heating where TJ > TA.
All limits are ensured by design or statistical analysis.
Typical values represent the parametric norm at the time of characterization.
On-Chip Pull Down Resistor of 30 kΩ.
Programming temperature range 0°C to 70°C .
Submit Documentation Feedback
Copyright © 2005–2013, Texas Instruments Incorporated
Product Folder Links: LM8342
3
LM8342
SNOSAM0B – NOVEMBER 2005 – REVISED MARCH 2013
www.ti.com
CONNECTION DIAGRAM
OUT
1
10
AVDD
2
9
SCL-S
WPN
3
8
SCL
WPP
4
7
SDA
GND
5
6
VDD
DAP
SET
Figure 1. 10-Pin SON
Top View
PIN DESCRIPTIONS
Pin Name
Pin #
Function
OUT
1
Current sink output, adjustable in 128 steps. See Application Section for details.
AVDD
2
Analog reference voltage input
WPN
3
Write protect (input)
READ (I2C)
WRITE→Reg
WPN = Low
yes
yes
no
open
WPN = High
yes
yes
yes
closed
WRITE→EE
WPP
4
Inverted WPN (output)
GND
5
Ground
VDD
6
Supply voltage
SDA
7
I2C compatible serial data input/output
SCL
8
I2C compatible serial clock input
SCL-S
9
Switched SCL connection. Serial clock input when WPN is set to high
SET
10
Maximum output current adjustment pin (see block diagram)
DAP
4
SCL Switch
Left floating or connect to GND
Submit Documentation Feedback
Copyright © 2005–2013, Texas Instruments Incorporated
Product Folder Links: LM8342
LM8342
www.ti.com
SNOSAM0B – NOVEMBER 2005 – REVISED MARCH 2013
Block Diagram
VDD
LM8342
AVDD
6
2
EE
MEMORY
19R
SDA
SCL
OUT
2
7
I C COMPATIBLE
INTERFACE CONTROL
1
8
7 BITS
WP
REF
INPUT
SCL-S
WPN
DAC
+
SET
9
R
3
4
5
WPP
GND
10
Submit Documentation Feedback
Copyright © 2005–2013, Texas Instruments Incorporated
Product Folder Links: LM8342
5
LM8342
SNOSAM0B – NOVEMBER 2005 – REVISED MARCH 2013
www.ti.com
Typical Performance Characteristics
At TJ = 25°C, VDD = 3V, AVDD = 15V, VOUT = 1/2 AVDD and RSET = 10 kΩ, unless otherwise specified.
IDD vs. VDD
IDD vs. Temperature
60
60
55
55
50
50
85°C
40
35
VDD = 3.0V
45
IDD (PA)
IDD (PA)
45
VDD = 3.6V
40
35
25°C
30
30
VDD = 2.25V
25
-40°C
20
2.2
2.4
2.6
25
2.8
3.0
3.2
3.4
20
-40
3.6
-15
VDD (V)
10
35
60
85
TEMPERATURE (°C)
Figure 2.
Figure 3.
AVDD Startup (Full Scale)
VDD Startup (Full Scale)
INTERMEDIATE STARTUP
CODE (MID SCALE)
RSET = 10 k:
VOLTAGE (1 V/DIV)
VOLTAGE (2V/DIV)
RL = 40 k:
AVDD
VOUT
VDD
VOUT
0V
RSET = 10 k:
0V
RL = 40 k:
TIME (20 Ps/DIV)
TIME (20 Ps/DIV)
Figure 4.
Figure 5.
IOUT vs. RSET
IOUT vs. RSET
10000
10000
VDD = 3.6V
100
1000
VDD = 3V
AVDD = 18V
IOUT (PA)
IOUT (PA)
1000
VDD = 2.25V
10
100
AVDD = 4.5V
AVDD = 10V
10
AVDD = 10V
VOUT = 5V
1
0.1
1
10
100
RSET (k:)
1
10
100
RSET (k:)
Figure 6.
6
1
0.1
Figure 7.
Submit Documentation Feedback
Copyright © 2005–2013, Texas Instruments Incorporated
Product Folder Links: LM8342
LM8342
www.ti.com
SNOSAM0B – NOVEMBER 2005 – REVISED MARCH 2013
Typical Performance Characteristics (continued)
At TJ = 25°C, VDD = 3V, AVDD = 15V, VOUT = 1/2 AVDD and RSET = 10 kΩ, unless otherwise specified.
IOUT Current Step Positive (Full Scale)
IOUT (25 PA/DIV)
IOUT (25 PA/DIV)
IOUT Current Step Negative (Full Scale)
TIME (10 Ps/DIV)
TIME (10 Ps/DIV)
Figure 8.
Figure 9.
IOUT vs. VOUT
IOUT Error vs. VOUT
20
1
FULL SCALE
18
0.8
16
IOUT ERROR (LSB)
0.6
IOUT (PA)
14
12
MID SCALE
10
8
6
0.4
0
-0.2
MID SCALE
-0.4
FULL SCALE
4
-0.6
ZERO SCALE
2
0
ZERO SCALE
0.2
-0.8
0
2
4
6
8
10 12
14
16
-1
18
1
2
3
4
7
8
9
10
Figure 11.
Gain & Offset Change vs. VOUT
Differential Non-Linearity Error vs. DAC
(VOUT = 18V)
0.2
4
0.1
3
OFFSET CHANGE
0
2
-0.1
1
-0.2
0
GAIN CHANGE
6
10
14
-1
18
0.20
DIFFERENTIAL NON-LINEARITY (LSB)
5
2
6
Figure 10.
0.3
-0.3
5
VOUT (V)
GAIN CHANGE (%)
OFFSET CHANGE (LSB)
VOUT (V)
VOUT = 18V
0.15
0.10
0.05
0.00
-0.05
-0.10
-0.15
-0.20
0
16
32
48
64
80
VOUT (V)
DAC SETTING
Figure 12.
Figure 13.
96
112 128
Submit Documentation Feedback
Copyright © 2005–2013, Texas Instruments Incorporated
Product Folder Links: LM8342
7
LM8342
SNOSAM0B – NOVEMBER 2005 – REVISED MARCH 2013
www.ti.com
Typical Performance Characteristics (continued)
At TJ = 25°C, VDD = 3V, AVDD = 15V, VOUT = 1/2 AVDD and RSET = 10 kΩ, unless otherwise specified.
IOUT Error vs. AVDD
0.2
0.015
0.15
0.01
FULL SCALE
IOUT ERROR (LSB)
IOUT ERROR (LSB)
IOUT Error vs. VDD
0.02
0.005
0
-0.005
MID SCALE
ZERO SCALE
0.1
FULL SCALE
0.05
-0.05
MID SCALE
-0.01
-0.1
-0.015
-0.15
-0.02
2.25
2.5
2.75
3
3.25
ZERO SCALE
0
-0.2
3.5
15
12.5
Figure 14.
Figure 15.
IOUT Error vs. Temperature
17.5
20
Total Unadjusted Error vs. DAC
TOTAL UNADJUSTED ERROR (LSB)
0.2
0.15
IOUT ERROR (LSB)
10
AVDD (V)
0.2
0.1
0.05
0
-0.05
-0.1
-0.15
-0.2
7.5
5
VDD (V)
0
10
20
30
40
50
60
70
0.15
0.1
0.05
0
-0.05
-0.1
-0.15
-0.2
80
16
0
32
48
64
80
96
112 128
DAC SETTING
TEMPERATURE (°C)
Figure 16.
Figure 17.
Integral Non-Linearity Error vs. DAC
INTEGRAL NON-LINEARITY (LSB)
0.2
0.15
0.1
0.05
0
-0.05
-0.1
-0.15
-0.2
0
16
32
48
64
80
96
112 128
DAC SETTING
Figure 18.
8
Submit Documentation Feedback
Copyright © 2005–2013, Texas Instruments Incorporated
Product Folder Links: LM8342
LM8342
www.ti.com
SNOSAM0B – NOVEMBER 2005 – REVISED MARCH 2013
Typical Performance Characteristics (continued)
At TJ = 25°C, VDD = 3V, AVDD = 15V, VOUT = 1/2 AVDD and RSET = 10 kΩ, unless otherwise specified.
RON vs. SCL-S Voltage
450
0.15
400
SCL VIA SERIES
RESISTOR 1.5 k:
CONNECTED TO VDD
350
0.1
300
0.05
RON (:)
DIFFERENTIAL NON-LINEARITY (LSB)
Differential Non-Linearity Error vs. DAC
0.2
0
-0.05
VDD = 2.25V
250
200
150
-0.1
VDD = 3.0V
100
VDD = 3.6V
-0.15
50
-0.2
0
16
32
48
64
80
96
112 128
DAC SETTING
0
0
0.4 0.8 1.2 1.6
2
2.4 2.8 3.2 3.6
SCL-S VOLTAGE (V)
Figure 19.
Figure 20.
Submit Documentation Feedback
Copyright © 2005–2013, Texas Instruments Incorporated
Product Folder Links: LM8342
9
LM8342
SNOSAM0B – NOVEMBER 2005 – REVISED MARCH 2013
www.ti.com
APPLICATION SECTION
INTRODUCTION
The LM8342 is an integrated combination of a digitally controlled current sink and a non-volatile register (7 bits
EEPROM). Programming the register can be done using the I2C compatible interface. The LM8342 replaces the
potentiometer adjustment, and thereby simplifies the VCOM calibration procedure. With the LM8342, the factory
operator can physically view the screen head-on when performing this step, easing manufacturing especially for
large TFT panel sizes.
The following sections discuss the principle of operation of a TFT-LCD and, subsequently give a description of
how to use the LM8342, including the I2C compatible interface and control inputs. After this, two typical LM8342
configurations are presented. Subsequently an evaluation system is introduced, including a μC-board
programming using the I2C compatible interface. At the end of this application section board layout
recommendations are given.
PRINCIPLE OF OPERATION OF A TFT-LCD
This section offers a brief overview of the principle of operation of TFT-LCD’s. It gives a detailed description of
how information is presented on the display. Further an explanation of how data is written to the screen pixels
and how the pixels are selected is included.
TRANSMITTED LIGHT
POLARIZER
GLASS
SUBSTRATE
LIQUID CRYSTAL
MATERIAL
GLASS
SUBSTRATE
TOP ITO
PLATE
BOTTOM ITO
PLATE
VPIXEL
± POLARITY
POLARIZER
LIGHT SOURCE
Figure 21. Individual LCD Pixel
Figure 21 shows a simplified illustration of an individual LCD pixel. The top and bottom plates of a pixel consist of
Indium-Tin Oxide (ITO), which is a transparent, electrically conductive material. ITO is at the inner surfaces of
two glass substrates that are the front and back glass panels of a TFT display. Sandwiched between two ITO
plates is an insulating material (liquid crystal). Liquid crystals alter the polarization of light, depending on how
much voltage (VPIXEL) is applied across the two plates. Polarizers are placed on the outer surfaces of the two
glass substrates. In combination with the liquid crystal, the polarizers create an electrically variable light filter that
modulates light transmitted from the back to the front of a display. A pixel’s bottom plate is at the backside of a
display where a light source is applied, and the top plate is at the front, facing the viewer. For most TFT displays,
a pixel transmits the greatest amount of light when VPIXEL ≤ ±0.5V, and it becomes less transparent as the
voltage increases with either positive or negative polarity.
10
Submit Documentation Feedback
Copyright © 2005–2013, Texas Instruments Incorporated
Product Folder Links: LM8342
LM8342
www.ti.com
SNOSAM0B – NOVEMBER 2005 – REVISED MARCH 2013
ROW DRIVERS
COLUMN DRIVERS
CSTRAY
CSTRAY
CSTRAY
VCOM
VCOM
VCOM
PIXEL
PIXEL
PIXEL
APPROX
TFT-LCD PANEL
VDD/2
VCOM BUFFER
Figure 22. TFT Display
Figure 22 shows a simplified diagram of a TFT display, showing how individual pixels are connected to the row,
column and VCOM driver. Each pixel is represented by a capacitor with an NMOS transistor connected to its top
plate. Pixels in a TFT panel are arranged in rows and columns. Row lines are connected to the NMOS gates,
and column lines to the NMOS sources. The back plate of every pixel is connected to a common voltage called
VCOM. The voltage applied to the top plates (i.e. Gamma Voltage) controls the pixel brightness. The column
drivers supply this gamma voltage via the column lines, and ‘write’ this voltage to the pixels one row at a time.
This is accomplished by having the row drivers selecting an individual row of pixels when the column drivers
write the gamma voltage levels. The row drivers sequentially apply a large positive pulse (typically 25V to 35V) to
each row line. This turns on the NMOS transistors connected to an individual row, allowing voltage from the
column lines to be written to the pixels.
VCOM
GAMMA CORRECTION CURVE
LM8342
CALIBRATOR
LM8207
VREF
18 GAMMA BUFFER
TIMING
CONTROL
MULTI
SOURCE
DC/DC
CONVERTER
& LDO
VCOM
BUFFER
COLUMN DRIVER
ROW
DRIVER
DISPLAY
Figure 23. TFT Panel Block Diagram
Figure 23 shows a block diagram of a TFT panel. The VCOM buffer supplies a common voltage (VCOM) to all the
pixels in a TFT panel. In general, VCOM is a DC voltage that is in the middle of the gamma voltage range. Screen
performance can be optimized by tuning the VCOM voltage in the calibration procedure. Using the LM8342, the
VCOM calibration procedure is simplified by elimination of the potentiometer adjustment task. This task is currently
performed at the factory using a trimmer adjustment tool and visual inspection, when using a stable reference
voltage and a potentiometer as a voltage divider to generate the VCOM voltage.
Submit Documentation Feedback
Copyright © 2005–2013, Texas Instruments Incorporated
Product Folder Links: LM8342
11
LM8342
SNOSAM0B – NOVEMBER 2005 – REVISED MARCH 2013
www.ti.com
PRINCIPLE OF OPERATION OF THE LM8342
The LM8342 is an integrated combination of a digitally controlled current sink and a non-volatile register (7 bits
EEPROM). Writing data can be done using the I2C compatible interface. Data can be written to a volatile register
and can also be stored in the non-volatile EEPROM. A simplified block diagram of the LM8342 is given in
Figure 24.
LM8342
AVDD
OUT
IOUT
2
I C COMPATIBLE BUS
CONTROLLER
MEMORY
DIGITAL/
ANALOG
CONVERTER
+
-
SET
RSET
Figure 24. Block Diagram of the LM8342
The maximum output current of the LM8342 can be defined using an external resistor RSET in combination with
an analog reference voltage AVDD. This maximum current can be calculated using Equation 1.
IOUT_MAX =
AVDD
1
x
RSET
20
(1)
The operating range for the output current is given in the Electrical Characteristics table. Variations of the voltage
reference AVDD or the external resistor RSET will affect this output current. Using a resistor with a low temperature
coefficient is recommended.
The relative value of IOUT with respect to the maximum current can be controlled digitally in 128 steps, using the
internal DAC. This results in an output current described by Equation 2.
IOUT = IOUT_MAX x
DAC10 + 1
128
(2)
Using the serial interface bus the operator can store the DAC value in the LM8342s 7-bits volatile register
temporarily, or permanent in the EEPROM. During a start-up sequence the LM8342 will copy the contents of the
EEPROM to the register setting the DC value.
CONTROLLING THE DEVICE
The LM8342s current sink can be programmed using a serial interface bus. Additional functions (e.g. storing data
in the EEPROM) can be controlled in combination with external inputs. Table 1 shows the pins of the LM8342
and gives a short functional description.
Table 1. Pin Descriptions
Pin name
Function
SDA & SCL
(Serial interface bus)
The LM8342 output current can be controlled using the serial I2C compatible interface. This 2Wire interface uses a clock and a data signal. New values can be written to the memory, or the
current value can be read back from the device. The I2C compatible interface is discussed in
more detail in the next chapter.
AVDD
Analog reference voltage for the DAC.
VDD
Supply voltage for both the analog and digital circuitry.
SET
An external resistor RSET connected to the SET pin determines the maximum output current, see
Equation 1.
OUT
The output of the programmable current sink.
12
Submit Documentation Feedback
Copyright © 2005–2013, Texas Instruments Incorporated
Product Folder Links: LM8342
LM8342
www.ti.com
SNOSAM0B – NOVEMBER 2005 – REVISED MARCH 2013
Table 1. Pin Descriptions (continued)
Pin name
Function
SCL-S
For in-circuit PCB testing, the LM8342 can use the additional Switched SCL signal (SCL-S) input
for applying the SCL clock signal.
WPN
“Write Protect Not” (Input) has 2 functions:
1. Prohibits programming the EEPROM, when low or left floating (Internal a pull-down resistor is
connected) When WPN is set to a low level, only the volatile register is accessible. If WPN is set
to a high level also the EEPROM is accessible. Actual writing to the EEPROM or the register is
done using the “P-bit” in the serial communication.
2. WPN switches the SCL-S clock line. When WPN is set to a high level SCL-S is connected to
SCL. The operator should turn off the original SCL clock.
WPP
Write Protect Signal (Output). This is the inverted WPN signal.
I2C SERIAL INTERFACE BUS
The LM8342 supports an I2C compatible communication protocol, which is a bidirectional bus oriented
communication protocol. Any device that sends data on the bus is defined as a transmitter and the receiving
device as a receiver. The I2C compatible communication protocol uses 2 wires: SDA (Serial Data Line) and SCL
(Serial Clock Line). For both lines an external pull-up resistor, connected to the supply voltage, is required. The
device controlling the bus is known as the master, and the device or devices being controlled are the slaves.
Each device has its own specific address. The address of the LM8342 is 9EHEX. The master initiates the
communication and provides the clock. The LM8342 always operates as a slave. A typical system using an I2C
compatible interface bus is given in Figure 25.
VDD
PULL-UP
RESISTORS
SDA
MASTER
SCL
LM8342
SLAVE A
SLAVE B
Figure 25. System Using an I2C compatible Bus
The LM8342 can be used in an I2C compatible system. All specifications of the LM8342, dealing with the
interface bus, are ensured by design. Except for the bus speed, which is specified in the Electrical
Characteristics table.
KEY ASPECT OF I2C COMPATIBLE COMMUNICATION
In this section a brief overview is presented, discussing the key aspect of I2C compatible communication.
Figure 26 shows the timing aspects of the I2C compatible serial interface.
START
SLAVE ADDRESS
1
R/W
0
0
1
1
1
1
0
0
1
1
1
1
A
DATA
A
D6
D5
D4
D3
D2
D1
D0
P
D6
D5
D4
D3
D2
D1
D0
P
STOP
SCL
1
SDA
R/ W
A
START
A
STOP
Figure 26. Timing Diagram
Submit Documentation Feedback
Copyright © 2005–2013, Texas Instruments Incorporated
Product Folder Links: LM8342
13
LM8342
SNOSAM0B – NOVEMBER 2005 – REVISED MARCH 2013
www.ti.com
The timing diagram shows the major aspect of the communication protocol and represents a typical data stream.
In case a master wants to setup a data transfer, it tests if “the bus is busy.” If it is not busy, then the master
starts the data transfer by creating a “start data transfer” situation. Accordingly the corresponding receiver is
selected by sending the appropriate “slave address.” This receiver gives an “acknowledge” on recognizing its
address on the bus. The master continues the data transfer by sending the data stream. Again the receiver gives
an “acknowledge” after receipt. Depending on the amount of data the master will continue or create a “stop data
transfer” situation. Table 2 gives a more detailed description of the I2C compatible communication.
Table 2. Detailed Description of I2C compatible Communication Definitions
Bus not busy
The I2C compatible bus is not busy when both data (SDA) and clock (SCL) lines remain
HIGH. The controller can initiate data transfer only when the bus is not busy.
Start Data Transfer
Starting from an idle state (bus not busy) a START condition consists of a HIGH to
LOW transition of SDA while SCL is HIGH. All commands must start with a START
condition.
Slave address
After generating a start condition, the master transmits a 7-bit slave address. (The
LM8342 uses the 8th bit for selecting the R/W operation, but this does not affect the
address.) The address for the LM8342 is 9EHEX.
R/W-bit
If the value of the R/W bit is HIGH, the data is read from the register of the LM8342.
Otherwise the current DAC setting is written to the LM8342.
Acknowledge
A receive device, when addressed, is obliged to generate an “acknowledge” after the
reception of each byte. The master generates an extra clock cycle that is associated
with this acknowledge bit. The receiver has to pull down the SDA line during the
acknowledge clock pulse so that the SDA line is stable LOW during the HIGH period of
SCL, with respect to the SCL timing specifications.
Data byte
A data byte consists of 8 bits. 7 bits are used for the DAC setting of the LM8342. The
8th bit is known as the P-bit.
P-bit
The function of the P-bit depends on the Read/Write operation (R/W-bit). During a Read
operation of the LM8342, the P-bit indicates the programming state of the EEPROM.
During a Write operation, the register or both the register and the EEPROM of the
LM8342 can be selected as destination. A more detailed description of the P-bit is given
in Table 3 .
Stop Data Transfer
A STOP condition consists of a LOW to HIGH transition of SDA while SCL is HIGH. All
operations must be ended with a STOP condition.
Table 3. P-bit Truth Table
Operation
P-bit
Description
Read
1
Programming Ready
Read
0
Programming Busy
(don’t turn off the device)
Write
1
Register Write
Write
0
EEPROM Write
The LM8342 can be used in I2C compatible systems with clock speeds of up to 400 kbps (Fast mode). For low
speed applications, an initial resistor value for the pull-up resistors is 15 kΩ is suitable. When increasing the
speed of the interface bus, the user should decrease the value of the pull-up resistors.
Typical Application
The following section discusses two typical applications for the LM8342. In the first application the LM8342 is
used as a programmable current sink, for example to drive a programmable bias generator. In the second
application the LM8342 is used to adjust the voltage level of a VCOM driver.
PROGRAMMABLE CURRENT SINK
As described in the “Principle of Operation of the LM8342” section the LM8342 basically operates as a
programmable current sink. Figure 27 shows a general current sink application.
14
Submit Documentation Feedback
Copyright © 2005–2013, Texas Instruments Incorporated
Product Folder Links: LM8342
LM8342
www.ti.com
SNOSAM0B – NOVEMBER 2005 – REVISED MARCH 2013
VDD
I C INTERFACE
15 k:
15 k:
15 k:
2
AVDD
OUT
SDA
7
1
IOUT
SCL
8
2
6
VDD
LM8342
SCL-S
9
CONTROLLER
WPN
3
SET
10
RSET
GND
WPP
4
5
Figure 27. Programmable Current Sink
The output current of the LM8342 can be calculated using Equation 3.
IOUT =
AVDD
20
x
1
DAC10 + 1
x
RSET
128
(3)
DRIVING A VCOM LEVEL
Another typical application, given in Figure 28, is using the LM8342 to adjust the “voltage tap” of a resistive
voltage divider. The VCOM driver buffers the “voltage tap” in this application.
VDD
I C INTERFACE
15 k:
15 k:
15 k:
7
8
2
AVDD
6
2
VDD
AVDD
R1
+
-
OUT
SDA
1
SCL
IOUT
VCOM
R2
LM8342
9
CONTROLLER
3
SCL-S
SET
WPN
10
RSET
WPP
4
GND
5
Figure 28. Typical Application Driving a VCOM Level
The voltage level of the VCOM driver, for a general setting of (DAC10) , is calculated using Equation 4.
§
§ R2
(DAC10 + 1) x R1
VCOM = AVDD x ¨
x ¨¨1 ¨ R1 + R2
128 x RSET x 20
©
©
§
¨
¨
©
(4)
§
¨
¨
©
For calibrating the VCOM level (see Figure 28) the tuning range of the design needs to be aligned to the required
VCOM tuning range (ΔVCOM). Figure 29 gives a graphical presentation of the desired voltage levels.
Submit Documentation Feedback
Copyright © 2005–2013, Texas Instruments Incorporated
Product Folder Links: LM8342
15
LM8342
SNOSAM0B – NOVEMBER 2005 – REVISED MARCH 2013
www.ti.com
AVDD
VCOM_HIGH
VMID
' VCOM
OPERATING VCOM RANGE
VCOM_LOW
GND
Figure 29. VCOM Voltage Levels
Assume the calibrator needs to cover the voltage range given in Equation 5.
' VCOM = VCOM_HIGH ± VCOM_LOW
(5)
The limits of VCOM for DAC10 = 0 (high limit) and DAC10 = 127 (low limit) are given by:
R2
R1
x §1 VCOM_HIGH = AVDD x §
R1
+
R2
128
x
RSET x 20
©
©
§
©
(6)
§
©
R2
R1
x §1 ©R1 + R2 © RSET x 20
§
©
VCOM_LOW = AVDD x §
(7)
§
©
Using Equation 5,Equation 6, and Equation 7 the value for resistors R1 and R2 can be obtained, resulting in
Equation 8 and Equation 9:
R1 =
40 x RSET x 'VCOM
AVDD + 'VCOM
(8)
and
R2 =
40 x RSET x 'VCOM
AVDD - 'VCOM
(9)
Table 4 gives an overview of resistor values for a typical value of AVDD, and 2 RSET values. All settings are for a
VCOM level at VMID = ½ AVDD, and a maximum variation of ΔVCOM.
1
1
VMID - 'VCOM VCOM VMID + 'VCOM
2
2
(10)
Table 4. Overview Resistor Values for Different RSET Settings at AVDD = 15V
AVDD = 15V (VCOM Level = 7.5 V)
RSET = 10 kΩ
ΔVCOM
(V)
16
RSET = 45 kΩ
R1
(Ω)
R2
(Ω)
ΔVCOM
(V)
R1
(Ω)
R2
(Ω)
±0.5
25k
28.6k
±0.5
113k
129k
±1
47.1k
61.5k
±1
212k
277k
±1.5
66.7k
100k
±1.5
300k
450k
±2
84.2k
146k
±2
379k
655k
Submit Documentation Feedback
Copyright © 2005–2013, Texas Instruments Incorporated
Product Folder Links: LM8342
LM8342
www.ti.com
SNOSAM0B – NOVEMBER 2005 – REVISED MARCH 2013
Table 4. Overview Resistor Values for Different RSET Settings at AVDD = 15V (continued)
±2.5
100k
200k
±2.5
450k
900k
±3
114k
267k
±3
514k
1.2M
EVALUATION SYSTEM
For the LM8342 a complete evaluation system is available, including two boards. Figure 30 gives a schematic
representation.
• LM8342 Evaluation BoardThis board demonstrates the functionality of the LM8342 using the I2C compatible
interface for communication. The LM8342 can easily be demonstrated in 2 applications:
– Programmable current sink
– Programmable VCOM level driver
• LM8342 Programmer BoardThis test board has dedicated functionality for communicating with the LM8342,
using the I2C compatible interface. This board can operate in two different modes:
– Write mode: The digitized value of a potentiometer setting is written to the LM8342. The user can select
on the programmer board to write the data to the register or to store the data in the EEPROM.
– Read mode: The board reads the stored values from the LM8342’s EEPROM and presents this data onto
a 3-digit display.
VDD
AVDD
2
BUFFERED
I C COMPATIBLE
BUS
VCOM
LM8342
EVALUATION
BOARD
IOUT
LM8342
PROGRAMMER
BOARD
WPN
WPP
Figure 30. LM8342 Evaluation System
LAYOUT RECOMMENDATIONS
A proper layout is necessary for optimum performance of the LM8342. A low impedance and proper ground
plane (free of disturbances) is recommended, since a current of up to 10 mA can flow with HF contents during
programming. The traces from the GND pin to the ground plane should be as short as possible. It is
recommended to place decoupling capacitors close to the VDD and AVDD pins. Connections of these decoupling
capacitors to the ground plane should be short.
As SET is a sensitive input, crosstalk to that pin should be prevented. Special care should be taken when routing
the interface connections. The signals on the serial interface can be more than 60 dB larger than the equivalent
LSB at the SET input pin. Crosstalk between the interface bus and RSET results in disturbance of the output
current IOUT of the LM8342.
For applications requiring a low output current (using high values for RSET in combination with low DAC settings)
special attention should be paid to the parasitic capacitance (CPAR) parallel to RSET. For CPAR larger than tens of
pF, a small (
工商网监
湘ICP备2023018690号
