LM8850
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SNVS647C – AUGUST 2010 – REVISED MAY 2013
LM8850 High-Performance, Step-Up DC-DC Converter for High-Power Applications in
Mobile Devices
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FEATURES
APPLICATIONS
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6µA typ. Quiescent Current
VOUT = 3.6V to 5.7V (max VO = 5.7V)
Operates from a Single Lithium Ion Cell (2.3V
to 5.5V)
8 User-selectable Output Voltages via I2C
High-speed 3.4 MHz I2C-compatible Interface
Up to 1.0A Maximum Load Current Capability
4 Levels of Current Limiting
Auto-mode Operation and Forced PWM
2.5 MHz Switching Drequency (typ.)
±2.5% DC Output Voltage Precision
1.0 µH Inductor (2520 Case Size)
4.7 µF Input and Output Capacitors (0603 case
size)
PGOOD Signal
True Shutdown Isolation
Output Over-voltage Protection
Internal Active Voltage Balancing for
Supercapacitors
DSBGA 9-bump Package
– (1.58 mm x 1.62 mm x 0.35 mm)(0.5 mm
pitch)
Flash LED
Mobile Phones
WiMAX
USB
Audio Amplifier
DESCRIPTION
LM8850 is a step-up DC-DC converter optimized for
use with a supercapacitor to protect a battery from
power surges and enable new high power
applications in mobile device architectures. The
device creates an ideal rail from 3.6V to 5.7V
boosting from a single Li-Ion cell with an input voltage
range of 2.3V to 5.5V; Target VOUT must be at least
10% higher than VIN.
An I2C interface controlling multiple output voltage
settings, input current limits, and load currents up to
1A provides superior user flexibility. The LM8850
operates in Auto mode, where the converter is in
PFM mode at light loads and switches to PWM mode
at heavy loads. Hysteretic PFM extends the battery
life by reduction of the quiescent current to 6µA (typ.)
during
light load and
standby
conditions.
Synchronous operation provides true shutdown
isolation and improves its efficiency at medium-to-full
load conditions.
Typical Application Circuit
3.6V
4.7 PF
VIN
1 PH
5V
VOUT
SW
LM8850
4.7 PF
PG
BAL
0.05F to 1.0F
SDA
SCLK
EN
GND
1
2
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
All trademarks are the property of their respective owners.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
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LM8850
SNVS647C – AUGUST 2010 – REVISED MAY 2013
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DESCRIPTION (CONTINUED)
High-switching frequency enables smaller passive components. Internal compensation is used for a broader
range of inductor and output capacitor values to meet system demand and achieve small system solution size.
LM8850 is available in a 9-bump ultra-thin DSBGA package. Only four external surface-mount components, a 1.0
µH inductor, a 4.7 µF for input capacitor, 4.7 µF for output capacitor and 0.05F-1.0F supercapacitor for energy
storage are required.
Connection Diagram
Figure 1. 9-Bump Ultra-Thin DSBGA Package
See Package Number YPD0009
PIN DESCRIPTIONS
Pin #
Name
Description
A1
VIN
Power Supply Input. Connect to input filter capacitor (See Typical Application
Circuit)
A2
SW
Switching node. Connection to the internal NFET switch and PFET synchronous
rectifier
A3
GND
Ground Pin
B1
SDA
I2C data (Use a 2kΩ pull-up resistor)
B2
PG
B3
VOUT
Power Good indicator
Output pin.
C1
SCLK
I2C Clock (Use a 2kΩ pull-up resistor)
C2
EN
Enable pin. The device is in shutdown when voltage to this pin is 1.2V. Do not leave this pin floating.
C3
BAL
Balancing pin for active voltage balancing of supercapacitor
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
2
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Absolute Maximum Ratings (1) (2)
−0.2V to 6.5V
VIN Pin to GND
−0.2V to 6.0V
EN, PG, SDA, SCLK pins to GND
VOUT to GND
(GND−0.2V) to
6.5V
−0.2V to 6.5V
SW pin to GND
−0.2V to VOUT
BAL to GND
Junction Temperature (TJ-MAX)
+150°C
Storage Temperature Range
−65°C to +150°C
Continuous Power Dissipation (3)
Internally Limited
Maximum Lead Temperature
(Soldering, 10 sec.)
ESD Rating (4)
(1)
(2)
(3)
(4)
260°C
Human Body Model
2kV
Machine Model
200V
Charged Device Model
500V
Absolute Maximum Ratings indicate limits beyond which damage to the component may occur. Operating Ratings are conditions under
which operation of the device is ensured. Operating Ratings do not imply ensured performance limits. For ensured performance limits
and associated test conditions, see the Electrical Characteristics tables.
If Military/Aerospace specified devices are required, please contact the Texas Instruments Sales Office/ Distributors for availability and
specifications.
Internal thermal shutdown circuitry protects the device from permanent damage. Thermal shutdown engages at TJ = 150°C (typ.) and
disengages at TJ = 140°C (typ.).
The Human Body Model is a 100 pF capacitor discharged through a 1.5 kΩ resistor into each pin. The machine model is a 200 pF
capacitor discharged directly into each pin. MIL-STD-883–3015.7.
Operating Ratings (1) (2)
Input Voltage Range
2.3V to 5.5V
Recommended Load Current
0mA to 1.0A
−40°C to +125°C
Junction Temperature (TJ) Range
Ambient Temperature (TA) Range (3)
(1)
(2)
(3)
−40°C to +85°C
Absolute Maximum Ratings indicate limits beyond which damage to the component may occur. Operating Ratings are conditions under
which operation of the device is ensured. Operating Ratings do not imply ensured performance limits. For ensured performance limits
and associated test conditions, see the Electrical Characteristics tables.
All voltages are with respect to the potential at the GND pin.
In applications where high power dissipation and/or poor package resistance is present, the maximum ambient temperature may have to
be derated. Maximum ambient temperature (TA-MAX) is dependent on the maximum operating junction temperature (TJ-MAX-OP = 125°C),
the maximum power dissipation of the device in the application (PD-MAX) and the junction-to-ambient thermal resistance of the
part/package (θJA) in the application, as given by the following equation: TA-MAX = TJ-MAX− (θJAx PD-MAX).
Thermal Properties
Junction-to-Ambient Thermal Resistance (θJA)
(DSBGA) (1)
(1)
70°C/W
Junction-to-ambient thermal resistance is highly application and board-layout dependent. In applications where high power dissipation
exists, special care must be given to thermal dissipation issues in board design.
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Electrical Characteristics (1) (2) (3) (4)
Limits in standard typeface are for TA = 25°C. Limits in boldface type apply over the operating junction temperature range
(−40°C ≤ TJ = TA ≤ +85°C). Unless otherwise noted, specifications apply to the LM8850 open loop Typical Application Circuit
with VIN = EN = 3.6V.
Symbol
Parameter
VOUT
Condition
Output Voltage
Min
IOUT = 0mA, VOUT = 5V
Output Voltage Range
Register 0
VOUT
Output Voltage Range
Register 1
Typ
-2.5
VSEL bits = 0 0 0
3.6
VSEL bits = 0 0 1
3.9
VSEL bits = 0 1 0
4.2
VSEL bits = 0 1 1
4.5
VSEL bits = 1 0 0
4.7
VSEL bits = 1 0 1
5.0
VSEL bits = 1 1 0
5.3
VSEL bits = 1 1 1
5.7
Max
Units
+2.5
%
V
ISHDN
Shutdown Supply Current
0.4
3
IQ_PFM
Quiescent Current in PFM
Mode
6
10
IQ_PWM
Quiescent Current in PWM
Mode
330
RDSON (NFET)
Pin-Pin Resistance for Sync VIN = VGS = 3.6V
NFET
200
RDSON (PFET)
Pin-Pin Resistance for
PFET
215
ILIM
VIN = VGS = 5.0V
Switch Peak Current Limit
TON
Turn on Time
µA
1350
1500
1650
ISEL bits = 101
VIN = 4.5V
923
1025
1128
ISEL bits = 011
VIN = 4.5V
666
740
814
ISEL bits = 001
VIN = 4.5V
477
530
583
TON = 00
5
TON = 01
7.5
TON = 10
10
TON = 11
12.5
Pin Input current
FOSC
Internal Oscillator
Frequency
2.25
VIH
Logic High Input
1.2
VIL
Logic Low Input
VOH
Logic Output High
VOL
Logic Input High
(3)
(4)
mΩ
ISEL bits = 111
VIN = 4.5V
IEN
(1)
(2)
500
EN
mA
secs.
0.01
1
2.5
2.75
0.4
1.2
µA
MHz
V
0.4
All voltages are with respect to the potential at the GND pin.
Min and Max limits are specified by design, test or statistical analysis. Typical numbers are not ensured, but do represent the most likely
norm.
The parameters in the electrical characteristic table are tested under open loop conditions at VIN = 3.6V unless otherwise specified. For
performance over the input voltage range and closed loop condition, refer to the datasheet curves.
Open-loop Electrical Characteristics taken without supercapacitor.
Table 1. Dissipation Rating Table
4
θJA
TA ≤ 25°C
Power Rating
TA ≤ 60°C
Power Rating
TA ≤ 85°C
Power Rating
70°C/W
1500 mW
980 mW
600 mW
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Block Diagram
SW
VOUT
VIN
Amp
BAL
SCL
PFM Generator
SDA
Control Logic
Error Amp
PG
VREF
EN
+
-
2.5 MHz
Oscillator
Ramp Generator
GND
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Typical Performance Characteristics
Unless otherwise noted: VOUT = 5.0V, TA = 25°C, Supercapacitor = TDK EDLC272020–501–2F-50).
Iq Shutdown
Iq, PFM, No Load
9.0
1,000
8.5
800
CURRENT ( A)
8.0
Iq(nA)
600
-40°C
25°C
85°C
400
200
7.5
-40°C
25°C
85°C
7.0
6.5
6.0
0
5.5
-200
2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5
5.0
2.0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
VIN (V)
VIN(V)
Figure 2.
Figure 3.
Iq, PWM
Efficiency, VOUT = 5V, PWM Mode, 25°C
420
400
CURRENT ( A)
380
360
340
320
-40°C
25°C
85°C
300
280
260
2.0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
VIN (V)
6
Figure 4.
Figure 5.
Efficiency Room temp, 100 mV PFM ripple
Efficiency over PFM ripple, VIN = 3.9V, Room Temp
Figure 6.
Figure 7.
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Typical Performance Characteristics (continued)
Unless otherwise noted: VOUT = 5.0V, TA = 25°C, Supercapacitor = TDK EDLC272020–501–2F-50).
Line Regulation, VOUT 5V
VIN = 3.6V, 100 mV Ripple, Auto Mode
Load Regulation, VOUT 5V,
VIN = 3.6V, 100 mV Ripple, Auto Mode
Figure 8.
Figure 9.
Line Regulation, VOUT 5V,
250 mA Load, 100 mV Ripple, Auto Mode
Osc Freq Error Normalized to 3.6V
Figure 10.
Figure 11.
Startup VIN 2.7V, VOUT 5.3V,
5sec Delay, Room Temp
Startup VIN 3.6V, VOUT 5.0V,
5sec Delay, Room Temp
2V/DIV
2V/DIV
VOUT
VOUT
INPUT
CURRENT
500 mA/
DIV
500 mA/
DIV
INPUT
CURRENT
5V/DIV
5V/DIV
PGOOD
PGOOD
1.0s/DIV
2.0s/DIV
Figure 12.
Figure 13.
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Typical Performance Characteristics (continued)
Unless otherwise noted: VOUT = 5.0V, TA = 25°C, Supercapacitor = TDK EDLC272020–501–2F-50).
Input Current and VOUT, 1.5A Current Limit
VOUT
2V/DIV
INPUT
CURRENT
500 mA/
DIV
Input Current and VOUT, 500 mA Current Limit
VOUT
2V/DIV
INPUT
CURRENT
500 mA/
DIV
200 ms/DIV
200 ms/DIV
Figure 14.
Figure 15.
Line Transient
VIN 2.7V - 3.6V, ILOAD = 600 mA
Line Transient
VIN 3.6V - 4.2V, ILOAD = 600 mA
50 mV/
DIV
VOUT
50 mV/
DIV
VOUT
500 mV/
DIV
VIN
500 mV/
DIV
VIN
100 Ps/DIV
100 Ps/DIV
Figure 16.
Figure 17.
Load Transient
VIN = 2.7V, VOUT 5.0V, ILOAD 0-1000 mA
Load Transient
VIN = 2.7V, VOUT 5.0V, ILOAD 1000-0 mA
VOUT
100 mV/
DIV
100 mV/
DIV
VOUT
1A/DIV
INPUT
CURRENT
INPUT
CURRENT
8
1A/DIV
10 Ps/DIV
10 Ps/DIV
Figure 18.
Figure 19.
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Typical Performance Characteristics (continued)
Unless otherwise noted: VOUT = 5.0V, TA = 25°C, Supercapacitor = TDK EDLC272020–501–2F-50).
Load Transient
VIN = 3.6V, VOUT 5.0V, ILOAD 200-800 mA
VOUT
Load Transient
VIN = 3.6V, VOUT 5.0V, ILOAD 800-200 mA
100 mV/
DIV
VOUT
500 mA/
DIV
INPUT
CURRENT
INPUT
CURRENT
100 mV/
DIV
500 mA/
DIV
4 Ps/DIV
4 Ps/DIV
Figure 20.
Figure 21.
Load Transient
VIN = 4.2V, VOUT 5.0V, ILOAD 0-200 mA
Load Transient
VIN = 4.2V, VOUT 5.0V, ILOAD200-0mA
50 mV/
DIV
VOUT
200 mA/
DIV
100 mV/
DIV
VOUT
INPUT
CURRENT
200 mA/
DIV
INPUT
CURRENT
10 Ps/DIV
10 Ps/DIV
Figure 22.
Figure 23.
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OPERATION DESCRIPTION
LM8850 FUNCTIONALITY
The LM8850, a high-efficiency, step-up DC-DC switching boost converter, delivers a constant voltage from a
stable DC input voltage source. Using a voltage mode architecture with synchronous rectification, the LM8850
has the ability to deliver up to 600 mA of load current, depending on the input voltage, output voltage, ambient
temperature, and the inductor chosen.
There are three modes of operation depending on the current required - PWM (Pulse Width Modulation), PFM
(Pulse Frequency Modulation), and shutdown. The device operates in PWM mode at load currents of
approximately 200 mA or higher. Lighter output current loads cause the device to automatically switch into PFM
for reduced current consumption (Iq = 6µA typ). Shutdown mode turns off the voltage regulation and offers the
lowest current consumption (ISHUTDOWN = 0.4 µA typ).
Once enabled, the LM8850 charges the supercapacitor utilizing all of the default settings in the registers. The I2C
must be used to change the default settings and this can only be done with the LM8850 enabled. Once a register
is written to, the changes will transition immediately. Every time the EN pin transitions from VIL to VIH, registers
0 and 1 are reset to their defaults settings and any settings need to be rewritten into the appropriate registers.
AUTO MODE
The LM8850 utilizes AUTO mode to reduce the amount of energy required to maintain the regulated output
voltage under light load conditions. The transition from Auto mode to PWM mode varies depending on input
voltage and output voltage. For an output voltage of 5.0V and an input voltage of 3.6V, the transition will occur
around 225 mA.
Auto mode can only be used with a supercapacitor. If no supercapacitor is being used in the circuit, Auto-Mode
must be disabled via I2C.
VRIPPLE
The ripple voltage used in Auto-Mode is programmable via I2C. The ripple voltage can be set to 50, 100, 200 and
250 mV. The larger the ripple voltage, the more constant energy will be supplied by the supercapacitor. The
regulator will remain asleep until the effective energy to reduce the supercapacitor’s voltage by the ripple value
has been used by the load.
POWER GOOD
The Power Good signal is both an output and a read only register bit. The Power Good signal will have a VOH
value if the VOUT is greater than 85% of its programmed value. This is a typical value for 5.0V and 3.6V VIN. The
typical value will vary based on input and output voltage.
PROGRAMMABLE VOUT
The output voltage of the LM8850 can be programmed via I2C to any of 8 different values: 3.6, 3.9, 4.2, 4.5, 4.7,
5.0, 5.3, and 5.7V. The only requirement is that the input voltage must remain 10% below the desired output
voltage for it to remain in regulation. The output voltage can be changed while the part is enabled and regulating.
The transition time will depend on load conditions.
TURN-ON TIME
The LM8850 has four programmable turn time values, 5, 7.5, 10, and 12.5 seconds. During the turn on time, the
LM8850 is ramping to the output voltage while limiting the inrush current which charges the supercapacitor.
BALANCING CIRCUIT
The LM8850 has an internal balancing circuit that helps maintain voltage balance between the two capacitors
within the super capacitor. The BAL pin regulates a voltage of VOUT/ 2 between the two capacitors. If one
capacitor is overcharged or less charged, the LM8850 will use the balancing circuit to correct this charge
inbalance. The balancing circuit can be turned off/on via the I2C registers (BALMODE – Control Reg01, bit 3).
The balancing circuit also has the ability to stay ON even after the LM8850 is shutting down (BAL – Control
Reg00, bit 4).
10
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I2C Interface
Control of LM8850 is done via I2C compatible interface. This includes switch over from AUTO to PWM mode,
adjustment of current limit, output voltage, PFM Hysteresis voltage, and start-up time. The I2C interface can also
switch the active voltage balance circuit ON during shutdown. Additionally, there is a flag bit that reads back
PGOOD condition.
I2C SIGNALS
In I2C-compatible mode, the SCL pin is used for the I2C clock and the SDA pin is used for the I2C data. Both
these signals need a pull-up resistor according to I2C specification. The values of the pull-up resistors are
determined by the capacitance of the bus. See I2C specification from Philips for further details. Signal timing
specifications are according to the I2C bus specification. Maximum frequency is 400 kHz or 3.4 MHz if in HighSpeed Mode.
I2C DATA VALIDITY
The data on SDA line must be stable during the HIGH period of the clock signal (SCL). In other words, state of
the data line can only be changed when CLK is LOW.
SCL
SDA
data
change
allowed
data
valid
data
change
allowed
data
valid
data
change
allowed
Figure 24. I2C Signals: Data Validity
I2C START AND STOP CONDITIONS
START and STOP bits classify the beginning and the end of the I2C session. START condition is defined as SDA
signal transitioning from HIGH to LOW while SCL line is HIGH. STOP condition is defined as the SDA
transitioning from LOW to HIGH while SCL is HIGH. The I2C master always generates START and STOP bits.
The I2C bus is considered to be busy after START condition and free after STOP condition. During data
transmission, I2C master can generate repeated START conditions. First START and repeated START
conditions are equivalent, function-wise.
SDA
SCL
S
P
START CONDITION
STOP CONDITION
Figure 25. START and STOP Conditions
TRANSFERRING DATA
Every byte put on the SDA line must be eight bits long, with the most significant bit (MSB) being transferred first.
Each byte of data has to be followed by an acknowledge bit. All clock pulses are generated by the master. The
transmitter releases the SDA line (HIGH) during the acknowledge clock pulse. The receiver must pull down the
SDA line during the ninth clock pulse, signifying an acknowledge. A receiver which has been addressed must
generate an acknowledge after each byte has been received.
After the START condition, the I2C master sends a chip address. This address is seven bits long followed by an
eighth bit which is a data direction bit (R/W). The LM8850 address is 0x60. the eighth bit, a “0” indicates a
WRITE and a “1” indicates a READ. The second byte selects the register to which the data will be written. The
third byte contains data to write to the selected register.
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Chip address: 60h
MSB
LSB
ADR6
Bit 7
ADR5
Bit 6
ADR4
Bit 5
ADR3
Bit 4
ADR2
Bit 3
R/W
Bit 0
ADR0
Bit 1
ADR1
Bit 2
2
I C Slave Address (chip address)
Figure 26. I2C Chip Address
ack from slave
ack from slave
ack from slave
start
MSB Chip Addr LSB
w
ack
MSB Register Addr LSB
ack
MSB
Data LSB
ack
stop
start
id = 0x60h
w
ack
addr = 02h
ack
address h¶0E data
ack
stop
SCL
SDA
Figure 27. I2C Write Cycle
•
•
•
•
•
w = write (SDA = “0”)
r = read (SDA = “1)
ack = acknowledge (SDA pulled down by either master or slave)
rs = repeated start
id = chip address
When a READ function is to be accomplished, a WRITE function must precede the READ function as shown in
the Read Cycle waveform.
ack from slave
start
MSB Chip Addr LSB
w
ack from slave
MSB Register Addr LSB
repeated start
ack from slave data from slave ack from master
rs
MSB Chip Address LSB
rs
address = 0x60h
r
MSB
Data
LSB
stop
SCL
SDA
start
id =0x60h
w ack
addr = h¶01
ack
r ack
0x6Ah data
ack
stop
Figure 28. I2C Read Cycle
HIGH-SPEED, 3.4 MHZ MODE
High-speed mode is entered by:
1. Start condition;
2. Chip Address: 0000 1XXXX (X = don't care);
3. Wait a clock for the acknowledge;
4. Now everything is in HS mode...do a repeated start (do NOT do a “stop” then a “start” because a “stop” kicks
the part out of HS mode);
5. Send read or writes in HS mode. (Remember to use “repeated starts” between commands.); then
6. When you are done with the last command send a “stop” condition to put the part back into regular 400 kHz
mode.
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I2C-COMPATIBLE CHIP ADDRESS
The device address for LM8850 is 60 (HEX).
Table 2. Register Information and Details
Location
Type
CONTROL
Register name
0
R/W
Control Register 1
CONTROL
1
R/W
Control Register 2
MSB
7
Register
LSB
6
5
4
3
2
1
0
Register location = 00
Output Voltage Change
0 0 0 = 3.6V
0 0 1 = 3.9V
0 1 0 = 4.2V
0 1 1 = 4.5V
1 0 0 = 4.7V
1 0 1 = 5.0V (default)
1 1 0 = 5.3V
1 1 1 = 5.7V
`
FromRegister Location
01, bit 5
From Register
Location 00, bits 0
and 1
PFM Voltage Ripple
0 0 = 50 mV
0 1 = 100 mV (default)
1 0 = 200 mV
1 1 = 250 mV
Balance Circuit
0 = OFF
1 = ON (default)
Effective when part is enabled
Mode
0 = AUTO (PFM/PWM ± default)
1 = FORCED PWM
Ton Time
0 0 = 5s (default)
0 1 = 7.5s
1 0 = 10s
1 1 = 12.5s
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MS B
7
LS B
6
5
4
3
2
1
0
Register location = 01
Switch Current Limit ± (Max values)
111 = 1500 mA (default)
101 = 1025 mA
001 = 740 mA
000 = 530 mA
Balmode
0 = OFF (default)
1 = ON
Effective when part is disabled
Enable
0 = OFF
1 = ON (default)
Bit 5 used to determine output voltage
0 0 0 = 3.6V
0 0 1 = 3.9V
0 1 0 = 4.2V
0 1 1 = 4.5V
1 0 0 = 4.7V
1 0 1 = 5.0V (default)
1 1 0 = 5.3V
1 1 1 = 5.7V
From Register
Location 01, bit 5
From Register
Location 00,
bits 0 and 1
PGOOD (Read only)
14
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Copyright © 2010–2013, Texas Instruments Incorporated
Product Folder Links: LM8850
LM8850
www.ti.com
SNVS647C – AUGUST 2010 – REVISED MAY 2013
REVISION HISTORY
Changes from Revision B (May 2013) to Revision C
•
Page
Changed layout of National Data Sheet to TI format .......................................................................................................... 13
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Copyright © 2010–2013, Texas Instruments Incorporated
Product Folder Links: LM8850
15
PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
(4/5)
(6)
LM8850URE/NOPB
ACTIVE
DSBGA
YPD
9
250
RoHS & Green
SNAGCU
Level-1-260C-UNLIM
-40 to 125
SK
LM8850URX/NOPB
ACTIVE
DSBGA
YPD
9
3000
RoHS & Green
SNAGCU
Level-1-260C-UNLIM
-40 to 125
SK
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of
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