LM96530
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SNAS499F – AUGUST 2010 – REVISED MAY 2013
LM96530 Ultrasound Transmit/Receive Switch
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FEATURES
DESCRIPTION
•
The LM96530 is an eight-channel monolithic highvoltage, high-speed T/R (Transmit/Receive) switch for
multi-channel medical ultrasound applications. It is
well-suited for use with Texas Instrument’s LM965XX
series chipset which offers a complete medical
ultrasound solution targeted towards low-power,
portable systems.
1
2
•
•
•
•
•
•
•
•
•
8-Channel High-Voltage Receive Side Switches
without Charge-Injection
Can be Used for Receive Protection and/or
Receive Multiplexing with SPI™ Compatible
Bus Control
Channel Bandwidth Supports 1MHz to 20MHz
Transducers
Input Accepts Pulses and Continuous-Wave
Signals within ±60V
Integrated Output Clamping Diodes Limit
Output to ±0.7V
Low Harmonic Distortion HD2 at -75dBc at
5MHz
Continuous-Wave Operation
Soft-Switcher Based on a Diode Bridge
Architecture Yielding Better Noise
Performance and Faster Turn-On and -Off
Times than Competing T-Gate Switch
Architectures
2.5V to 3.3V CMOS SPI™ Compatible Logic
Interface with Daisy Chain Capability
Bias Current Source (IS) can be Scaled
between 0 and 8mA via an External Resistor
The LM96530 contains eight high-voltage T/R
switches with integrated clamping diodes. This chip
protects the inputs of the receive channel's LNA (Low
Noise Amplifier) from the high-voltage pulses of the
transmit channel. Advanced features include a diode
bridge with internal current sources that are
programmable via an external resistor. Low-power
operation is enabled via per-channel-selectable
switching.
Texas Instruments also offers a development
package for sale which includes a driver hardware
and software package with a graphical user interface
for configuration and monitoring.
APPLICATIONS
•
Ultrasound Imaging
Table 1. Key Specifications
VALUE
UNIT
Input voltage
±60
V
Output voltage clamp ( IS= 1mA)
±0.7
V
On-resistance
18
Ω
Off-isolation at 5MHz
-58
dB
Noise spectral density at 5MHz
0.5
nV/√Hz
HD2
-75
dB
HD3
-75
dB
-73
dB
0 to +70
°C
Harmonic distortion
Channel crosstalk at 5MHz
Operating Temp.
1
2
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
All trademarks are the property of their respective owners.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
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LM96530
SNAS499F – AUGUST 2010 – REVISED MAY 2013
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Block Diagram
VLL
VDD
SPI_EN
SDI
SCSI
P0
P1
P2
Pn
P3
P4
P5
P6
P7
SCSO
SCLKI
VPP
SCLKO
Pin
SDO
OUTn
VOUT
INn
.
High-voltage
pulser
Nin
RT
SW_OFF
VNN
BG
RREF
RREF
AGND
VSS
VSUB
HVGND
Figure 1.
Typical Application
Figure 2. 8-Channel Transmit/Receive Chipset
2
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SPI_EN
SW_OFF
SCSI
SCLKI
SDI
HVGND
VLL
SDO
SCLKO
SCSO
VDD
VDD
VSS
VSS
AGND
Pin Diagram
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
IN0
1
45
OUT0
HVGND
2
44
AGND
IN1
3
43
OUT1
HVGND
4
42
AGND
IN2
5
41
OUT2
HVGND
6
40
AGND
IN3
7
39
OUT3
HVGND
8
38
AGND
IN4
9
37
OUT4
HVGND
10
36
AGND
IN5
11
35
OUT5
HVGND
12
34
AGND
IN6
13
33
OUT6
HVGND
14
32
AGND
IN7
15
31
OUT7
0: VSUB
23
24
25
26
27
28
29
30
VDD
VDD
VSS
VSS
AGND
AGND
22
RREF
AGND
21
AGND
VSUB
20
AGND
19
AGND
18
AGND
17
AGND
16
HVGND
LM96530
WQFN
Figure 3. WQFN Package
See Package Number NKA0060A
PIN DESCRIPTIONS
Pin No.
Name
Type
1, 3, 5, 7, 9, 11, 13,
15
INn
n=0,...,7
Input
High-voltage input
45, 43, 41, 39, 37,
35, 33, 31
OUTn
n=0,...
Output
Low-voltage output
External resistor to AGND. Used to set internal current sources.
RREF = 6.25 kΩ → IS = 8mA;
RREF = 12.5 kΩ → IS = 4mA;
RREF = 25 kΩ → IS = 2mA;
RREF = 50 kΩ → IS = 1mA
25
RREF
Output
59
SW_OFF
Input
Function and Connection
1 = Switch all channels OFF
0 = Use SPI™ to control switch
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PIN DESCRIPTIONS (continued)
Pin No.
60
Name
Type
SPI_EN
58
Input
SCSI
Function and Connection
1 = Enable the SPI™ Interface
0 = Disable the SPI™ Interface and presets SPI™ registers for all switches
ON.
Input
SPI™ chip select input,
0 = Chip Select
57
SCKI
Input
SPI™ compatible clock input
56
SDI
Input
SPI™ compatible data input
53
SDO
Output
SPI™ compatible data buffered output
52
SCKO
Output
SPI™ compatible clock buffered output
51
SCSO
Output
SPI™ chip select buffered output
26, 27, 49, 50
VDD
Power
Positive analog supply voltage (+5V)
28, 29, 47, 48
VSS
Power
Negative analog supply voltage (-5V)
54
VLL
Power
Logic voltage supply (+2.5 to 3.3V)
VSUB
Power
Negative high voltage supply (-65V)
HVGND
Ground
High voltage reference potential (0V)
AGND
Ground
Analog and logic low voltage reference input, logic ground (0V)
0, 17
2, 4, 6, 8, 10, 12, 14,
16, 55
All others
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
Absolute Maximum Ratings
(1) (2)
Maximum Junction Temperature (TJMAX)
+150°C
−40°C to +125°C
Storage Temperature Range
Supply Voltage (VDD)
+0.3V to +5.5V
+0.3V and −5.5V
Supply Voltage (VSS)
−70V (Must always be most negative voltage)
Supply Voltage (VSUB)
−0.3V to +3.6V
IO Supply Voltage (VLL)
−70V to 70V
Voltage at High Voltage Analog Inputs
−0.3V to VLL+0.3v
Voltage at Logic Inputs (SCLKI, SDI SCSI, SW_OFF)
(1)
(2)
Absolute Maximum Ratings are limits beyond which damage to the device may occur. Operating Ratings are conditions under which
operation of the device is specified to be functional, but do not ensure specific performance limits. For ensured specifications and test
conditions, see the Electrical Characteristics.
If Military/Aerospace specified devices are required, please contact the Texas Instruments Sales Office/ Distributors for availability and
specifications.
Operating Ratings
Operation Junction Temperature
0°C to + 70°C
VDD, −VSS, Analog Supply
+4.7V to 5.3V
VLL, Logic Supply
+2.4V to 3.5V
−60V to +60V, VSUB must be most negative supply
High Voltage Analog Inputs
−50V to −65V
VSUB, Substrate bias supply
Package Thermal Resistance (θJA)
ESD Tolerance
(1)
4
20°C/W
Human Body Model (1)
2kV
Machine Model
150V
Charge Device Model
750V
The human body model is a 100pF capacitor discharged through a 1.5kΩ resistor into each pin.
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Analog Characteristics
Unless otherwise stated, the following conditions apply.
VLL = +2.5V, VDD = −VSS = 5V, VSUB = −60V, RREF = 50 kΩ, RT = 50Ω, fIN = 5 MHz, SW_OFF = SPI_EN = 0V, TA =
25°C. (1)
Parameter
Test Conditions
Min
-60
Typ
Max
Units
+60
V
VIN
High Voltage Analog Inputs
VSUB must be most negative voltage.
See (2)
en
Voltage Noise
at 5MHz
0.8
nV/√Hz
BW
-3dB Bandwidth
150
MHz
HD2
Second harmonic distortion
-60
dBc
HD3
Third harmonic distortion
-65
dBc
XTALK
Channel crosstalk
-69
dB
TON
Turn-on time
2
µs
TOFF
Turn-off time
0.2
µs
Iso_off
Off isolation
-55
dB
RON
On resistance of TR switch
IL
Insertion Loss
VCLAMP
Output clamped voltage
±0.7
IMISMATCH
Current source mis-match
0.03
0.2
mA
14
20
mA
0.1VPP 5MHz tone applied as input
0.1Vpp 5MHz tone is applied as input
fIN = 5MHz
VDD, VSS
VLL
Power Supply Current
VSUB
(1)
(2)
125
Ω
-5.5
dB
V
5
µA
0.45
mA
Min and Max limits are 100% production tested at 25°C. Limits over the operating temperature range are specified through correlation
using Statistical Quality Control (SQC) methods. Limits are used to calculate Average Outgoing Quality Level (AOQL).
Total input signal levels, including any transient voltage overshoots, must be within this maximum voltage range.
Unless otherwise stated, the following conditions apply
VLL = +2.5V, VDD = −VSS = 5V, VSUB = −60V, RREF = 25 kΩ, RT = 50Ω, fIN = 5MHz, SW_OFF = SPI_EN = 0V, TA =
25°C. (1)
Parameter
Test Conditions
Min
-60
Typ
Max
Units
+60
V
VIN
High Voltage Analog Inputs
VSUB must be most negative voltage.
See (2)
en
Voltage Noise
at 5MHz
0.7
nV/√Hz
BW
-3dB Bandwidth
150
MHz
HD2
Second harmonic distortion
-67
dBc
HD3
Third harmonic distortion
-70
dBc
XTALK
Channel crosstalk
-73
dB
TON
Turn-on time
2
µs
TOFF
Turn-off time
Iso_off
Off isolation
RON
On resistance of TR switch
IL
Insertion Loss
VCLAMP
Output clamped voltage
IMISMATCH
Current source mis-match
0.1VPP 5MHz tone applied as input
0.1Vpp 5MHz tone is applied as input
fIN = 5MHz
Power Supply Current
VSUB
(1)
(2)
µs
dB
48
Ω
-4
dB
±0.75
VDD, VSS
VLL
0.2
-58
V
0.1
0.35
mA
23
30
mA
5
µA
1
mA
Min and Max limits are 100% production tested at 25°C. Limits over the operating temperature range are specified through correlation
using Statistical Quality Control (SQC) methods. Limits are used to calculate Average Outgoing Quality Level (AOQL).
Total input signal levels, including any transient voltage overshoots, must be within this maximum voltage range.
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Unless otherwise stated, the following conditions apply
VLL = +2.5V, VDD = −VSS = 5V, VSUB = −60V, RREF = 12.5 kΩ, RT = 50Ω, fIN = 5MHz, SW_OFF = SPI_EN = 0V, TA =
25°C. (1)
Parameter
Test Conditions
Min
-60
Typ
Max
Units
+60
V
VIN
High Voltage Analog Inputs
VSUB must be most negative voltage.
See (2)
en
Voltage Noise
at 5MHz
BW
-3dB Bandwidth
HD2
Second harmonic distortion
HD3
Third harmonic distortion
XTALK
Channel crosstalk
TON
Turn-on time
TOFF
Turn-off time
Iso_off
Off isolation
RON
On resistance of TR switch
IL
Insertion Loss
VCLAMP
Output clamped voltage
±0.78
IMISMATCH
Current source mis-match
0.25
0.6
mA
40
49
mA
0.1VPP 5MHz tone applied as input
0.1Vpp 5MHz tone is applied as input
fIN = 5MHz
VDD, VSS
VLL
Power Supply Current
VSUB
(1)
(2)
0.55
nV/√Hz
180
MHz
-73
dBc
-75
dBc
-73
dB
2
µs
0.2
µs
-58
dB
27
Ω
-3
dB
V
5
µA
2.2
mA
Min and Max limits are 100% production tested at 25°C. Limits over the operating temperature range are specified through correlation
using Statistical Quality Control (SQC) methods. Limits are used to calculate Average Outgoing Quality Level (AOQL).
Total input signal levels, including any transient voltage overshoots, must be within this maximum voltage range.
Unless otherwise stated, the following conditions apply
VLL = +2.5V, VDD = −VSS = 5V, VSUB = −60V, RREF = 6.25 kΩ, RT = 50Ω, fIN = 5MHz, SW_OFF = SPI_EN = 0V, TA =
25°C. (1)
Parameter
Test Conditions
Min
-60
Typ
Max
Units
+60
V
VIN
High Voltage Analog Inputs
VSUB must be most negative voltage.
See (2)
en
Voltage Noise
at 5MHz
BW
-3dB Bandwidth
HD2
Second harmonic distortion
HD3
Third harmonic distortion
XTALK
Channel crosstalk
TON
TOFF
Iso_off
Off isolation
RON
On resistance of TR switch
IL
Insertion Loss
VCLAMP
Output clamped voltage
±0.8
IMISMATCH
Current source mis-match
0.6
1.2
mA
75
86
mA
0.5
nV/√Hz
180
MHz
-75
dBc
-75
dBc
-73
dB
Turn-on time
2
µs
Turn-off time
0.2
µs
0.1Vpp 5MHz tone is applied as input
-58
dB
18
Ω
fIN = 5MHz
-2.5
dB
0.1VPP 5MHz tone applied to input
VDD, VSS
VLL
Power Supply Current
VSUB
(1)
(2)
6
V
5
µA
5
mA
Min and Max limits are 100% production tested at 25°C. Limits over the operating temperature range are specified through correlation
using Statistical Quality Control (SQC) methods. Limits are used to calculate Average Outgoing Quality Level (AOQL).
Total input signal levels, including any transient voltage overshoots, must be within this maximum voltage range.
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Digital Characteristics
Unless otherwise stated, the following conditions apply.
VLL = +2.5V, VDD = −VSS = 5V, VSUB = −60V, RREF = 50 kΩ, RT = 50Ω, SW_OFF = 0V, SPI_EN = 2.5V, TA = 25°C. (1)
Parameter
Test Conditions
Min
Typ
Max
Unit
VIH
Logical Input “HI” Voltage
VIL
Logical Input “LO” Voltage
IIN-H/L
Logic Input Current
-1
VOH
Logical Output “HI” Voltage
2.2
VOL
Logical Output “LO” Voltage
tSSELS
SPI™ SCSI Setup Time
11
tSSELH
SPI™ SCSI Hold Time
11
tSSELHI
SPI™ SCSI HI Time
tWS
SPI™ SDI Setup Time
11
ns
tWH
SPI™ SDI Hold Time
11
ns
tOD
SPI™ SCLKI to SDO
Propagation Delay
tVALID
SPI™ SCSI to T/R Switch
State Change Delay
tSCLK
SPI™ SCLKI Period
SPI™ SCLKI Duty Cycle
2
V
0.2
0.5
V
+1
µA
V
0.3
ns
ns
250
CL = 5 pF
ns
25
ns
100
See
(2)
ns
45
55
SPI™ SCLKI-HI to SCLKOHI Propagation Delay
12
tSCLKOD-L
SPI™ SCLKI-LO to SCLKOLO Propagation Delay
12
tSCSOD-H
SPI™ SCSI-HI to SCSO-HI
Propagation Delay
12
tSCSOD-L
SPI™ SCLSI-LO to SCLSOLO Propagation Delay
12
(1)
(2)
ns
30
tSCLKOD-H
Maximum Number of DaisyChained devices
V
SCLKI Freq. = 10MHz
% of CLK
Period
ns
ns
ns
ns
16
Min and Max limits are 100% production tested at 25°C. Limits over the operating temperature range are specified through correlation
using Statistical Quality Control (SQC) methods. Limits are used to calculate Average Outgoing Quality Level (AOQL).
Specified by design.
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SPI™ Timing
TO T/R SWITCH
Update
SCSI
UPDATED SPI DATA REGISTER
SHIFT REGISTER
SDI
SDO
P0 P1 P2 P3 P4 P5 P6 P7
UPDATED SPI DATA REGISTER
SPI_EN
tSPI_EN
tVALID
/SCSI
tSSELHI
tSCLKI
tWH
tSCLKIL
tSSELS
tSCLKIF
tSCLKIR
tWS
tSSELH
tSCLKIH
90%
10%
90%
10%
SCLKI
SDI
Din4
Din7
Din3
Din0
tSCSOD-H
/SCSO
tSCLKOD-H
tSCLKOD-L
tSCSOD-L
SCLKO
tOD
tOD
SDO
Dout7
Dout4
Dout3
Dout0
Figure 4. SPI™ Timing Diagram
8
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Typical Performance Characteristics
VLL = +2.5V, VDD = −VSS = 5V, VSUB = −60V, RREF = 50 kΩ, RT = 50Ω, fIN = 5 MHz, TA = 25°C.
Input Referred Noise
vs
Rref
2nd Harmonic Distortion
vs
Rref
-55
0.80
-60
HD2 (dBc)
en(nV/¥+])
0.75
0.70
0.65
0.60
0.56
-65
-70
-75
0.50
-80
0.45
0
10
20
30
RREF(K )
40
50
0
Figure 6.
Crosstalk
vs
frequency
Isolation
vs
Frequency
40
50
-20
-30
I solation (dBc)
-40
X talk (dBc)
20
30
RREF(K )
Figure 5.
-30
-50
-60
-70
-40
-50
-60
-70
-80
1M
10
-80
10M
F requency (Hz)
100M
1M
10M
F requency (Hz)
Figure 7.
Figure 8.
Turn On Respone
Turn Off Response
Figure 9.
Figure 10.
100M
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FUNCTIONAL DESCRIPTION
The LM96530 RX switch provides an 8-channel receive side interface solution for medical ultrasound
applications suitable for integration into multi-channel (128 / 256 channel) systems. Its diode-bridge-based
architecture allows high-speed low-distortion channel designs targeting low-power, portable systems. A complete
system can be designed using Texas Instruments’ companion LM965XX chipset.
VLL
VDD
SPI_EN
SDI
SCSI
P0
P1
P2
Pn
P3
P4
P5
P6
P7
SCSO
SCLKI
VPP
SCLKO
Pin
SDO
OUTn
VOUT
INn
.
High-voltage
pulser
Nin
RT
SW_OFF
VNN
BG
RREF
RREF
AGND
VSUB
VSS
HVGND
Figure 11. Block Diagram of T/R Channel
A functional block diagram of the IC is shown in Figure 11. Each RX switch channel on the IC has a high-voltage
input that can be directly connected to a transducer driven by a high-voltage pulser, such as the LM96550. The
input feeds into a diode bridge with its output being diode-clamped to ± 0.7V. The diode bridge bias current is set
to 1 mA with Rref = 50KΩ. Therefore, the output can be directly connected to a low noise amplifier (LNA) stage
which must be protected from the high-voltage signals on the transducer.
The bias current of the bridge is determined by two equally-sized current sources with their current value ranging
between 0 and 8mA depending on the external resistor Rref at the input of the bandgap reference block. While
the bias current is the same value for all channels on the IC, each channel can be switched on and off
individually with an 8–bit shift register that is programmed via a SPI™ compatible bus.
The on-chip analog circuitry requires dual 5V supplies VDD and VSS, a single logic supply VLL, and a high
voltage negative bias, VSUB.
SERIAL INTERFACE OPERATION
The digital interface is comprised of an 8-bit shift register and a latch. Each bit controls one T/R switch channel,
where the MSB bit, i.e., the first bit written (D7) controls channel 7, and the LSB bit (D0) controls channel 0. The
three input pins, SDI, SCSI and SCKl, are all Schmitt Trigger inputs with 0.5V typical hysteresis. The output pins
SDO, SCSO, and SCLKO are SPI™ compatible. The serial data input SDI is synchronously read into the shift
register on the rising edge of the clock SCKI. When SCSI changes from low to high, the data in the shift register
is transferred to the latch circuit, and output on the parallel data signals P0 through P7 which drive the switched
bias current sources for channels n=0,…, 7, respectively. When SCSI changes from high to low, the latch output
Pn, and thus the biasing condition, does not change.
10
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DAISY CHAINING MULTIPLE LM96530 ICs
For connecting multiple T/R switch ICs, the LM965XX SPI™-compatible bus can be daisy-chained up to 16 ICs
at 10MHz SCLKI for easy PCB routing. The inputs SDI, SCSI and SCLKI are daisy-chained together with SDO,
SCSO and SCLKO. Therefore, the next IC’s SDI is connected to the previous IC’s SDO. Similarly, the next IC’s
SCSI is connected to the previous IC’s SCSO, and the next IC’s SCLKI is connected to the previous IC’s
SCLKO, as shown in Figure 12. Daisy-chaining multiple LM96530 devices amounts to one large shift register
with the number of bits being equal to 8 times the number of LM96530 ICs. For example, if 3 LM96530 ICs are
daisy-chained, one can picture a 24–bit shift register. Thus, the MSB or first bit written on the SDI line (D23) will
control channel 7 of the last LM96530, i.e., the IC that is daisy-chained the farthest away from the SPI master.
The LSB or last bit written on the SDI line (D0) will control channel 0 of the first LM96530, i.e., the IC that is
closest to the SPI master. It is important to note that If only one particular channel of an IC in the daisy-chain
requires updating, all of the ICs, i.e., the entire shift register, must be written to.
P0
P7
LM96530-1
P0
P7
LM96530-2
P0
«
LM96530-3
SCSO
SCLKO
SDO
SDI
SCSI
P7
SCLKI
«.
«.
«.
SCSO
SDO
P0
SCLKO
SDI
SCSI
SCLKI
SCLKO
SCSO
SDO
SCLKI
SDI
SCSI
SCLKO
SCSO
SDO
SDI
SCLKI
SCSI
SPI
MASTER
P7
LM96530-16
Figure 12. 16 LM96530 Devices Daisy Chained at SCLKI = 16MHz
BASIC OPERATION WITHOUT SERIAL INTERFACE COMMUNICATION
To disable the SPI™ compatible interface, connect the pin SPI_EN to AGND. To reverse bias all 8 channels of
the T/R switch, connect the pin, SW_OFF to VLL. To forward bias all 8 channels of the T/R switch, connect the
pin, SW_OFF to AGND.
POWER-UP AND POWER-DOWN SEQUENCES
VSUB needs to always be the most negative supply – equal to or more negative than VSS or the most negative
transmit pulse at all times. The power sequence should be to applied to VSUB first, followed by the
remaining supplies in any order.
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Copyright © 2010–2013, Texas Instruments Incorporated
Product Folder Links: LM96530
11
LM96530
SNAS499F – AUGUST 2010 – REVISED MAY 2013
www.ti.com
REVISION HISTORY
Changes from Revision E (May 2013) to Revision F
•
12
Page
Changed layout of National Data Sheet to TI format .......................................................................................................... 11
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Copyright © 2010–2013, Texas Instruments Incorporated
Product Folder Links: LM96530
PACKAGE OPTION ADDENDUM
www.ti.com
9-Nov-2016
PACKAGING INFORMATION
Orderable Device
Status
(1)
LM96530SQ/NOPB
LIFEBUY
Package Type Package Pins Package
Drawing
Qty
WQFN
NKA
60
1000
Eco Plan
Lead/Ball Finish
MSL Peak Temp
(2)
(6)
(3)
Green (RoHS
& no Sb/Br)
CU SN
Level-2-260C-1 YEAR
Op Temp (°C)
Device Marking
(4/5)
0 to 70
LM96530SQ
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
Samples
PACKAGE OPTION ADDENDUM
www.ti.com
9-Nov-2016
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
8-May-2013
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
LM96530SQ/NOPB
Package Package Pins
Type Drawing
WQFN
NKA
60
SPQ
Reel
Reel
A0
Diameter Width (mm)
(mm) W1 (mm)
1000
330.0
16.4
Pack Materials-Page 1
9.3
B0
(mm)
K0
(mm)
P1
(mm)
W
Pin1
(mm) Quadrant
9.3
1.3
12.0
16.0
Q1
PACKAGE MATERIALS INFORMATION
www.ti.com
8-May-2013
*All dimensions are nominal
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
LM96530SQ/NOPB
WQFN
NKA
60
1000
367.0
367.0
38.0
Pack Materials-Page 2
MECHANICAL DATA
NKA0060A
SQA60A (Rev A)
www.ti.com
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