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LM96551SQX/NOPB

LM96551SQX/NOPB

  • 厂商:

    BURR-BROWN(德州仪器)

  • 封装:

    WFQFN80

  • 描述:

    Medical Ultrasound Imaging, Sonar PMIC 80-WQFN (12x12)

  • 数据手册
  • 价格&库存
LM96551SQX/NOPB 数据手册
LM96551 www.ti.com SNAS511B – OCTOBER 2011 – REVISED MAY 2013 LM96551 Ultrasound Transmit Pulser Check for Samples: LM96551 FEATURES APPLICATIONS • • 1 2 • • • • • • • • • • • • • 8-Channel High-Voltage CMOS Pulse Generator Output Pulses with ±50V and 2A Peak Current Active Damper with Built-In Blocking Diodes Built-In Floating Supply Voltages for Output Stage Up to 15 MHz Operating Frequency Matched Delays for Rising and Falling Edges Low Second Harmonic Distortion Allows and Improves Harmonic Imaging Continuous-Wave (CW) Operation Down to ±3.3V Low Phase Noise Enables Doppler Measurements – -145 dBc/Hz Phase Noise at 10 MHz (1 kHz offset) Output State Over-Temperature Protection Blocking Diodes for Direct Interface to Transducer 2.5V to 5.0V CMOS Logic Interface Low-Power Consumption per Channel Over Temperature Protection Ultrasound Imaging DESCRIPTION The LM96551 is an eight-channel monolithic highvoltage, high-speed pulse generator for multi-channel medical ultrasound applications. It is well-suited for use with Texas Instrument’s LM965XX series chipset which offers a complete medical ultrasound solution targeted towards low-power, portable systems. The LM96551 contains eight high-voltage pulsers with integrated diodes generating ±50V bipolar pulses with peak currents of up to 2A and pulse rates of up to 15 MHz. Advanced features include low-jitter and low-phase-noise output pulses ideal for continuouswave (CW) modes of operation. Active clamp circuitry is integrated for ensuring low harmonic distortion of the output signal waveform. The LM96551 also featuers a low-power operation mode and over-temperature protection (OTP) which are enabled by on-chip temperature sensing and power-down logic. KEY SPECIFICATIONS • • • • • • Output voltage ±50 V Output peak current ±2.0 A Output pulse rate Up to 15 MHz Rise/fall delay matching (max) < 3.7 ns Pulser HD2 (5 MHz) -40 dB Operating Temp. 0 to +70 °C 1 2 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. All trademarks are the property of their respective owners. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright © 2011–2013, Texas Instruments Incorporated LM96551 SNAS511B – OCTOBER 2011 – REVISED MAY 2013 www.ti.com Block Diagram VLL VDD VPP VPF VDN MOD EN Level Shifter Up PIN n NIN n Input Buffer Level Shifter Buffer Vout n OTP Level Shifter Down Temp Sensor Buffer Active Damper Regulates VSUB AGND VNF VNN HVGND Typical Application Figure 1. 8-Channel Transmit/Receive Chipset 2 Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated Product Folder Links: LM96551 LM96551 www.ti.com SNAS511B – OCTOBER 2011 – REVISED MAY 2013 HVGND Vout1 Vout1 HVGND Vout2 Vout2 HVGND Vout3 Vout3 HVGND HVGND Vout4 Vout4 HVGND Vout5 Vout5 HVGND Vout6 Vout6 HVGND Pin Diagram 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 Vout0 1 60 Vout7 Vout0 2 59 Vout7 HVGND 3 VPP 4 57 VPP VPP 5 56 VPP VPP 6 55 VPP VPP 7 54 VPP VPF 8 53 VPF HVGND 9 52 HVGND 58 HVGND 0: VSUB LM96551 LLP VNF 10 VNN 11 51 VNF 50 VNN VNN 12 49 VNN VNN 13 48 VNN VNN 14 47 VNN VSUB 15 46 VSUB VDN 16 45 VDN AGND 17 44 AGND VDD 18 43 VDD AGND 19 42 AGND 33 34 35 36 37 38 39 40 Pin7 Nin7 Pin3 32 Nin6 Nin2 31 Pin6 Pin2 30 Nin5 Nin1 29 Pin5 Pin1 28 Nin4 27 Pin4 26 AGND 25 MODE 24 OTP 23 EN 22 Nin3 21 Nin0 41 VLL Pin0 VLL 20 Figure 2. WQFN Package See Package Number NKF0080A Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated Product Folder Links: LM96551 3 LM96551 SNAS511B – OCTOBER 2011 – REVISED MAY 2013 www.ti.com PIN DESCRIPTIONS Pin No. Name Type 21, 23, 25, 27, 33, 35, 37, 39 PIN n=0...7 Input Logic control positive output channel P 1 = ON 0 = OFF 22, 24, 26, 28, 34, 36, 38, 40 NIN n=0...7 Input Logic control negative output channel N 1 = ON 0 = OFF 59, 60 VOUT7 62, 63 VOUT6 65, 66 VOUT5 68, 69 VOUT4 72, 73 VOUT3 75, 76 VOUT2 78, 79 VOUT1 1, 2 VOUT0 29 EN Input Chip power enable 1 = ON 0 = OFF 31 MODE Input Output current mode control 1 = Max Current 0 = Low Current Output Function and Connection High voltage output of channels 0 to 7 30 OTP Output Over-temperature indicating IC temp > 125°C 0 = Over-temperature 1 = Normal temperature This pin is open-drain. 4, 5, 6, 7, 54, 55, 56, 57 VPP Power Positive high voltage power supply (+3.3V to +50V) 11, 12, 13, 14, 47, 48, 49, 50 VNN Power Negative high voltage power supply (-3.3V to -50V) 8, 53 VPF Power Positive internal floating power supply (VPP -10V) 10, 51 VNF Power Negative internal floating power supply (VNN +10V) 18, 43 VDD Power Positive level-shifter supply voltage (+10V) 16, 45 VDN Power Negative level-shifter supply voltage (-10V) 20, 41 VLL Power Logic supply voltage. Hi voltage reference input (+2.5 to +5V) VSUB Power All VSUB pins must be connected to most negative potential of the IC. NOTE: The exposed thermal pad is connected to VSUB. HVGND Ground High voltage reference potential (0V) AGND Ground Analog and Logic voltage reference input, logic ground (0V) 0, 15, 46 3, 9, 52, 58, 61, 64, 67, 70, 71, 74, 77, 80 17, 19, 32, 42, 44 4 Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated Product Folder Links: LM96551 LM96551 www.ti.com SNAS511B – OCTOBER 2011 – REVISED MAY 2013 These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates. Absolute Maximum Ratings (1) (2) Maximum Junction Temperature (TJMAX) +150°C −40°C to +125°C Storage Temperature Range Supply Voltage (VDD) –0.3V to +12V Supply Voltage (VDN) +0.3V and −12V Supply Voltage (VPP) –0.3V and +55V Supply Voltage (VNN) +0.3V and −55V −65V Supply Voltage (VSUB) −0.3V to +5.5V IO Supply Voltage (VLL) −0.3V to VLL +0.3V Voltage at Logic Inputs (1) (2) Absolute Maximum Ratings are limits beyond which damage to the device may occur. Operating Ratings are conditions under which operation of the device is specified to be functional, but do not specify specific performance limits. For specifications and test conditions, see the Electrical Characteristics. If Military/Aerospace specified devices are required, please contact the Texas Instruments Sales Office/ Distributors for availability and specifications. Operating Ratings Operation Junction Temperature 0°C to + 70°C VPP, −VNN; High-voltage supply +3.3V to +50V VDD, −VDN; Level-shift supply +9V to 11V VLL, Logic Supply +2.4V to +5.3V VSUB, Substrate bias supply must be most negative supply Package Thermal Resistance (θJA ) ESD Tolerance 19.7 °C/W Human Body Model 2KV Machine Model 150V Charge Device Model 750V Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated Product Folder Links: LM96551 5 LM96551 SNAS511B – OCTOBER 2011 – REVISED MAY 2013 www.ti.com Analog Characteristics Unless otherwise stated, the following conditions apply VLL = +3.3V, VPP = −VNN = 50V, VSUB = −55V, VDD = −VDN = 10V, RL = 2KΩ, TA = 25°C, Fin=5MHz, Mode = LO, EN = HI. Symbol FOUT Parameter Output Frequency Range Conditions Min RL = 100Ω Output Voltage Range Max Units 1 Typ 15 MHz -48.5 +48.5 V Output Current 2% Duty Cycle Output Current 100% Duty Cycle, Mode=HI 0.6 HD2 Second harmonic distortion RL = 100Ω, CL = 330pF -40 RON Output ON Resistance 100 mA 7 Output clamp Positive or Negative pulse 2 Power Supply Current 2 Pin = Nin = LO En = LO A dBc 11 Ω A VPP 3.2 VNN 3.4 7 8 VDD 12 18 VDN 8 13 VLL 25 50 µA VSUB 0.7 6 mA VPP 3.2 7 VNN 3.4 8 VDD 4 7 VDN 3 6.5 VLL 25 50 µA VSUB 0.7 6 mA mA mA OTP Over Temperature Protection 125 °C σOTP OTP sigma 3.0 °C HsysOTP OTP hysteresis 5.5 °C AC and Timing Characteristics Unless otherwise stated, the following conditions apply VLL = +3.3V, VDD = −VDN = 10V, VSUB = −55V, VPP = −VNN = 50V, RL = 100Ω, CL = 330pF, Fin=5MHz, TA = 25°C. Mode = LO, EN = HI. Typ Max tr Symbol Output rise time 19 29 tf Output fall time 19 29 tE Enable time 1 tdr Delay time on inputs rise 32 tdf Delay time on inputs fall | tdr - tdr | Delay time mismatch tdm Delay on mode change (1) 6 Parameter Conditions Min 32 P-to-N (1) Unit ns µs 39 39 ns 3.7 1 µs The delay time mismatch can be adjust to be less than 0.8ns with the LM96570 duty cycle control function. Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated Product Folder Links: LM96551 LM96551 www.ti.com SNAS511B – OCTOBER 2011 – REVISED MAY 2013 DC Characteristics Unless otherwise stated, the following conditions apply. VLL = +3.3V, VDD = −VDN = 10V, VSUB = −55V, VPP = −VNN = 50V, TA = 25°C, Symbol Parameter Conditions VIL Low Input “LO” threshold VIH High Input “HI” threshold IIN input current Min Typ Max Unit 1 V 2.3 V 1 µA Overview The LM96551 pulser provides an 8-channel transmit side solution for medical ultrasound applications suitable for integration into multi-channel (128/256 channel) systems. Its flexible, integrated ±50V pulser architecture enables low-power designs targeting portable systems. A complete system can be designed using Texas Instrument’s companion LM965XX chipset. VLL VDD VPP VPF VDN MOD EN Level Shifter Up PIN n NIN n Input Buffer Level Shifter Buffer Vout n OTP Level Shifter Down Temp Sensor Buffer Active Damper Regulates AGND VSUB VNF HVGND VNN Figure 3. Block Diagram of High-Voltage Pulser Channel A functional block diagram of the LM96551 is shown in Figure 3. It has an input buffer at its CMOS logic interface, which is powered by VLL (2.5 to 5.0V). When EN=HI, driving a channel’s inputs (PIN n or NIN n) HI will result in a positive or negative pulse at the channel’s output pin (VOUT n), respectively. The output pins VOUT are pulled to either the positive or negative supplies, VPP or VNN by power MOSFETs. When PIN and NIN are both LO, Vout is actively clamped to GNDHI at 0V. This clamping reduces harmonic distortions compared to competing architectures that use bleeding resistors for implementing the return to zero of the output. The user must avoid the condition in which PIN and NIN are both HI simultaneously, as this will damage the output stage! The impedance of the output stage can be controlled via the Mode-pin. When the Mode = HI as shown, only one output transistor pair drives the output resulting in a peak current of 600 mA at VPP = -VNN = 50V. When Mode=LO, a peak-current of 2A is achievable resulting in faster transients at the output. However, faster output transients can lead to significant overshoot of the output signal. This can be avoided using the lower drive current option. Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated Product Folder Links: LM96551 7 LM96551 SNAS511B – OCTOBER 2011 – REVISED MAY 2013 www.ti.com Continuous-wave (CW) applications are supported for low power consumption down to VPP = -VNN = 3.3V with Mode =HI. Internally, the CMOS logic input signals are level shifted to VDD = 10V and VDN = -10V for pulse transmission. The outputs of the level shifter drive the high-voltage P and N drivers that control the output power MOSFETs, which are supplied from the positive and negative rails VPP and VNN, respectively. The high-voltage rails are designed for a maximum of 50V; however, they can be operated down to 3.3V. The necessary gate-overdrive voltage levels for the output drivers are internally generated from the high-voltage rails. Over-Temperature Protection (OTP) is implemented by continuously monitoring the on-chip temperature. The OTP output (open drain) pin goes LO when the chip temperature exceeds a critical level. Prior to this event, the user must ensure that the chip is powered down before fatal damage occurs. In addition to a primary software controlled safety shutdown, the OTP pin can be also be hard-wired to the EN pin as a secondary safety measure. Timing Diagrams RISE AND FALL TIME The timing diagram shown in Figure 4 defines the rise and fall times tr and tf. NINx PINx VPP 10% 90% Output 0 tf tr 10% 90% Figure 4. Timing Diagram Defining Rise and Fall Times tr and tf, respectively INPUT TO OUTPUT DELAY The timing diagram shown in Figure 5 defines the delays between the input and output signals. NINx 50% PINx 50% tdr tdf VPP Output 0 50% 50% Figure 5. Timing Diagram Defining Input-to-Output Delays Times 8 Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated Product Folder Links: LM96551 LM96551 www.ti.com SNAS511B – OCTOBER 2011 – REVISED MAY 2013 Typical Performance Characteristics Unless otherwise stated, the following conditions apply VLL = +3.3V, VDD = −VDN = 10V, VSUB = −55V, VPP = −VNN = 50V, RL = 100Ω, CL = 330pF, Fin=5MHz, TA = 25°C. Mode = LO, EN = HI Return-to-Zero Rise Time (RL=2KΩ) Return-to-Zero Fall Time (RL=2KΩ) Figure 6. Figure 7. Harmonic Distortion (8 pulses) Differential Input vs. Pulser Output Phase Noise (1) Figure 8. Figure 9. Constant 5W Total Power RL=300Ω 100% CW mode, Mode=HI, VSUB=-10V Over Temperature Protection 120 10 100 8 # of Samples CW Frequency (MHz) 9 7 6 CL=150pF 5 CL=330pF 4 CL=470pF 3 80 60 40 20 2 0 1 3 4 5 6 7 VPP=-VNN (V) 8 9 134 OTP Trip Point (°C) Figure 10. (1) 114 Figure 11. 10.24 MHz Differential Input signal from LMK04800 Evaluation board with 122.88 MHz Crystek CVHD-950 VCXO clock source. The LMK04800 clock output channel was configured with a divide value of 12 and LVCMOS outputs with opposite polarity. Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated Product Folder Links: LM96551 9 LM96551 SNAS511B – OCTOBER 2011 – REVISED MAY 2013 www.ti.com FUNCTIONAL DESCRIPTION Note that the case, PINn = NNn = HI is not allowed as it will damage the output transistors. Logic inputs Output EN PINn NINn 1 0 0 Voutn 0V 1 1 0 VPP - 0.7V 1 0 1 VNN + 0.7V 1 1 1 not allowed 0 X X 0V APPLICATIONS INFORMATION POWER-UP AND POWER-DOWN SEQUENCES VSUB must always be the most negative supply, i.e., it must be equal to or more negative than the most negative supply, VNN or VDN. Power UP Sequence: 1. Turn ON VSUB, hold EN pin LO 2. Turn On VLL 3. Turn ON VDD, VDN, VPP, and VNN Power DOWN Sequence: 1. Turn OFF VDD, VDN, VPP & VNN 2. Turn OFF VLL 3. Turn OFF VSUB 10 Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated Product Folder Links: LM96551 LM96551 www.ti.com SNAS511B – OCTOBER 2011 – REVISED MAY 2013 REVISION HISTORY Changes from Revision A (May 2013) to Revision B • Page Changed layout of National Data Sheet to TI format .......................................................................................................... 10 Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated Product Folder Links: LM96551 11 PACKAGE OPTION ADDENDUM www.ti.com 9-Nov-2016 PACKAGING INFORMATION Orderable Device Status (1) LM96551SQE/NOPB LIFEBUY Package Type Package Pins Package Drawing Qty WQFN NKF 80 250 Eco Plan Lead/Ball Finish MSL Peak Temp (2) (6) (3) Green (RoHS & no Sb/Br) CU SN | Call TI Level-3-260C-168 HR Op Temp (°C) Device Marking (4/5) LM96551SQ (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device. (6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish value exceeds the maximum column width. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. Addendum-Page 1 Samples PACKAGE OPTION ADDENDUM www.ti.com 9-Nov-2016 Addendum-Page 2 PACKAGE MATERIALS INFORMATION www.ti.com 15-Jun-2016 TAPE AND REEL INFORMATION *All dimensions are nominal Device LM96551SQE/NOPB Package Package Pins Type Drawing WQFN NKF 80 SPQ 250 Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) 178.0 24.4 Pack Materials-Page 1 12.3 B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant 12.3 1.0 16.0 24.0 Q1 PACKAGE MATERIALS INFORMATION www.ti.com 15-Jun-2016 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) LM96551SQE/NOPB WQFN NKF 80 250 213.0 191.0 55.0 Pack Materials-Page 2 MECHANICAL DATA NKF0080A SQA80A (Rev A) www.ti.com IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest issue. 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