LM96570SQ/NOPB

LM96570 LM96570 Ultrasound Configurable Transmit Beamformer Literature Number: SNAS505D LM96570 Ultrasound Configurable Transmit Beamformer General Description Features The LM96570 is an eight-channel monolithic beamformer for pulse generators in multi-channel medical ultrasound applications. It is well-suited for use with National’s LM965XX series chipset which offers a complete medical ultrasound solution targeted towards low-power, portable systems. The LM96570 offers eight P and N output channels with individual delays of up to 102.4 µs operating at pulse rates of up to 80 MHz. A pulse sequence is launched on all channels simultaneously through a single firing signal. Advanced features include delay resolution down to 0.78 ns and programmable patterns of up to 64 pulses. Pulse patterns and delay settings are pre-programmed through a serial interface, thereby simplifying the timing requirements on the driving circuitry. The LM96570 is packaged in a 32-pin LLP. ■ Full control over selecting beam directions and pulse ■ ■ ■ ■ patterns by programming individual channel parameters Outputs interface seamlessly with positive and negative inputs on octal high-voltage pulser ICs Beamformer timing provides: — Delay resolution of 0.78 ns — Delay range of up to 102.4 μs Pulse patterns are locally generated with: — Sequences of up to 64 pulses — Adjustable Pulse widths 2.5V to 3.3V CMOS logic interface Key Specifications I/O voltage Core supply voltage Output pulse rate Reference frequency Applications ■ Ultrasound Imaging 1σ Output Jitter (@ 5MHz) Output Phase Noise (@ 5MHz, 1kHz offset) Delay resolution 2.5 to 3.3 1.8 80 40 (±5%) 25 −116 0.78 Delay range 102.4 Max. pattern length Serial interface speed Total Power Operating Temp. 64 80 0.063 0 to +70 V V MHz MHz ps dBc/Hz ns μs pulses Mbps Watts °C Typical Application 8-Channel Transmit/Receive Chipset 30129703 © 2011 National Semiconductor Corporation 301297 www.national.com LM96570 Ultrasound Configurable Transmit Beamformer September 15, 2011 LM96570 Connection Diagram 30129701 FIGURE 1. Pin Diagram of LM96570 Ordering Information Part Number Package NSC Drawing 32–Lead LLP SQA32A LM96570SQ LM96570SQE 1000 LM96570SQX www.national.com Quantity 250 4500 2 LM96570 Pin Descriptions Pin No. Name Type 1 – 4, 21 – 32 P0-7, N0-7 Output Control signals for pulser. P outputs control positive pulses and N outputs control negative pulses. See logic Table 1. 13 PLL_CLK+ Input PLL Reference Clock PLUS Input, LVDS compatible or Single-Ended LV CMOS input, programmable through 4-Wire Serial Interface (Register 1Bh[0]) 14 PLL_CLK- Input PLL Reference Clock MINUS input, LVDS compatible. For Single-Ended PLL Reference Clock operation, tie this pin to AGND or VDDA. 7 TX_EN Input 1 = Beamformer starts firing 0 = Beamformer ceases firing 16 PLL_Vin Input Voltage range 0.8-1.2V for tuning internal PLL noise performance. Under normal conditions, 0.94V is recommended. 17 PLL_Iin Input 100 μA current input 8 RST Input Asynchronous Chip Reset 1 = Reset 0 = No Reset 12 sCLK Input 4-Wire Serial Interface Clock 10 sLE Input 4-Wire Serial Interface Latch Enable 11 sWR Input 4-Wire Serial Interface Data Input for writing data registers 9 sRD Output 4-Wire Serial Interface Data Output for reading data registers 15 VDDA Power Analog supply voltage (1.8V) 6 VDDC Power Digital core supply voltage (1.8V) 19 VIO Power Digital I/O supply voltage (2.5 to 3.3V) AGND Ground PLL Analog ground 5 DGND Ground Digital core ground 20 DGNDIO Ground Digital I/O ground 0, 18 Function and Connection 3 www.national.com LM96570 Absolute Maximum Ratings (Note 1) Operating Ratings If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/ Distributors for availability and specifications. Operating Temperature Range(TA) VDDA, Analog Supply VDDC, Digital Core Supply VIO, Digital IO Supply (Note 1) 0°C to + 70°C +1.71V to +1.89V +1.71V to +1.89V +2.37 to +3.47 37°C/W Package Thermal Resistance (θJA) (Note 3) ESD Tolerance (Note 4) Human Body Model 2kV Machine Model 200V Charge Device Model 750V Maximum Junction Temperature (TJMAX) +150°C Storage Temperature Range −40°C to +125°C Supply Voltage (VDDA) −0.3V to +2.0V Supply Voltage (VDDC) −0.3V and +2.0V Supply Voltage (VIO) −0.3V and +3.6V Voltage at Analog Inputs −0.3V and VDDA+0.3V Voltage at Logic Inputs −0.3V and VIO+0.3 Analog Electrical Characteristics Unless otherwise stated, the following conditions apply VIO = +3.3V, VDDA = VDDC = +1.8V, TA = 25°C. Pin Parameter PLL Phase Noise Conditions Min 5MHz pulse rate, 1kHz offset Typ –116 VDDA VDDC Power Supply Current Register with No Pattern (08h - 19h) Power Supply Current Register Default Pluse Pattern (08h - 19h), TX_EN = 15 kHz, Pulse rate = 5 MHz dBc/Hz 2.4 mA 0.3 VDDA VIO PLL_CLK+ Units 18.5 VIO VDDC Max PLL Reference Clock Frequency 16.0 mA 6.50 13.4 38 40 42 MHz Max Units 80 MHz Beamformer Output Timing Characteristics Unless otherwise stated, the following conditions apply VIO = +3.3V, VDDA = VDDC = +1.8V, TA = 25°C. Symbol Parameter Conditions Output Pulse Rate Min Typ 0.625 Output Delay Range 102.4 Output Delay Resolution 0.78 Output Pattern Length tOD Output Propagation Delay Delay Profile (00−07h) = 0 Asynchronous TX_EN tR/F Output Rise/Fall ILOAD = 2mA www.national.com 32 0.5 4 µs ns 64 Pulses 47.5 ns 1.9 ns LM96570 Digital Electrical Characteristics Unless otherwise stated, the following conditions apply VIO = +3.3V, VDDA = VDDC = +1.8V, TA = 25°C. Symbol Parameter Conditions Min Typ Max Unit 200 400 mV PLL DIFFERENTIAL REFERENCE CLOCK DC SPECIFICATIONS VID PLL Reference Clock AC Coupled to pins 13 & 14. 1B[0] = 0 Differential Input Amplitude (see (Note 2)) VICM PLL Reference Clock Input Pins 13 & 14 bias voltage, VICM ≈ 0.5 Common Mode Voltage X VDDA 0.9 V RIN Single-ended Input Resistance 11 kΩ PLL 1.8V LVCMOS SINGLE-ENDED REFERENCE CLOCK DC SPECIFICATIONS VIH LVCMOS Input “HI” Voltage Pin 13. Register 1B[0] = 1 VIL LVCMOS Input “LO” Voltage RIN LVCMOS Input Resistance Pin 13 = 0V or VIO 1.5 Pin 13. Register 1B[0] = 1 V 0.3 11 kΩ 3.3V I/O DC SPECIFICATIONS VIH Logic Input “HI” Voltage 2.2 VIL Logic Input “LO” Voltage IIN-H/L Input Current −1 VOH Logical Output “HI” Voltage IOH = 2 mA 2.9 VOL Logical Output “LO” Voltage IOL = 2 mA IO-H/L Logic Output Current V 0.5 1 µA V 0.34 ±10 mA Serial Interface Timing Characteristics Unless otherwise stated, the following conditions apply VIO = +3.3V, VDDA = VDDC = +1.8V, TA = 25°C. Symbol Parameter Conditions Min Typ tLES sLE Setup Time 1.4 tLEH sLE Hold Time 1.9 tLEHI sLE HI Time 2.4 tWS sWR Setup Time 1.4 tWH sWR Hold Time 2.4 tRS sRD Data Valid Setup Time 6.3 tRH sRD Data Valid Hold Time 6.2 tSCLKR sCLK Rise Time 1.7 tSCLKF sCLK Fall Time 1.7 tSCLKH sCLK High Time 2.4 tSCLKL sCLK Low Time 3.4 fSCLK sCLK Frequency Max Units ns ns ns 80 MHz Note 1: Absolute Maximum Ratings are those values beyond which the safety of the device cannot be guaranteed. They are not meant to imply that the device can or should be operated at these limits. Operating Ratings indicate conditions for which the device is guaranteed to be functional, but do not guarantee specific performance limits. Guaranteed specifications and test conditions are specified in the Electrical Characteristics section. Operation of the device beyond the Operating Ratings is not recommended as it may degrade the lifetime of the device. Note 2: The combination of common mode and voltage swing on the clock input must ensure that the positive voltage peaks are not above VDDA and the negative voltage peaks are not below AGND. Note 3: The maximum power dissipation is a function of TJMAX, θJA and TA. The maximum allowable power dissipation at any ambient temperature is PD = (TJMAX - TA)/ θJA. All numbers apply for package soldered directly into a 2 layer PC board with zero air flow. Note 4: Human Body Model, applicable std. JESD22–A114–C. Machine Model, applicable std. JESD22–A115–A. Field induced Charge Device Model, applicable std. JESD22–C101–C. 5 www.national.com LM96570 Timing Diagrams 30129704 FIGURE 2. 4-Wire Serial Interface WRITE Timing 30129705 FIGURE 3. 4-Wire Serial Interface READ Timing www.national.com 6 LM96570 Typical Performance Characteristics 1δ Output Jitter 30129718 Output Phase Noise 30129717 7 www.national.com LM96570 flexible, integrated pulse pattern generation and delay architecture enables low-power designs suitable for ultra-portable applications. A complete system can be designed using National’s companion LM9655x chipset. Overview The LM96570 beamformer provides an 8-channel transmit side solution for medical ultrasound applications suitable for integration into multi-channel (128 / 256 channel) systems. Its 30129702 FIGURE 4. Block Diagram of Beamformer with Pattern and Delay Generator A functional block diagram of the IC is shown in Figure 4. Each of the 8 output channels are designed to drive the positive and negative pulse control inputs, Pn and Nn, respectively, of a high-voltage ultrasound pulser, such as the LM96550. Upon assertion of the common firing signal, each channel launches an individually programmable pulse pattern with a maximum delay of 102.4µs in adjustable in increments of 0.78 ns. The length of a fired pulse pattern can extend up to 64 pulses. Accurate timing of the pulse generation is enabled by an onchip PLL generating 8-phase 160 MHz internal clocks derived from an external differential or single-ended 40MHz reference. The pulse patterns and delay settings can be programmed into and read out from the individual channel controls via a four-wire serial interface. When the Latch Enable signal (sLE) is low, the targeted on-chip registers can be written though the serial data Write pin (sWR) at the positive clock edge (sCLK). In the same way, they can also be read out through the serial data Read pin (sRD). The writing and reading operations have the same timing requirements, which are shown in Figure 2 and Figure 3. The serial data stream starts with a 6-bit address, in which the first 5-bits identify the mode www.national.com of updating which is interpreted by the Finite State Machine (FSM), and the sixth bit of the address indicates the 4-wire serial operation, either “WRITE” (0) or “READ” (1). The address is followed by the data word, whose length can vary from 8 bits to 64 bits. The data stream starts with the LSB and ends with the MSB. The first 5-bit address indicates which of the 27 registers is being accessed. The register map is shown in Table 3. In each 4-wire serial operation, only one register can be written to or read from at a time. TX_EN must be inactive during 4-wire serial interface operation. Upon a rising edge of the transmit signal “TX_EN”, the internal “Fire” signal is pulled high after an internal propagation delay relative to TX_EN elapses. Then the delay counter of each channel begins counting according to the programmable delay profile. When the counter reaches the 17-bit programmed delay value, the programmed pulse pattern is sent out continuously at the programmed frequency until it reaches the length of the pulse pattern. The interface is compatible with CMOS logic powered at 2.5V or 3.3V. The internal core supply is derived from 1.8V referenced to 0V. 8 P/N OUTPUT PATTERN PROGRAMMING The output pulse pattern for each of the 8 P channels is set by programming registers 08h to 0Fh, respectively. The output pulse pattern for each of the 8 N channels is set by programming registers 10h to 17h, respectively. Programming each bit of these registers yields P/N output pulses TABLE 1. Truth Table — Beamformer Output-to-Pulser Output P Pattern Register Bit Value N Pattern Register Bit Value Beamformer P Output Beamformer N Output 0 0 0 0 0 1 0 1 0 VPP − 0.7V 0 1 0 1 VNN + 0.7V 1 1 0 0 0 If the user wishes to program the same pulse pattern for all 8 P channels or all 8 N channels, there are two additional “global channel” registers available for ease and convenience. Programming a pulse pattern via Register 18h will internally apply the same pulse pattern to all 8 P channels Similarly, programming a pulse pattern via Register 19h will internally apply the same pulse pattern to all 8 N channels. Pulser Output These bit depths of these registers, i.e., pulse pattern lengths, are user-programmable via bits 0 to 2 of Register 1Ah. These 3 bits (1Ah[2:0]) determine the bit depth or pulse pattern according to Table 2. The outputs will not function correctly if a different number of bits, inconsistent with what is set by Register 1Ah[2:0], is programmed into any of the registers, 08h to 19h. TABLE 2. Pulse Pattern Length Truth Table 1Ah[2:0] Registers 08h to 19h Bit Depth Pulse Pattern Length 000 4 bits 4 pulses 001 8 bits 8 pulses 010 16 bits 16 pulses 011 24 bits 24 pulses 100 32 bits 32 pulses 101 40 bits 40 pulses 110 48 bits 48 pulses 111 64 bits 64 pulses bits control the number of internal clock cycles (ranging from 0 to 16,383) that the P/N output is delayed in addition to the internal propagation delay. DELAY ADJUSTMENT The delay between the rising edge of the TX_EN signal and the first programmed P/N output pulse typically consists of: (1) an internal propagation delay relative to the TX_EN rising edge plus (2) a user-programmed delay value. The internal propagation delay is specified in the Beamformer Output Timing Characteristics with the programmable delay set at 0. The user-defined delay value is set by programming the 17 Least Significant Bits in Registers 00h to 07h for each of the 8 output channels, respectively. The 17 Least Significant Bits in Delay Profile Registers 00h to 07h (00-07h[17:0]) are further divided into Coarse Delay Adjustment bits and Fine Delay Adjustment bits. Fine Delay Adjustment Bits 0 to 2 (00-07h[2:0]) set the clock phase for the internal programmable counter, which in turn set the fine delay value. In addition to the coarse delay, these 3 bits control the fractional amount of delay that the P/N output is delayed by relative to the internal Fire signal. The fine delay is phase adjustable in increments of 1/8 of an internal clock cycle, i.e., 45°. See Figure 5. Coarse Delay Adjustment Bits 3 to 16 (00-07h[16:3]) set the internal programmable counter, which in turn set the coarse delay value. These 14 9 www.national.com LM96570 according to Table 1. Each bit represents one pulse, thus the full bit stream of each register is equivalent to one full length pulse pattern. However, note that the LSB of the register is transmitted as an output pulse first and the MSB is transmitted as an output pulse last. For example: a register value of “10110100” will yield an output pulse pattern versus time such as “00101101”. Functional Description LM96570 30129714 FIGURE 5. Fine Delay Adjustment (00–07h[2:0]) in 1/8 Internal Clock Phase Angle Steps Since an internal clock cycle is 6.25 ns, the total 17-bit userprogrammable delay ranges from 0 up to approximately 102.4μs. The following example illustrates a 64-bit pulse pattern with various delay profiles. Here, the user-programmable pulse Ch. Register output frequency is 10 MHz. The delays are programmed such that the delay between adjacent channels is approximately 13.28 ns, which is 2 coarse delays plus one fine delay (1 coarse step or internal clock cycle = 6.25 ns & 1 fine step or 1/8 internal clock cycle = 0.78 ns). Data Fire Delay Ch 0 Reg. 00h 00 000 00000000000000 000 b no user-programmed delay Ch 1 Reg. 01h 00 000 00000000000010 001 b 2 coarse delays + 1 fine delay Ch 2 Reg. 02h 00 000 00000000000100 010 b 4 coarse delays + 2 fine delay Ch 3 Reg. 03h 00 000 00000000000110 011 b 6 coarse delays + 3 fine delay Ch 4 Reg. 04h 00 000 00000000001000 100 b 8 coarse delays + 4 fine delay Ch 5 Reg. 05h 00 000 00000000001010 101 b 10 coarse delays + 5 fine delay Ch 6 Reg. 06h 00 000 00000000001100 110 b 12 coarse delays + 6 fine delay Ch 7 Reg. 07h 00 000 00000000001110 111 b 14 coarse delays + 7 fine delay Here, the pulse pattern may be programmed to each individual channel via Registers 08h to 0Fh for the P channels and 10h to 17h for the N channels with the following 64 bits of data (shown in hexadecimal format). Channel Register Data P part Ch 0 - 7 Reg. 08h - 0Fh 5555 5555 5555 5555 h N part Ch 0 - 7 Reg. 10h - 17h AAAA AAAA AAAA AAAA h Alternatively, since these 8 channels have the same pulse patterns, they can also be programmed directly to Register 18h (P part of pulse pattern ) and Register 19h (N part of pulse pattern) instead of writing the same pulse pattern to each individual channel 8 times. Channel Register Data P part Ch 0 - 7 Reg. 18h 5555 5555 5555 5555 h N part Ch 0 - 7 Reg. 19h AAAA AAAA AAAA AAAA h Figure 6 shows the Beamformer channel outputs and TX_EN timing. After the internal propagation delay has elapsed, each channel counts its programmed delay value. When it reaches this value, it will transmit the programmed pulse pattern. Channel 0, which has no user-programmed delay, outputs www.national.com first and then is followed by Channel 1 after 2 coarse delays plus one fine delay (13.28 ns). Each bit of the 64-bit register’s pulse pattern is continuously transmitted from its LSB to MSB until all 64 bits are output. 10 LM96570 30129710 FIGURE 6. Beamformer Output Example PULSE WIDTH ADJUST 30129706 FIGURE 7. High-Voltage Pulser Figure 7 is a diagram for a high-voltage pulser such as the LM96550. The input control signals Pn/Nn are provided by the beamformer output. These signals are level shifted up/down to the high voltage “HV”/”-HV” and buffered to drive the output stage of M1/M2 to generate high-voltage outputs. High linearity and low distortion are typically required for pulser outputs. To achieve this, the duty cycles of output pulses should be as close to 50% as possible. Due to the non-ideal nature and differences between the two signal paths, from Pn to g1, and from Nn to g2, it is very difficult achieve an ideal 50% duty cycle at the pulser outputs, even if the Pn and Nn inputs are perfectly at equal pulse width. To address this challenge, the LM96570 can tune the pulse width of its outputs Pn/Nn to compensate the path difference, as shown in Figure 8. In the ideal case, the pulse width of Pn and Nn is equal, tp1’=tp2’, and the corresponding pulser output duty cycle is 50%, tp1=tp2. However, in the typical case, tp1 is not equal to tp2; instead, for example, tp1>tp2. The LM96570 can then change the pulse width of Pn and Nn so that tp1'