LMC567
Low Power Tone Decoder
General Description
Features
The LMC567 is a low power general purpose LMCMOS™
tone decoder which is functionally similar to the industry
standard LM567. It consists of a twice frequency voltagecontrolled oscillator (VCO) and quadrature dividers which
establish the reference signals for phase and amplitude
detectors. The phase detector and VCO form a phaselocked loop (PLL) which locks to an input signal frequency
which is within the control range of the VCO. When the PLL
is locked and the input signal amplitude exceeds an internally pre-set threshold, a switch to ground is activated on the
output pin. External components set up the oscillator to run
at twice the input frequency and determine the phase and
amplitude filter time constants.
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Block Diagram
Functionally similar to LM567
2V to 9V supply voltage range
Low supply current drain
No increase in current with output activated
Operates to 500 kHz input frequency
High oscillator stability
Ground-referenced input
Hysteresis added to amplitude comparator
Out-of-band signals and noise rejected
20 mA output current capability
(with External Components)
00867001
Order Number LMC567CM or LMC567CN
See NS Package Number M08A or N08E
LMCMOS™ is a trademark of National Semiconductor Corp.
© 2004 National Semiconductor Corporation
DS008670
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LMC567 Low Power Tone Decoder
June 1999
LMC567
Absolute Maximum Ratings (Note 1)
Storage Temperature Range
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales Office/
Distributors for availability and specifications.
Soldering Information
Input Voltage, Pin 3
−55˚C to +150˚C
Dual-In-Line Package
Soldering (10 sec.)
2 Vp–p
260˚C
Small Outline Package
Supply Voltage, Pin 4
10V
Vapor Phase (60 sec.)
215˚C
Output Voltage, Pin 8
13V
Infrared (15 sec.)
220˚C
Voltage at All Other Pins
Vs to Gnd
Output Current, Pin 8
See AN-450 “Surface Mounting Methods and Their Effect
on Product Reliability” for other methods of soldering
surface mount devices.
30 mA
Package Dissipation
500 mW
Operating Temperature Range (TA)
−25˚C to +125˚C
Electrical Characteristics
Test Circuit, TA = 25˚C, Vs = 5V, RtCt #2, Sw. 1 Pos. 0, and no input, unless otherwise noted.
Symbol
I4
Parameter
Power Supply
Current
Conditions
Min
RtCt #1, Quiescent
or Activated
Typ
Max
Units
0.5
0.8
mAdc
0.8
1.3
Vs = 2V
0.3
Vs = 5V
Vs = 9V
V3
Input D.C. Bias
0
mVdc
R3
Input Resistance
40
kΩ
I8
Output Leakage
f0
Center Frequency,
Fosc ÷ 2
1
RtCt #2, Measure Oscillator
Frequency and Divide by 2
Vs = 2V
Vs = 5V
92
Vs = 9V
∆f0
Vin
Set Input Frequency Equal to f0 Measured
Above, Increase Input Level Until Pin 8
Goes Low.
∆Vin
Input Hysteresis
Starting at Input Threshold, Decrease Input
Level Until Pin 8 goes High.
V8
Output "Sat’ Voltage
Input Level > Threshold
Choose RL for Specified I8
L.D.B.W.
Largest Detection
Bandwidth
Measure Fosc with Sw. 1 in
Pos. 0, 1, and 2;
Vs = 2V
11
Vs = 5V
17
Vs = 9V
113
kHz
1.0
2.0
%/V
20
27
30
45
103
mVrms
45
1.5
I8 = 2 mA
0.06
I8 = 20 mA
0.7
mVrms
0.15
Vdc
Vs = 2V
7
11
15
Vs = 5V
11
14
17
%
± 1.0
%
Vs = 9V
∆BW
nAdc
105
Center Frequency
Shift with Supply
Input Threshold
100
98
15
Bandwidth Skew
0
fmax
Highest Center Freq.
RtCt #3, Measure Oscillator Frequency and Divide by 2
Vin
Input Threshold at
fmax
Set Input Frequency Equal to fmax measured Above,
Increase Input Level Until Pin 8 goes Low.
700
35
kHz
mVrms
Note 1: Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for which the device is
functional, but do not guarantee specific performance limits. Electrical Characteristics state DC and AC electrical specifications under particular test conditions which
guarantee specific performance limits. This assumes that the device is within the Operating Ratings. Specifications are not guaranteed for parameters where no limit
is given, however, the typical value is a good indication of device performance.
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2
LMC567
Test Circuit
00867002
RtCt
Rt
Ct
#1
100k
300 pF
#2
10k
300 pF
#3
5.1k
62 pF
3
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LMC567
Typical Performance Characteristics
Supply Current vs.
Operating Frequency
Bandwidth vs.
Input Signal Level
00867003
00867007
Largest Detection
Bandwidth vs. Temp.
Bandwidth as
a Function of C2
00867008
00867009
Frequency Drift
with Temperature
Frequency Drift
with Temperature
00867010
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00867011
4
SUPPLY DECOUPLING
The decoupling of supply pin 4 becomes more critical at high
supply voltages with high operating frequencies, requiring
C4 to be placed as close as possible to pin 4.
(refer to Block
Diagram)
GENERAL
The LMC567 low power tone decoder can be operated at
supply voltages of 2V to 9V and at input frequencies ranging
from 1 Hz up to 500 kHz.
INPUT PIN
The input pin 3 is internally ground-referenced with a nominal 40 kΩ resistor. Signals which are already centered on 0V
may be directly coupled to pin 3; however, any d.c. potential
must be isolated via a coupling capacitor. Inputs of multiple
LMC567 devices can be paralleled without individual d.c.
isolation.
The LMC567 can be directly substituted in most LM567
applications with the following provisions:
1. Oscillator timing capacitor Ct must be halved to double
the oscillator frequency relative to the input frequency
(See OSCILLATOR TIMING COMPONENTS).
2. Filter capacitors C1 and C2 must be reduced by a factor
of 8 to maintain the same filter time constants.
3. The output current demanded of pin 8 must be limited to
the specified capability of the LMC567.
LOOP FILTER
Pin 2 is the combined output of the phase detector and
control input of the VCO for the phase-locked loop (PLL).
Capacitor C2 in conjunction with the nominal 80 kΩ pin 2
internal resistance forms the loop filter.
OSCILLATOR TIMING COMPONENTS
For small values of C2, the PLL will have a fast acquisition
time and the pull-in range will be set by the built in VCO
frequency stops, which also determine the largest detection
bandwidth (LDBW). Increasing C2 results in improved noise
immunity at the expense of acquisition time, and the pull-in
range will begin to become narrower than the LDBW (see
Bandwidth as a Function of C2 curve). However, the maximum hold-in range will always equal the LDBW.
The voltage-controlled oscillator (VCO) on the LMC567 must
be set up to run at twice the frequency of the input signal
tone to be decoded. The center frequency of the VCO is set
by timing resistor Rt and timing capacitor Ct connected to
pins 5 and 6 of the IC. The center frequency as a function of
Rt and Ct is given by:
OUTPUT FILTER
Pin 1 is the output of a negative-going amplitude detector
which has a nominal 0 signal output of 7/9 Vs. When the PLL
is locked to the input, an increase in signal level causes the
detector output to move negative. When pin 1 reaches
2/3 Vs the output is activated (see OUTPUT PIN).
Capacitor C1 in conjunction with the nominal 40 kΩ pin 1
internal resistance forms the output filter. The size of C1 is a
tradeoff between slew rate and carrier ripple at the output
comparator. Low values of C1 produce the least delay between the input and output for tone burst applications, while
larger values of C1 improve noise immunity.
Pin 1 also provides a means for shifting the input threshold
higher or lower by connecting an external resistor to supply
or ground. However, reducing the threshold using this technique increases sensitivity to pin 1 carrier ripple and also
results in more part to part threshold variation.
Since this will cause an input tone of half Fosc to be decoded,
This equation is accurate at low frequencies; however,
above 50 kHz (Fosc = 100 kHz), internal delays cause the
actual frequency to be lower than predicted.
The choice of Rt and Ct will be a tradeoff between supply
current and practical capacitor values. An additional supply
current component is introduced due to Rt being switched to
Vs every half cycle to charge Ct:
Is due to Rt = Vs/(4Rt)
Thus the supply current can be minimized by keeping Rt as
large as possible (see supply current vs. operating frequency curves). However, the desired frequency will dictate
an RtCt product such that increasing Rt will require a smaller
Ct. Below Ct = 100 pF, circuit board stray capacitances begin
to play a role in determining the oscillation frequency which
ultimately limits the minimum Ct.
To allow for I.C. and component value tolerances, the oscillator timing components will require a trim. This is generally
accomplished by using a variable resistor as part of Rt,
although Ct could also be padded. The amount of initial
frequency variation due to the LMC567 itself is given in the
electrical specifications; the total trim range must also accommodate the tolerances of Rt and Ct.
OUTPUT PIN
The output at pin 8 is an N-channel FET switch to ground
which is activated when the PLL is locked and the input tone
is of sufficient amplitude to cause pin 1 to fall below 2/3 Vs.
Apart from the obvious current component due to the external pin 8 load resistor, no additional supply current is required to activate the switch. The on resistance of the switch
is inversely proportional to supply; thus the “sat” voltage for
a given output current will increase at lower supplies.
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LMC567
Applications Information
LMC567
Physical Dimensions
inches (millimeters) unless otherwise noted
Molded Small Outline (SO) Package (M)
Order Number LMC567CM
NS Package Number M08A
Molded Dual-In-Line Package (N)
Order Number LMC567CN
NS Package Number N08E
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6
LMC567 Low Power Tone Decoder
Notes
National does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and National reserves
the right at any time without notice to change said circuitry and specifications.
For the most current product information visit us at www.national.com.
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