LMC568
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SNAS559B – MAY 1999 – REVISED APRIL 2013
LMC568 Low Power Phase-Locked Loop
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FEATURES
DESCRIPTION
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The LMC568 is an amplitude-linear phase-locked
loop consisting of a linear VCO, fully balanced phase
detectors, and a carrier detect output. LMCMOS
technology is employed for high performance with low
power consumption.
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2
Demodulates ±15% Deviation FM/FSK Signals
Carrier Detect Output with Hysteresis
Operation to 500 kHz Input Frequency
Low THD—0.5% Typ. for ±10% Deviation
2V to 9V Supply Voltage Range
Low Supply Current Drain
The VCO has a linearized control range of ±30% to
allow demodulation of FM and FSK signals. Carrier
detect is indicated when the PLL is locked to an input
signal greater than 26 mVrms. LMC568 applications
include FM SCA and TV second audio program
decoders, FSK data demodulators, and voice pagers.
Typical Application
(100 kHz input frequency, refer to Notes to Typical Application)
Figure 1. 8-Pin SOIC or PDIP
See D or P Package
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2
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
All trademarks are the property of their respective owners.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 1999–2013, Texas Instruments Incorporated
LMC568
SNAS559B – MAY 1999 – REVISED APRIL 2013
www.ti.com
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
Absolute Maximum Ratings (1) (2)
Input Voltage, Pin 3
2 Vp–p
Supply Voltage, Pin 4
10V
Output Voltage, Pin 8
13V
Voltage at All Other Pins
Vs to Gnd
Output Current, Pin 8
30 mA
Package Dissipation
500 mW
−25°C to +125°C
Operating Temperature Range (TA)
−55°C to +150°C
Storage Temperature Range
Soldering Information
(1)
(2)
PDIP Package
Soldering (10 seconds)
260°C
SOIC Package
Vapor Phase (60 seconds)
215°C
Infrared (15 seconds)
220°C
“Absolute Maximum Ratings” indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for
which the device is functional, but do not ensure specific performance limits.
If Military/Aerospace specified devices are required, please contact the Texas Instruments Sales Office/Distributors for availability and
specifications.
Electrical Characteristics
Test Circuit, TA= 25°C, VS= 5V, RtCt #2, Sw. 1 Pos. 0; and no input unless otherwise noted.
Symbol
I4
Parameter
Power Supply Current
Conditions
RtCt # 1, Quiescent or Activated
Min
Typ
0.75
1.5
VS = 9V
1.2
2.4
Input D.C. Bias
0
Input Resistance
40
I8
Output Leakage
1
f0
Center Frequency Fosc ÷ 2 RtCt #2, Measure Oscillator Frequency and
Divide by 2
115
kHz
1.0
2.0
%/V
8
16
25
15
26
42
98
90
103
105
Center Frequency Shift
with Supply
VS = 2V
Set Input Frequency Equal to f0 Measured
Above, Increase Input Level until Pin 8 Goes VS = 5V
Low.
VS = 9V
Input Hysteresis
Starting at Input Threshold, Decrease Input Level until Pin
8 Goes High
V8
Output "Sat" Voltage
Input Level > Threshold Choose RL for
Specified I8
I8 = 2 mA
0.06
I8 = 20 mA
0.7
Measure Fosc with Sw. 1 in Pos. 0, 1, and 2;
VS = 2V
Largest Detection
Bandwidth
VS = 5V
VS = 9V
ΔBW
1.5
2
mVrms
0.15
Vdc
30
40
55
%
60
Bandwidth Skew
1
Vout
mVrms
45
ΔVin
L.D.B.W.
kΩ
nAdc
VS = 2V
VS = 5V
mVdc
100
VS = 9V
Input Threshold
mAdc
0.35
VS = 5V
R3
Vin
Units
VS = 2V
V3
Δf0
Max
Recovered Audio
Typical Application Circuit
Input = 100 mVrms, F = 100 kHz
Fmod = 400 Hz, ± 10 kHz Dev.
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VS = 2V
170
VS = 5V
270
VS = 9V
400
±5
%
mVrms
Copyright © 1999–2013, Texas Instruments Incorporated
Product Folder Links: LMC568
LMC568
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SNAS559B – MAY 1999 – REVISED APRIL 2013
Electrical Characteristics (continued)
Test Circuit, TA= 25°C, VS= 5V, RtCt #2, Sw. 1 Pos. 0; and no input unless otherwise noted.
Symbol
THD
fmax
Parameter
Conditions
Min
Typ
Max
Units
Total Harmonic Distortion
Typical Application Circuit as Above, Measure Vout
Distortion.
0.5
%
Signal to Noise Ratio
Typical Application Circuit
Remove Modulation, Measure Vn
(S + N)/N = 20 log (Vout/Vn).
65
dB
RtCt #3, Measure Oscillator Frequency and Divide by 2
700
kHz
Highest Center Freq.
Test Circuit
RtCt
Rt
Ct
#1
100k
300 pF
#2
10k
300 pF
#3
5.1k
62 pF
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3
LMC568
SNAS559B – MAY 1999 – REVISED APRIL 2013
www.ti.com
Notes to Typical Application
SUPPLY DECOUPLING
The decoupling of supply pin 4 becomes more critical at high supply voltages with high operating frequencies,
requiring C4 to be placed as close to possible to pin 4. Also, due to pin voltages tracking supply, a large C4 is
necessary for low frequency PSRR.
OSCILLATOR TIMING COMPONENTS
The voltage-controlled oscillator (VCO) on the LMC568 must be set up to run at twice the frequency of the input
signal. The components shown in the typical application are for Fosc = 200 kHz (100 kHz input frequency). For
operation at lower frequencies, increase the capacitor value; for higher frequencies proportionally reduce the
resistor values.
If low distortion is not a requirement, the series diode/resistor between pins 6 and 5 may be omitted. This will
reduce VCO supply dependence and increase Vout by approximately 2 dB with THD = 2% typical. The center
frequency as a function of Rt and Ct is given by:
(1)
To allow for I.C. and component value tolerences, the oscillator timing components will require a trim. This is
generally accomplished by using a variable resistor as part of Rt, although Ct could also be padded. The amount
of initial frequency variation due to the LMC568 itself is given in the electrical specifications; the total trim range
must also accommodate the tolerances of Rt and Ct.
INPUT PIN
The input pin 3 is internally ground-referenced with a nominal 40 kΩ resistor. Signals that are centered on 0V
may be directly coupled to pin 3; however, any d.c. potential must be isolated via C3.
OUTPUT TAKEOFF
The output signal is taken off the loop filter at pin 2. Pin 2 is the combined output of the phase detector and
control input of the VCO for the phase-locked loop (PLL). The nominal pin 2 source resistance is 80 kΩ, requiring
the use of an external buffer transistor to drive nominal loads.
For small values of C2, the PLL will have a fast acquisition time and the pull-in range will be set by the built-in
VCO frequency stops, which also determine the largest detection bandwidth (LDBW). Increasing C2 results in
improved noise immunity at the expense of acquisition time, and the pull-in range will become narrower than the
LDBW. However, the maximum hold-in range will always equal the LDBW. The 2 kHz de-emphasis pole shown
may be modified or omitted as required by the application.
CARRIER DETECT
Pin 1 is the output of a negative-going amplitude detector which has a nominal 0 signal output of 7/9 Vs. The
output at pin 8 is an N-channel FET switch to ground which is activated when the PLL is locked and the input is
of sufficient amplitude to cause pin 1 to fall below 2/3 Vs. The carrier detect threshold is internally set to 26
mVrms typical on a 5V supply.
Capacitor C1 in conjunction with the nominal 40 kΩ pin 1 internal resistance forms the output filter. The size of
C1 is a tradeoff between slew rate and carrier ripple at the output comparator. Optional resistor RH increases the
hysteresis in the pin 8 output for applications such as audio mute control. The minimum allowable value for RH is
330 kΩ.
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LMC568
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SNAS559B – MAY 1999 – REVISED APRIL 2013
LMC568 Typical Performance Characteristics
Frequency Drift with Temperature
Peak Deviation vs Input Signal Level
Figure 2.
Figure 3.
Pull-In Range as a Function of C2
Figure 4.
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Copyright © 1999–2013, Texas Instruments Incorporated
Product Folder Links: LMC568
5
LMC568
SNAS559B – MAY 1999 – REVISED APRIL 2013
www.ti.com
REVISION HISTORY
Changes from Revision A (April 2013) to Revision B
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Page
Changed layout of National Data Sheet to TI format ............................................................................................................ 5
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PACKAGE OPTION ADDENDUM
www.ti.com
5-Nov-2017
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
LMC568CM/NOPB
LIFEBUY
SOIC
D
8
LMC568CMX/NOPB
LIFEBUY
SOIC
D
8
2500
Eco Plan
Lead/Ball Finish
MSL Peak Temp
(2)
(6)
(3)
Op Temp (°C)
Device Marking
TBD
Call TI
Call TI
-25 to 100
LMC
568CM
Green (RoHS
& no Sb/Br)
CU SN
Level-1-260C-UNLIM
0 to 0
LMC
568CM
(4/5)
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of