LMC6022
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SNOS622D – NOVEMBER 1994 – REVISED MARCH 2013
LMC6022 Low Power CMOS Dual Operational Amplifier
Check for Samples: LMC6022
FEATURES
DESCRIPTION
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The LMC6022 is a CMOS dual operational amplifier
which can operate from either a single supply or dual
supplies. Its performance features include an input
common-mode range that reaches V−, low input bias
current, and voltage gain (into 100k and 5 kΩ loads)
that is equal to or better than widely accepted bipolar
equivalents, while the power supply requirement is
less than 0.5 mW.
1
2
Specified for 100 kΩ and 5 kΩ Loads
High Voltage Gain: 120 dB
Low Offset Voltage Drift: 2.5 μV/°C
Ultra Low Input Bias Current: 40 fA
Input Common-Mode Range Includes V−
Operating Range from +5V to +15V Supply
Low Distortion: 0.01% at 1 kHz
Slew Rate: 0.11 V/μs
Micropower Operation: 0.5 mW
APPLICATIONS
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This chip is built with National's advanced DoublePoly Silicon-Gate CMOS process.
See the LMC6024 datasheet for a CMOS quad
operational amplifier with these same features.
High-Impedance Buffer or Preamplifier
Current-to-Voltage Converter
Long-Term Integrator
Sample-and-Hold Circuit
Peak Detector
Medical Instrumentation
Industrial Controls
Connection Diagram
Figure 1. 8-Pin SOIC
Top View
Figure 2. LMC6022 Circuit Topology
(Each Amplifier)
1
2
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
All trademarks are the property of their respective owners.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 1994–2013, Texas Instruments Incorporated
LMC6022
SNOS622D – NOVEMBER 1994 – REVISED MARCH 2013
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These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
ABSOLUTE MAXIMUM RATINGS (1)
Differential Input Voltage
±Supply Voltage
Supply Voltage (V+ − V−)
16V
Lead Temperature (Soldering, 10 sec.)
260°C
−65°C to +150°C
Storage Temperature Range
Junction Temperature
150°C
ESD Tolerance (2)
1000V
(V+) +0.3V, (V−) −0.3V
Voltage at Output/Input Pin
Current at Output Pin
±18 mA
Current at Power Supply Pin
35 mA
Power Dissipation
See (3)
Current at Input Pin
±5 mA
Output Short Circuit to V−
See (4)
Output Short Circuit to V+
See (5)
(1)
Absolute Maximum Ratings indicate limits beyond which damage to component may occur. Operating Ratings indicate conditions for
which the device is intended to be functional, but do not guarantee specific performance limits. For guaranteed specifications and test
conditions, see the Electrical Characteristics. The guaranteed specifications apply only for the test conditions listed.
Human body model, 100 pF discharged through a 1.5 kΩ resistor.
The maximum power dissipation is a function of TJ(max), θJA and TA. The maximum allowable power dissipation at any ambient
temperature is PD = (TJ(max) − TA)/θJA.
Applies to both single-supply and split-supply operation. Continuous short circuit operation at elevated ambient temperature and/or
multiple Op Amp shorts can result in exceeding the maximum allowed junction temperature of 150°C. Output currents in excess of ±30
mA over long term may adversely affect reliability.
Do not connect output to V+ when V+ is greater than 13V or reliability may be adversely affected.
(2)
(3)
(4)
(5)
OPERATING RATINGS
−40°C ≤ TJ ≤ +85°C
Temperature Range
Supply Voltage Range
4.75V to 15.5V
See (1)
Power Dissipation
Thermal Resistance (θJA)
(2)
8-Pin SOIC
165°C/W
For operating at elevated temperatures the device must be derated based on the thermal resistance θJA with PD = (TJ−TA)/θJA.
All numbers apply for packages soldered directly into a PC board.
(1)
(2)
DC ELECTRICAL CHARACTERISTICS
The following specifications apply for V+ = 5V, V− = 0V, VCM = 1.5V, VO = 2.5V, and RL = 1M unless otherwise noted.
Boldface limits apply at the temperature extremes; all other limits TJ = 25°C.
Symbol
Parameter
Conditions
Typical (1)
Limit (2)
Units
VOS
Input Offset Voltage
ΔVOS/ΔT
Input Offset Voltage
Average Drift
2.5
μV/°C
IB
Input Bias Current
0.04
pA
IOS
Input Offset Current
0.01
RIN
(1)
(2)
2
1
LMC6022I
Input Resistance
>1
9
mV
11
max
200
max
100
max
pA
TeraΩ
Typical values represent the most likely parametric norm.
All limits are guaranteed by testing or correlation.
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DC ELECTRICAL CHARACTERISTICS (continued)
The following specifications apply for V+ = 5V, V− = 0V, VCM = 1.5V, VO = 2.5V, and RL = 1M unless otherwise noted.
Boldface limits apply at the temperature extremes; all other limits TJ = 25°C.
Symbol
CMRR
+PSRR
−PSRR
VCM
AV
Parameter
Conditions
Typical (1)
Common Mode Rejection
Ratio
0V ≤ VCM ≤ 12V
V+ = 15V
83
Positive Power Supply
Rejection Ratio
5V ≤ V+ ≤ 15V
83
Negative Power Supply
Rejection Ratio
0V ≤ V− ≤ −10V
Input Common-Mode
Voltage Range
V+ = 5V & 15V
For CMRR ≥ 50 dB
Large Signal Voltage Gain
RL = 100 kΩ (3)
Sinking
Sourcing
94
RL = 5 kΩ
Sourcing
Sinking
VO
Output Voltage Swing
V+ = 5V
RL = 100 kΩ to 2.5V
min
63
dB
61
min
−0.4
−0.1
V
0
max
V+ − 1.9
V+ − 2.3
V
V+ − 2.5
min
200
V/mV
1000
1000
100
min
90
V/mV
40
min
100
V/mV
75
min
250
50
V/mV
20
min
4.987
4.40
V
4.43
min
4.940
14.970
14.840
0.110
(3)
dB
61
dB
0.007
V+ = 15V
RL = 5 kΩ to 7.5V
63
min
0.040
V+ = 15V
RL = 100 kΩ to 7.5V
Units
73
0.004
V+ = 5V
RL = 5 kΩ to 2.5V
Limit (2)
74
500
(3)
LMC6022I
0.06
V
0.09
max
4.20
V
4.00
min
0.25
V
0.35
max
14.00
V
13.90
min
0.06
V
0.09
max
13.70
V
13.50
min
0.32
V
0.40
max
V+ = 15V, VCM = 7.5V, and RL connected to 7.5V. For Sourcing tests, 7.5V ≤ VO ≤ 11.5V. For Sinking tests, 2.5V ≤ VO ≤ 7.5V.
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DC ELECTRICAL CHARACTERISTICS (continued)
The following specifications apply for V+ = 5V, V− = 0V, VCM = 1.5V, VO = 2.5V, and RL = 1M unless otherwise noted.
Boldface limits apply at the temperature extremes; all other limits TJ = 25°C.
Symbol
IO
Parameter
V+ = 5V
Sourcing, VO = 0V
Sinking, VO = 5V (4)
Output Current
IS
Supply Current
(4)
Typical (1)
Conditions
LMC6022I
Limit (2)
22
21
V+ = 15V
Sourcing, VO = 0V
Sinking, VO = 13V (5)
40
Both Amplifiers
VO = 1.5V
Units
13
mA
9
min
13
mA
9
min
23
mA
15
min
39
23
mA
15
min
86
140
μA
165
max
Applies to both single-supply and split-supply operation. Continuous short circuit operation at elevated ambient temperature and/or
multiple Op Amp shorts can result in exceeding the maximum allowed junction temperature of 150°C. Output currents in excess of ±30
mA over long term may adversely affect reliability.
Do not connect output to V+ when V+ is greater than 13V or reliability may be adversely affected.
(5)
AC ELECTRICAL CHARACTERISTICS
The following specifications apply for V+ = 5V, V− = 0V, VCM = 1.5V, VO = 2.5V, and RL = 1M unless other otherwise noted.
Boldface limits apply at the temperature extremes; all other limits TJ = 25°C.
Symbol
Parameter
SR
Slew Rate
GBW
Gain-Bandwidth Product
φM
GM
Conditions
See (3)
Typical (1)
0.11
LMC6022I
Limit (2)
0.05
0.03
Units
V/μs
min
0.35
MHz
Phase Margin
50
Deg
Gain Margin
17
dB
(4)
Amp-to-Amp Isolation
See
130
dB
en
Input-Referred Voltage Noise
F = 1 kHz
42
nV/√Hz
in
Input-Referred Current Noise
F = 1 kHz
0.0002
pA/√Hz
(1)
(2)
(3)
(4)
4
Typical values represent the most likely parametric norm.
All limits are guaranteed by testing or correlation.
V+ = 15V. Connected as Voltage Follower with 10V step input. Number specified is the slower of the positive and negative slew rates.
Input referred. V+ = 15V and RL = 100 kΩ connected to 7.5V. Each amp excited in turn with 1 kHz to produce VO = 13 VPP.
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TYPICAL PERFORMANCE CHARACTERISTICS
VS = ±7.5V, TA = 25°C unless otherwise specified
Supply Current
vs. Supply Voltage
Input Bias Current
vs. Temperature
Figure 3.
Figure 4.
Input Common-ModeVoltage Range vs.Temperature
Output Characteristics Current Sinking
Figure 5.
Figure 6.
Output Characteristics Current Sourcing
Input Voltage Noise
vs. Frequency
Figure 7.
Figure 8.
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TYPICAL PERFORMANCE CHARACTERISTICS (continued)
VS = ±7.5V, TA = 25°C unless otherwise specified
6
Crosstalk Rejection
vs. Frequency
CMRR
vs. Frequency
Figure 9.
Figure 10.
CMRR
vs. Temperature
Power Supply Rejection Ratio
vs. Frequency
Figure 11.
Figure 12.
Open-Loop Voltage Gain
vs. Temperature
Open-Loop Frequency Response
Figure 13.
Figure 14.
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TYPICAL PERFORMANCE CHARACTERISTICS (continued)
VS = ±7.5V, TA = 25°C unless otherwise specified
Gain and Phase Responses
vs. Load Capacitance
Gain and Phase Responses
vs. Temperature
Figure 15.
Figure 16.
Gain Error (VOS
vs. VOUT)
Non-Inverting Slew Rate
vs. Temperature
Figure 17.
Figure 18.
Inverting Slew Rate
vs. Temperature
Large-Signal Pulse Non-Inverting Response
(AV = +1)
Figure 19.
Figure 20.
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TYPICAL PERFORMANCE CHARACTERISTICS (continued)
VS = ±7.5V, TA = 25°C unless otherwise specified
Non-Inverting Small Signal Pulse Response
(AV = +1)
Inverting Large-Signal Pulse Response
Figure 21.
Figure 22.
Inverting Small-Signal Pulse Response
Stability
vs. Capacitive Load
Figure 23.
Note: Avoid resistive loads of less than 500Ω, as they may cause
instability.
Figure 24.
Stability
vs. Capacitive Load
Figure 25.
8
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APPLICATION HINTS
AMPLIFIER TOPOLOGY
The topology chosen for the LMC6022 is unconventional (compared to general-purpose op amps) in that the
traditional unity-gain buffer output stage is not used; instead, the output is taken directly from the output of the
integrator, to allow rail-to-rail output swing. Since the buffer traditionally delivers the power to the load, while
maintaining high op amp gain and stability, and must withstand shorts to either rail, these tasks now fall to the
integrator.
As a result of these demands, the integrator is a compound affair with an embedded gain stage that is doubly fed
forward (via Cf and Cff) by a dedicated unity-gain compensation driver. In addition, the output portion of the
integrator is a push-pull configuration for delivering heavy loads. While sinking current the whole amplifier path
consists of three gain stages with one stage fed forward, whereas while sourcing the path contains four gain
stages with two fed forward.
Figure 26. LMC6022 Circuit Topology (Each Amplifier)
The large signal voltage gain while sourcing is comparable to traditional bipolar op amps for load resistance of at
least 5 kΩ. The gain while sinking is higher than most CMOS op amps, due to the additional gain stage;
however, when driving load resistance of 5 kΩ or less, the gain will be reduced as indicated in the Electrical
Characteristics. The op amp can drive load resistance as low as 500Ω without instability.
COMPENSATING INPUT CAPACITANCE
Refer to the LMC660 or LMC662 datasheets to determine whether or not a feedback capacitor will be necessary
for compensation and what the value of that capacitor would be.
CAPACITIVE LOAD TOLERANCE
Like many other op amps, the LMC6022 may oscillate when its applied load appears capacitive. The threshold of
oscillation varies both with load and circuit gain. The configuration most sensitive to oscillation is a unity-gain
follower. See the TYPICAL PERFORMANCE CHARACTERISTICS.
The load capacitance interacts with the op amp's output resistance to create an additional pole. If this pole
frequency is sufficiently low, it will degrade the op amp's phase margin so that the amplifier is no longer stable at
low gains. The addition of a small resistor (50Ω to 100Ω) in series with the op amp's output, and a capacitor (5
pF to 10 pF) from inverting input to output pins, returns the phase margin to a safe value without interfering with
lower-frequency circuit operation. Thus, larger values of capacitance can be tolerated without oscillation. Note
that in all cases, the output will ring heavily when the load capacitance is near the threshold for oscillation.
Figure 27. Rx, Cx Improve Capacitive Load Tolerance
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Capacitive load driving capability is enhanced by using a pull up resistor to V+ (Figure 28). Typically a pull up
resistor conducting 50 μA or more will significantly improve capacitive load responses. The value of the pull up
resistor must be determined based on the current sinking capability of the amplifier with respect to the desired
output swing. Open loop gain of the amplifier can also be affected by the pull up resistor (see Electrical
Characteristics).
Figure 28. Compensating for Large
Capacitive Loads with a Pull Up Resistor
PRINTED-CIRCUIT-BOARD LAYOUT FOR HIGH-IMPEDANCE WORK
It is generally recognized that any circuit which must operate with less than 1000 pA of leakage current requires
special layout of the PC board. When one wishes to take advantage of the ultra-low bias current of the
LMC6022, typically less than 0.04 pA, it is essential to have an excellent layout. Fortunately, the techniques for
obtaining low leakages are quite simple. First, the user must not ignore the surface leakage of the PC board,
even though it may sometimes appear acceptably low, because under conditions of high humidity or dust or
contamination, the surface leakage will be appreciable.
To minimize the effect of any surface leakage, lay out a ring of foil completely surrounding the LMC6022's inputs
and the terminals of capacitors, diodes, conductors, resistors, relay terminals, etc. connected to the op-amp's
inputs. See Figure 29. To have a significant effect, guard rings should be placed on both the top and bottom of
the PC board. This PC foil must then be connected to a voltage which is at the same voltage as the amplifier
inputs, since no leakage current can flow between two points at the same potential. For example, a PC board
trace-to-pad resistance of 1012Ω, which is normally considered a very large resistance, could leak 5 pA if the
trace were a 5V bus adjacent to the pad of an input. This would cause a 100 times degradation from the
LMC6022's actual performance. However, if a guard ring is held within 5 mV of the inputs, then even a
resistance of 1011Ω would cause only 0.05 pA of leakage current, or perhaps a minor (2:1) degradation of the
amplifier's performance. See Figure 30a, Figure 30b, Figure 30c for typical connections of guard rings for
standard op-amp configurations. If both inputs are active and at high impedance, the guard can be tied to ground
and still provide some protection; see Figure 30d.
Figure 29. Example of Guard Ring in P.C. Board Layout (Using the LMC6024)
10
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(a) Inverting Amplifier Guard Ring Connections
(b) Non-Inverting Amplifier Guard Ring Connections
(c) Follower Guard Ring Connections
(d) Howland Current Pump Guard Ring Connections
Figure 30. Guard Ring Connections
The designer should be aware that when it is inappropriate to lay out a PC board for the sake of just a few
circuits, there is another technique which is even better than a guard ring on a PC board: Don't insert the
amplifier's input pin into the board at all, but bend it up in the air and use only air as an insulator. Air is an
excellent insulator. In this case you may have to forego some of the advantages of PC board construction, but
the advantages are sometimes well worth the effort of using point-to-point up-in-the-air wiring. See Figure 31.
(Input pins are lifted out of PC board and soldered directly to components. All other pins connected to PC board.)
Figure 31. Air Wiring
BIAS CURRENT TESTING
The test method of Figure 32 is appropriate for bench-testing bias current with reasonable accuracy. To
understand its operation, first close switch S2 momentarily. When S2 is opened, then
(1)
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Figure 32. Simple Input Bias Current Test Circuit
A suitable capacitor for C2 would be a 5 pF or 10 pF silver mica, NPO ceramic, or air-dielectric. When
determining the magnitude of I−, the leakage of the capacitor and socket must be taken into account. Switch S2
should be left shorted most of the time, or else the dielectric absorption of the capacitor C2 could cause errors.
Similarly, if S1 is shorted momentarily (while leaving S2 shorted)
(2)
where Cx is the stray capacitance at the + input.
Typical Single-Supply Applications
(V+ = 5.0 VDC)
Note: A 5V bias on the photodiode can cut its capacitance by a factor of 2 or 3, leading to improved response and
lower noise. However, this bias on the photodiode will cause photodiode leakage (also known as its dark current).
Figure 33. Photodiode Current-to-Voltage Converter
(Upper limit of output range dictated by input common-mode range;
lower limit dictated by minimum current requirement of LM385.)
Figure 34. Micropower Current Source
12
Figure 35. Low-Leakage Sample-and-Hold
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(V+ = 5.0 VDC)
If R1 = R5, R3 = R6, and R4 = R7;
Then
∴AV ≈ 100 for circuit shown
For good CMRR over temperature, low drift resistors should be used. Matching of R3 to R6 and R4 to R7 affects
CMRR. Gain may be adjusted through R2. CMRR may be adjusted through R7.
Figure 36. Instrumentation Amplifier
Oscillator frequency is determined by R1, R2, C1, and C2:
fOSC = 1/2πRC
where R = R1 = R2 and C = C1 = C2.
This circuit, as shown, oscillates at 2.0 kHz with a peak-to-peak output swing of 4.5V.
Figure 37. Sine-Wave Oscillator
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(V+ = 5.0 VDC)
Figure 38. 1 Hz Square-Wave Oscillator
Figure 39. Power Amplifier
fc = 10 Hz
d = 0.895
Gain = 1
fO = 10 Hz
Q = 2.1
Gain = −8.8
Figure 40. 10 Hz Bandpass Filter
Figure 41. 10 Hz High-Pass Filter (2 dB Dip)
Figure 42. 1 Hz Low-Pass Filter (Maximally Flat, Dual Supply Only)
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(V+ = 5.0 VDC)
Gain = −46.8
Output offset voltage reduced to the level of the input offset voltage of the bottom amplifier (typically 1 mV), referred
to VBIAS.
Figure 43. High Gain Amplifier with Offset Voltage Reduction
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REVISION HISTORY
Changes from Revision C (March 2013) to Revision D
•
16
Page
Changed layout of National Data Sheet to TI format .......................................................................................................... 15
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PACKAGE OPTION ADDENDUM
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10-Dec-2020
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
(4/5)
(6)
LMC6022IM/NOPB
ACTIVE
SOIC
D
8
95
RoHS & Green
SN
Level-1-260C-UNLIM
-40 to 85
LMC60
22IM
LMC6022IMX/NOPB
ACTIVE
SOIC
D
8
2500
RoHS & Green
SN
Level-1-260C-UNLIM
-40 to 85
LMC60
22IM
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of
