LMC660
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LMC660 CMOS Quad Operational Amplifier
Check for Samples: LMC660
FEATURES
DESCRIPTION
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The LMC660 CMOS Quad operational amplifier is
ideal for operation from a single supply. It operates
from +5V to +15.5V and features rail-to-rail output
swing in addition to an input common-mode range
that includes ground. Performance limitations that
have plagued CMOS amplifiers in the past are not a
problem with this design. Input VOS, drift, and
broadband noise as well as voltage gain into realistic
loads (2 kΩ and 600Ω) are all equal to or better than
widely accepted bipolar equivalents.
1
2
Rail-to-Rail Output Swing
Specified for 2 kΩ and 600Ω Loads
High Voltage Gain: 126 dB
Low Input Offset Voltage: 3 mV
Low Offset Voltage Drift: 1.3 μV/°C
Ultra Low Input Bias Current: 2 fA
Input Common-Mode Range Includes V−
Operating Range from +5V to +15.5V Supply
ISS = 375 μA/Amplifier; Independent of V+
Low Distortion: 0.01% at 10 kHz
Slew Rate: 1.1 V/μs
This chip is built with TI's advanced Double-Poly
Silicon-Gate CMOS process.
See the LMC662 datasheet for a dual CMOS
operational amplifier with these same features.
APPLICATIONS
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High-Impedance Buffer or Preamplifier
Precision Current-to-Voltage Converter
Long-Term Integrator
Sample-and-Hold Circuit
Peak Detector
Medical Instrumentation
Industrial Controls
Automotive Sensors
Connection Diagrams
Figure 1. 14-Pin SOIC/PDIP
Figure 2. LMC660 Circuit Topology (Each
Amplifier)
1
2
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
All trademarks are the property of their respective owners.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 1998–2013, Texas Instruments Incorporated
LMC660
SNOSBZ3D – APRIL 1998 – REVISED MARCH 2013
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These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
Absolute Maximum Ratings (1)
Differential Input Voltage
±Supply Voltage
Supply Voltage
16V
Output Short Circuit to V+
See (2)
Output Short Circuit to V−
See (3)
Lead Temperature
(Soldering, 10 sec.)
260°C
−65°C to +150°C
Storage Temp. Range
(V+) + 0.3V, (V−) − 0.3V
Voltage at Input/Output Pins
Current at Output Pin
±18 mA
Current at Input Pin
±5 mA
Current at Power Supply Pin
35 mA
Power Dissipation
See (4)
Junction Temperature
150°C
ESD tolerance (5)
1000V
(1)
(2)
(3)
(4)
(5)
Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for
which the device is intended to be functional, but do not ensure specific performance limits. For ensured specifications and test
conditions, see the Electrical Characteristics. The ensured specifications apply only for the test conditions listed.
Do not connect output to V+ when V+ is greater than 13V or reliability may be adversely affected.
Applies to both single supply and split supply operation. Continuous short circuit operation at elevated ambient temperature and/or
multiple Op Amp shorts can result in exceeding the maximum allowed junction temperature of 150°C. Output currents in excess of ±30
mA over long term may adversely affect reliability.
The maximum power dissipation is a function of TJ(MAX), θJA, and TA. The maximum allowable power dissipation at any ambient
temperature is PD = (TJ(MAX) − TA)/θJA.
Human Body Model is 1.5 kΩ in series with 100 pF.
Operating Ratings
Temperature Range
LMC660AI
−40°C ≤ TJ ≤ +85°C
LMC660C
0°C ≤ TJ ≤ +70°C
Supply Voltage Range
4.75V to 15.5V
See (1)
Power Dissipation
Thermal Resistance (θJA) (2)
(1)
(2)
2
14-Pin SOIC
115°C/W
14-Pin PDIP
85°C/W
For operating at elevated temperatures the device must be derated based on the thermal resistance θJA with PD = (TJ − TA)/θJA.
All numbers apply for packages soldered directly into a PC board.
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DC Electrical Characteristics
Unless otherwise specified, all limits ensured for TJ = 25°C. Boldface limits apply at the temperature extremes. V+ = 5V, V− =
0V, VCM = 1.5V, VO = 2.5V and RL > 1MΩ unless otherwise specified.
Parameter
Test Conditions
Input Offset Voltage
Typ (1)
LMC660AI
Limit (1)
1
LMC660C
Limit (1)
Units
3
6
mV
3.3
6.3
max
1.3
μV/°C
Input Bias Current
0.002
pA
Input Offset Current
0.001
Input Offset Voltage Average Drift
Input Resistance
4
2
max
2
1
max
70
63
dB
68
62
min
70
63
dB
68
62
min
84
74
dB
83
73
min
−0.1
−0.1
V
0
0
max
V+ − 2.3
V+ − 2.3
V
pA
>1
Common Mode
0V ≤ VCM ≤ 12.0V
Rejection Ratio
V+ = 15V
Positive Power Supply
5V ≤ V+ ≤ 15V
Rejection Ratio
VO = 2.5V
Negative Power Supply
0V ≤ V− ≤ −10V
TeraΩ
83
83
94
Rejection Ratio
Input Common-Mode
V+ = 5V & 15V
Voltage Range
For CMRR ≥ 50 dB
−0.4
V+ − 1.9
+
Large Signal
Voltage Gain
Output Swing
V − 2.5
V − 2.4
min
RL = 2 kΩ (2)
Sourcing
Sinking
2000
440
400
300
200
V/mV
min
500
180
120
90
80
V/mV
min
RL = 600Ω (2)
Sourcing
Sinking
1000
220
200
150
100
V/mV
min
250
100
60
50
40
V/mV
min
V+ = 5V
4.87
4.82
4.78
V
4.79
4.76
min
0.15
0.19
V
0.17
0.21
max
4.41
4.27
V
4.31
4.21
min
0.50
0.63
V
0.56
0.69
max
14.50
14.37
V
14.44
14.32
min
0.35
0.44
V
0.40
0.48
max
13.35
12.92
V
13.15
12.76
min
1.16
1.45
V
1.32
1.58
max
RL = 2 kΩ to V+/2
0.10
V+ = 5V
4.61
+
RL = 600Ω to V /2
0.30
V+ = 15V
14.63
RL = 2 kΩ to V+/2
0.26
V+ = 15V
13.90
RL = 600Ω to V+/2
0.79
(1)
(2)
+
Typical values represent the most likely parametric norm. Limits are specified by testing or correlation.
V+ = 15V, VCM = 7.5V and RL connected to 7.5V. For Sourcing tests, 7.5V ≤ VO ≤ 11.5V. For Sinking tests, 2.5V ≤ VO ≤ 7.5V.
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DC Electrical Characteristics (continued)
Unless otherwise specified, all limits ensured for TJ = 25°C. Boldface limits apply at the temperature extremes. V+ = 5V, V− =
0V, VCM = 1.5V, VO = 2.5V and RL > 1MΩ unless otherwise specified.
Parameter
Output Current
Test Conditions
Sourcing, VO = 0V
Typ (1)
LMC660AI
Limit (1)
LMC660C
Limit (1)
22
16
13
mA
14
11
min
16
13
mA
14
11
min
28
23
mA
25
21
min
23
mA
min
V+ = 5V
Sinking, VO = 5V
Output Current
Sourcing, VO = 0V
21
40
V+ = 15V
Supply Current
Sinking, VO = 13V (3)
39
28
24
20
All Four Amplifiers
1.5
2.2
2.7
mA
2.6
2.9
max
VO = 1.5V
(3)
Units
Do not connect output to V+ when V+ is greater than 13V or reliability may be adversely affected.
AC Electrical Characteristics
Unless otherwise specified, all limits ensured for TJ = 25°C. Boldface limits apply at the temperature extremes. V+ = 5V, V− =
0V, VCM = 1.5V, VO = 2.5V and RL > 1MΩ unless otherwise specified.
Parameter
Slew Rate
Test Conditions
See (2)
Typ (1)
LMC660AI
Limit (1)
LMC660C
Limit (1)
Units
1.1
0.8
0.8
V/μs
0.6
0.7
min
Gain-Bandwidth Product
1.4
MHz
Phase Margin
50
Deg
17
dB
Gain Margin
Amp-to-Amp Isolation
See (3)
130
dB
Input Referred Voltage Noise
F = 1 kHz
22
nV/√Hz
Input Referred Current Noise
f = 1 kHz
0.0002
pA//√Hz
Total Harmonic Distortion
f = 10 kHz, AV = −10
RL = 2 kΩ, VO = 8 VPP
V+ = 15V
0.01
%
(1)
(2)
(3)
4
Typical values represent the most likely parametric norm. Limits are specified by testing or correlation.
V+ = 15V. Connected as Voltage Follower with 10V step input. Number specified is the slower of the positive and negative slew rates.
Input referred. V+ = 15V and RL = 10 kΩ connected to V+/2. Each amp excited in turn with 1 kHz to produce VO = 13 VPP.
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Typical Performance Characteristics
VS = ±7.5V, TA = 25°C unless otherwise specified.
Supply Current
vs.
Supply Voltage
Offset Voltage
Figure 3.
Figure 4.
Input Bias Current
Output Characteristics Current Sinking
Figure 5.
Figure 6.
Output Characteristics Current Sourcing
Input Voltage Noise
vs.
Frequency
Figure 7.
Figure 8.
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Typical Performance Characteristics (continued)
VS = ±7.5V, TA = 25°C unless otherwise specified.
6
CMRR
vs.
Frequency
Open-Loop Frequency Response
Figure 9.
Figure 10.
Frequency Response
vs.
Capacitive Load
Non-Inverting Large Signal Pulse Response
Figure 11.
Figure 12.
Stability
vs.
Capacitive Load
Stability
vs.
Capacitive Load
Figure 13.
Figure 14.
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APPLICATION INFORMATION
AMPLIFIER TOPOLOGY
The topology chosen for the LMC660, shown in Figure 15, is unconventional (compared to general-purpose op
amps) in that the traditional unity-gain buffer output stage is not used; instead, the output is taken directly from
the output of the integrator, to allow rail-to-rail output swing. Since the buffer traditionally delivers the power to
the load, while maintaining high op amp gain and stability, and must withstand shorts to either rail, these tasks
now fall to the integrator.
As a result of these demands, the integrator is a compound affair with an embedded gain stage that is doubly fed
forward (via Cf and Cff) by a dedicated unity-gain compensation driver. In addition, the output portion of the
integrator is a push-pull configuration for delivering heavy loads. While sinking current the whole amplifier path
consists of three gain stages with one stage fed forward, whereas while sourcing the path contains four gain
stages with two fed forward.
Figure 15. LMC660 Circuit Topology (Each Amplifier)
The large signal voltage gain while sourcing is comparable to traditional bipolar op amps, even with a 600Ω load.
The gain while sinking is higher than most CMOS op amps, due to the additional gain stage; however, under
heavy load (600Ω) the gain will be reduced as indicated in DC Electrical Characteristics. Avoid resistive loads of
less than 500Ω, as they may cause instability.
COMPENSATING INPUT CAPACITANCE
The high input resistance of the LMC660 op amps allows the use of large feedback and source resistor values
without losing gain accuracy due to loading. However, the circuit will be especially sensitive to its layout when
these large-value resistors are used.
Every amplifier has some capacitance between each input and AC ground, and also some differential
capacitance between the inputs. When the feedback network around an amplifier is resistive, this input
capacitance (along with any additional capacitance due to circuit board traces, the socket, etc.) and the feedback
resistors create a pole in the feedback path. In the following General Operational Amplifier circuit, Figure 16 the
frequency of this pole is:
(1)
where CS is the total capacitance at the inverting input, including amplifier input capacitance and any stray
capacitance from the IC socket (if one is used), circuit board traces, etc., and RP is the parallel combination of RF
and RIN. This formula, as well as all formulae derived below, apply to inverting and non-inverting op amp
configurations.
When the feedback resistors are smaller than a few kΩ, the frequency of the feedback pole will be quite high,
since CS is generally less than 10 pF. If the frequency of the feedback pole is much higher than the “ideal”
closed-loop bandwidth (the nominal closed-loop bandwidth in the absence of CS), the pole will have a negligible
effect on stability, as it will add only a small amount of phase shift.
However, if the feedback pole is less than approximately 6 to 10 times the “ideal” −3 dB frequency, a feedback
capacitor, CF, should be connected between the output and the inverting input of the op amp. This condition can
also be stated in terms of the amplifier's low-frequency noise gain: To maintain stability a feedback capacitor will
probably be needed if:
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(2)
where:
(3)
is the amplifier's low-frequency noise gain and GBW is the amplifier's gain bandwidth product. An amplifier's lowfrequency noise gain is represented by the formula:
(4)
regardless of whether the amplifier is being used in inverting or non-inverting mode. Note that a feedback
capacitor is more likely to be needed when the noise gain is low and/or the feedback resistor is large.
If the above condition is met (indicating a feedback capacitor will probably be needed), and the noise gain is
large enough that:
(5)
the following value of feedback capacitor is recommended:
(6)
If
(7)
the feedback capacitor should be:
(8)
Note that these capacitor values are usually significant smaller than those given by the older, more conservative
formula:
(9)
CS consists of the amplifier's input capacitance plus any stray capacitance from the circuit board and socket. CF
compensates for the pole caused by CS and the feedback resistors.
Figure 16. General Operational Amplifier Circuit
Using the smaller capacitors will give much higher bandwidth with little degradation of transient response. It may
be necessary in any of the above cases to use a somewhat larger feedback capacitor to allow for unexpected
stray capacitance, or to tolerate additional phase shifts in the loop, or excessive capacitive load, or to decrease
the noise or bandwidth, or simply because the particular circuit implementation needs more feedback
capacitance to be sufficiently stable. For example, a printed circuit board's stray capacitance may be larger or
smaller than the breadboard's, so the actual optimum value for CF may be different from the one estimated using
the breadboard. In most cases, the values of CF should be checked on the actual circuit, starting with the
computed value.
8
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CAPACITIVE LOAD TOLERANCE
Like many other op amps, the LMC660 may oscillate when its applied load appears capacitive. The threshold of
oscillation varies both with load and circuit gain. The configuration most sensitive to oscillation is a unity-gain
follower. See Typical Performance Characteristics.
The load capacitance interacts with the op amp's output resistance to create an additional pole. If this pole
frequency is sufficiently low, it will degrade the op amp's phase margin so that the amplifier is no longer stable at
low gains. As shown in Figure 17, the addition of a small resistor (50Ω to 100Ω) in series with the op amp's
output, and a capacitor (5 pF to 10 pF) from inverting input to output pins, returns the phase margin to a safe
value without interfering with lower-frequency circuit operation. Thus larger values of capacitance can be
tolerated without oscillation. Note that in all cases, the output will ring heavily when the load capacitance is near
the threshold for oscillation.
Figure 17. Rx, Cx Improve Capacitive Load Tolerance
Capacitive load driving capability is enhanced by using a pull up resistor to V+ (Figure 18). Typically a pull up
resistor conducting 500 μA or more will significantly improve capacitive load responses. The value of the pull up
resistor must be determined based on the current sinking capability of the amplifier with respect to the desired
output swing. Open loop gain of the amplifier can also be affected by the pull up resistor (see DC Electrical
Characteristics).
Figure 18. Compensating for Large Capacitive Loads with a Pull Up Resistor
PRINTED-CIRCUIT-BOARD LAYOUT FOR HIGH-IMPEDANCE WORK
It is generally recognized that any circuit which must operate with less than 1000 pA of leakage current requires
special layout of the PC board. When one wishes to take advantage of the ultra-low bias current of the LMC662,
typically less than 0.04 pA, it is essential to have an excellent layout. Fortunately, the techniques for obtaining
low leakages are quite simple. First, the user must not ignore the surface leakage of the PC board, even though
it may sometimes appear acceptably low, because under conditions of high humidity or dust or contamination,
the surface leakage will be appreciable.
To minimize the effect of any surface leakage, lay out a ring of foil completely surrounding the LMC660's inputs
and the terminals of capacitors, diodes, conductors, resistors, relay terminals, etc. connected to the op amp's
inputs. See Figure 19. To have a significant effect, guard rings should be placed on both the top and bottom of
the PC board. This PC foil must then be connected to a voltage which is at the same voltage as the amplifier
inputs, since no leakage current can flow between two points at the same potential. For example, a PC board
trace-to-pad resistance of 1012Ω, which is normally considered a very large resistance, could leak 5 pA if the
trace were a 5V bus adjacent to the pad of an input. This would cause a 100 times degradation from the
LMC660's actual performance. However, if a guard ring is held within 5 mV of the inputs, then even a resistance
of 1011Ω would cause only 0.05 pA of leakage current, or perhaps a minor (2:1) degradation of the amplifier's
performance. See Figure 20a, Figure 20b, and Figure 20c for typical connections of guard rings for standard op
amp configurations. If both inputs are active and at high impedance, the guard can be tied to ground and still
provide some protection; see Figure 20d.
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Figure 19. Example, using the LMC660, of Guard Ring in P.C. Board Layout
(a) Inverting Amplifier
(b) Non-Inverting Amplifier
(c) Follower
(d) Howland Current Pump
Figure 20. Guard Ring Connections
10
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The designer should be aware that when it is inappropriate to lay out a PC board for the sake of just a few
circuits, there is another technique which is even better than a guard ring on a PC board: Don't insert the
amplifier's input pin into the board at all, but bend it up in the air and use only air as an insulator. Air is an
excellent insulator. In this case you may have to forego some of the advantages of PC board construction, but
the advantages are sometimes well worth the effort of using point-to-point up-in-the-air wiring. See Figure 21.
(Input pins are lifted out of PC board and soldered directly to components. All other pins connected to PC board.)
Figure 21. Air Wiring
BIAS CURRENT TESTING
The test method of Figure 21 is appropriate for bench-testing bias current with reasonable accuracy. To
understand its operation, first close switch S2 momentarily. When S2 is opened, then:
(10)
Figure 22. Simple Input Bias Current Test Circuit
A suitable capacitor for C2 would be a 5 pF or 10 pF silver mica, NPO ceramic, or air-dielectric. When
determining the magnitude of Ib−, the leakage of the capacitor and socket must be taken into account. Switch S2
should be left shorted most of the time, or else the dielectric absorption of the capacitor C2 could cause errors.
Similarly, if S1 is shorted momentarily (while leaving S2 shorted):
(11)
where Cx is the stray capacitance at the + input.
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TYPICAL SINGLE-SUPPLY APPLICATIONS
(V+ = 5.0 VDC)
Additional single-supply applications ideas can be found in the LM324 datasheet. The LMC660 is pin-for-pin
compatible with the LM324 and offers greater bandwidth and input resistance over the LM324. These features
will improve the performance of many existing single-supply applications. Note, however, that the supply voltage
range of the LMC660 is smaller than that of the LM324.
Figure 23. Low-Leakage Sample-and-Hold
Figure 24. Instrumentation Amplifier
If R1 = R5, R3 = R6, and R4 = R7; then
(12)
∴ AV ≈100 for circuit shown.
For good CMRR over temperature, low drift resistors should be used. Matching of R3 to R6 and R4 to R7 affect
CMRR. Gain may be adjusted through R2. CMRR may be adjusted through R7.
Figure 25. Sine-Wave Oscillator
Oscillator frequency is determined by R1, R2, C1, and C2:
12
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TYPICAL SINGLE-SUPPLY APPLICATIONS (continued)
+
(V = 5.0 VDC)
fosc = 1/2πRC, where R = R1 = R2 and
C = C1 = C2.
This circuit, as shown, oscillates at 2.0 kHz with a peak-to-peak output swing of 4.5V.
Figure 26. 1 Hz Square-Wave Oscillator
Figure 27. Power Amplifier
Figure 28. 10 Hz Bandpass Filter
fO = 10 Hz
Q = 2.1
Gain = −8.8
Figure 29. 10 Hz High-Pass Filter
fc = 10 Hz
d = 0.895
Gain = 1
2 dB passband ripple
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TYPICAL SINGLE-SUPPLY APPLICATIONS (continued)
+
(V = 5.0 VDC)
Figure 30. 1 Hz Low-Pass Filter
(Maximally Flat, Dual Supply Only)
fc = 1 Hz
d = 1.414
Gain = 1.57
Figure 31. High Gain Amplifier with Offset
Voltage Reduction
Gain = −46.8
Output offset voltage reduced to the level of the input offset voltage of the bottom amplifier (typically 1 mV).
14
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REVISION HISTORY
Changes from Revision C (March 2013) to Revision D
•
Page
Changed layout of National Data Sheet to TI format .......................................................................................................... 14
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PACKAGE OPTION ADDENDUM
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19-Mar-2015
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
Lead/Ball Finish
MSL Peak Temp
(2)
(6)
(3)
Op Temp (°C)
Device Marking
(4/5)
LMC660AIM
NRND
SOIC
D
14
55
TBD
Call TI
Call TI
-40 to 85
LMC660AIM
LMC660AIM/NOPB
ACTIVE
SOIC
D
14
55
Green (RoHS
& no Sb/Br)
CU SN
Level-1-260C-UNLIM
-40 to 85
LMC660AIM
LMC660AIMX
NRND
SOIC
D
14
2500
TBD
Call TI
Call TI
-40 to 85
LMC660AIM
LMC660AIMX/NOPB
ACTIVE
SOIC
D
14
2500
Green (RoHS
& no Sb/Br)
CU SN
Level-1-260C-UNLIM
-40 to 85
LMC660AIM
LMC660AIN/NOPB
ACTIVE
PDIP
NFF
14
25
Green (RoHS
& no Sb/Br)
CU SN
Level-1-NA-UNLIM
-40 to 85
LMC660AIN
LMC660CM
NRND
SOIC
D
14
55
TBD
Call TI
Call TI
0 to 70
LMC660CM
LMC660CM/NOPB
ACTIVE
SOIC
D
14
55
Green (RoHS
& no Sb/Br)
CU SN
Level-1-260C-UNLIM
0 to 70
LMC660CM
LMC660CMX/NOPB
ACTIVE
SOIC
D
14
2500
Green (RoHS
& no Sb/Br)
CU SN
Level-1-260C-UNLIM
0 to 70
LMC660CM
LMC660CN/NOPB
ACTIVE
PDIP
NFF
14
25
Green (RoHS
& no Sb/Br)
CU SN
Level-1-NA-UNLIM
0 to 70
LMC660CN
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
Addendum-Page 1
Samples
PACKAGE OPTION ADDENDUM
www.ti.com
19-Mar-2015
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
5-Dec-2014
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
Diameter Width (mm)
(mm) W1 (mm)
B0
(mm)
K0
(mm)
P1
(mm)
W
Pin1
(mm) Quadrant
LMC660AIMX
SOIC
D
14
2500
330.0
16.4
6.5
9.35
2.3
8.0
16.0
Q1
LMC660AIMX/NOPB
SOIC
D
14
2500
330.0
16.4
6.5
9.35
2.3
8.0
16.0
Q1
LMC660CMX/NOPB
SOIC
D
14
2500
330.0
16.4
6.5
9.35
2.3
8.0
16.0
Q1
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
5-Dec-2014
*All dimensions are nominal
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
LMC660AIMX
SOIC
D
14
2500
367.0
367.0
35.0
LMC660AIMX/NOPB
SOIC
D
14
2500
367.0
367.0
35.0
LMC660CMX/NOPB
SOIC
D
14
2500
367.0
367.0
35.0
Pack Materials-Page 2
MECHANICAL DATA
NFF0014A
N0014A
N14A (Rev G)
www.ti.com
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