LMC6953CMX/NOPB

LMC6953 www.ti.com SNVS132D – APRIL 1998 – REVISED APRIL 2013 LMC6953 PCI Local Bus Power Supervisor Check for Samples: LMC6953 FEATURES DESCRIPTION • • The LMC6953 is a voltage supervisory chip designed to meet PCI (Peripheral Component Interconnect) Specifications Revision 2.1. It monitors 5V and 3.3V power supplies. In cases of power-up, power-down, brown-out, power failure and manual reset interrupt, the LMC6953 provides an active low reset. RESET holds low for 100 ms after both 5V and 3.3V powers recover, or after manual reset signal returns to high state. The external capacitor on pin 8 adjusts the reset delay. 1 2 • • • • • • • • • Compliant to PCI Specifications Revision 2.1. Under and Over Voltage Detectors for 5V and 3.3V Power Failure Detection (5V Falling Under 3.3V by 300 mV Max) Manual Reset Input Pin Specified RESET Assertion at VDD = 1.5V Integrated Reset Delay Circuitry Open Drain Output Adjustable Reset Delay Response Time for Over and Under Voltage Detection: 490 ns Max Power Failure Response Time: 90 ns Max Requires Minimal External Components APPLICATIONS • • • This part is ideal on PCI motherboards or add-in cards to ensure the integrity of the entire system when there is a fault condition. The active low reset sets the microprocessor or local device in a known state. The LMC6953 has a built-in bandgap reference that accurately determines all the threshold voltages. The internal reset delay circuitry eliminates additional discrete components. Desktop PCs PCI-Based Systems Network servers Typical Application Circuits Figure 1. On Mother Board Figure 2. On Add-in Cards 1 2 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. All trademarks are the property of their respective owners. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright © 1998–2013, Texas Instruments Incorporated LMC6953 SNVS132D – APRIL 1998 – REVISED APRIL 2013 www.ti.com Connection Diagram Figure 3. 8–Pin SOIC Top View These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates. ABSOLUTE MAXIMUM RATINGS (1) (2) ESD Tolerance (3) Human Body Model 2 kV Machine Model 200V Voltage at Input Pin 7V Supply Voltage 7V Current at Output Pin Current at Power Supply Pin 15 mA (4) 10 mA Lead Temp. (Soldering, 10 sec.) 260°C −65°C to +150°C Storage Temperature Range Junction Temperature (1) (2) (3) (4) 150°C Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for which the device is intended to be functional, but specific performance is not ensured. For ensured specifications and the test conditions, see DC ELECTRICAL CHARACTERISTICS and AC ELECTRICAL CHARACTERISTICS. If Military/Aerospace specified devices are required, please contact the Texas Instruments Sales Office/Distributors for availability and specifications. Human body model, 1.5 kΩ in series with 100 pF. Machine model. 200Ω in series with 100 pF. Supply current measured at pins 1, 2, and 3. The 4.7 kΩ pull-up resistor on pin 7 is not tied to VDDin this measurement. OPERATING RATINGS (1) Supply Voltage 1.5V to 6V Junction Temperature Range −40°C to +85°C LMC6953C Thermal Resistance (θJA) D Package (1) 2 165°C/W Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for which the device is intended to be functional, but specific performance is not ensured. For ensured specifications and the test conditions, see DC ELECTRICAL CHARACTERISTICS and AC ELECTRICAL CHARACTERISTICS. Submit Documentation Feedback Copyright © 1998–2013, Texas Instruments Incorporated Product Folder Links: LMC6953 LMC6953 www.ti.com SNVS132D – APRIL 1998 – REVISED APRIL 2013 DC ELECTRICAL CHARACTERISTICS Unless otherwise specified, all boldface limits specified for TJ = −40°C to +85°C, VDD = 5V, RPULL-UP = 4.7 kΩ and CEXT = 0.01 μF. Typical numbers are room temperature (25°C) performance. Symbol VH5 Parameter Conditions VDD Over-Voltage Threshold TJ = 0°C to 70°C (1) TJ = −40°C to 85°C VL5 VDD Under-Voltage Threshold TJ = 0°C to 70°C (1) TJ = −40°C to 85°C VH3.3 3.3V Over-Voltage Threshold TJ = 0°C to 70°C 3.3V Under-Voltage Threshold TJ = 0°C to 70°C Manual RESET Threshold VPF Power Failure Differential Voltage (2) (2) TJ = −40°C to 85°C VMR (1) (2) TJ = −40°C to 85°C VL3.3 (1) (2) Min Typ Max Units 5.45 5.60 5.75 V 5.30 5.60 5.90 V 4.25 4.40 4.55 V 4.10 4.40 4.70 V 3.80 3.95 4.10 V 3.60 3.95 4.30 V 2.50 2.65 2.80 V 2.30 2.65 3.00 V 2.50 2.80 V 150 300 mV (3) (3.3V Pin–5V Pin) RIN Input Resistance at 5V and 3.3V Pins VOL RESET Output Low 35 TJ = 0°C to 70°C VDD = 1.5V to 6V TJ = −40°C to 85°C VDD = 1.55V to 6V IS (1) (2) (3) (4) (4) Supply Current kΩ 0.05 0.10 V 0.8 1.50 mA PCI Specifications Revision 2.1, Section 4.2.1.1 and Section 4.3.2. PCI Specifications Revision 2.1, Section 4.2.2.1 and Section 4.3.2. PCI Specifications Revision 2.1 and Section 4.3.2. Supply current measured at pins 1, 2, and 3. The 4.7 kΩ pull-up resistor on pin 7 is not tied to VDDin this measurement. AC ELECTRICAL CHARACTERISTICS Unless otherwise specified, all boldface limits specified for TJ = −40°C to 85°C, VDD = 5V, RPULL-UP = 4.7 kΩ and CEXT = 0.01 μF. Typical numbers are room temperature (25°C) performance. Symbol Parameter Conditions Typ LMC6953 Limit 490 tD Over or Under Voltage Response Time (1) 150 tPF Power Failure Response Time (2) 40 tRESET Reset Delay (1) (2) CEXT = 0.01 μF 100 90 Units ns max ns max ms PCI Specifications Revision 2.1, Section 4.3.2. The response time is measured individually with ±750 mV of overdrive applied to pin 2 then ±600 mV of overdrive applied to pin 3 and taking the worst number of the four measurements. PCI Specifications Revision 2.1, Section 4.3.2. The power failure response time is measured with a signal changing from 5V to 3V applied to pin 2 and a 3.3V DC applied to pin 3. Submit Documentation Feedback Copyright © 1998–2013, Texas Instruments Incorporated Product Folder Links: LMC6953 3 LMC6953 SNVS132D – APRIL 1998 – REVISED APRIL 2013 www.ti.com LMC6953 TIMING DIAGRAM Note: tRESET, tD and tPF are not to scale. 4 Submit Documentation Feedback Copyright © 1998–2013, Texas Instruments Incorporated Product Folder Links: LMC6953 LMC6953 www.ti.com SNVS132D – APRIL 1998 – REVISED APRIL 2013 TYPICAL PERFORMANCE CHARACTERISTICS Unless otherwise specified, TA = 25°C Supply Current vs Temperature Output Voltage vs Supply Voltage Figure 4. Figure 5. Power-Up Supply Voltage vs Temperature VH5 vs Temperature Figure 6. Figure 7. VL5 vs Temperature VH3.3 vs Temperature Figure 8. Figure 9. Submit Documentation Feedback Copyright © 1998–2013, Texas Instruments Incorporated Product Folder Links: LMC6953 5 LMC6953 SNVS132D – APRIL 1998 – REVISED APRIL 2013 www.ti.com TYPICAL PERFORMANCE CHARACTERISTICS (continued) Unless otherwise specified, TA = 25°C 6 VL3.3 vs Temperature Over-Voltage Response Time vs Temperature Figure 10. Figure 11. 3Under-Voltage Response Time vs Temperature Power Failure Response Time vs Temperature Figure 12. Figure 13. VOL vs RPULL-UP IOL vs RPULL-UP Figure 14. Figure 15. Submit Documentation Feedback Copyright © 1998–2013, Texas Instruments Incorporated Product Folder Links: LMC6953 LMC6953 www.ti.com SNVS132D – APRIL 1998 – REVISED APRIL 2013 TYPICAL PERFORMANCE CHARACTERISTICS (continued) Unless otherwise specified, TA = 25°C Reset Delay vs CEXT Reset Delay vs Temperature with CEXT = 0.01 μF Figure 16. Figure 17. Submit Documentation Feedback Copyright © 1998–2013, Texas Instruments Incorporated Product Folder Links: LMC6953 7 LMC6953 SNVS132D – APRIL 1998 – REVISED APRIL 2013 www.ti.com BLOCK DIAGRAM OF THE LMC6953 ** All five comparators' positive power supplies are connected to VDD TRUTH TABLE (1) Power Failure (1) 5V Over-Voltage 5V Under-Voltage 3.3V Over-Voltage 3.3V Under-Voltage MR RESET Fail X X X X High Low X Fail X X X High Low X X Fail X X High Low X X X Fail X High Low X X X X Fail High Low X X X X X Low Low OK OK OK OK OK High High X = Don't Care PIN DESCRIPTION Pin Name 1 VDD 5V input supply voltage. This pin supplies power to the internal comparators. It can be connected to a capacitor acting as a back-up battery. Otherwise, it should be shorted to the 5V pin. 2 5V 5V input supply voltage. This pin is not connected to the positive power supply of the internal comparators. It provides input signal to the 5V window comparators as well as the power failure comparator. 3 3.3V 3.3V input supply voltage. This pin provides input signal to the 3.3V window comparators and the power failure comparator. 4 MR Manual reset input pin. It takes 5V CMOS logic low and triggers RESET . If not used, this pin should be connected to VDD. 5 PWR―GND 6 GND 7 RESET 8 CEXT 8 Function Ground. This pin should be grounded at all times. Active low reset output. RESET holds low for 100 ms after both 5V and 3.3V powers recover, or after manual reset signal returns to high state. External capacitor pin. The value of CEXT sets the reset delay. Submit Documentation Feedback Copyright © 1998–2013, Texas Instruments Incorporated Product Folder Links: LMC6953 LMC6953 www.ti.com SNVS132D – APRIL 1998 – REVISED APRIL 2013 APPLICATION NOTE HOW THE LMC6953 FUNCTIONS The LMC6953 is a power supply supervisor with its performance specifications compliant to PCI Specifications Revision 2.1. The chip monitors power-up, power-down, brown-out, power failure and manual reset interrupt situations. During power-up, the LMC6953 holds RESET low for 100 ms after both 5V and 3.3V are within specified windows. It asserts reset in 490 ns when a brown-out is detected. Brown-out occurs when 5V supply is above 5.75V over-voltage or below 4.25V under-voltage or when 3.3V supply is above 4.1V over-voltage or 2.5V undervoltage. In case of power failure where the 5V supply falls under 3.3V supply by 300 mV maximum, reset is asserted in 90 ns. RESET also can be asserted by sending a 5V CMOS logic low to the manual reset pin. Each time RESET is asserted, it holds low for 100 ms after a fault condition is recovered. The 100 ms reset delay is generated by the 0.01 μF CEXT capacitor, and can be adjusted by changing the value of CEXT. It is highly recommended to place lands on printed circuit boards for 120 pF capacitors between pin 2 and ground and also between pin 3 and ground. As power supplies may change abruptly, there can be very high frequency noise present and the capacitors can minimize the noise, MINIMUM SUPPLY VOLTAGE FOR RESET ASSERTION The LMC6953 specifies VDD = 1.55V as the minimum supply voltage to achieve consistent RESET assertion. This ensures system stability in initialization state. Figure 18. Output Voltage vs Supply Voltage Figure 18 is measured by shorting pins 1, 2 and 3 together when supply voltage is from 0V to 3.3V. Then pin 3 is connected with a constant 3.3 VDC and pins 1 and 2 are connected to a separate power supply that continues to vary from 3.3V to 6V. 5V AND VDD PINS By having the 5V and the VDD pins separate, a capacitor can be used as a back-up power supply in event of a sudden power supply failure. This circuit is shown in Figure 22. Under normal condition, the diode is forwardbiased and the capacitor is charged up to VDD − 0.7V. If the power supply goes away, the diode becomes reverse-biased, isolating the 5V and the VDD pins. The capacitor provides power to the internal comparators for a short duration for the LMC6953 to operate. CEXT SETS RESET DELAY IN LINEAR FASHION The LMC6953 has internal delay circuitry to generate the reset delay. By choosing different values of capacitor CEXT, reset delay can be programmed to the desired length for the system to stabilize after a fault condition occurs. Submit Documentation Feedback Copyright © 1998–2013, Texas Instruments Incorporated Product Folder Links: LMC6953 9 LMC6953 SNVS132D – APRIL 1998 – REVISED APRIL 2013 www.ti.com EVALUATING THE LMC6953 To Measure Over-Voltages And Under-Voltages Connect a 3.3V DC to the 3.3V pin and a 5V DC to the VDD and the 5V pins (VDD and 5V pins are shorted). RESET output is high because voltages are within window. These voltages should be monitored. While keeping the 3.3V constant, increase the 5V DC signal until a RESET low is detected. The point on the 5V DC signal at which RESET changes from high to low is the 5V over-voltage. It is typically 5.6V. To detect 5V under-voltage, start the 5V DC signal from 5V and decrease it until a RESET low is detected. The point on the 5V DC signal at which RESET changes from high to low is the 5V under-voltage. It is typically 4.4V. To find 3.3V over-voltage and under-voltage, keep the 5V DC at 5V and vary the 3.3V DC signal until a RESET low is detected. To Measure Timing Specifications For evaluation purposes only, the VDD and the 5V pins should have separate signals. It is easier to measure response time in this manner. The VDD pin is connected to a steady 5V DC and the 5V pin is connected to a pulse generator. To simulate the power supply voltages going out of window, a pulse generator with disable/enable feature and rise and fall time adjustment is recommended. To measure the RESET signal, a oscilloscope is recommended because of its ability to capture and store a signal. To measure the 5V under-voltage response time on the LMC6953, set the pulse generator to trigger mode and program the amplitude to have a high value of 5V and a low value of the 5V under-voltage threshold measured previously with 50 mV overdrive. For example, if the measured 5V under-voltage is 4.4V, then a 50 mV overdrive on this signal is 4.35V. The disable feature on the pulse generator should be on. Program the fall time of the pulse to be 30 ns and program the scope to trigger on the falling edge, with trigger level of 4.5V. Set the scope to 200 ns/division. The probes should be connected to the 5V pin and the RESET pin. Now enable the 5V signal from the pulse generator and trigger the signal. Be aware that when the signal is enabled, there is high frequency noise present, and putting a 120 pF capacitor between the 5V pin and ground suppresses some of the noise. Response time is measured by taking the 5V under-voltage threshold on the 5V signal to the point where RESET goes low. Figure 19 shows a scope photo of 5V under-voltage waveforms. It is taken with a signal going from 5V to 4.25V at the 5V pin. To measure the 100 ms RESET delay, change the scope to 50 ms/division and trigger the 5V signal again. RESET should stay low for 100 ms after the 5V is recovered and within window. Other over-voltages and under-voltages can be measured by changing the pulse generator to different voltage steps. Putting a 120 pF capacitor between the 3.3V pin and ground is recommended in evaluating 3.3V signal. To measure power-failure response time, set the pulse generator from 5V to 3V with fall time of the pulse 3 ns and connect it to the 5V pin. RESET should go low within 90 ns of power failure. Figure 20 shows a scope photo of power failure waveforms. It is taken with a signal going from 5V to 3V at the 5V pin. Figure 19. 5V Under-Voltage Waveforms 10 Submit Documentation Feedback Copyright © 1998–2013, Texas Instruments Incorporated Product Folder Links: LMC6953 LMC6953 www.ti.com SNVS132D – APRIL 1998 – REVISED APRIL 2013 Figure 20. Power Failure Waveforms Typical Application Circuits Figure 21. On Mother Board Figure 22. On Mother Board with Capacitor as a Back-up Power Supply Submit Documentation Feedback Copyright © 1998–2013, Texas Instruments Incorporated Product Folder Links: LMC6953 11 LMC6953 SNVS132D – APRIL 1998 – REVISED APRIL 2013 www.ti.com Figure 23. On Add-In Cards 12 Submit Documentation Feedback Copyright © 1998–2013, Texas Instruments Incorporated Product Folder Links: LMC6953 LMC6953 www.ti.com SNVS132D – APRIL 1998 – REVISED APRIL 2013 REVISION HISTORY Changes from Revision C (April 2013) to Revision D • Page Changed layout of National Data Sheet to TI format .......................................................................................................... 12 Submit Documentation Feedback Copyright © 1998–2013, Texas Instruments Incorporated Product Folder Links: LMC6953 13 PACKAGE OPTION ADDENDUM www.ti.com 3-Jan-2020 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan Lead/Ball Finish MSL Peak Temp (2) (6) (3) Op Temp (°C) Device Marking (4/5) LMC6953CM/NOPB NRND SOIC D 8 95 Green (RoHS & no Sb/Br) CU SN Level-1-260C-UNLIM 0 to 70 LMC69 53CM LMC6953CMX/NOPB NRND SOIC D 8 2500 Green (RoHS & no Sb/Br) CU SN Level-1-260C-UNLIM 0 to 70 LMC69 53CM (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of