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LMG1210
SNOSD12D – NOVEMBER 2018 – REVISED JANUARY 2019
LMG1210 200-V, 1.5-A, 3-A half-bridge MOSFET and GaN FET driver with adjustable dead
time for applications up to 50 MHz
1 Features
3 Description
•
•
•
•
•
The LMG1210 is a 200-V, half-bridge MOSFET and
Gallium Nitride Field Effect Transistor (GaN FET)
driver designed for ultra-high frequency, highefficiency applications that features adjustable
deadtime capability, very small propagation delay,
and 3.4-ns high-side low-side matching to optimize
system efficiency. This part also features an internal
LDO which ensures a gate-drive voltage of 5-V
regardless of supply voltage.
1
•
•
•
•
•
•
•
Up to 50-MHz operation
10-ns typical propagation delay
3.4-ns high-side to low-side matching
Minimum pulse width of 4 ns
Two control input options
– Single PWM input with adjustable dead time
– Independent input mode
1.5-A peak source and 3-A peak sink currents
External bootstrap diode for flexibility
Internal LDO for adaptability to voltage rails
High 300-V/ns CMTI
HO to LO capacitance less than 1 pF
UVLO and overtemperature protection
Low-inductance WQFN package
To enable best performance in a variety of
applications, the LMG1210 allows the designer to
choose the optimal bootstrap diode to charge the
high-side bootstrap capacitor. An internal switch turns
the bootstrap diode off when the low side is off,
effectively preventing the high-side bootstrap from
overcharging and minimizing the reverse recovery
charge. Additional parasitic capacitance across the
GaN FET is minimized to less than 1 pF to reduce
additional switching losses.
2 Applications
•
•
•
•
•
The LMG1210 features two control input modes:
Independent Input Mode (IIM) and PWM mode. In IIM
each of the outputs is independently controlled by a
dedicated input. In PWM mode the two
complementary output signals are generated from a
single input and the user can adjust the dead time
from 0 to 20 ns for each edge. The LMG1210
operates over a wide temperature range from –40°C
to 125°C and is offered in a low-inductance WQFN
package.
High-speed DC-DC converters
RF envelope tracking
Class-D audio amplifiers
Class-E wireless charging
High-precision motor control
Device Information(1)
PART NUMBER
PACKAGE
LMG1210
WQFN (19)
BODY SIZE (NOM)
3.00 mm × 4.00 mm
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
Simplified Typical Application
BST
200 V
HB
6 ± 18 V
VIN
HO
LDO
HS
UVLO
OTP
EN
PWM
EN
PWM
VDD
Dead
Time
DHL
Delay
Match
5V
LO
VSS
DLH
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
LMG1210
SNOSD12D – NOVEMBER 2018 – REVISED JANUARY 2019
www.ti.com
Table of Contents
1
2
3
4
5
6
Features ..................................................................
Applications ...........................................................
Description .............................................................
Revision History.....................................................
Pin Configuration and Functions .........................
Specifications.........................................................
6.1
6.2
6.3
6.4
6.5
6.6
6.7
6.8
7
1
1
1
2
3
4
Absolute Maximum Ratings ...................................... 4
ESD Ratings ............................................................ 4
Recommended Operating Conditions....................... 4
Thermal Information ................................................. 5
Electrical Characteristics........................................... 5
Switching Characteristics .......................................... 7
Typical Characteristics .............................................. 8
Timing Diagrams ..................................................... 10
Detailed Description ............................................ 11
7.1 Overview ................................................................. 11
7.2 Functional Block Diagram ....................................... 11
7.3 Feature Description................................................. 11
4
7.4 Device Functional Modes........................................ 15
8
Application and Implementation ........................ 16
8.1 Application Information............................................ 16
8.2 Typical Application ................................................. 16
8.3 Do's and Don'ts ...................................................... 20
9 Power Supply Recommendations...................... 20
10 Layout................................................................... 21
10.1 Layout Guidelines ................................................. 21
10.2 Layout Example .................................................... 21
11 Device and Documentation Support ................. 22
11.1
11.2
11.3
11.4
11.5
11.6
22
22
22
22
22
22
12 Mechanical, Packaging, and Orderable
Information ........................................................... 22
Revision History
Changes from Revision C (December 2018) to Revision D
•
Documentation Support .......................................
Receiving Notification of Documentation Updates
Community Resources..........................................
Trademarks ...........................................................
Electrostatic Discharge Caution ............................
Glossary ................................................................
Page
Changed Maximum High-side dynamic current from 0.61mA/MHz to 0.7mA/MHz .............................................................. 5
Changes from Revision B (November 2018) to Revision C
Page
•
Changed mismatch from 2.5 ns to 3.4 ns ............................................................................................................................. 1
•
Changed minimum pulse width from 3 ns to 4 ns ................................................................................................................. 1
•
Changed Reordered Pin Functions table in alphabetical order.............................................................................................. 3
•
Added Figure 14 IIM Timing Diagram ................................................................................................................................. 10
•
Added CMTI performance reference app note..................................................................................................................... 13
•
Added charge per cycle removed from the bootstrap due to dynamic high side current .................................................... 17
•
Added Power Consumption Calculation reference app note ............................................................................................... 19
Changes from Revision A (May 2018) to Revision B
•
2
Page
Changed marketing status from Product Preview to final. Initial release. .............................................................................. 1
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SNOSD12D – NOVEMBER 2018 – REVISED JANUARY 2019
5 Pin Configuration and Functions
HS
NC
NC1
HS
HB
NC
RVR Package
19-Pin WQFN
Top View
15
14
13
12
11
(HS)
16
BST
17
EN/HI
18
PWM/LI
19
Thermal Pad
10
HO
9
HS
8
LO
7
VSS
6
DLH
(VSS)
3
4
VDD
5
DHL
2
VSS
NC
1
VIN
Thermal Pad
Pin Functions
PIN
NAME
BST
NO.
I/O
DESCRIPTION
17
O
Bootstrap diode anode connection point.
5
I
Sets the dead time for a high-to-low transition in PWM mode by connecting a resistor to VSS. If
using IIM this pin can be left floating, tied to GND, tied to VDD.
6
I
Sets the dead time for a low-to-high transition in PWM mode by connecting a resistor to VSS. Tie
to VDD to select IIM.
18
I
Enable input or high-side driver control. In PWM mode this is the EN pin. In IIM mode this is the
HI pin.
19
I
PWM input or low-side driver control. In PWM mode this is the PWM pin. In IIM mode this is the
LI pin.
12
I
High-side driver supply. Bootstrap diode cathode connection point.
HO
10
O
High-side driver output.
HS
9,13,16
I
Switch node and high-side driver ground. These pins are internally connected.
LO
8
O
Low-side driver output.
NC
1,11,15
—
Not internally connected.
NC1
14
I
Thermal Pad
(HS)
21
I
Thermal Pad
(VSS)
20
I
VDD
4
O
Low-side driver supply and LDO output. 5 V
6 V to 18 V input to LDO. If LDO is not required, connect to VDD.
DHL
DLH
EN/HI
PWM/LI
HB
VIN
2
I
VSS
3,7
—
For proper operation, this pin should be either unconnected or tied to HS.
Connected to HS.
Connected to VSS.
Low-side ground return: all low-side signals are referenced to this ground.
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SNOSD12D – NOVEMBER 2018 – REVISED JANUARY 2019
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6 Specifications
6.1 Absolute Maximum Ratings
Over operating free-air temperature range (unless otherwise noted) (1)
MIN
MAX
-0.5
20
V
-0.5
5.5
V
-300
300
V
5.5
V
-0.5
10
V
-0.5
VDD + 0.5
V
Low-side gate driver output
-0.5
VDD + 0.5
V
VHO
High-side gate driver output
VHS-0.5
VHB+ 0.5
V
VBST
Bootstrap pin voltage
-0.5
VDD + 0.5
V
TJ
Operating Junction Temperature Range
-40
150
°C
TSTG
Storage Temperature
-55
150
°C
VIN
Input Supply Voltage
VDD
5V Supply Voltage
VHS
High Side Voltage Without Bootstrap Diode
VHB-VHS
Bootstrap supply voltage, continuous
-0.5
VLI/PWM, VHI/EN
Input Pin Voltage on LI or HI
VDHL, VDHL
Voltage on DLH and DHL pins
VLO
(1)
UNIT
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
6.2 ESD Ratings
VALUE
V(ESD)
(1)
(2)
Electrostatic discharge
Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001 (1)
±2000
Charged-device model (CDM), per JEDEC specification JESD22C101 (2)
±500
UNIT
V
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. Manufacturing with
less than 500-V HBM is possible with the necessary precautions. Pins listed as ±XXX V may actually have higher performance.
JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process. Manufacturing with
less than 250-V CDM is possible with the necessary precautions. Pins listed as ±YYY V may actually have higher performance.
6.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
MIN
VIN
Input Supply Voltage (if using internal LDO)
VDD
5V Supply Voltage (if bypassing internal LDO)
4.75
VHS-VSS
High-Side Voltage Without Bootstrap diode
(1)
VHB-VHS
VLI,VHI
NOM
MAX
UNIT
18
V
5.25
V
-200
200
V
Bootstrap Supply Voltage
3.80
5.25
V
Input Pin Voltage
-0.3
10
V
TJ
Operating Junction Temperature Range
-40
125
°C
CMTI
High Side Slew Rate
300
V/ns
RDHL, RDLH
Dead Time Adjustment External Resistance
20
1800
kΩ
VDT
Dead Time Voltage Range
0.8
1.8
(1)
4
6
5.00
V
If using a bootstrap diode, actual negative HS pin voltage may be more limited, see Section 7.3.6 for details.
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SNOSD12D – NOVEMBER 2018 – REVISED JANUARY 2019
6.4 Thermal Information
LMG1210
THERMAL METRIC (1)
RVR (QFN)
UNIT
19 PINS
RθJA
Junction-to-ambient thermal resistance
RθJC(top)
Junction-to-case (top) thermal resistance
RθJB
Junction-to-board thermal resistance
ψJT
Junction-to-top characterization parameter
2.9
°C/W
ψJB
Junction-to-board characterization parameter
16.4
°C/W
(1)
40.5
°C/W
40
°C/W
16.2
°C/W
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
6.5 Electrical Characteristics
VDD=5V, HB-HS=4.6V, outputs unloaded over operating junction temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
SUPPLY CURRENT
Quiescent Current for Low-Side
Circuits Only, Vin=6V, powered
through LDO
LI, HI=0V, Independent Mode
300
475
μA
IDD
EN=0V, PWM=X, PWM Input Mode,
RDHL and RDLH = 1.78MΩ
380
550
μA
IHB
HB Quiescent Current
HI=0V, Independent Mode
520
850
μA
IHBS
HB to VSS Quiescent Current
VHS=100V
1
IHBSO
HB to VSS Operating Current
VHS=100V, FSW=1MHz
1
ILSDyn
Low-side dynamic current
Unloaded, PWM Mode
1
1.25
mA/MHz
IHSDyn
High-side dynamic current
Unloaded
0.5
0.7
mA/MHz
nA
nA
LOW-SIDE TO HIGH-SIDE CAPACITANCE
Capacitance from High to Low Side
Low Side Pins Shorted Together,
High Side Pins Shorted Together
V5V
LDO Output
VIN=10V
VDO
Dropout Voltage
IO=100mA
ILDOM
Maximum Current
VIN=12V
100
ISC
Short Circuit Current
VIN=12V
105
COUT
Minimum Required Output
Capacitance (1)
Effective Capacitance at Bias
Voltage
CISO
0.25
pF
5V LDO
4.75
5.00
5.25
V
400
750
mV
mA
250
mA
0.3
µF
DIGITAL INPUT PINS (LI/PWM & HI/EN)
VIR
Input Rising Edge Threshold
1.70
2.45
V
VIF
Input Falling Edge Threshold
0.70
1.30
V
VIHYS
Input Hysteresis
RIPD
Input Pull-Down Resistance
1
VLI, VHI=1V
V
100
200
300
kΩ
V
UNDERVOLTAGE LOCKOUT
VDDR
VDD Rising Threshold
4.00
4.25
4.50
VDDF
VDD Falling Threshold
3.8
4.05
4.3
VDDH
VDD Hysteresis
VHBR
HB-HS Rising Threshold
3.40
3.55
3.8
VHBF
HB-HS Falling Threshold
3.30
3.45
3.65
VHBH
HB-HS Hysteresis
200
V
mV
V
V
130
mV
0.4
Ω
BOOTSTRAP DIODE SWITCH
RSW
Diode Switch On Resistance
ID=100mA
GATE DRIVER
VOL
(1)
Low-Level Output Voltage
IOL=100mA
0.16
V
Ensured by design
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Electrical Characteristics (continued)
VDD=5V, HB-HS=4.6V, outputs unloaded over operating junction temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
VDD-VOH
High-Level Output Voltage
IOH= -100mA
0.30
V
IOL
Peak Sink Current
VLO,VHO=5V
2.0
3.1
4.3
A
IOH
Peak Source Current
VLO,VHO=0V
0.85
1.58
2.4
A
VCLAMP
Unpowered Gate Clamp Voltage
VDD, VHB Floating, 1 mA pull-up
applied to LO/HO
0.55
0.8
V
THERMAL SHUTDOWN
TSD
Thermal Shutdown Switching, Rising
Edge (2)
150
°C
TSD_LDO
Thermal Shut Down LDO, Rising
Edge (2)
160
°C
THYS_SD
Thermal Hysteresis, LDO &
Switching (2)
TSD_HS
Thermal Shutdown for High-Side,
Rising Edge (2)
3
10
°C
160
°C
DEADTIME CONTROL RESISTORS
RPU
(2)
6
Internal Pullup Resistor
23.5
25
27
kΩ
Ensured by design
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6.6 Switching Characteristics
VDD=5V, VHB-HS=4.6V, outputs unloaded over operating junction temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
INDEPENDENT INPUT MODE
tPHL
Turn-Off Delay
10
18
ns
tPLH
Turn-On Delay
10
18
ns
tMTCH
High-Off to Low-On and Low-Off to
High-On Delay Mismatch
1
3.4
ns
11
21
ns
-0.55
0.8
3.1
ns
16
20
26
ns
11
20
ns
Over temperature, TjHI=TjLO
PWM INPUT MODE
tPHL
Turn-Off Delay
PWM rising to LO falling and PWM
falling to HO falling
tDEAD_MIN
Minimum Dead Time
Rext=1.78 MΩ
tDEAD_MAX
Maximum Dead Time
Rext=20 kΩ
tEN
Enable Propagation Time
OTHER CHARACTERISTICS
tOR
Output Rise Time, Unloaded
10%-90%
0.5
ns
tOF
Output Fall Time, Unloaded
90%-10%
0.5
ns
tORL
Output Rise Time, Loaded
CO=1nF, 10%-90%
3.5
5.6
ns
tOFL
Output Fall Time, Loaded
CO=1nF, 90%-10%
2.3
3.3
ns
tPW
Minimum Input Pulse Width
(1)
Minimum input pulse width which
changes the output
1.8
4.0
ns
tPW,ext
H-L-H Pulse extender width
(1)
Unloaded (2)
4.5
10
ns
tSTLS
Start-Up Time of low side after VDD- Independent Control Mode
GND goes over UVLO threshold.
PWM Control Mode
25
60
µs
100
150
µs
tSTHS
Start-Up Time of High-Side After
VHB-VHS Goes Above UVLO
16
28
µs
tPWD
Pulse-Width Distortion
1
3
ns
(1)
(2)
|tPLH-tPHL|, Independent Input Mode
Ensured by design
Pulses longer than tPW, but shorter than tPW,ext get extended to tPW,ext
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6.7 Typical Characteristics
1.75
4
1.5
3.5
3
Current (A)
Current (A)
1.25
1
0.75
0.5
2.5
2
1.5
1
0.25
0.5
0
0
0
0.5
1
1.5
2
2.5
3
LO, HO (V)
3.5
4
4.5
5
0
Figure 1. Peak Source Current vs Output Voltage
2
2.5
3
LO, HO (V)
3.5
4
4.5
5
D002
-40 qC
25 qC
125 qC
24
IHBO (mA)
IDD (mA)
1.5
30
-40 qC
25 qC
125 qC
30
20
18
12
6
10
0
0.05
1
Figure 2. Peak Sink Current vs Output Voltage
50
40
0.5
D001
0.1
0.2 0.3 0.5
1
2 3 4 5 67 10
Frequency (MHz)
0
0.05
20 30 50
0.1
0.2 0.3 0.5
1
2 3 4 5 67 10
Frequency (MHz)
D003
Figure 3. IDD vs Frequency, Unloaded
20 30 50
D004
Figure 4. IHBO vs Frequency, Unloaded
315
700
310
305
650
295
IHB (PA)
IDD (PA)
300
290
285
600
550
280
275
500
270
265
-40
-20
0
20
40
60
80 100
Temperature (qC)
120
140
160
450
-40
-20
D005
Figure 5. IDD vs Temperature
8
0
20
40
60
80 100
Temperature (qC)
120
140
160
D006
Figure 6. IHB vs Temperature
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Typical Characteristics (continued)
1.1
13
DHL
DLH
Minimum Dead Time (ns)
Propagation Delay (ns)
1
12
11
10
9
-40
Low Side TPLH
Low Side TPHL
High Side TPLH
High Side TPHL
-20
0
20
40
60
80
Temperature (qC)
100
120
0.9
0.8
0.7
0.6
0.5
0.4
-40
140
Figure 7. Propagation Delay vs Temperature
20
40
60
80
Temperature (qC)
100
120
140
D008
12
0.7
50 V/ns
100 V/ns
300 V/ns
11.6
0.6
Propagation Delay (ns)
Propagation Delay Change (ns)
0
Figure 8. Minimum Dead Time vs Temperature
0.8
0.5
0.4
0.3
0.2
0.1
11.2
10.8
10.4
10
0
9.6
-0.1
-0.2
3.5
3.75
4
4.25
4.5
4.75
Bootstrap Voltage (V)
5
5.25
9.2
-20
5.5
-15
D009
-10
-5
0
5
10
Phase of CMTI Relative to Signal (ns)
15
20
D010
Figure 10. Propagation Delay vs relative phase of CMTI
Phase
Figure 9. Propagation Delay Change vs Bootstrap voltage
4.5
4.5
LO Sink
LO Source
HO Sink
HO Source
4
3.5
HO Rise Time
LO Rise Time
LO Fall Time
HO Fall Time
4
Rise/Fall Time (ns)
Ouput Current (A)
-20
D007
3
2.5
2
3.5
3
2.5
1.5
1
-40
-20
0
20
40
60
80
Temperature (qC)
100
120
140
2
-40
-20
D011
Figure 11. LO and HO Output Current vs Temperature
0
20
40
60
80
Temperature (qC)
100
120
140
D012
Figure 12. 1 nF Loaded Rise and Fall Time vs Temperature
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6.8 Timing Diagrams
TPHL
TPLH
TOR
TOF
50%
PWM
TON
90%
50%
HO
10%
TDLH
TDHL
LO
Figure 13. Timing diagram of LMG1210 in PWM mode under no load condition
HI
LI
HO
LO
tPHL
tPLH
tMTCH
tPHL
tMTCH
tPWD = |tPLH t tPHL|
tPHL
Figure 14. Timing diagram of LMG1210 in IIM mode under no load condition
10
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7 Detailed Description
7.1 Overview
The LMG1210 is a high-speed half-bridge driver specifically designed to work with enhancement mode GaN
FETs. Designed to operate up to 50 MHz, the LMG1210 is optimized for maximum performance and highly
efficient operation. This includes reducing additional capacitance at the switch node (HS) to less than 1 pF and
increased dV/dt noise immunity up to 300 V/ns on the HS pin to minimize additional switching losses. By having
a 21 ns maximum propagation delay with 3.4 ns maximum mismatch, excessive dead times can be greatly
reduced.
Auxiliary input voltages applied above 5 V enables an internal LDO to precisely regulate the output voltage at 5V, preventing damage on the gate. An external bootstrap diode allows the designer to select an optimal diode.
An integrated switch in series with the bootstrap diode stops overcharging of the bootstrap capacitor and
decreases Qrr losses in the diode.
The LMG1210 comes in a low-inductance WQFN package designed for small gate drive loops with minimal
voltage overshoot.
7.2 Functional Block Diagram
BST
HB
VIN
LDO
HO
HS
EN
VDD
Dead Time
PWM
Delay
Match
LO
VSS
1.8 V
1.8 V
UVLO
OTP
DHL DLH
7.3 Feature Description
The LMG1210 provides numerous features optimized for driving external GaN FETs.
7.3.1 Bootstrap Diode Operation
An internal low impedance switch enables the bootstrap only when the low-side GaN FET is on. If used in a
converter where the low-side FET operates in third quadrant conduction during the dead times, this provides two
main benefits. First, it stops the bootstrap diode from overcharging the high-side bootstrap rail. Second, if using a
p-n junction diode with Qrr as the bootstrap diode, it decreases the Qrr losses of the diode. There is a 1 kΩ
resistor connected between the drain and source of this internal bootstrap switch to allow the bootstrap capacitor
to slowly charge at start-up before the low-side FET is turned on.
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Feature Description (continued)
The part does not have an actual clamp on the high-side bootstrap supply. The bootstrap switch disables
conduction during the dead times, and the actual bootstrap capacitor voltage is set by the operating conditions of
the circuit during the low-side on-time. The bootstrap voltage can be approximately calculated in Equation 1
through Equation 3.
The bootstrap voltage is given by Equation 1:
VBST = VDD – VF – VHS
where
•
VF is the forward voltage drop of the bootstrap diode and series bootstrap switch.
(1)
VHS is calculated in Equation 2:
VHS = –IL × RDSON
where
•
•
IL is the inductor current defined as flowing out of the half-bridge
and RDSON is the FET on resistance.
(2)
Substituting (2) into (1) gives the expression for the bootstrap voltage as Equation 3:
VBST = VDD – VF + IL × RDSON
(3)
From (3) one can determine that in an application where the current flows out of the half-bridge (IL is positive) the
bootstrap voltage can be charged up to a voltage higher than VDD if IL × RDSON is greater than VF. Take care not
to overcharge the bootstrap too much in this application by choosing a diode with a larger VF or limiting the IL ×
RDSON product.
In an application where IL is negative, the IL × RDSON product subtracts from the available bootstrap cap voltage.
In this case using a smaller VF diode is recommended if IL × RDSON is large.
7.3.2 LDO Operation
An internal LDO allows the driver to run off higher voltages from 6 V to 18 V and regulates the supply to 5 V, so
the LMG1210 can run off of higher input voltages with wide tolerances. To maintain stability of the internal LDO,
care must be taken to make sure a capacitor of at least 0.3 µF from VDD to VSS with an ESR below 500 mΩ is
used. A high-quality ceramic capacitor with an X7R dielectric is recommended. There is no maximum limit on the
capacitance allowed on the output of the LDO.
If the input supply is already 5 V ±5%, then the LDO can be bypassed. This is achieved by connecting the 5 V
supply directly to the VDD pin. The VIN pin should be tied to the VDD pin, and the capacitor on the VIN pin can be
removed. Do not ground the VIN pin.
12
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Feature Description (continued)
7.3.3 Dead Time Selection
In PWM mode the dead time can be set with a resistor placed between DHL/DLH and VSS. For a desired dead
time (tdt), the corresponding required resistance can be calculated in Equation 4 with tdt in ns and Rext in kΩ.
Rext = (900/tdt ) – 25
(4)
The maximum dead time is 20 ns, which gives a minimum resistor value of 20 kΩ. The minimum dead time is
0.5ns, which gives a maximum resistor value of 1.8 MΩ. There is an internal pull-up resistor at DHL/DLH pin,
which forms a voltage divider with the external resistor. This voltage decides the final dead time. The calculation
between dead time tDT in ns and VDT is shown in Equation 5.
tdt = (1.8-VDT ) x20
(5)
Before being used to generate the dead times, the voltages on the DHL and DLH pins are first filtered through an
internal RC filter with a nominal corner frequency of 10 kHz to attenuate switching noise.
The pulse widths of the HO and LO outputs are decreased from the PWM input by the chosen dead-times. The
timing diagram under no load condition is shown in Figure 13 and Figure 14. PWM mode and Independent mode
configurations can be found in Figure 16 .
7.3.4 Overtemperature Protection
The LMG1210 has three separate overtemperature thresholds: two on the low-side and one on the high-side.
The lowest overtemperature threshold is the low-side switching threshold at 150 degrees minimum. When
exceeded, this disables switching on both the low and high sides. However, the 5 V LDO continues to operate.
If the low-side temperature continues to rise, due to a short or external load on the 5 V LDO, then at 10 degrees
higher, the low-side shuts down the 5 V LDO.
The high-side has an independent overtemperature threshold at 160 minimum. When triggered, it only shuts off
the high-side while the low-side may continue to operate.
If it is undesirable in an application to have only the high side shut off and not the low side, TI recommends
designing the thermal cooling of the board in a way to make the low-side die hotter. This can be achieved by
controlling the size of the thermal planes connected to each thermal pad.
7.3.5 High-Performance Level Shifter
The LMG1210 uses a high-performance level shifter to translate the signal from the low side to the high side.
The level shifter is built using TI's proprietary high-voltage capacitor technology, which showcases best-in-class
CMTI (common-mode transient immunity), or dV/dt on the HS pin. The level shifter can handle very high CMT
(common-mode transient) rates while simultaneously providing low propagation time which does not vary
depending on CMT rate. For more information on LMG1210 CMTI performance refer to section 2.4 from Design
Considerations for LMG1205 Advanced GaN FET Driver During High-Frequency Operation.
7.3.6 Negative HS Voltage Handling
The LMG1210 by itself can operate with -200V on the HS pin as stated in the recommended operating conditions
table. However, if using a bootstrap diode, the system will be more limited based on the potential of high-currents
flowing through the bootstrap diode.
HS goes most negative during the dead times when the low-side FET is off. This also means the bootstrap
switch is off so the BST pin is relatively high impedance. Therefore as HS goes negative, the bootstrap diode
becomes forward biased and pulls the voltage at BST down with it. Because the bootstrap switch is off, very little
current will flow until the bootstrap diode attempts to pull the BST pin below ground at which point the ESD diode
on the BST pin will clamp the voltage at a diode drop below ground. The point where significant current begins to
flow through the bootstrap diode is given in Equation 6
VHS = – VBST – VESD – (VHB – VHS)
(6)
Where VBST is the forward voltage drop of the selected bootstrap diode and VESD is the forward voltage drop of
the ESD diode of the BST pin which is typically 0.7V at room temp. Figure 15 shows a schematic of this current
path.
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Feature Description (continued)
VDD
Bootstrap
Switch (open)
BST
Bootstrap
Diode
HB
CBST
ESD Diode
HS
Current Path
Figure 15. Current Path Across Bootstrap Diode
Once this negative voltage is exceeded, large currents will begin to flow out of the BST pin and through the
bootstrap diode. The currents may be limited by the following: resistance of the BST ESD diode, resistance of
the bootstrap diode, inductance of the bootstrap loop, or additional resistance purposely added in series with the
bootstrap diode. If this current is too high, damage to the bootstrap diode or the LMG1210 can result. If this
current delivers significant enough total charge, this can over-charge the bootstrap rail as well.
The BST pin ESD diode has been specifically designed to be robust to carry up to a couple amps surge current
without damage.
14
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7.4 Device Functional Modes
The mode of operation is determined by the state of DHL and DLH pins during power up. The state of the pins is
sampled at power up and cannot be changed during operation. There are two different modes: independent
operation where separate HI and LI signals are required, and PWM mode where one PWM input signal is
required and the LMG1210 generates the complementary HI and LI signals. For PWM input, the dead time for
the low-to-high and high-to-low switch-node transition is independently set by an external resistor at DHL and
DLH. For independent input mode, DLH is tied to VDD and DHL is internally set to high-impedance and can be
tied to VDD, tied to ground or left floating.
Operating
Mode
DLH
DHL
PWM
Independent
Input Mode
Leave
Floating or
Tie to VSS
VDD
Figure 16. Operation Mode Selection
Table 1 lists the functional modes for the LMG1210.
Table 1. LMG1210 Truth Table
INPUTS
PWM MODE
INDEPENDENT MODE
EN/HI
PWM/LI
HO
LO
HO
LO
0
0
0
0
0
0
0
1
0
0
0
1
1
0
0
1
1
0
1
1
1
0
1
1
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8 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
8.1 Application Information
The LMG1210 is designed to optimally drive GaN FETs in half-bridge configurations, such as synchronous buck
and boost converters, as well as more complex topologies. By integrating the level shifting and bootstrap
operation the complexities of driving the high-side device are solved for the designer.
The list below shows some sample values for a typical 48 V to 12 V application synchronous buck.
•
•
•
•
•
•
•
Input Voltage: 48 V
Output Voltage: 12 V
Output Current: 10 A
Bias Voltage: 6 V
Duty Cycle: 25 %
Switching Frequency: 1 MHz
Inductor: 4.7 µH
8.2 Typical Application
0 ± 200 V
BST
HB
6 ± 18 V
VIN
HO
LDO
HS
VDD
5V
EN
Dead
Time
PWM
LO
VSS
LMG1210
DHL
DLH
Controller
Figure 17. Simplified LMG1210 Configured as Synchronous Buck Converter
16
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Typical Application (continued)
8.2.1 Design Requirements
When designing a multi-MHz application that incorporates the LMG1210 gate driver and GaN power FETs, some
design considerations must be evaluated first to make the most appropriate selection. Among these
considerations are layout optimization, circuit voltages, passive components, operating frequency, and controller
selection.
8.2.2 Detailed Design Procedure
8.2.2.1 Bypass Capacitor
To properly drive the GaN FETs, TI recommends placing high-quality ceramic bypass capacitors as close as
possible between the HB to HS and VDD to VSS. If using the LDO, the VDD-VSS capacitor is required to be at least
0.3 µF at bias for stability. However, a larger capacitor may be required for many applications.
The bootstrap capacitor must be large enough to support charging the high-side FET and supplying the high-side
quiescent current when the high-side FET is on. The required capacitance can be calculated as Equation 7:
(0.5 nC + Qrr + QgH + IHB × ton)/ΔV = CBST,min
where
•
•
•
•
•
•
QgH is the gate charge of the high-side GaN FET,
IHB is the quiescent current of the high-side driver,
tON is the maximum on time period of the high side,
Qrr is the reverse recovery of the bootstrap diode,
0.5 nC is the additional charge per cycle removed from the bootstrap due to high side dynamic current,
and ΔV is the acceptable droop on the bootstrap capacitor voltage.
(7)
When using larger bootstrap capacitors, TI recommends that the VDD-VSS capacitor also be increased to keep
the ratio at least 5 to 1. If this is not maintained, the charging of the bootstrap capacitor can pull the VDD-VSS rail
down sufficiently to cause UVLO conditions and potentially unwanted behavior.
8.2.2.2 Bootstrap Diode Selection
The bootstrap diode blocks the high voltage from the gate drive circuitry when the switch node swings high, with
the rated blocking voltage equal to the maximum Vds of the GaN FET. For low or moderate frequency operation
ultra-fast recovery diodes (
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