LMG3422R030, LMG3425R030
SNOSDA7D – SEPTEMBER 2020 – REVISED MARCH 2022
LMG342xR030 600-V 30-mΩ GaN FET With Integrated Driver, Protection, and
Temperature Reporting
1 Features
3 Description
•
The LMG342xR030 GaN FET with integrated driver
and protection enables designers to achieve new
levels of power density and efficiency in power
electronics systems.
•
•
•
Qualified for JEDEC JEP180 for hard-switching
topologies
600-V GaN-on-Si FET with Integrated gate driver
– Integrated high precision gate bias voltage
– 200-V/ns CMTI
– 2.2-MHz switching frequency
– 30-V/ns to 150-V/ns slew rate for optimization
of switching performance and EMI mitigation
– Operates from 7.5-V to 18-V supply
Robust protection
– Cycle-by-cycle overcurrent and latched shortcircuit protection with < 100-ns response
– Withstands 720-V surge while hard-switching
– Self-protection from internal overtemperature
and UVLO monitoring
Advanced power management
– Digital temperature PWM output
– Ideal diode mode reduces third-quadrant losses
in LMG3425R030
2 Applications
•
•
•
•
•
High density industrial power supplies
Solar inverters and industrial motor drives
Uninterruptable power supplies
Merchant network and server PSU
Merchant telecom rectifiers
The LMG342xR030 integrates a silicon driver that
enables switching speed up to 150 V/ns. TI’s
integrated precision gate bias results in higher
switching SOA compared to discrete silicon gate
drivers. This integration, combined with TI's lowinductance package, delivers clean switching and
minimal ringing in hard-switching power supply
topologies. Adjustable gate drive strength allows
control of the slew rate from 20 V/ns to 150 V/ns,
which can be used to actively control EMI and
optimize switching performance. The LMG3425R030
includes ideal diode mode, which reduces thirdquadrant losses by enabling adaptive dead-time
control.
Advanced power management features include digital
temperature reporting and fault detection. The
temperature of the GaN FET is reported through
a variable duty cycle PWM output, which simplifies
managing device loading. Faults reported include
overtemperature, overcurrent, and UVLO monitoring.
Device Information
PART NUMBER
LMG3422R030
LMG3425R030
(1)
PACKAGE (1)
BODY SIZE (NOM)
VQFN (54)
12.00 mm × 12.00 mm
For all available packages, see the orderable addendum at
the end of the data sheet.
DRAIN
Slew
Rate
Direct-Drive
GaN
SOURCE
RDRV
IN
VDD
VNEG
LDO5V
LDO,
BB
OCP, SCP,
OTP, UVLO
Current
TEMP
FAULT
OC
SOURCE
Simplified Block Diagram
Switching Performance at > 100 V/ns
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
LMG3422R030, LMG3425R030
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SNOSDA7D – SEPTEMBER 2020 – REVISED MARCH 2022
Table of Contents
1 Features............................................................................1
2 Applications..................................................................... 1
3 Description.......................................................................1
4 Revision History.............................................................. 2
5 Device Comparison......................................................... 3
6 Pin Configuration and Functions...................................4
7 Specifications.................................................................. 5
7.1 Absolute Maximum Ratings........................................ 5
7.2 ESD Ratings............................................................... 5
7.3 Recommended Operating Conditions.........................5
7.4 Thermal Information....................................................6
7.5 Electrical Characteristics.............................................6
7.6 Switching Characteristics............................................8
7.7 Typical Characteristics.............................................. 10
8 Parameter Measurement Information.......................... 12
8.1 Switching Parameters............................................... 12
9 Detailed Description......................................................15
9.1 Overview................................................................... 15
9.2 Functional Block Diagram......................................... 16
9.3 Feature Description...................................................17
9.4 Device Functional Modes..........................................26
10 Application and Implementation................................ 27
10.1 Application Information........................................... 27
10.2 Typical Application.................................................. 28
10.3 Do's and Don'ts.......................................................32
11 Power Supply Recommendations..............................33
11.1 Using an Isolated Power Supply............................. 33
11.2 Using a Bootstrap Diode......................................... 33
12 Layout...........................................................................35
12.1 Layout Guidelines................................................... 35
12.2 Layout Examples.................................................... 37
13 Device and Documentation Support..........................39
13.1 Documentation Support.......................................... 39
13.2 Receiving Notification of Documentation Updates..39
13.3 Support Resources................................................. 39
13.4 Trademarks............................................................. 39
13.5 Electrostatic Discharge Caution..............................39
13.6 Export Control Notice..............................................39
13.7 Glossary..................................................................39
14 Mechanical, Packaging, and Orderable
Information.................................................................... 39
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision C (December 2021) to Revision D (March 2021)
Page
• Changed LMG3425R030 from Advance Information to Production Data...........................................................1
• Revised text and Figure 9-4 in Ideal-Diode Mode Operation section............................................................... 23
Changes from Revision B (April 2021) to Revision C (December 2021)
Page
• Changed the data sheet status from Advance Information to Production Data..................................................1
2
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SNOSDA7D – SEPTEMBER 2020 – REVISED MARCH 2022
5 Device Comparison
DEVICE NAME
DUAL OVERCURRENT /
SHORT-CIRCUIT PROTECTION
TEMPERATURE REPORTING
OPERATIONAL IDEAL-DIODE
MODE
LMG3422R030
Yes
Yes
No
LMG3425R030
Yes
Yes
Yes
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SNOSDA7D – SEPTEMBER 2020 – REVISED MARCH 2022
6 Pin Configuration and Functions
16
SOURCE
NC2
NC1
NC1
DRAIN
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
17
54
NC2
18
53
LDO5V
19
52
RDRV
20
51
TEMP
21
50
OC
22
49
GND
23
48
FAULT
24
47
IN
25
46
VDD
26
45
GND
27
44
GND
THERMAL PAD
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
BBSW
28
VNEG
SOURCE
Figure 6-1. RQZ Package 54-Pin VQFN (Top View)
Table 6-1. Pin Functions
PIN
DESCRIPTION
NO.
NC1
1, 16
—
Used to anchor QFN package to PCB. Pins must be soldered to PCB landing pads. The PCB landing pads
are non-solder mask defined pads and must not be physically connected to any other metal on the PCB.
Internally connected to DRAIN.
DRAIN
2-15
P
GaN FET drain. Internally connected to NC1.
NC2
17, 54
—
Used to anchor QFN package to PCB. Pins must be soldered to PCB landing pads. The PCB landing pads
are non-solder mask defined pads and must not be physically connected to any other metal on the PCB.
Internally connected to SOURCE, GND, and THERMAL PAD.
SOURCE
18-40
P
GaN FET source. Internally connected to GND, NC2, and THERMAL PAD.
VNEG
41-42
P
Internal buck-boost converter negative output. Used as the negative supply to turn off the depletion mode
GaN FET. Bypass to ground with a 2.2-µF capacitor.
BBSW
43
P
Internal buck-boost converter switch pin. Connect an inductor from this point to ground.
GND
44, 45, 49
G
Signal ground. Internally connected to SOURCE, NC2, and THERMAL PAD.
VDD
46
P
Device input supply.
IN
47
I
CMOS-compatible non-inverting input used to turn the FET on and off.
FAULT
48
O
Push-pull digital output that asserts low during a fault condition. Refer to Fault Detection for details.
OC
50
O
Push-pull digital output that asserts low during overcurrent and short-circuit fault conditions. Refer to Fault
Detection for details.
TEMP
51
O
Push-pull digital output that gives information about the GaN FET temperature. Outputs a fixed 9-kHz pulsed
waveform. The device temperature is encoded as the duty cycle of the waveform.
RDRV
52
I
Drive strength selection pin. Connect a resistor from this pin to ground to set the turn-on drive strength to
control slew rate. Tie the pin to GND to enable 150 V/ns and tie the pin to LDO5V to enable 100 V/ns.
LDO5V
53
P
5-V LDO output for external digital isolator
THERMAL
PAD
—
—
Thermal pad. Internally connected to SOURCE, GND, and NC2. The thermal pad can be used to conduct
rated device current.
(1)
4
TYPE(1)
NAME
I = input, O = output, P = power, G = ground
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SNOSDA7D – SEPTEMBER 2020 – REVISED MARCH 2022
7 Specifications
7.1 Absolute Maximum Ratings
Unless otherwise noted: voltages are respect to GND(1)
MIN
MAX
UNIT
VDS
Drain-source voltage, FET off
600
V
VDS(surge)
Drain-source surge voltage, FET switching, surge condition(2)
720
V
VDS(tr)
Drain-source surge transient ringing peak voltage, FET off, surge condition(2) (3)
800
V
(surge)
VDD
–0.3
20
V
LDO5V
–0.3
5.5
V
–16
0.3
V
VVNEG–1 VVDD+0.5
V
VNEG
BBSW
Pin voltage
ID(RMS)
IN
–0.3
20
V
FAULT, OC, TEMP
V
+0.
–0.3 LDO5V
3
V
RDRV
–0.3
5.5
V
55
A
–120
Internally
Limited
A
Drain RMS current, FET on
ID(pulse)
Drain pulsed current, FET on, tp < 10 µs(4)
IS(pulse)
Source pulsed current, FET off, tp < 1 µs
80
A
TJ
Operating junction temperature(5)
–40
150
°C
Tstg
Storage temperature
–55
150
°C
(1)
(2)
(3)
(4)
(5)
Stresses beyond those listed under Absolute Maximum Rating may cause permanent damage to the device. These are stress
ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated
under Recommended Operating Condition. Exposure to absolute-maximum-rated conditions for extended periods may affect device
reliability.
See Section 9.3.3 for an explanation of the switching cycle drain-source voltage ratings.
t1 < 200 ns in Figure 9-1.
The positive pulsed current must remain below the overcurrent threshold to avoid the FET being automatically shut off. The FET drain
intrinsic positive pulsed current rating for tp < 10 µs is 120 A.
Refer to the Electrical and Switching Characteristics Tables for junction temperature test conditions.
7.2 ESD Ratings
PARAMETER
V(ESD)
(1)
(2)
Electrostatic discharge
VALUE
Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1)
±2000
Charged-device model (CDM), per ANSI/ESDA/JEDEC JS-002(2)
±500
UNIT
V
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
7.3 Recommended Operating Conditions
Unless otherwise noted: voltages are respect to GND, SOURCE connected to GND
ID(RMS)
Supply voltage
VDD
(Maximum switching frequency derated
for VVDD < 9 V)
Input voltage
IN
MIN
NOM
MAX
7.5
12
18
V
0
5
18
V
40
A
Drain RMS current
Positive source current
LDO5V
UNIT
25
mA
RRDRV
RDRV to GND resistance from external slew-rate control resistor
0
500
kΩ
CVNEG
VNEG to GND capacitance from external bypass capacitor
1
10
uF
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SNOSDA7D – SEPTEMBER 2020 – REVISED MARCH 2022
7.3 Recommended Operating Conditions (continued)
Unless otherwise noted: voltages are respect to GND, SOURCE connected to GND
LBBSW
MIN
NOM
MAX
3
4.7
10
BBSW to GND inductance from external buck-boost inductor
UNIT
uH
7.4 Thermal Information
LMG342xR030
THERMAL METRIC(1)
RQZ (VQFN)
UNIT
54 PINS
RθJA
Junction-to-ambient thermal resistance
16.6
°C/W
RθJC(top)
Junction-to-case (top) thermal resistance
4.2
°C/W
RθJB
Junction-to-board thermal resistance
3.1
°C/W
ΨJT
Junction-to-top characterization parameter
0.12
°C/W
ΨJB
Junction-to-board characterization parameter
3
°C/W
RθJC(bot)
Junction-to-case (bottom) thermal resistance
0.33
°C/W
(1)
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
7.5 Electrical Characteristics
Unless otherwise noted: voltage, resistance, capacitance, and inductance are respect to GND; –40℃ ≤ TJ ≤ 125℃;
VDS = 480 V; 9 V ≤ VVDD ≤ 18 V; VIN = 0 V; RDRV connected to LDO5V; LBBSW = 4.7 µH
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
26
35
UNIT
GAN POWER TRANSISTOR
RDS(on)
VSD
VIN = 5 V, TJ = 25°C
Drain-source on resistance
Third-quadrant mode source-drain
voltage
VIN = 5 V, TJ = 125°C
45
mΩ
IS = 0.1 A
3.8
V
IS = 20 A
3
VDS = 600 V, TJ = 25°C
IDSS
Drain leakage current
COSS
Output capacitance
CO(er)
Energy related effective output
capacitance
CO(tr)
Time related effective output
capacitance
QOSS
Output charge
QRR
Reverse recovery charge
mΩ
VDS = 600 V, TJ = 125°C
VDS = 400 V
5
V
1
uA
10
uA
130
170
pF
230
276
VDS = 0 V to 400 V
160
335
pF
430
pF
175
nC
0
nC
VDD – SUPPLY CURRENTS
VDD quiescent current (LMG3422)
VVDD = 12 V, VIN = 0 V or 5V
700
1200
uA
VDD quiescent current (LMG3425)
VVDD = 12 V, VIN = 0 V or 5V
780
1300
uA
VDD operating current
VVDD = 12 V, fIN = 140 kHz, soft-switching
13
18
mA
BUCK BOOST CONVERTER
VNEG output voltage
VNEG sinking 50 mA
Peak BBSW sourcing current at low
peak current mode setting
(Peak external buck-boost inductor
current)
6
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0.3
0.4
V
0.5
A
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SNOSDA7D – SEPTEMBER 2020 – REVISED MARCH 2022
7.5 Electrical Characteristics (continued)
Unless otherwise noted: voltage, resistance, capacitance, and inductance are respect to GND; –40℃ ≤ TJ ≤ 125℃;
VDS = 480 V; 9 V ≤ VVDD ≤ 18 V; VIN = 0 V; RDRV connected to LDO5V; LBBSW = 4.7 µH
MIN
TYP
MAX
Peak BBSW sourcing current at high
peak current mode setting
(Peak external buck-boost inductor
current)
PARAMETER
TEST CONDITIONS
UNIT
0.8
1
1.2
A
High peak current mode setting
enable – IN positive-going threshold
frequency
280
420
515
kHz
LDO5V
Output voltage
4.75
5
5.25
V
Short-circuit current
LDO5V sourcing 25 mA
25
50
100
mA
VIN,IT+
Positive-going input threshold voltage
1.7
1.9
2.45
V
VIN,IT–
Negative-going input threshold voltage
0.7
1
1.3
V
IN
Input threshold hysteresis
Input pulldown resistance
VIN = 2 V
0.7
0.9
1.3
V
100
150
200
kΩ
0.16
0.4
V
0.2
0.45
V
FAULT, OC, TEMP – OUPUT DRIVE
Low-level output voltage
Output sinking 8 mA
High-level output voltage
Output sourcing 8 mA, Measured as
VLDO5V – VO
VDD, VNEG – UNDER VOLTAGE LOCKOUT
VVDD,T+
(UVLO)
VDD UVLO – positive-going threshold
voltage
6.5
7
7.5
V
VDD UVLO – negative-going threshold
voltage
6.1
6.5
7
V
VDD UVLO – Input threshold voltage
hysteresis
510
mV
VNEG UVLO – negative-going
threshold voltage
–13.6
–13.0
–12.3
V
VNEG UVLO – positive-going threshold
voltage
–13.2
–12.75
–12.1
V
GATE DRIVER
Turn-on slew rate
From VDS < 320 V to VDS < 80 V, RDRV
disconnected from LDO5V, RRDRV = 300
kΩ, TJ = 25℃, VBUS = 400 V, LHB current
= 10 A, see Figure 8-1
20
V/ns
From VDS < 320 V to VDS < 80 V, TJ =
25℃, VBUS = 400 V, LHB current = 10 A,
see Figure 8-1
100
V/ns
From VDS < 320 V to VDS < 80 V, RDRV
disconnected from LDO5V, VRDRV = 0 V,
TJ = 25℃, VBUS = 400 V, LHB current = 10
A, see Figure 8-1
150
V/ns
VNEG rising to > –13.25 V, soft-switched,
maximum switching frequency derated for
VVDD < 9 V
Maximum GaN FET switching
frequency.
2.2
MHz
FAULTS
IT(OC)
DRAIN overcurrent fault – threshold
current
60
70
80
A
IT(SC)
DRAIN short-circuit fault – threshold
current
80
95
110
A
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7.5 Electrical Characteristics (continued)
Unless otherwise noted: voltage, resistance, capacitance, and inductance are respect to GND; –40℃ ≤ TJ ≤ 125℃;
VDS = 480 V; 9 V ≤ VVDD ≤ 18 V; VIN = 0 V; RDRV connected to LDO5V; LBBSW = 4.7 µH
PARAMETER
TEST CONDITIONS
di/dt threshold between overcurrent and
short-circuit faults
MIN
TYP
MAX
150
UNIT
A/µs
Short-circuit current to overcurrent fault
trip difference
25
A
GaN temperature fault – postive-going
threshold temperature
175
°C
GaN Temperature fault – threshold
temperature hysteresis
30
°C
Driver temperature fault – positivegoing threshold temperature
185
°C
20
°C
Driver Temperature fault – threshold
temperature hysteresis
TEMP
Output Frequency
4.5
GaN TJ = 150℃
Output PWM Duty Cycle
9
14
82
kHz
%
GaN TJ = 125℃
58.5
64.6
70
%
GaN TJ = 85℃
36.2
40
43.7
%
GaN TJ = 25℃
0.3
3
6
%
–0.15
0
0.15
V
–0.2
0
0.2
A
–0.35
0
0.35
A
IDEAL-DIODE MODE CONTROL
VT(3rd)
Drain-source third-quadrant detection –
threshold voltage
IT(ZC)
Drain zero-current detection – threshold 0℃ ≤ TJ ≤ 125℃
current
–40℃ ≤ TJ ≤ 0℃
7.6 Switching Characteristics
Unless otherwise noted: voltage, resistance, capacitance, and inductance are respect to GND; –40℃ ≤ TJ ≤ 125℃;
VDS = 480 V; 9 V ≤ VVDD ≤ 18 V; VIN = 0 V; RDRV connected to LDO5V; LBBSW = 4.7 µH
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
SWITCHING TIMES
Drain-current turn-on delay time
From VIN > VIN,IT+ to ID > 1 A, VBUS =
400 V, LHB current = 10 A, see Figure 8-1
and Figure 8-2
28
42
ns
td(on)
Turn-on delay time
From VIN > VIN,IT+ to VDS < 320 V, VBUS =
400 V, LHB current = 10 A, see Figure 8-1
and Figure 8-2
32
52
ns
tr(on)
Turn-on rise time
From VDS < 320 V to VDS < 80 V, VBUS =
400 V, LHB current = 10 A, see Figure 8-1
and Figure 8-2
2.5
4
ns
td(off)
Turn-off delay time
From VIN < VIN ,IT– to VDS > 80 V, VBUS =
400 V, LHB current = 10 A, see Figure 8-1
and Figure 8-2
44
65
ns
tf(off)
Turn-off fall time(1)
From VDS > 80 V to VDS > 320 V, VBUS =
400 V, LHB current = 10 A, see Figure 8-1
and Figure 8-2
21
ns
Minimum IN high pulse-width for FET
turn-on
VIN rise/fall times < 1 ns, VDS falls to <
200 V, VBUS = 400 V, LHB current = 10 A,
see Figure 8-1
24
ns
td(on)
(Idrain)
STARTUP TIMES
8
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7.6 Switching Characteristics (continued)
Unless otherwise noted: voltage, resistance, capacitance, and inductance are respect to GND; –40℃ ≤ TJ ≤ 125℃;
VDS = 480 V; 9 V ≤ VVDD ≤ 18 V; VIN = 0 V; RDRV connected to LDO5V; LBBSW = 4.7 µH
PARAMETER
TEST CONDITIONS
Driver start-up time
TYP
MAX
UNIT
From VVDD > VVDD,T+
(UVLO) to FAULT high, CLDO5V = 100
nF, CVNEG = 2.2 µF at 0-V bias linearly
decreasing to 1.5 µF at 15-V bias
MIN
310
470
us
FAULT TIMES
toff(OC)
Overcurrent fault FET turn-off time, FET
on before overcurrent
VIN = 5 V, From ID > IT(OC) to ID < 50 A, ID
di/dt = 100 A/µs
110
145
ns
toff(SC)
Short-circuit current fault FET turn-off
time, FET on before short circuit
VIN = 5 V, From ID > IT(SC) to ID < 50 A, ID
di/dt = 700 A/µs
65
100
ns
Overcurrent fault FET turn-off time, FET
turning on into overcurrent
From ID > IT(OC) to ID < 50 A
200
250
ns
Short-circuit fault FET turn-off time, FET
turning on into short circuit
From ID > IT(SC) to ID < 50 A
80
180
ns
IN reset time to clear FAULT latch
From VIN < VIN,IT– to FAULT high
380
580
us
250
IDEAL-DIODE MODE CONTROL TIMES
Ideal-diode mode FET turn-on time
VDS < VT(3rd) to FET turn-on, VDS being
discharged by half-bridge configuration
inductor at 5 A
50
65
ns
Ideal-diode mode FET turn-off time
ID > IT(ZC) to FET turn-off, ID di/dt =
100 A/µs created with a half-bridge
configuration
50
76
ns
230
360
ns
Overtemperature-shutdown ideal-diode
mode IN falling blanking time
(1)
150
During turn-off, VDS rise time is the result of the resonance of COSS and loop inductance as well as load current.
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140
85
80
75
70
65
60
55
50
45
40
35
30
25
20
−40°C
0°C
25°C
85°C
125°C
50
100
150 200 250 300 350
RDRV Resistance (k)
400
450
80
60
20
500
Figure 7-1. Drain-Current Turn-On Delay Time vs Drive Strength
Resistance
0
Turn-On Slew Rate (V/ns)
10
5
400
450
500
−40°C
0°C
25°C
85°C
125°C
80
60
40
20
0
0
50
100
150 200 250 300 350
RDRV Resistance (k)
400
450
Figure 7-3. Turn-On Rise Time vs Drive Strength Resistance
6.5
−40°C
0°C
25°C
85°C
125°C
5
4.5
4
3.5
3
5
10
15
20
Source Current (A)
25
30
0
500
35
50
100
150 200 250 300 350
RDRV Resistance (k)
400
450
500
Figure 7-4. Turn-On Slew Rate vs Drive Strength Resistance
Normalized Drain-Source On Resistance (m)
0
0
150 200 250 300 350
RDRV Resistance (k)
100
15
5.5
100
120
−40°C
0°C
25°C
85°C
125°C
20
6
50
Figure 7-2. Turn-On Delay Time vs Drive Strength Resistance
25
Turn-On Rise Time (ns)
100
40
0
Source-Drain Voltage (V)
−40°C
0°C
25°C
85°C
125°C
120
Turn-On Delay Time (ns)
Drain-Current Turn-On Delay Time (ns)
7.7 Typical Characteristics
2.2
2
1.8
1.6
1.4
1.2
1
0.8
0.6
-40
-20
0
20
40
60
80 100
Junction Temperature (°C)
120
140
160
Figure 7-6. Normalized On-Resistance vs Junction Temperatue
IN = 0 V
Figure 7-5. Off-State Source-Drain Voltage vs Source Current
10
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7.7 Typical Characteristics (continued)
250
VDS = 0 V
VDS = 50 V
VDS = 400 V
200
150
VDS = 400 V
VDD Supply Current (mA)
VDD Supply Current (mA)
250
VDS = 50 V
100
VDS = 0 V
50
0
VDS = 0 V
VDS = 50 V
VDS = 400 V
200
150
VDS = 50 V
100
VDS = 0 V
50
0
0
400
800
1200
1600
IN Switching Frequency (kHz)
2000
0
TJ = 25°C
400
800
1200
1600
IN Switching Frequency (kHz)
2000
TJ = 125°C
Figure 7-7. VDD Supply Current vs IN Switching Frequency
Figure 7-8. VDD Supply Current vs IN Switching Frequency
1750
120
1250
1000
750
500
100
Switching Energy (J)
−40°C
0°C
25°C
85°C
125°C
1500
Output Capacitance (pF)
VDS = 400 V
80
60
Turn-On Switching Energy (J)
Turn-Off Switching Energy (J)
40
20
250
0
0
0
50
100
150 200 250 300 350
Drain-Source Voltage (V)
400
450
500
Figure 7-9. Output Capacitance vs Drain-Source Voltage
0
3
6
9
12
15
18
21
Inductive Load Current (A)
24
27
30
Figure 7-10. Half-Bridge Switching Energy vs Inductive Load
Current
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8 Parameter Measurement Information
8.1 Switching Parameters
Figure 8-1 shows the circuit used to measure most switching parameters. The top device in this circuit is used
to re-circulate the inductor current and functions in third-quadrant mode only. Only the LMG3422R030 must be
used as the top device as it does not have the ideal-diode mode feature. Do not use the LMG3425R030 for the
top device. If the top device has the ideal-diode mode feature, it will automatically turn on the GaN FET when
the inductor current is re-circulating and cause a shoot-through current event when the bottom device turns on.
The bottom device is the active device that turns on to increase the inductor current to the desired test current.
The bottom device is then turned off and on to create switching waveforms at a specific inductor current. Both
the drain current (at the source) and the drain-source voltage is measured. Figure 8-2 shows the specific timing
measurement. TI recommends to use the half-bridge as double pulse tester. Excessive third-quadrant operation
can overheat the top device.
DRAIN
RDRV
Slew
Rate
Direct- Drive
GaN
SOURCE
IN
VDD
VNEG
OCP, OTP, Current
LDO,
UVLO,
BB
TEMP
LDO5V
LHB
TEMP
FAULT
OC
VBUS
+
SOURCE
CPCB
±
DRAIN
RDRV
Slew
Rate
Direct- Drive
GaN
SOURCE
+
IN
VDD
LDO5V
VNEG
OCP, OTP, Current
LDO,
UVLO,
BB
TEMP
VDS
_
TEMP
PWM input
FAULT
OC
SOURCE
Figure 8-1. Circuit Used to Determine Switching Parameters
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IN
50%
50%
td(on)(Idrain)
ID
1A
td(on)
td(off)
tr(on)
VDS
tf(off)
80%
80%
20%
20%
Figure 8-2. Measurement to Determine Propagation Delays and Slew Rates
8.1.1 Turn-On Times
The turn-on transition has three timing components: drain-current turn-on delay time, turn-on delay time, and
turn-on rise time . The drain-current turn-on delay time is from when IN goes high to when the GaN FET
drain-current reaches 1 A. The turn-on delay time is from when IN goes high to when the drain-source voltage
falls 20% below the bus voltage. Finally, the turn-on rise time is from when drain-source voltage falls 20% below
the bus voltage to when the drain-source voltage falls 80% below the bus voltage. Note that the turn-on rise time
is the same as the VDS 80% to 20% fall time. All three turn-on timing components are a function of the RDRV pin
setting.
8.1.2 Turn-Off Times
The turn-off transition has two timing components: turn-off delay time, and turn-off fall time. The turn-off delay
time is from when IN goes low to when the drain-source voltage rises to 20% of the bus voltage. The turn-off
fall time is from when the drain-source voltage rises to 20% of the bus voltage to when the drain-source voltage
rises to 80% of the bus voltage. Note that the turn-off fall time is the same as the VDS 20% to 80% rise time.
The turn-off timing components are independent of the RDRV pin setting, but heavily dependent on the LHB load
current.
8.1.3 Drain-Source Turn-On Slew Rate
The drain-source turn-on slew rate, measured in volts per nanosecond, is the inverse of the turn-on rise time or
equivalently the inverse of the VDS 80% to 20% fall time. The RDRV pin is used to program the slew rate.
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8.1.4 Turn-On and Turn-Off Switching Energy
The turn-on and turn-off switching energy shown in Figure 7-10 represent the energy absorbed by the low-side
device during the turn-on and turn-off transients of the circuit. As the circuit in Figure 8-1 represents a boost
converter with input shorted to output, the switching energy is dissipated in the low-side device. The turn-on
transition is lossy while the turn-off transition is essentially lossless with the output capacitance energy charged
by the inductor current. The turn-on and turn-off losses have been calculated from experimental waveforms by
integrating the product of the drain current with the drain-source voltage over the turn-on and turn-off times,
respectively. The skew of probes for voltage and current are very important for accurate measurement of turn-on
and turn-off energy.
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9 Detailed Description
9.1 Overview
The LMG342xR030 is a high-performance power GaN device with integrated gate driver. The GaN device
offers zero reverse recovery and ultra-low output capacitance, which enables high efficiency in bridge-based
topologies. Direct Drive architecture is applied to control the GaN device directly by the integrated gate driver.
This architecture provides superior switching performance compared to the traditional cascode approach and
helps solve a number of challenges in GaN applications.
The integrated driver ensures the device stays off for high drain slew rates. The integrated driver also protects
the GaN device from overcurrent, short-circuit, undervoltage, and overtemperature. Regarding fault signal
reporting, LMG342xR030 provides different reporting method which is shown in Table 9-1. Refer to Fault
Detection for more details. The integrated driver is also able to sense the die temperature and send out the
temperature signal through a modulated PWM signal.
Unlike Si MOSFETs, GaN devices do not have a p-n junction from source to drain and thus have no reverse
recovery charge. However, GaN devices still conduct from source to drain similar to a p-n junction body diode,
but with higher voltage drop and higher conduction loss. Therefore, source-to-drain conduction time must be
minimized while the LMG342xR030 GaN FET is turned off. The ideal-diode mode feature in the LMG3425R030
automatically minimizes the source-to-drain conduction loss that occur on the GaN FET soft-switched turn-on
edge, similar to optimum dead-time control.
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9.2 Functional Block Diagram
TEMP
VDD
LDO5V
DRAIN
Third-Quadrant
Detection
GaN
LDO
UVLO
(+5V, VDD, VNEG)
FAULT
Thermal
Shutdown
Die
Temp
Sensing
Series
Si FET
Short Circuit Protection
OC
Overcurrent Protection
IN
Gating logic control
& level shifting
BBSW
Buck-Boost
Controller
VNEG
RDRV
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9.3 Feature Description
The LMG342xR030 includes advanced features to provide superior switching performance and converter
efficiency.
9.3.1 GaN FET Operation Definitions
For the purposes of this data sheet, the following terms are defined below. The SOURCE pin is assumed to be at
0 V for these definitions.
First-Quadrant Current = Positive current flowing internally from the DRAIN pin to the SOURCE pin.
Third-Quadrant Current = Positive current flowing internally from the SOURCE pin to the DRAIN pin.
First-Quadrant Voltage = Drain pin voltage – Source pin voltage = Drain pin voltage
Third-Quadrant Voltage = SOURCE pin voltage – DRAIN pin voltage = –DRAIN pin voltage
FET On-State = FET channel is at rated RDS(on). Both first-quadrant current and third-quadrant current can flow
at rated RDS(on).
FET Off-State = FET channel is fully off for positive first-quadrant voltage. No first-quadrant current can flow.
While first-quadrant current cannot flow in the FET Off-State, third-quadrant current still flows if the DRAIN
voltage is taken sufficiently negative (positive third-quadrant voltage). For devices with an intrinsic p-n junction
body diode, current flow begins when the DRAIN voltage drops enough to forward bias the p-n junction.
GaN FETS do not have an intrinsic p-n junction body diode. Instead, current flows because the GaN FET
channel turns back on. In this case, the DRAIN pin becomes the electrical source and the SOURCE pin
becomes the electrical drain. To enhance the channel in third-quadrant, the DRAIN (electrical source) voltage
must be taken sufficiently low to establish a VGS voltage greater than the GaN FET threshold voltage. The GaN
FET channel is operating in saturation and only turns on enough to support the third-quadrant current as its
saturated current.
LMG342xR030 GaN FET On-State = GaN FET internal gate voltage is held at the SOURCE pin voltage to
achieve rated RDS(on). The GaN FET channel is at rated RDS(on) with VGS = 0 V because the LMG342xR030 GaN
FET is a depletion mode FET.
LMG342xR030 GaN FET Off-State = GaN FET internal gate voltage is held at the VNEG pin voltage to block
all first-quadrant current. The VNEG voltage is lower than the GaN FET negative threshold voltage to cut off the
channel.
To enhance the channel in off-state third quadrant, the LMG342xR030 DRAIN (electrical source) voltage must be
taken sufficiently close to VNEG to establish a VGS voltage greater than the GaN FET threshold voltage. Again,
because the LMG342xR030 GaN FET is a depletion mode FET with a negative threshold voltage, this means
the GaN FET turns on with DRAIN (electrical source) voltage between 0 V and VNEG. The typical off-state
third-quadrant voltage is 4.5 V for third-quadrant current at 20 A. Thus, the off-state third-quadrant losses for
the LMG342xR030 are significantly higher than a comparable power device with an intrinsic p-n junction body
diode. The ideal-diode mode function described in Ideal-Diode Mode Operation can help mitigate these losses in
specific situations.
9.3.2 Direct-Drive GaN Architecture
The LMG342xR030 uses a series Si FET to ensure the power IC stays off when VDD bias power is not applied.
When the VDD bias power is off, the series Si FET is interconnected with the GaN device in a cascode mode,
which is shown in the Functional Block Diagram. The gate of the GaN device is held within a volt of the series
Si FET's source. When a high voltage is applied on the module and the silicon FET blocks the drain voltage, the
VGS of the GaN device decreases until the GaN device passes the threshold voltage. Then, the GaN device is
turned off and blocks the remaining major part of drain voltage. There is an internal clamp to make sure that the
VDS does not exceed its maximum rating. This feature avoids the avalanche of the series Si FET when there is
no bias power.
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When LMG342xR030 is powered up with VDD bias power, the internal buck-boost converter generates a
negative voltage (VVNEG) that is sufficient to directly turn off the GaN device. In this case, the series Si FET is
held on and the GaN device is gated directly with the negative voltage. During operation, this action removes the
switching loss of the series Si FET.
9.3.3 Drain-Source Voltage Capability
Due to the silicon FET’s long reign as the dominant power-switch technology, many designers are unaware
that the headline drain-source voltage cannot be used as an equivalent point to compare devices across
technologies. The headline drain-source voltage of a silicon FET is set by the avalanche breakdown voltage.
The headline drain-source voltage of a GaN FET is set by the long term reliability with respect to data sheet
specifications.
Exceeding the headline drain-source voltage of a silicon FET can lead to immediate and permanent damage.
Meanwhile, the breakdown voltage of a GaN FET is much higher than the headline drain-source voltage. For
example, the breakdown voltage of the LMG342xR030 is more than 800 V.
A silicon FET is usually the weakest link in a power application during an input voltage surge. Surge protection
circuits must be carefully designed to ensure the silicon FET avalanche capability is not exceeded because it
is not feasible to clamp the surge below the silicon FET breakdown voltage. Meanwhile, it is easy to clamp the
surge voltage below a GaN FET breakdown voltage. In fact, a GaN FET can continue switching during the surge
event which means output power is safe from interruption.
The LMG342xR030 drain-source capability is explained with the assistance of Figure 9-1. The figure shows the
drain-source voltage versus time for a GaN FET for a single switch cycle in a switching application. No claim is
made about the switching frequency or duty cycle.
VDS(tr)
VDS(off)
VDS(switching)
t0
t1
t2
Figure 9-1. Drain-Source Voltage Switching Cycle
The waveform starts before t0 with the FET in the on state. At t0 the GaN FET turns off and parasitic elements
cause the drain-source voltage to ring at a high frequency. The peak ring voltage is designated VDS(tr). The
high frequency ringing has damped out by t1. Between t1 and t2 the FET drain-source voltage is set by
the characteristic response of the switching application. The characteristic is shown as a flat line, but other
responses are possible. The voltage between t1 and t2 is designated VDS(off). At t2 the GaN FET is turned on at
a non-zero drain-source voltage. The drain-source voltage at t2 is designated VDS(switching). Unique VDS(tr), VDS(off)
and VDS(switching) parameters are shown because each can contribute to stress over the lifetime of the GaN FET.
The LMG342xR030 drain-source surge voltage capability is seen with the absolute maximum ratings VDS(tr)(surge)
and VDS(surge) in Absolute Maximum Ratings where VDS(tr)(surge) maps to VDS(tr) in Figure 9-1 and VDS(surge) maps
to both VDS(off) and VDS(switching) in Figure 9-1. More information about the surge capability of TI GaN FETs is
found in A New Approach to Validate GaN FET Reliability to Power-line Surges Under Use-conditions.
9.3.4 Internal Buck-Boost DC-DC Converter
An internal inverting buck-boost converter generates a regulated negative rail for the turn-off supply of the
GaN device. The buck-boost converter is controlled by a peak current mode, hysteretic controller. In normal
operation, the converter remains in discontinuous-conduction mode, but can enter continuous-conduction mode
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during start-up and overload the conditions. The converter is controlled internally and requires only a single
surface-mount inductor and output bypass capacitor.
The LMG342xR030 supports the GaN operation up to 2.2 MHz. As power consumption is very different in a
wide switching frequency range enabled by the GaN device, two peak current limits are used to control the
buck-boost converter. The two ranges are separated by IN positive-going threshold frequency. When switching
frequency is in the lower range, the peak current is set to the lower value (around 0.4 A) so a smaller inductor
can be selected. When switching frequency is in the higher range, the peak current is raised to the higher value
(around 1 A) and requires a larger inductor. There is a filter on this frequency detection logic, therefore the
LMG342xR030 requires five consecutive cycles at the higher frequency before it is set to the higher buck-boost
peak current limit. The current limit does not go down again until power off after the higher limit is set. Even if the
switching frequency returns to the lower range, the current limit does not decrease to the lower limit.
9.3.5 VDD Bias Supply
Wide VDD voltage ranges from 7.5 V to 18 V are supported by an internal LDO which regulates supplies
the internal low voltage and buck-boost converter circuits. If the VDD input voltage is less than 9 V, then the
maximum switching frequency is de-rated. TI recommends to use a 12-V unregulated power supply to supply
VDD, otherwise no external LDO is needed.
9.3.6 Auxiliary LDO
There is a 5-V voltage regulator inside the part used to supply external loads, such as digital isolators for the
high-side drive signal. The digital outputs of the part use this rail as their supply. No capacitor is required for
stability, but transient response is poor if no external capacitor is provided. If the application uses this rail to
supply external circuits, TI recommends to have a capacitor of at least 0.1 μF for improved transient response.
A larger capacitor can be used for further transient response improvement. The decoupling capacitor used
here must be a low-ESR ceramic type. Capacitances above 0.47 μF will slow down the start-up time of the
LMG342xR030 due to the ramp-up time of the 5-V rail.
9.3.7 Fault Detection
The GaN power IC integrates overcurrent protection (OCP), short-circuit protection (SCP), overtemperature
protection (OTP) and undervoltage lockout (UVLO).
9.3.7.1 Overcurrent Protection and Short-Circuit Protection
There are two types of current faults which can be detected by the driver: overcurrent fault and short-circuit fault.
The overcurrent protection (OCP) circuit monitors drain current and compares that current signal with an
internally set limit. Upon detection of the overcurrent, the LMG342xR030 conducts cycle-by-cycle overcurrent
protection as shown in Figure 9-2. In this mode, the GaN device is shut off when overcurrent happens, but
the overcurrent signal clears after the input PWM goes low. In the next cycle, the GaN device can turn on as
normal. The cycle-by-cycle function can be used in cases where steady-state operation current is below the
OCP level but transient response can still reach current limit, while the circuit operation cannot be paused.
The cycle-by-cycle function also prevents the GaN device from overheating by overcurrent induced conduction
losses.
The short-circuit protection (SCP) monitors drain current and compares that current signal with a internally set
limit higher than that of OCP as shown in Figure 9-3. The short-circuit protection is designed to protect the GaN
device from high-current short-circuit fault. If a short-circuit fault is detected, the driver turn-off is intentionally
slowed down to obtain lower di/dt so that a lower overshoot voltage and ringing can be achieved during the
turn-off event. On detection of an overcurrent fault, LMG342xR030 latches off. This fast response circuit helps
protect the GaN device even under a hard short-circuit condition. In this protection, the GaN device is shut
off and held off until the fault is reset by either holding the IN pin low for a period of time defined in the
Specifications or removing power from VDD.
During OCP or SCP in a half bridge, after the current reaches the upper limit and the device is turned off by
protection, the PWM input of the device could still be high and the PWM input of the complementary device
could still be low. In this case, the load current can flow through the third quadrant of the complementary device
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with no synchronous rectification. The extra high negative voltage drop (–6 V to –8 V) from drain to source could
lead to high third-quadrant loss, similar to dead-time loss but for a longer time.
For safety considerations, OCP allows cycle-by-cycle operation while SCP latches the device until reset. By
reading the FAULT and OC pins, the exact current fault type can be determined. Refer to Fault Reporting for
detailed information.
IT(OC)
Inductor current
VSW
Input PWM
Figure 9-2. Cycle-by-Cycle OCP Operation
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toff(SC)
toff(OC)
IT(SC)
IT(OC)
ID
IN
OC
Cycle by cycle OCP
Latched SCP
Figure 9-3. Overcurrent Detection vs Short-Circuit Detection
9.3.7.2 Overtemperature Shutdown
The LMG342xR030 implements two overtemperature-shutdown (OTSD) functions, the GaN OTSD and the
Driver OTSD. Two OTSD functions are needed to maximize device protection by sensing different locations in
the device and protecting against different thermal-fault scenarios.
The GaN OTSD senses the GaN FET temperature. The GaN FET can overheat from both first-quadrant current
and third-quadrant current. As explained in GaN FET Operation Definitions, a FET can prevent first-quadrant
current by going into the off-state but is unable to prevent third-quadrant current. FET third-quadrant losses are
a function of the FET technology, current magnitude, and if the FET is operating in the on-state or off-state.
As explained in GaN FET Operation Definitions, the LMG342xR030 has much higher GaN FET third-quadrant
losses in the off-state.
When the GaN FET is too hot, the best protection is to turn off the GaN FET when first-quadrant current tries
to flow and turn on the GaN FET when third-quadrant current is flowing. This type of FET control is known
as ideal-diode mode (IDM). When the GaN OTSD trip point is exceeded, the GaN OTSD puts the GaN FET
into overtemperature-shutdown ideal-diode mode (OTSD-IDM) operation to achieve this optimum protection.
OTSD-IDM is explained in Ideal-Diode Mode Operation.
The Driver OTSD senses the integrated driver temperature and trips at a higher temperature compared to the
GaN OTSD. This second OTSD function exists to protect the LMG342xR030 from driver thermal-fault events
while allowing sufficient temperature difference for OTSD-IDM to operate. These driver thermal events include
shorts on the LD05V, BBSW, and VNEG device pins. When the Driver OTSD trip point is exceeded, the Driver
OTSD shuts off the LDO5V regulator, the VNEG buck-boost converter, and the GaN FET. Note that OTSD-IDM
does not function in Driver OTSD. This is why the Driver OTSD must trip higher than the GaN OTSD function.
Otherwise, GaN FET third-quadrant overheating cannot be addressed.
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Besides the temperature difference in the GaN OTSD and Driver OTSD trip points, further temperature
separation is obtained due to the thermal gradient difference between the GaN OTSD and Driver OTSD sense
points. The GaN OTSD sensor is typically at least 20°C hotter than the driver OTSD sensor when the device is in
GaN OTSD due to GaN FET power dissipation.
The FAULT pin is asserted for either or both the GaN OTSD state and the Driver OTSD state. FAULT de-asserts
and the device automatically returns to normal operation after both the GaN OTSD and Driver OTSD fall below
their negative-going trip points. During cool down, when the device exits the Driver OTSD state but is still in the
GaN OTSD state, the device automatically resumes OTSD-IDM operation.
9.3.7.3 UVLO Protection
The LMG342xR030 supports a wide range of VDD voltages. However, when the device is below UVLO
threshold, the GaN device stops switching and is held off. The FAULT pin is pulled low as an indication of
UVLO. The LDO is turned on by the rising-edge of the VIN UVLO and shuts off around 5 V to 6 V.
9.3.7.4 Fault Reporting
The FAULT and OC outputs form a fault reporting scheme together. The FAULT and OC outputs are both
push-pull outputs indicating the readiness and fault status of the driver. These two pins are logic high in normal
operation, and change logic according to Table 9-1.
Table 9-1. Fault Types and Reporting
NORMAL
UVLO, OT, and RDRV-OPEN
OVERCURRENT
SHORT-CIRCUIT
FAULT
1
0
1
0
OC
1
1
0
0
FAULT is held low when starting up until the series Si FET is turned on. During operation, if the power supplies
go below the UVLO thresholds or the device temperature go above the OT thresholds, power device is disabled
and FAULT is held low until a fault condition is no longer detected. If RDRV is open, FAULT is also held low.
In a short-circuit or overtemperature fault condition, FAULT is held low until the fault latches are reset or fault is
cleared. The OC pin is held low if there is a short-circuit or overcurrent fault. The signals help notify the controller
the exact type of faults by reading the truth table. If a combined reporting of the faults on a single pin is desired,
one can short the OC pin to ground during power up. All faults assert the FAULT pin then and the OC pin is not
used. Please note: internal protection happens regardless of the connection of the pin outputs, which means that
the protection features continue to operate even if fault reporting is ignored..
9.3.8 Drive Strength Adjustment
The LMG342xR030 allows users to adjust the drive strength of the device and obtain a desired slew rate, which
provides flexibility when optimizing switching losses and noise coupling.
To adjust drive strength, a resistor can be placed between the RDRV pin and GND pin. The resistance
determines the slew rate of the device, from 30 V/ns to 150 V/ns, during turn-on. On the other hand, there
are two dv/dt values that can be selected without the resistor: shorting the RDRV pin to ground sets the slew rate
to 150 V/ns, and shorting the RDRV pin to LDO5V sets the slew rate to 100 V/ns. The device detects the short
to LDO5V one time at power up. Once the short to LDO5V condition is detected, the device no longer monitors
the RDRV pin. Otherwise, the RDRV pin is continuously monitored and the dv/dt setting can be changed by
modulating the resistance during device operation. The modulation must be fairly slow since there is there is
significant internal filtering to reject switching noise.
9.3.9 Temperature-Sensing Output
The integrated driver senses the GaN die temperature and outputs the information through a modulated PWM
signal on the TEMP pin. The typical PWM frequency is 9 kHz with the same refresh rate. The minimum PWM
duty cycle is around 1%, which can be observed at temperature below 25°C. The target temperature range is
from 25°C to 150°C, and the corresponding PWM duty cycle is typically from 3% to 82%. At temperatures above
150°C, the duty cycle continues to increase linearly until overtemperature fault happens. When overtemperature
happens, the TEMP pin is pulled high to indicate this fault until the temperature is reduced to the normal range.
There is a hysteresis to clear overtemperature fault.
22
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9.3.10 Ideal-Diode Mode Operation
Off-state FETs act like diodes by blocking current in one direction (first quadrant) and allowing current in the
other direction (third quadrant) with a corresponding diode like voltage drop. FETs, though, can also conduct
third-quadrant current in the on-state at a significantly lower voltage drop. Ideal-diode mode (IDM) is when an
FET is controlled to block first-quadrant current by going to the off-state and conduct third-quadrant current by
going to the on-state, thus achieving an ideal lower voltage drop.
FET off-state third-quadrant current flow is commonly seen in power converters, both in normal and fault
situations. As explained in GaN FET Operation Definitions, GaN FETs do not have an intrinsic p-n junction
body diode to conduct off-state third-quadrant current. Instead, the off-state third-quadrant voltage drop for the
LMG342xR030 is several times higher than a p-n junction voltage drop, which can impact efficiency in normal
operation and device ruggedness in fault conditions.
To mitigate efficiency degradation, the LMG3425R030 implements an operational ideal-diode mode (OP-IDM)
function. Meanwhile, to improve device ruggedness in a GaN FET overtemperature fault situation, all devices
in the LMG342xR030 family implement a GaN FET overtemperature-shutdown ideal-diode mode (OTSD-IDM)
function as referenced in Overtemperature Shutdown. Both OP-IDM and OTSD-IDM are described in more detail
below.
Operational Ideal-Diode Mode (LMG3425R030)
Operational ideal-diode mode (OP-IDM) is implemented in the LMG3425R030 but not in the LMG3422R030.
Understand that the OP-IDM function is not a general-purpose ideal-diode mode function which allows the
LMG342xR030 to autonomously operate as a diode, including as an autonomous synchronous rectifier.
Furthermore, the OP-IDM function is not intended to support an ideal-diode mode transition from the on-state to
the off-state in a high-voltage, hard-switched application. Exposing the LMG342xR030 to this situation is akin to
operating a half-bridge power stage with negative dead time with corresponding high shoot-through current.
Instead, as described below, the LMG342xR030 OP-IDM function is narrowly implemented to address a specific
off-state third-quadrant current flow situation while minimizing situations where the ideal-diode mode can create
a dangerous shoot-through current event.
OP-IDM is intended to minimize GaN FET off-state third-quadrant losses that occur in a zero-voltage switched
(ZVS) event. ZVS events are seen in applications such as synchronous rectifiers and LLC converters. The ZVS
event occurs at the FET off-state to on-state transition when an inductive element discharges the FET drain
voltage before the FET is turned-on. The discharge ends with the inductive element pulling the FET drain-source
voltage negative and the FET conducting off-state third-quadrant current.
Power supply controllers use dead-time control to set the time for the ZVS event to complete before turning
on the FET. Both the ZVS time and resulting FET off-state third-quadrant current are a function of the power
converter operation. Long ZVS time and low third-quadrant current occur when the inductive element is slewing
the FET with low current and short ZVS time and high third-quadrant current occur when the inductive element
is slewing at the FET with high current. Sophisticated controllers optimally adjust the dead time to minimize
third-quadrant losses. Simpler controllers use a fixed dead time to handle the longest possible ZVS time.
Thus, in a fixed dead-time application, the highest possible off-state third-quadrant losses occur for the longest
possible time.
OP-IDM mitigates the losses in a fixed dead-time application by automatically turning on the GaN FET as soon
as third-quadrant current is detected. In this sense, OP-IDM can be described as providing a turn-on assist
function with optimum dead-time control. Meanwhile, OP-IDM is not intended to be used to turn-off the GaN
FET in normal operation. OP-IDM turnoff capability is only provided as a protection mechanism to guard against
shoot-through current.
OP-IDM works within the confines of normal LMG342xR030 switching operation as controlled by the IN pin.
The key consideration for the OP-IDM operation is to ensure the turn-on assist function is only activated on
the ZVS edge. For example, third-quadrant current is seen in a LMG342xR030 used as a synchronous rectifier
both before the IN pin goes high to turn on the GaN FET and after the IN pin goes low to turn off the GaN
FET. OP-IDM turns on the GaN FET before the IN pin goes high when OP-IDM detects third-quadrant current.
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But it would be a mistake for OP-IDM to turn the GaN FET back on right after IN has turned it off because
OP-IDM detects third-quadrant current. If OP-IDM were to turn on the GaN FET in this situation, it would create
a shoot-through current event when the opposite-side power switch turns on. OP-IDM avoids this shoot-through
current problem on the turn-off edge by requiring the drain voltage to first go positive before looking for the ZVS
event.
The OP-IDM state machine is shown in Figure 9-4. Each state is assigned a state number in the upper right side
of the state box.
1
FET OFF
IN low
FET ON
OP-IDM looking for
positive VDS
5
OP-IDM idle
IN high
Positive VDS
IN high
IN high
2
FET OFF
OP-IDM looking for
negative VDS
Power
Up
IN high
FET ON
Negative VDS due to
third-quadrant drain
current
OP-IDM looking for firstquadrant drain current
4
3
FET Off
First-quadrant drain
current
OP-IDM locks FET off
Exit OTSD
Figure 9-4. Operational Ideal-Diode Mode (OP-IDM) State Machine
1. A new OP-IDM cycle begins in OP-IDM state #1 after the IN pin goes low in OP-IDM state #5. OP-IDM turns
off the GaN FET in OP-IDM state #1. OP-IDM monitors the GaN FET drain voltage, looking for a positive
drain voltage to know it can now start looking for a ZVS event. After a positive GaN FET drain voltage is
detected, the device moves to OP-IDM state #2.
2. OP-IDM keeps the GaN FET off in OP-IDM state #2. OP-IDM continues monitoring the GaN FET drain
voltage. But this time it is looking for a negative drain voltage which means third-quadrant current is flowing
after a ZVS event. This is also the starting state when the device powers up or exits OTSD. After a negative
GaN FET drain voltage is detected, the device moves to OP-IDM state #3.
3. OP-IDM turns on the GaN FET in OP-IDM state #3. OP-IDM monitors the drain current in this state. Ideally,
the device simply stays in this state until IN goes high. The drain current is monitored to protect against
an unexpected shoot-through current event. If first-quadrant drain current is detected, the device moves to
OP-IDM state #4.
4. OP-IDM locks the GaN FET off in OP-IDM state #4. The GaN FET only turns back on when the IN pin goes
high.
5. The device moves to OP-IDM state #5 from any other state when the IN pin goes high. The GaN FET is
commanded on in OP-IDM state #5. OP-IDM is idle in this state. A new OP-IDM switching cycle begins when
IN goes low moving the device into OP-IDM state #1.
OP-IDM can only turn on the GaN FET once per IN cycle. If an unexpected shoot-through current is detected
between OP-IDM turning on the GaN FET and the IN pin going high, OP-IDM locks the GaN FET off for the
remainder of the IN cycle.
Understand that the OP-IDM function turns on the GaN FET, after IN goes low, if it sees a positive drain voltage
followed by a negative drain voltage. A design using the LMG3425R030 must be analyzed for any situations
where this sequence of events creates a shoot-through current event. The analysis must include all power
system corner cases including start-up, shutdown, no load, overload, and fault events. Note that discontinuous
24
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mode conduction (DCM) operation can easily create an OP-IDM shoot-through current event when the ringing at
the end of a DCM cycle triggers OP-IDM to turn on the GaN FET.
Overtemperature-Shutdown Ideal-Diode Mode
Overtemperature-shutdown ideal-diode mode (OTSD-IDM) is implemented in all devices in the LMG342xR030
family. As explained in Overtemperature Shutdown, ideal-diode mode provides the best GaN FET protection
when the GaN FET is overheating.
OTSD-IDM accounts for all, some, or none of the power system operating when OTSD-IDM is protecting the
GaN FET. The power system may not have the capability to shut itself down, in response to the LMG342xR030
asserting the FAULT pin in a GaN OTSD event, and just continue to try to operate. Parts of the power system
can stop operating due to any reason such as a controller software bug or a solder joint breaking or a device
shutting off to protect itself. At the moment of power system shutdown, the power system stops providing gate
drive signals but the inductive elements continue to force current flow while they discharge.
The OTSD-IDM state machine is shown in Figure 9-5. Each state is assigned a state number in the upper right
side of the state box. The OTSD-IDM state machine has a similar structure to the OP-IDM state machine. Similar
states use the same state number.
1
FET OFF
OTSD-IDM waiting for IN
falling-edge blank time to
expire
IN falling-edge blank
time expired
IN falling edge
FET OFF
2
IN falling edge
First-quadrant drain
current
3
FET ON
OTSD-IDM looking for negative
VDS
OTSD-IDM looking for firstquadrant drain current
Negative VDS due to
third-quadrant drain
current
Enter OTSD
Figure 9-5. Overtemperature-Shutdown Ideal-Diode Mode (OTSD-IDM) State Machine
1. The LMG342xR030 GaN FET always goes to state #1 if a falling edge is detected on the IN pin. OTSD-IDM
turns off the GaN FET in OTSD-IDM state #1. OTSD-IDM is waiting for the IN falling edge blank time to
expire. This time gives the opposite-side FET time to switch to create a positive drain voltage. After the blank
time expires, the device moves to OTSD-IDM state #2.
2. For OTSD-IDM state #2, OTSD-IDM keeps the GaN FET off if it is coming from OTSD-IDM state #1 and
turns the GaN FET off if it is coming from OTSD-IDM state #3. OTSD-IDM is monitoring the GaN FET drain
voltage in OP-IDM state #2. It is looking for a negative drain voltage which means third-quadrant current is
flowing. This is also the starting state when the device enters OTSD. After a negative GaN FET drain voltage
is detected, the device moves to OTSD-IDM state #3
3. OP-IDM turns on the GaN FET in OTSD-IDM state #3. OP-IDM monitors the drain current in this state. If
first-quadrant drain current is detected, the device moves to OP-IDM state #2.
State #1 is used to protect against shoot-through current in a similar manner to OP-IDM state #1. The difference
is that state #1 in the OTSD-IDM state machine simply waits for a fixed time period before proceeding to state
#2. The fixed time period is to give the opposite-side switch time to switch and create a positive drain voltage. A
fixed time is used to avoid a stuck condition for cases where a positive drain voltage is not created.
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State #1 will help protect against shoot-through currents if the converter continues switching when the
LMG342xR030 enters OTSD. Meanwhile, if the converter initiates switching with the LMG342xR030 already
in OTSD, shoot-through current protection can be obtained by switching the OTSD device first to force it to
progress though state #1. For example, the synchronous rectifier in a boost PFC can go into OTSD during initial
input power application as the inrush current charges the PFC output cap. A shoot-through current event can be
avoided if converter switching begins by switching the synchronous rectifier FET before switching the boost PFC
FET.
If there is no IN signal, the state machine only moves between states #2 and #3 as a classic ideal-diode
mode state machine. This allows all the inductive elements to discharge, when the power system shuts off, with
minimum discharge stress created in the GaN FET.
Note that the OTSD-IDM state machine has no protection against repetitive shoot-through current events. There
are degenerate cases, such as the LMG342xR030 losing its IN signal during converter operation, which can
expose the OTSD-IDM to repetitive shoot-through current events. There is no good solution in this scenario.
If OTSD-IDM did not allow repeated shoot-thru current events, the GaN FET would instead be exposed to
excessive off-state third-quadrant losses.
9.4 Device Functional Modes
The device has one mode of operation that applies when operated within the Recommended Operating
Conditions.
26
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10 Application and Implementation
Note
Information in the following applications sections is not part of the TI component specification,
and TI does not warrant its accuracy or completeness. TI’s customers are responsible for
determining suitability of components for their purposes, as well as validating and testing their design
implementation to confirm system functionality.
10.1 Application Information
The LMG342xR030 is a power IC targeting hard-switching and soft-switching applications operating up to
480V bus voltages. GaN devices offer zero reverse-recovery charge enabling high-frequency, hard-switching in
applications like the totem-pole PFC. Low Qoss of GaN devices also benefits soft-switching converters, such as
the LLC and phase-shifted full-bridge configurations. As half-bridge configurations are the foundation of the two
mentioned applications and many others, this section describes how to use the LMG342xR030 in a half-bridge
configuration.
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10.2 Typical Application
CAUTION
For applications where the drain slew rate is programmed for greater than a typical 100 V/ns (RRDRV < 10 kΩ or VRDRV = 5 V), the following
application design modifications must be implemented to minimize the risk of LDO5V pin damage.
1. Remove C2.
2. Put a 10-Ω resistor between the U1 LDO5V pin and C10. No other components must be between the resistor and the U1 LDO5V pin.
3. Remove C12.
4. Put a 10-Ω resistor between the U2 LDO5V pin and C27. No other components must be between the resistor and the U2 LDO5V pin.
ISO_12V _L
R2 DNP
2.05
PGND i
D1
VHV
i
VHV
i
U1
ISO_12V_H
GB01SLT06-214
5V_H
R1
0
LMG342x Half-Bridge GaN Daughter Card
46
53
C1
10uF
D6
5V_H
AGND
20k 100V/ns
70k 50V/ns
U3
15
9
INGND i
GND2
GND2
8
2
GND1
GND1
R7
Top_FET_PWM
11
49.9
Top_FET_FAULT
C6
68pF
R8
Top_FET_OC
300
R9
12
300
C24
C25
68pF 68pF
13
Top_FET_TEMP
16
5V
AGND
PGND
14
EN1
IND
OUTD
OUTC
INC
OUTB
INB
OUTA
INA
VCC2
C26
1uF
AGND AGND
TP3
EN2
42
41
25V
2.2uF
DNP R3
0
SW
43
L1 SDEM20161T-4R7MS
LDO5V
VNEG
VNEG
BBSW
RDRV_H
SW
20.0k
C7
50V
R6
100pF
Have R6 close to GaN FET
SW
7
VNEG_H
C3
C2
SW
0.22µF
SW
R5
SW
5V_H
10
5V
16V
VDD
6
52
C5
22pF
300
IN_H
47
5
TEMP_H
51
4
FAULT_H
48
OC_H
50
3
5V_H
RDRV
IN
TEMP
FAULT
OC
1
VCC1
C10
0.1uF
ISO7741FDBQR
SW
AGND
TP4
PGND
HV
TP5
TH1
SW
NC1
VSWNET i
Power Connector
HVBUS
TH2
TH3
NC3
SW
SOURCE
SOURCE
SOURCE
SOURCE
SOURCE
SOURCE
SOURCE
SOURCE
SOURCE
SOURCE
SOURCE
SOURCE
SOURCE
SOURCE
SOURCE
SOURCE
SOURCE
SOURCE
SOURCE
SOURCE
SOURCE
SOURCE
SOURCE
SOURCE
U1NC1
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
U1NC17
i VSWNET
SW
HVBUS
U1NC16
i VHV
TH4
NC4
TP6
NC2
PGND
DRAIN
DRAIN
DRAIN
DRAIN
DRAIN
DRAIN
DRAIN
DRAIN
DRAIN
DRAIN
DRAIN
DRAIN
DRAIN
DRAIN
DRAIN
DRAIN
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
HS push-pin
LMG342x
GND
GND
GND
GND
PAD
44 SW
45
49
54 U1NC54
55
i VSWNET
VSWNET i
PGND
U2
12V
R10
0
INGND i
TSW-106-08-G-D-RA
J1
1
2 Top_FET_TEMP
3
4 Top_FET_OC
5
6 Top_FET_FAULT
7
8 Top_FET_PWM
9
11
AGND
3
C14
68pF
5V
AGND
AGND
ISO7762FQDBQRQ1
10
11
Bot_FET_FAULT
12
Bot_FET_OC
13
Bot_FET_TEMP
14
OUTA
15
5V
16
AGND
TP11
GND2
GND1
INF
OUTF
PGND
R18
7
INE
OUTE
OUTD
IND
OUTC
INC
OUTB
INB
OUTA
INA
VCC2
VCC1
20.0k
46
5V_L
53
VDD
LDO5V
OC_L
3
TEMP_L
2
INA
5V_L
42
41
25V
2.2uF
PGND
PGND
43
L2
SDEM20161T-4R7MS
PGND
Have R15 close to GaN FET
FAULT_L
4
C13
5V_L
C8
50V
100pF
PGND
6
5
C12
0.22µF PGND
R12
0 DNP
R14
20.0k
Q1
MGSF1N02LT1G
1
8
10.0
Bot_FET_PWM
TP10
U4
9
Top_FET_FAULT
49.9
R16
20k 100V/ns
70k 50V/ns
R17 DNP
AGND
10
12
12V
C11
10uF
ISO_12V_L
DNP
VNEG_L
2
Bot_FET_PWM
Bot_FET_FAULT
Bot_FET_OC
Bot_FET_TEMP
R15
52
C23
22pF
IN_L
47
VNEG
VNEG
BBSW
RDRV
IN
TEMP_L 51
TEMP
FAULT_L 48
FAULT
OC_L
OC
50
TP2
PGND
C27
0.1uF
AGND
PGND
AGND
TP8
Top_FET_FAULT
i PGND
1 U2NC1
i VSWNET
2
3
4
5
6
7
8
TP1
9
10
5016
11
12
13
14
15
16 U2NC16
TP9
Bot_FET_FAULT
LMG342x
SOURCE
SOURCE
SOURCE
SOURCE
SOURCE
SOURCE
SOURCE
SOURCE
SOURCE
SOURCE
SOURCE
SOURCE
SOURCE
SOURCE
SOURCE
SOURCE
SOURCE
SOURCE
SOURCE
SOURCE
SOURCE
SOURCE
SOURCE
SOURCE
GND
GND
GND
GND
PAD
C15
0.022µF
C16
0.022µF
C17
0.022µF
C18
0.022µF
C19
0.1uF
C20
0.1uF
C21
0.1uF
C38
0.1uF
i VSWNET
300
1
C9
1uF
DRAIN
DRAIN
DRAIN
DRAIN
DRAIN
DRAIN
DRAIN
DRAIN
DRAIN
DRAIN
DRAIN
DRAIN
DRAIN
DRAIN
DRAIN
DRAIN
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
U2NC17
i PGND
PGND
44 PGND
45
49
54 U2NC54
i PGND
55
Figure 10-1. Typical Half-Bridge Application
28
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10.2.1 Design Requirements
This design example is for a hard-switched boost converter which is representative of PFC applications. Table
10-1 shows the system parameters for this design.
Table 10-1. Design Parameters
DESIGN PARAMETER
EXAMPLE VALUE
Input voltage
200 VDC
Output voltage
400 VDC
Input (inductor) current
20 A
Switching frequency
100 kHz
10.2.2 Detailed Design Procedure
In high-voltage power converters, circuit design and PCB layout are essential for high-performance power
converters. As designing a power converter is out of the scope of this document, this data sheet describes how
to build well-behaved half-bridge configurations with the LMG342xR030.
10.2.2.1 Slew Rate Selection
The slew rate of LMG342xR030 can be adjusted between approximately 20 V/ns and 150 V/ns by connecting a
resistor, RDRV, from the RDRV pin to GND. The slew rate affects GaN device performance in terms of:
•
•
•
•
Switching loss
Voltage overshoot
Noise coupling
EMI emission
Generally, high slew rates provide low switching loss, but high slew rates can also create higher voltage
overshoot, noise coupling, and EMI emissions. Following the design recommendations in this data sheet helps
mitigate the challenges caused by a high slew rate. The LMG342xR030 offers circuit designers the flexibility to
select the proper slew rate for the best performance of their applications.
10.2.2.1.1 Start-Up and Slew Rate With Bootstrap High-Side Supply
Using a bootstrap supply introduces additional constraints on the start-up of the high-side LMG342xR030. Prior
to powering up, the GaN device operates in cascode mode with reduced performance. In some circuits, a proper
slew rate can be required for the start-up of a bootstrap-supplied half-bridge configuration.
10.2.2.2 Signal Level-Shifting
In half-bridges, high-voltage level shifters or digital isolators must be used to provide isolation for signal paths
between the high-side device and control circuit. Using an isolator is optional for the low-side device. However,
using and isolator equalizes the propagation delays between the high-side and low-side signal paths, and
provides the ability to use different grounds for the GaN device and the controller. If an isolator is not used on
the low-side device, the control ground and the power ground must be connected at the device and nowhere
else on the board. For more information, see Layout Guidelines. With fast-switching devices, common ground
inductance can easily cause noise issues without the use of an isolator.
Choosing a digital isolator for level-shifting is important for improvement of noise immunity. As GaN device
can easily create high dv/dt, > 50 V/ns, in hard-switching applications, TI highly recommends to use isolators
with high common-mode transient immunity (CMTI). Isolators with low CMTI can easily generate false signals,
which could cause shoot-through. Additionally, TI strongly encourages to select isolators which are not edgetriggered. In an edge-triggered isolator, a high dv/dt event can cause the isolator to flip states and cause circuit
malfunction.
Generally, ON/OFF keyed isolators are preferred, such as the TI ISO77xxF series, as a high CMTI event would
only cause a very short false pulse, a few nanoseconds, which can be filtered out. To filter these false pulses, TI
recommends a low pass filter, like 1 kΩ and 22 pF R-C filter, to be placed at the driver input.
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10.2.2.3 Buck-Boost Converter Design
The buck-boost converter generates the negative voltage to turn off the direct-drive GaN device. While the
buck-boost converter is controlled internally, it requires an external power inductor and output capacitor. The
converter is designed to use a 4.7-µH inductor and a 2.2-µF output capacitor.
As the peak current of the buck-boost is subject to two different peak current limits which are 0.4 A and 1 A
for low and high frequency operation (see Internal Buck-Boost DC-DC Converter), so the inductor must have a
saturation current well above the rated peak current limit. After the higher limit is established by switching at a
higher frequency, the current limit does not go back to the lower level even when GaN device is then switched
at a lower frequency. Therefore, select an inductor according to the higher 1-A limit if higher frequency GaN
operation is anticipated.
The buck-boost converter uses a peak current hysteretic control. As shown in Figure 10-2, the inductor current
increases at the beginning of a switching cycle until the inductor reaches the peak current limit. The inductor
current goes down to zero. The idle time between each current pulse is determined automatically by the output
current, and can be reduced to zero. Therefore, the maximum output current happens when the idle time is zero,
and is decided by the peak current but independent of the inductor value.
A minimum inductance value of 3 µH is preferred for the buck-boost converter so that the di/dt across the
inductor is not too high. This leaves enough margin for the control loop to respond. As a result, the maximum
di/dt of the inductor is limited to 6 A/µs. On the other hand, large inductance also limits the transient response for
stable output voltage, and it is preferred to have inductors less than 10 µH.
VNEG_avg
ûVNEG
VNEG
IDCDC,PK
Smaller
inductor
Buck-boost
inductor current
Larger
inductor
Idle time
1/(buck-boost frequency)
Figure 10-2. Buck-Boost Converter Inductor Current
30
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10.2.3 Application Curves
VDS (50 V/div)
ID (2.5 A/div)
VDS (50 V/div)
ID (1.25 A/div)
VOUT = 400V
IL = 5 A
RDRV = 40 k:
VBUS = 400 V
IL = 5 A
RDRV = 40 k:
Time (5 ns/div)
Time (5 ns/div)
D006
Figure 10-3. Turn-On Waveform in Application
Example
D007
Figure 10-4. Turn-Off Waveform in Application
Example
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10.3 Do's and Don'ts
The successful use of GaN devices in general, and LMG342xR030 in particular, depends on proper use of the
device. When using the LMG342xR030, DO:
•
•
•
•
•
•
Read and fully understand the data sheet, including the application notes and layout recommendations.
Use a four-layer board and place the return power path on an inner layer to minimize power-loop inductance.
Use small, surface-mount bypass and bus capacitors to minimize parasitic inductance.
Use the proper size decoupling capacitors and locate them close to the IC as described in Layout Guidelines.
Use a signal isolator to supply the input signal for the low-side device. If not, ensure the signal source is
connected to the signal GND plane which is tied to the power source only at the LMG342xR030 IC.
Use the FAULT pin to determine power-up state and to detect overcurrent and overtemperature events and
safely shut off the converter.
To avoid issues in your system when using the LMG342xR030, DON'T:
•
•
•
•
•
32
Use a single-layer or two-layer PCB for the LMG342xR030 as the power-loop and bypass capacitor
inductances is excessive and prevent proper operation of the IC.
Reduce the bypass capacitor values below the recommended values.
Allow the device to experience drain transients above 600 V as they can damage the device.
Allow significant third-quadrant conduction when the device is OFF or unpowered, which can cause
overheating. Self-protection features cannot protect the device in this mode of operation.
Ignore the FAULT pin output.
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11 Power Supply Recommendations
The LMG342xR030 only requires an unregulated 12-V supply. The low-side supply can be obtained from the
local controller supply. The supply of the high-side device must come from an isolated supply or a bootstrap
supply.
11.1 Using an Isolated Power Supply
Using an isolated power supply to power the high-side device has the advantage that it works regardless of
continued power-stage switching or duty cycle. Using an isolated power supply can also power the high-side
device before power-stage switching begins, eliminating the power-loss concern of switching with an unpowered
LMG342xR030 (see Start-Up and Slew Rate With Bootstrap High-Side Supply for details). Finally, a properlyselected isolated supply introduces less parasitics and reduces noise coupling.
The isolated supply can be obtained with a push-pull converter, a flyback converter, a FlyBuck™ converter, or
an isolated power module. When using an unregulated supply, the input of LMG342xR030 must not exceed
the maximum supply voltage. A 16-V TVS diode can be used to clamp the VDD voltage of LMG342xR030 for
additional protection. Minimizing the inter-winding capacitance of the isolated power supply or transformer is
necessary to reduce switching loss in hard-switched applications. Furthermore, capacitance across the isolated
bias supply inject high currents into the signal-ground of the LMG342xR030 and can cause problematic groundbounce transients. A common-mode choke can alleviate most of these issues.
11.2 Using a Bootstrap Diode
In half-bridge configuration, a floating supply is necessary for the high-side device. To obtain the best
performance of LMG342xR030, Ti highly recommends Using an Isolated Power Supply. A bootstrap supply
can be used with the recommendations of this section.
In applications like a boost converter, the low side LMG342xR030 always start switching while high side
LMG342xR030 is unpowered. If the low side is adjusted to achieve very high slew rate before the high side
bias is fully settled, there can be unintentional turn-on at the high side due to parasitic coupling at high slew rate.
The start-up slew rate must be slowed down to 30 V/ns by changing the resistance of RDRV pin of the low side.
This slow down can be achieved by controlling the low side RDRV resistance with the high side FAULT as given
in Figure 10-1.
11.2.1 Diode Selection
The LMG342xR030 offers no reverse-recovery charge and very limited output charge. Hard-switching circuits
using the LMG342xR030 also exhibit high voltage slew rates. A compatible bootstrap diode must not introduce
high output charge and reverse-recovery charge.
A silicon carbide diode, like the GB01SLT06-214, can be used to avoid reverse-recovery effects. The SiC diode
has an output charge of 3 nC. Althought there is additional loss from its output charge, it does not dominate the
losses of the switching stage.
11.2.2 Managing the Bootstrap Voltage
In a synchronous buck or other converter where the low-side switch occasionally operates in third-quadrant,
the bootstrap supply charges through a path that includes the third-quadrant voltage drop of the low-side
LMG342xR030 during the dead time as shown in Figure 11-1. This third-quadrant drop can be large, which can
over-charge the bootstrap supply in certain conditions. The VDD supply of LMG342xR030 must be kept below 18
V.
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VDD
DRAIN
VF
SOURCE
+
±
DRAIN
VDD
VF
SOURCE
Figure 11-1. Charging Path for Bootstrap Diode
As shown in Figure 11-2, the recommended bootstrap supply includes a bootstrap diode, a series resistor,
and a 16-V TVS or zener diode in parallel with the VDD bypass capacitor to prevent damaging the high-side
LMG342xR030. The series resistor limits the charging current at start-up and when the low-side device
is operating in third-quadrant mode. This resistor must be selected to allow sufficient current to power
the LMG342xR030 at the desired operating frequency. At 100-kHz operation, TI recommends a value of
approximately 2 Ω . At higher frequencies, this resistor value must be reduced or the resistor omitted entirely to
ensure sufficient supply current.
+12 V
VDD
DRAIN
VF
SOURCE
Figure 11-2. Suggested Bootstrap Regulation Circuit
34
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12 Layout
12.1 Layout Guidelines
The layout of the LMG342xR030 is critical to its performance and functionality. Because the half-bridge
configuration is typically used with these GaN devices, layout recommendations are considered with this
configuration. A four-layer or higher layer count board is required to reduce the parasitic inductances of the
layout to achieve suitable performance.
12.1.1 Solder-Joint Reliability
Large QFN packages can experience high solder-joint stress. TI recommends several best practices to ensure
solder-joint reliability. First, the instructions for the NC1 and NC2 anchor pins found in Table 6-1 must be
followed. Second, all the LMG342xR030 board solder pads must be non-solder-mask defined (NSMD) as shown
in the land pattern example in Mechanical, Packaging, and Orderable Information. Finally, any board trace
connected to an NSMD pad must be less than 2/3 the width of the pad on the pad side where it is connected.
The trace must maintain this 2/3 width limit for as long as it is not covered by solder mask. After the trace is
under solder mask, there are no limits on the trace dimensions. All these recommendations are followed in the
Layout Example.
12.1.2 Power-Loop Inductance
The power loop, comprising the two devices in the half bridge and the high-voltage bus capacitance, undergoes
high di/dt during switching events. By minimizing the inductance of this loop, ringing and electro-magnetic
interference (EMI) can be reduced, as well as reducing voltage stress on the devices.
Place the power devices as close as possible to minimize the power-loop inductance. The decoupling capacitors
are positioned in line with the two devices. They can be placed close to either device. In Layout Examples,
the decoupling capacitors are placed on the same layer as the devices. The return path (PGND in this case)
is located on second layer in close proximity to the top layer. By using inner layer and not bottom layer, the
vertical dimension of the loop is reduced, thus minimizing inductance. A large number of vias near both the
device terminal and bus capacitance carries the high-frequency switching current to inner layer while minimizing
impedance.
12.1.3 Signal-Ground Connection
The LMG342xR030's SOURCE pin is internally connected to GND pins of the power IC, the signal-ground
reference. Local signal-ground planes must be connected to GND pins with low impedance star connection. In
addition, the return path for the passives associated to the driver (for example, bypass capacitance) must be
connected to the GND pins. In Layout Example, local signal-ground planes are located on second layer to act
as the return path for the local circuitry. The local signal-ground planes are not connected to the high-current
SOURCE pins except the star connection at GND pins.
12.1.4 Bypass Capacitors
The gate drive loop impedance must be minimized to obtain good performance. Although the gate driver is
integrated on package, the bypass capacitance for the driver is placed externally. As the GaN device is turned
off to a negative voltage, the impedance of the path to the external VNEG capacitor is included in the gate drive
loop. The VNEG capacitor must be placed close to VNEG and GND pins.
The VDD pin bypass capacitors, C1 and C11, must also be placed close to the VDD pin with low impedance
connections.
12.1.5 Switch-Node Capacitance
GaN devices have very low output capacitance and switch quickly with a high dv/dt, yielding very low switching
losses. To preserve this low switching losses, additional capacitance added to the output node must be
minimized. The PCB capacitance at the switch node can be minimized by following these guidelines:
•
•
•
Minimize overlap between the switch-node plane and other power and ground planes.
Make the GND return path under the high-side device thinner while still maintaining a low-inductance path.
Choose high-side isolator ICs and bootstrap diodes with low capacitance.
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•
•
•
•
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Place the power inductor as close to the GaN device as possible.
Power inductors must be constructed with a single-layer winding to minimize intra-winding capacitance.
If a single-layer inductor is not possible, consider placing a small inductor between the primary inductor and
the GaN device to effectively shield the GaN device from the additional capacitance.
If a back-side heat-sink is used, use the least amount of area of the switch-node copper coverage on the
bottom copper layer to improve the thermal dissipation.
12.1.6 Signal Integrity
The control signals to the LMG342xR030 must be protected from the high dv/dt caused by fast switching.
Coupling between the control signals and the drain can cause circuit instability and potential destruction. Route
the control signals (IN, FAULT and OC) over a ground plane placed on an adjacent layer. In Layout Example, for
example, all the signals are routed on layers close to the local signal ground plane.
Capacitive coupling between the traces for the high-side device and the static planes, such as PGND and
HVBUS, could cause common mode current and ground bounce. The coupling can be mitigated by reducing
overlap between the high-side traces and the static planes. For the high-side level shifter, ensure no copper from
either the input or output side extends beneath the isolator or the CMTI of the device can be compromised.
12.1.7 High-Voltage Spacing
Circuits using the LMG342xR030 involve high voltage, potentially up to 600 V. When laying out circuits using
the LMG342xR030, understand the creepage and clearance requirements for the application and how they
apply to the GaN device. Functional (or working) isolation is required between the source and drain of each
transistor, and between the high-voltage power supply and ground. Functional isolation or perhaps stronger
isolation (such as reinforced isolation) can be required between the input circuitry to the LMG342xR030 and the
power controller. Choose signal isolators and PCB spacing (creepage and clearance) distances which meet your
isolation requirements.
If a heat sink is used to manage thermal dissipation of the LMG342xR030, ensure necessary electrical isolation
and mechanical spacing is maintained between the heat sink and the PCB.
12.1.8 Thermal Recommendations
The LMG342xR030 is a lateral device grown on a Si substrate. The thermal pad is connected to the source
of device. The LMG342xR030 can be used in applications with significant power dissipation, for example,
hard-switched power converters. In these converters, cooling using just the PCB can not be sufficient to keep the
part at a reasonable temperature. To improve the thermal dissipation of the part, TI recommends a heat sink is
connected to the back of the PCB to extract additional heat. Using power planes and numerous thermal vias, the
heat dissipated in the LMG342xR030 can be spread out in the PCB and effectively passed to the other side of
the PCB. A heat sink can be applied to bare areas on the back of the PCB using an thermal interface material
(TIM). The solder mask from the back of the board underneath the heat sink can be removed for more effective
heat removal.
Refer to the High Voltage Half Bridge Design Guide for LMG3410 Smart GaN FET application note for more
recommendations and performance data on thermal layouts.
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12.2 Layout Examples
Correct layout of the LMG342xR030 and its surrounding components is essential for correct operation. The
layouts shown here reflect the GaN device schematic in Figure 10-1 . These layouts are shown to produce
good results and is intended as a guideline. However, it can be possible to obtain acceptable performance with
alternate layout schemes. Additionally, please refer to the land pattern example in Mechanical, Packaging, and
Orderable Information for the latest recommended PCB footprint of the device.
The the top-layer layout and mid-layer layout are shown. The layouts are zoomed in to the LMG342xR030 U1
and U2 component placements. The mid-layer layout includes the outlines of the top level components to assist
the reader in lining up the top-layer and mid-layer layouts.
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Figure 12-1. Half-Bridge Top-Layer Layout
Figure 12-2. Half-Bridge Mid-Layer Layout
38
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13 Device and Documentation Support
13.1 Documentation Support
13.1.1 Related Documentation
•
•
Texas Instruments, High Voltage Half Bridge Design Guide for LMG3410 Smart GaN FET application note.
Texas Instruments, A New Approach to Validate GaN FET Reliability to Power-line Surges Under Useconditions.
13.2 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. Click on
Subscribe to updates to register and receive a weekly digest of any product information that has changed. For
change details, review the revision history included in any revised document.
13.3 Support Resources
TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straight
from the experts. Search existing answers or ask your own question to get the quick design help you need.
Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do
not necessarily reflect TI's views; see TI's Terms of Use.
13.4 Trademarks
FlyBuck™ is a trademark of Texas Instruments.
TI E2E™ is a trademark of Texas Instruments.
All trademarks are the property of their respective owners.
13.5 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled
with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may
be more susceptible to damage because very small parametric changes could cause the device not to meet its published
specifications.
13.6 Export Control Notice
Recipient agrees to not knowingly export or re-export, directly or indirectly, any product or technical data (as
defined by the U.S., EU, and other Export Administration Regulations) including software, or any controlled
product restricted by other applicable national regulations, received from disclosing party under nondisclosure
obligations (if any), or any direct product of such technology, to any destination to which such export or re-export
is restricted or prohibited by U.S. or other applicable laws, without obtaining prior authorization from U.S.
Department of Commerce and other competent Government authorities to the extent required by those laws.
13.7 Glossary
TI Glossary
This glossary lists and explains terms, acronyms, and definitions.
14 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
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SNOSDA7D – SEPTEMBER 2020 – REVISED MARCH 2022
PACKAGE OUTLINE
RQZ0054A-C01
VQFN - 1 mm max height
SCALE 1.100
PLASTIC QUAD FLATPACK - NO LEAD
12.1
11.9
B
A
PIN 1 ID
INDEX AREA
12.1
11.9
1.0
0.8
C
SEATING PLANE
0.08 C
0.05
0.00
7.8 0.1
(2.75)
PKG
54X
(2.65)
4X 0.975
0.65
0.55
16
28
4X
10.2 0.1
2X 8.45
26X 0.65
PIN 1 ID
(45 X 0.3)
46X
43
1
4X (0.2)
1.1
1.0
0.1
0.05
C A B
C
55
PKG SYMM
4X (0.25)
(0.1) TYP
27
17
54
44
2X 1.285
4X
16X 0.65
2X 5.2
0.45
0.35
0.1
0.05
0.65
0.55
0.1
0.05
C A B
C
C A B
C
4X 0.75
4228230/A 11/2021
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. The package thermal pad must be soldered to the printed circuit board for thermal and mechanical performance.
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EXAMPLE BOARD LAYOUT
RQZ0054A-C01
VQFN - 1 mm max height
PLASTIC QUAD FLATPACK - NO LEAD
(7.8)
(4.906)
(2.65)
(4.449) TYP
54X (0.8)
(0.914) TYP
54
4X (1.05)
44
(0.508) TYP
43
1
( 0.2) TYP
VIA
(4.572)
(4.826)
46X (0.4)
(10.2)
55
PKG SYMM
(11.6)
(R0.05) TYP
42X (0.65)
4X (0.975)
28
16
27
17
4X (0.75)
(1.25)
2X (2.035)
PAD
4X (0.6)
PKG
(11.6)
LAND PATTERN EXAMPLE
0.07 MAX
ALL AROUND
EXPOSED METAL SHOWN
SCALE:8X
METAL EDGE
EXPOSED
METAL
SOLDER MASK
OPENING
NON SOLDER MASK
DEFINED
SOLDER MASK DETAIL
4228230/A 11/2021
NOTES: (continued)
4. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments
literature number SLUA271 (www.ti.com/lit/slua271).
5. All pads must be NSMD for mechanical performance, refer to the device datasheet for trace connection recommendations to the pads.
6. Filling the thermal pad with thermal vias is recommended for thermal performance, refer to the device datasheet. Vias must be filled and
planarized.
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SNOSDA7D – SEPTEMBER 2020 – REVISED MARCH 2022
EXAMPLE STENCIL DESIGN
RQZ0054A-C01
VQFN - 1 mm max height
PLASTIC QUAD FLATPACK - NO LEAD
(4.225)
50X (0.8)
4X (0.76)
(1.19) TYP
54
44
43
1
4X (1)
48X ( 0.99)
(1.19) TYP
(4.165)
46X (0.4)
55
PKG SYMM
(11.6)
(R0.05) TYP
42X (0.65)
4X (0.975)
28
16
17
4X (0.75)
PKG
27
4X (0.6)
2X (2.035)
(11.6)
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
PRINTED SOLDER COVERAGE BY AREA UNDER PACKAGE
PADS 1, 16, 28 & 43: 90%
PAD 55: 60%
SCALE:8X
4228230/A 11/2021
NOTES: (continued)
7. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
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PACKAGE OPTION ADDENDUM
www.ti.com
23-Jun-2023
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
Samples
(4/5)
(6)
LMG3422R030RQZR
ACTIVE
VQFN
RQZ
54
2000
RoHS-Exempt
& Green
NIPDAU
Level-3-260C-168 HR
-40 to 150
LMG3422
R030
Samples
LMG3422R030RQZT
ACTIVE
VQFN
RQZ
54
250
RoHS-Exempt
& Green
NIPDAU
Level-3-260C-168 HR
-40 to 150
LMG3422
R030
Samples
LMG3425R030RQZR
ACTIVE
VQFN
RQZ
54
2000
RoHS-Exempt
& Green
NIPDAU
Level-3-260C-168 HR
-40 to 150
LMG3425
R030
Samples
LMG3425R030RQZT
ACTIVE
VQFN
RQZ
54
250
RoHS-Exempt
& Green
NIPDAU
Level-3-260C-168 HR
-40 to 150
LMG3425
R030
Samples
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of
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