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LMG5200
SNOSCY4E – MARCH 2015 – REVISED OCTOBER 2018
LMG5200 80-V, 10-A GaN Half-Bridge Power Stage
1 Features
3 Description
•
•
•
The LMG5200 device, an 80-V, 10-A driver plus GaN
half-bridge power stage, provides an integrated
power stage solution using enhancement-mode
Gallium Nitride (GaN) FETs. The device consists of
two 80-V GaN FETs driven by one high-frequency
GaN FET driver in a half-bridge configuration.
1
•
•
•
•
•
•
•
Integrated 15-mΩ GaN FETs and Driver
80-V Continuous, 100-V Pulsed Voltage Rating
Package Optimized for Easy PCB Layout,
Eliminating Need for Underfill, Creepage, and
Clearance Requirements
Very Low Common Source Inductance to Ensure
High Slew Rate Switching Without Causing
Excessive Ringing in Hard-Switched Topologies
Ideal for Isolated and Non-Isolated Applications
Gate Driver Capable of Up to 10 MHz Switching
Internal Bootstrap Supply Voltage Clamping to
Prevent GaN FET Overdrive
Supply Rail Undervoltage Lockout Protection
Excellent Propagation Delay (29.5 ns Typical) and
Matching (2 ns Typical)
Low Power Consumption
GaN FETs provide significant advantages for power
conversion as they have near zero reverse recovery
and very small input capacitance CISS. All the devices
are mounted on a completely bond-wire free package
platform with minimized package parasitic elements.
The LMG5200 device is available in a 6 mm × 8 mm
× 2 mm lead-free package and can be easily
mounted on PCBs.
The TTL logic compatible inputs can withstand input
voltages up to 12 V regardless of the VCC voltage.
The proprietary bootstrap voltage clamping technique
ensures the gate voltages of the enhancement mode
GaN FETs are within a safe operating range.
2 Applications
•
•
•
•
The device extends advantages of discrete GaN
FETs by offering a more user-friendly interface. It is
an ideal solution for applications requiring highfrequency, high-efficiency operation in a small form
factor. When used with the TPS53632G controller,
the LMG5200 enables direct conversion from 48-V to
point-of-load voltages (0.5-1.5 V).
Wide VIN Multi-MHz Synchronous Buck
Converters
Class D Amplifiers for Audio
48-V Point-of-Load (POL) Converters for Telecom,
Industrial, and Enterprise Computing
High Power Density Single- and Three-Phase
Motor Drive
Device Information(1)
PART NUMBER
LMG5200
PACKAGE
QFM (9)
BODY SIZE (NOM)
6.00 mm × 8.00 mm
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
Simplified Block Diagram
HS
HB
3
2
LMG5200
HI
4
HI
HS
HB
5
LI
VCC
AGND
6
7
VCC
AGND
VIN
8
SW
9
PGND
HO
GaN Driver
LI
1
LO
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
LMG5200
SNOSCY4E – MARCH 2015 – REVISED OCTOBER 2018
www.ti.com
Table of Contents
1
2
3
4
5
6
Features ..................................................................
Applications ...........................................................
Description .............................................................
Revision History.....................................................
Pin Configuration and Functions .........................
Specifications.........................................................
1
1
1
2
3
4
6.1
6.2
6.3
6.4
6.5
6.6
4
4
4
5
5
7
Absolute Maximum Ratings ......................................
ESD Ratings..............................................................
Recommended Operating Conditions.......................
Thermal Information ................................................
Electrical Characteristics...........................................
Typical Characteristics ..............................................
7
Parameter Measurement Information .................. 8
8
Detailed Description .............................................. 9
7.1 Propagation Delay and Mismatch Measurement ...... 8
8.1 Overview ................................................................... 9
8.2 Functional Block Diagram ....................................... 10
8.3 Feature Description................................................. 10
8.4 Device Functional Modes........................................ 12
9
Application and Implementation ........................ 12
9.1 Application Information............................................ 12
9.2 Typical Application ................................................. 12
10 Power Supply Recommendations ..................... 15
11 Layout................................................................... 16
11.1 Layout Guidelines ................................................. 16
11.2 Layout Examples................................................... 16
12 Device and Documentation Support ................. 20
12.1
12.2
12.3
12.4
12.5
12.6
12.7
Device Support ....................................................
Documentation Support .......................................
Receiving Notification of Documentation Updates
Community Resources..........................................
Trademarks ...........................................................
Electrostatic Discharge Caution ............................
Glossary ................................................................
20
20
20
20
20
20
20
13 Mechanical, Packaging, and Orderable
Information ........................................................... 20
13.1 Package Information ............................................. 21
4 Revision History
Changes from Revision D (March 2017) to Revision E
•
deleted footnote..................................................................................................................................................................... 5
Changes from Revision C (December 2016) to Revision D
•
Page
Page
general editorial global authoring and SDS updates .............................................................................................................. 1
Changes from Revision B (January 2016) to Revision C
Page
•
Changed from GaN Technology Preview to Production Data ................................................................................................ 1
•
Added Device Functional Modes Section ............................................................................................................................ 12
•
Added Typical Application Section ...................................................................................................................................... 12
•
Updated Power Supply Recommendations Section ............................................................................................................ 15
•
Added Links in Development Support Section ..................................................................................................................... 20
Changes from Revision A (March 2015) to Revision B
•
Page
Changed part number typographical error in Figure 14 ....................................................................................................... 16
Changes from Original (March 2015) to Revision A
Page
•
Corrected typographical error in Simplified Block Diagram.................................................................................................... 1
•
Corrected typographical error in Figure 5............................................................................................................................... 8
•
Corrected typographical error in Figure 10........................................................................................................................... 10
•
Corrected typographical error in Figure 11........................................................................................................................... 12
2
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5 Pin Configuration and Functions
HS
HB
MOF Package
9-Pin QFM
Top View
3
2
1 VIN
HI 4
LMG5200
9 PGND
6
7
VCC
AGND
LI 5
8 SW
Pin Functions
PIN
I/O (1)
DESCRIPTION
NAME
NO.
AGND
7
G
Analog ground. Ground of driver device.
HB
2
P
High-side gate driver bootstrap rail.
HI
4
I
High-side gate driver control input
HS
3
P
High-side GaN FET source connection
LI
5
I
Low-side driver control input
PGND
9
G
Power ground. Low-side GaN FET source. Electrically shorted to AGND pin.
SW
8
P
Switching node. Electrically shorted to HS pin. Ensure low capacitance at this node on PCB.
VCC
6
P
5-V positive gate drive supply
VIN
1
P
Input voltage pin. Electrically connected to high-side GaN FET drain.
(1)
I = Input, O = Output, G = Ground, P = Power
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6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted) (1)
PARAMETER
VIN to PGND
VIN to PGND (pulsed, 100-ms max duration)
MIN
MAX
0
80
V
(2)
UNIT
100
V
HB to AGND
-0.3
86
V
HS to AGND
-5
80
V
HI to AGND
-0.3
12
V
LI to AGND
-0.3
12
V
VCC to AGND
-0.3
6
V
HB to HS
-0.3
6
V
0
80
V
-5
80
V
10
A
HB to VCC
SW to PGND
IOUT from SW pin
Junction Temperature, TJ
-40
125
°C
Storage Temperature, Tstg
-40
150
°C
(1)
(2)
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress
ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under
Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
Device can withstand 1000 pulses up to 100V of 100ms duration and less than 1% duty cycle over its lifetime.
6.2 ESD Ratings
Electrostatic
Discharge
V(ESD)
(1)
(2)
VALUE
UNIT
Human-body model (HBM), per
ANSI/ESDA/JEDEC JS-001 (1)
±1000
V
Charged-device model (CDM), per
JEDEC specification JESD22-C101 (2)
±500
V
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
6.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
VCC
MIN
NOM
MAX
UNIT
4.75
5
5.25
V
LI or HI Input
0
12
V
VIN
0
80
V
-5
80
V
VHS+ 4
VHS+ 5.25
HS, SW
HB
HS, SW Slew rate (1)
Junction Temperature, TJ
(1)
4
-40
V
50
V/ns
125
°C
This parameter is guaranteed by design. Not tested in production.
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6.4
SNOSCY4E – MARCH 2015 – REVISED OCTOBER 2018
Thermal Information
LMG5200
THERMAL METRIC
(1)
QFN
UNIT
9 PINS
R θJA
Junction-to-ambient thermal resistance
35
R θJC(top)
Junction-to-case (top) thermal resistance
18
R θJB
Junction-to-board thermal resistance
16
°C/W
ψ JT
Junction-to-top characterization parameter
1.8
°C/W
ψ JB
Junction-to-board characterization parameter
16
°C/W
(1)
°C/W
For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953 .
6.5 Electrical Characteristics
over operating free-air temperature range (unless otherwise noted) (1)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
0.08
0.125
mA
3.0
5.0
mA
0.09
0.150
mA
1.5
2.5
mA
SUPPLY CURRENTS
ICC
VCC Quiescent Current
LI = HI = 0V, VCC = 5V, HB-HS =
4.6V
ICCO
Total VCC Operating Current
f = 500 kHz
IHB
HB Quiescent Current
LI = HI = 0V, VCC = 5V, HB-HS =
4.6V
IHBO
HB Operating Current
f = 500 kHz, 50% Duty cycle, VDD =
5V
VIH
High-Level Input Voltage Threshold
Rising Edge
1.87
2.06
2.22
V
VIL
Low-Level Input Voltage Threshold
Falling Edge
1.48
1.66
1.76
V
VHYS
Hysteresis between rising and falling
threshold
RI
Input pull down resistance
INPUT PINS
400
100
mV
200
300
3.8
4.5
kΩ
UNDER VOLTAGE PROTECTION
VCCR
VCC Rising edge threshold
VCC(hyst)
VCC UVLO threshold hysteresis
VHBR
HB Rising edge threshold
VHB(hyst)
HB UVLO threshold hysteresis
Rising
3.2
200
Rising
2.5
3.2
V
mV
3.9
200
V
mV
BOOTSTRAP DIODE
VDL
Low-Current forward voltage
IVDD-HB = 100µA
0.45
0.65
VDH
High current forward voltage
IVDD-HB = 100mA
0.9
1.0
V
RD
Dynamic Resistance
IVDD-HB = 100mA
1.85
2.8
Ω
HB-HS Clamp
Regulation Voltage
5
5.2
V
tBS
Bootstrap diode reverse recovery
time
IF = 100 mA, IR = 100 mA
QRR
Bootstrap diode reverse recovery
charge
VVIN = 50 V
4.65
V
40
ns
2
nC
POWER STAGE
RDS(ON)HS
High-side GaN FET on-resistance
LI=0V, HI=VCC=5V, HB-HS=5V,
VIN-SW=10A, TJ = 25℃
15
20
mΩ
RDS(ON)LS
Low-side GaN FET on-resistance
LI=VCC=5V, HI=0V, HB-HS=5V,
SW-PGND=10A, TJ = 25℃
15
20
mΩ
VSD
GaN 3rd quadrant conduction drop
ISD = 500 mA, VIN floating, VVCC = 5
V, HI = LI = 0V
2
IL-VIN-SW
Leakage from VIN to SW when the
high-side GaN FET and low-side
GaN FET are off
VIN = 80V, HI = LI = 0V, VVCC = 5V,
TJ=25℃
25
(1)
V
150
µA
Parameters that show only a typical value are guaranteed by design and may not be tested in production
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Electrical Characteristics (continued)
over operating free-air temperature range (unless otherwise noted)(1)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
25
150
µA
IL-SW-GND
Leakage from SW to GND when the
high-side GaN FET and low-side
GaN FET are off
SW = 80V, HI = LI = 0V, VVCC =
5V, TJ=25℃
COSS
Output Capacitance of high-side
GaN FET and low-side GaN FET
VDS=40V, VGS= 0V (HI = LI = 0V)
266
pF
QG
Total Gate Charge
VDS=40V, ID= 10A, VGS= 5V
3.8
nC
QOSS
Output Charge
VDS=40V, ID= 10A
21
nC
QRR
Source to Drain Reverse Recovery
Charge
Not including internal driver
bootstrap diode
0
nC
tHIPLH
Propagation delay: HI Rising (2)
LI=0V, VCC=5V, HB-HS=5V,
VIN=30V
29.5
50
ns
tHIPHL
Propagation delay: HI Falling (2)
LI=0V, VCC=5V, HB-HS=5V,
VIN=30V
29.5
50
ns
tLPLH
Propagation delay: LI Rising (2)
HI=0V, VCC=5V, HB-HS=5V,
VIN=30V
29.5
50
ns
tLPHL
Propagation delay: LI Falling (2)
HI=0V, VCC=5V, HB-HS=5V,
VIN=30V
29.5
50
ns
tMON
Delay Matching: LI high & HI low (2)
2
8.0
ns
(2)
2
8.0
ns
tMOFF
Delay Matching: LI low & HI high
tPW
Minimum Input Pulse Width that
Changes the Output
(2)
6
10
ns
See Propagation Delay and Mismatch Measurement section
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6.6 Typical Characteristics
All the curves are based on measurements made on a PCB design with dimensions of 3.2 inches (W) × 2.7 inches (L) ×
0.062 inch (T) and 4 layers of 2 oz copper.
The safe operating area (SOA) curves displays the temperature boundaries within an operating system by incorporating the
thermal resistance and system power loss. A buck converter is used for measuring the SOA. Figure 2 outlines the
temperature and airflow conditions required for a given load current. The area under the curve dictates the SOA for different
airflow conditions.
90
100
Ambient Temperature (°C)
VDD Current (mA)
80
10
1
70
60
50
40
400 LFM
200 LFM
100 LFM
Natural convection
30
No Load
20
0.1
1
10
100
Frequency (kHz)
1k
0
10k
1
2
D001
VIN = 48 V
VDD = 5 V
3
4
Output Current (A)
VOUT = 5 V
5
6
D001
fSW = 1 MHz
Figure 2. Safe Operating Area
Figure 1. VDD Supply Current vs Switching Frequency
12
25
21
On-Resistance (m:)
Source-to-Drain Current (A)
23
10
8
6
4
19
17
15
13
11
9
2
7
5
-40 -25 -10
0
0
0.5
1
1.5
2
Source-to-Drain Voltage (V)
2.5
3
D001
GaN third quadrant conduction.
Figure 3. Source-to-Drain Current vs Source-to-Drain
Voltage
5
20 35 50 65 80 95 110 125 140
Junction Temperature (°C)
D001
.
Figure 4. GaN FET On-Resistance vs Junction Temperature
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7 Parameter Measurement Information
7.1 Propagation Delay and Mismatch Measurement
Figure 5 shows the typical test setup used to measure the propagation mismatch. As the gate drives are not
accessible, pullup and pulldown resistors in this test circuit are used to indicate when the low-side GaN FET
turns ON and the high-side GaN FET turns OFF and vice versa to measure the tMON and tMOFF parameters.
Resistance values used in this circuit for the pullup and pulldown resistors are in the order of 1 kΩ; the current
sources used are 2 A.
Figure 6 through Figure 9 show propagation delay measurement waveforms. For turnon propagation delay
measurements, the current sources are not used. For turnoff time measurements, the current sources are set to
2 A, and a voltage clamp limit is also set, referred to as VIN(CLAMP). When measuring the high-side component
turnoff delay, the current source across the high-side FET is turned on, the current source across the low-side
FET is off, HI transitions from high-to-low, and output voltage transitions from VIN to VIN(CLAMP). Similarly, for lowside component turnoff propagation delay measurements, the high-side component current source is turned off,
and the low-side component current source is turned on, LI transitions from high to low and the output transitions
from GND potential to VIN(CLAMP). The time between the transition of LI and the output change is the propagation
delay time.
4
HI
5
LI
3
2
HS
HB
Pattern
Generator
LMG5200
VIN
1
SW
8
VOUT
PGND
VCC
AGND
6
7
9
(A)
Delay Measurement
Figure 5. Propagation Delay and Propagation Mismatch Measurement
8
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Propagation Delay and Mismatch Measurement (continued)
50%
Voltage(V)
Voltage(V)
50%
HI
VIN
VIN
2
SW
10%
VIN
2
10%
SW
LI
GND
Time
Figure 6. High-Side Gate Driver Turnon
Time
Figure 7. Low-Side Gate Driver Turnon
HI
LI
50%
Voltage(V)
Voltage(V)
50%
VIN
SW
VIN(clamp)
10%
VIN(clamp)
SW
10%
GND
.
Figure 8. High-Side Gate Driver Turnoff
Time
Figure 9. Low-Side Gate Driver Turnoff
8 Detailed Description
8.1 Overview
Figure 10 shows the LMG5200, half-bridge, GaN power stage with highly integrated high-side and low-side gate
drivers, which includes built-in UVLO protection circuitry and an overvoltage clamp circuitry. The clamp circuitry
limits the bootstrap refresh operation to ensure that the high-side gate driver overdrive does not exceed 5.4 V.
The device integrates two, 15-mΩ GaN FETs in a half-bridge configuration. The device can be used in many
isolated and non-isolated topologies allowing very simple integration. The package is designed to minimize the
loop inductance while keeping the PCB design simple. The drive strengths for turnon and turnoff are optimized to
ensure high voltage slew rates without causing any excessive ringing on the gate or power loop.
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8.2 Functional Block Diagram
Figure 10 shows the functional block diagram of the LMG5200 device with integrated high-side and low-side GaN
FETs.
LMG5200
UVLO and
Clamp
VCC
6
HI
4
HB
1
VIN
3
HS
8
SW
9
PGND
7
AGND
Level
Shifter
UVLO
LI
2
5
Figure 10. Functional Block Diagram
8.3 Feature Description
The LMG5200 device brings ease of designing high power density boards without the need for underfill while
maintaining creepage and clearance requirements. The propagation delays between the high-side gate driver
and low-side gate driver are matched to allow very tight control of dead time. Controlling the dead time is critical
in GaN-based applications to maintain high efficiency. HI and LI can be independently controlled to minimize the
third quadrant conduction of the low-side FET for hard switched buck converters. A very small propagation
mismatch between the HI and LI to the drivers for both the falling and rising thresholds ensures dead times of <
10 ns. Co-packaging the GaN FET half-bridge with the driver ensures minimized common source inductance.
This minimized inductance has a significant performance impact on hard-switched topologies.
The built-in bootstrap circuit with clamp prevents the high-side gate drive from exceeding the GaN FETs
maximum gate-to-source voltage (Vgs) without any additional external circuitry. The built-in driver has an
undervoltage lockout (UVLO) on the VDD and bootstrap (HB-HS) rails. When the voltage is below the UVLO
threshold voltage, the device ignores both the HI and LI signals to prevent the GaN FETs from being partially
turned on. Below UVLO, if there is sufficient voltage (VVCC > 2.5 V), the driver actively pulls the high-side and
low-side gate driver output low. The UVLO threshold hysteresis of 200 mV prevents chattering and unwanted
turnon due to voltage spikes. Use an external VCC bypass capacitor with a value of 0.1 µF or higher. TI
recommends a size of 0402 to minimize trace length to the pin. Place the bypass and bootstrap capacitors as
close as possible to the device to minimize parasitic inductance.
8.3.1 Control Inputs
The LMG5200's inputs pins are independently controlled with TTL input thresholds and can withstand voltages
up to 12V regardless of the VDD voltage. This allows the inputs to be directly connected to the outputs of an
analog PWM controller with up to 12V power supply, eliminating the need for a buffer stage.
In order to allow flexibility to optimize deadtime according to design needs, the LMG5200 does not implement an
overlap protection functionality. If both HI and LI are asserted, both the high-side and low-side GaN FETs are
turned on. Careful consideration must be applied to the control inputs in order to avoid a shoot-through condition.
10
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Feature Description (continued)
8.3.2 Start-up and UVLO
The LMG5200 has an UVLO on both the VCC and HB (bootstrap) supplies. When the VCC voltage is below the
threshold voltage of 3.8 V, both the HI and LI inputs are ignored, to prevent the GaN FETs from being partially
turned on. Also, if there is insufficient VCC voltage, the UVLO actively pulls the high- and low-side GaN FET gates
low. When the HB to HS bootstrap voltage is below the UVLO threshold of 3.2 V, only the high-side GaN FET
gate is pulled low. Both UVLO threshold voltages have 200 mV of hysteresis to avoid chattering.
Table 1. VCC UVLO Feature Logic Operation
CONDITION (VHB-HS > VHBR for all cases below)
HI
LI
SW
VCC - VSS < VCCR during device start-up
VCC - VSS < VCCR during device start-up
H
L
Hi-Z
L
H
VCC - VSS < VCCR during device start-up
Hi-Z
H
H
Hi-Z
VCC - VSS < VCCR during device start-up
L
L
Hi-Z
VCC - VSS < VCCR - VCC(hyst) after device start-up
H
L
Hi-Z
VCC - VSS < VCCR - VCC(hyst) after device start-up
L
H
Hi-Z
VCC - VSS < VCCR - VCC(hyst) after device start-up
H
H
Hi-Z
VCC - VSS < VCCR - VCC(hyst) after device start-up
L
L
Hi-Z
Table 2. VHB-HS UVLO Feature Logic Operation
CONDITION (VCC > VCCR for all cases below)
HI
LI
SW
VHB-HS < VHBR during device start-up
H
L
Hi-Z
VHB-HS < VHBR during device start-up
L
H
PGND
VHB-HS < VHBR during device start-up
H
H
PGND
VHB-HS < VHBR during device start-up
L
L
Hi-Z
VHB-HS < VHBR - VHB(hyst) after device start-up
H
L
Hi-Z
VHB-HS < VHBR - VHB(hyst) after device start-up
L
H
PGND
VHB-HS < VHBR - VHB(hyst) after device start-up
H
H
PGND
VHB-HS < VHBR - VHB(hyst) after device start-up
L
L
Hi-Z
8.3.3 Bootstrap Supply Voltage Clamping
The high-side bias voltage is generated using a bootstrap technique and is internally clamped at 5 V (typical).
This clamp prevents the gate voltage from exceeding the maximum gate-source voltage rating of the
enhancement-mode GaN FETs.
8.3.4 Level Shift
The level-shift circuit is the interface from the high-side input HI to the high-side driver stage, which is referenced
to the switch node (HS). The level shift allows control of the high-side GaN FET gate driver output, which is
referenced to the HS pin and provides excellent delay matching with the low-side driver.
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8.4 Device Functional Modes
The LMG5200 operates in normal mode and UVLO mode. See Start-up and UVLO for information on UVLO
operation mode. In the normal mode, the output state is dependent on the states of the HI and LI pins. Table 3
lists the output states for different input pin combinations. Note that when both HI and LI are asserted, both GaN
FETs in the power stage are turned on. Careful consideration must be applied to the control inputs in order to
avoid this state, as it will result in a shoot-through condition, which can permanently damage the device.
Table 3. Truth Table
HI
LI
HIGH-SIDE GaN FET
LOW-SIDE GaN FET
SW
L
L
OFF
OFF
Hi-Z
L
H
OFF
ON
PGND
H
L
ON
OFF
VIN
H
H
ON
ON
---
9 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
9.1 Application Information
The LMG5200 GaN power stage is a versatile building block for various types of high-frequency, switch-mode
power applications. The high-performance gate driver IC integrated in the package helps minimize the parasitics
and results in extremely fast switching of the GaN FETs. The device design is highly optimized for synchronous
buck converters and other half-bridge configurations.
9.2 Typical Application
Figure 11 shows a synchronous buck converter application with VCC connected to a 5-V supply. It is critical to
optimize the power loop (loop impedance from VIN capacitor to PGND). Having a high power loop inductance
causes significant ringing in the SW node and also causes the associated power loss. Refer to the Layout
Guidelines section for information on how to minimize this power loop.
4
3
2
HS
HB
VIN
1
SW
8
PGND
9
HI
PWM
Controller
LMG5200
5
VOUT
LI
VCC
AGND
6
7
5-V VIN
Figure 11. Typical Connection Diagram For a Synchronous Buck Converter
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Typical Application (continued)
9.2.1 Design Requirements
When designing a synchronous buck converter application that incorporates the LMG5200 power stage, some
design considerations must be evaluated first to make the most appropriate selection. Among these
considerations are the input voltages, passive components, operating frequency, and controller selection.Table 4
shows some sample values for a typical application. See Power Supply Recommendations, Layout, and Power
Dissipation for other key design considerations for the LMG5200.
Table 4. Design Parameters
PARAMETER
SAMPLE VALUE
Half-bridge input supply voltage, VIN
48 V
Output voltage, VOUT
12 V
Output current
8A
VHB-HS bootstrap capacitor
0.1 uF, X5R
Switching frequency
1 MHz
Dead time
8 ns
Inductor
4.7 µH
Controller
TPS40400
9.2.2 Detailed Design Procedure
This procedure outlines the design considerations of LMG5200 in a synchronous buck converter. For additional
design help, see Related Documentation .
9.2.2.1 VCC Bypass Capacitor
The VCC bypass capacitor provides the gate charge for the low-side and high-side transistors and to absorb the
reverse recovery charge of the bootstrap diode. The required bypass capacitance can be calculated with
Equation 1.
CVCC = (QgH + QgL + Qrr) / ΔV
(1)
QgH and QgL are the gate charge of the high-side and low-side transistors, respectively. Qrr is the reverse
recovery charge of the bootstrap diode. ΔV is the maximum allowable voltage drop across the bypass capacitor.
A 0.1-µF or larger value, good-quality, ceramic capacitor is recommended. Place the bypass capacitor as close
as possible to the VCC and AGND pins of the device to minimize the parasitic inductance.
9.2.2.2 Bootstrap Capacitor
The bootstrap capacitor provides the gate charge for the high-side gate drive, dc bias power for HB UVLO circuit,
and the reverse recovery charge of the bootstrap diode. The required bypass capacitance can be calculated
using Equation 2.
CBST = (QgH + Qrr + IHB * tON(max)) / ΔV
where
•
•
•
•
•
IHB is the quiescent current of the high-side gate driver (150 µA, maximum)
tON(maximum) is the maximum on-time period of the high-side gate driver
Qrr is the reverse recovery charge of the bootstrap diode
QgH is the gate charge of the high-side GaN FET
ΔV is the permissible ripple in the bootstrap capacitor (< 100 mV, typical)
(2)
A 0.1-µF, 16-V, 0402 ceramic capacitor is suitable for most applications. Place the bootstrap capacitor as close
as possible to the HB and HS pins.
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9.2.2.3 Power Dissipation
Ensure that the power loss in the driver and the GaN FETs is maintained below the maximum power dissipation
limit of the package at the operating temperature. The smaller the power loss in the driver and the GaN FETs,
the higher the maximum operating frequency that can be achieved in the application. The total power dissipation
of the LMG5200 device is the sum of the gate driver losses, the bootstrap diode power loss and the switching
and conduction losses in the FETs.
The gate driver losses are incurred by charge and discharge of the capacitive load. It can be approximated using
Equation 3.
P = (2 u Qg ) u VDD u fSW
where
•
•
•
Qg is the gate charge
VDD is the bias supply
fSW is the switching frequency
(3)
There are some additional losses in the gate drivers due to the internal CMOS stages used to buffer the outputs.
Figure 1 shows the measured gate driver power dissipation versus frequency and load capacitance. Use this
graph to approximate the power losses due to the gate drivers.
The bootstrap diode power loss is the sum of the forward bias power loss that occurs while charging the
bootstrap capacitor and the reverse bias power loss that occurs during reverse recovery. Because each of these
events happens once per cycle, the diode power loss is proportional to the operating frequency. Higher input
voltages (VIN) to the half bridge also result in higher reverse recovery losses.
The power losses due to the GaN FETs can be divided into conduction losses and switching losses. Conduction
losses are resistive losses and can be calculated using Equation 4.
PCOND = ª(IRMS(HS) )2 u RDS(on)HS º + ª(IRMS(LS) )2 u RDS(on)LS º
¬
¼
¬
¼
where
•
•
•
•
RDS(on)HS is the high-side GaN FET on-resistance
RDS(on)LS is the low-side GaN FET on-resistance
IRMS(HS) is the high-side GaN FET RMS current
IRMS(LS) and low-side GaN FET RMS current
(4)
The switching losses can be computed to a first order using , tTR can be approximated by dividing VIN by 25V/ns,
which is a conservative estimate of the switched node slew rate. Equation 5.
PSW = VIN ´ IOUT ´ fSW ´ t TR
where
•
tTR is the switch transition time from ON to OFF and from OFF to ON
(5)
Note that the low-side FET does not suffer from this loss. The third quadrant loss in the low-side device is
ignored in this first order loss calculation.
As described previously, switching frequency has a direct effect on device power dissipation. Although the gate
driver of the LMG5200 device is capable of driving the GaN FETs at frequencies up to 10 MHz, careful
consideration must be applied to ensure that the running conditions for the device meet the recommended
operating temperature specification. Specifically, hard-switched topologies tend to generate more losses and selfheating than soft-switched applications.
The sum of the driver loss, the bootstrap diode loss, and the switching and conduction losses in the GaN FETs is
the total power loss of the device. Careful board layout with an adequate amount of thermal vias close to the
power pads (VIN and PGND) allows optimum power dissipation from the package. A top-side mounted heat sink
with airflow can also improve the package power dissipation.
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9.2.3 Application Curves
Figure 12. SW Node Behavior Showing the Dead Time
Figure 13. Zoom-In Showing the Dead Time of 7.7 ns and
the Overshoot of the SW Node
10 Power Supply Recommendations
The recommended bias supply voltage range for LMG5200 is from 4.75 V to 5.25 V. The lower end of this range
is governed by the internal undervoltage lockout (UVLO) protection feature of the VCC supply circuit. The upper
end of this range is driven by the 6 V absolute maximum voltage rating of VCC. Note that the gate voltage of the
low-side GaN FET is not clamped internally. Hence, it is important to keep the VCC bias supply within the
recommended operating range to prevent exceeding the low-side GaN transistor gate breakdown voltage.
The UVLO protection feature also involves a hysteresis function. This means that once the device is operating in
normal mode, if the VCC voltage drops, the device continues to operate in normal mode as far as the voltage
drop does not exceeds the hysteresis specification, VCC(hyst). If the voltage drop is more than hysteresis
specification, the device shuts down. Therefore, while operating at or near the 4.5 V range, the voltage ripple on
the auxiliary power supply output must be smaller than the hysteresis specification of LMG5200 to avoid
triggering device-shutdown.
Place a local bypass capacitor between the VDD and VSS pins. This capacitor must be located as close as
possible to the device. A low ESR, ceramic surface-mount capacitor is recommended. TI recommends using 2
capacitors across VDD and GND: a 100 nF ceramic surface-mount capacitor for high frequency filtering placed
very close to VDD and GND pin, and another surface-mount capacitor, 220 nF to 10 μF, for IC bias
requirements.
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11 Layout
11.1 Layout Guidelines
To maximize the efficiency benefits of fast switching, it is extremely important to optimize the board layout such
that the power loop impedance is minimal. When using a multilayer board (more than 2 layers), power loop
parasitic impedance is minimized by having the return path to the input capacitor (between VIN and PGND),
small and directly underneath the first layer as shown in Figure 14 and Figure 15. Loop inductance is reduced
due to flux cancellation as the return current is directly underneath and flowing in the opposite direction. It is also
critical that the VCC capacitors and the bootstrap capacitors are as close as possible to the device and in the
first layer. Carefully consider the AGND connection of LMG5200 device. It must NOT be directly connected to
PGND so that PGND noise does not directly shift AGND and cause spurious switching events due to noise
injected in HI and LI signals.
11.2 Layout Examples
Placements shown in Figure 14 and in the cross section of Figure 15 show the suggested placement of the
device with respect to sensitive passive components, such as VIN, bootstrap capacitors (HS and HB) and VSS
capacitors. Use appropriate spacing in the layout to reduce creepage and maintain clearance requirements in
accordance with the application pollution level. Inner layers if present can be more closely spaced due to
negligible pollution.
The layout must be designed to minimize the capacitance at the SW node. Use as small an area of copper as
possible to connect the device SW pin to the inductor, or transformer, or other output load. Furthermore, ensure
that the ground plane or any other copper plane has a cutout so that there is no overlap with the SW node, as
this would effectively form a capacitor on the printed circuit board. Additional capacitance on this node reduces
the advantages of the advanced packaging approach of the LMG5200 and may result in reduced performance.
Figure 16, Figure 17, Figure 18, and Figure 19 show an example of how to design for minimal SW node
capacitance on a four-layer board. In these figures, U1 is the LMG5200 device.
PGND
Metal underneath solder mask
VIN Capacitors
VIN
HS
VIN
HB
HI
LMG5200
PGND
PGND
LI
Legend
VCC
AGND
SW
Metal 1
Metal 2 (PGND)
Vias
SW
Figure 14. External Component Placement (Single Layer)
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Layout Examples (continued)
Legend
VIN
SW
PGND
PGND
Metal 3
Small Return Path
Minimizes Power Loop
Impedance
xxx
VIN Capacitors
LMG5200
4 Layer PCB
Figure 15. Four-Layer Board Cross Section With Return Path Directly Underneath for Power Loop
Figure 16. Top Layer
Figure 17. Ground Plane
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Layout Examples (continued)
Figure 18. Middle Layer
Figure 19. Bottom Layer
VIN Capacitors
VIN
HS
VIN
HB
HI
LMG5200
PGND
PGND
Legend
LI
Metal 1
Bottom Layer
VCC
AGND
SW
SW
Metal 1 (SW)
Vias
VIN Capacitors (Bottom Layer)
Figure 20. External Component Placement (Double Layer PCB)
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Layout Examples (continued)
Legend
VIN
SW (Top Layer)
PGND
PGND (Bottom Layer)
Small Return Path
Minimizes Power Loop
Impedance
xxx
LMG5200
2 Layer PCB
VIN Capacitors
Figure 21. Two-Layer Board Cross Section With Return Path
Two-layer boards are not recommended for use with LMG5200 device due to the larger power loop inductance.
However, if design considerations allow only two board layers, place the input decoupling capacitors immediately
behind the device on the back-side of the board to minimize loop inductance. Figure 20 and Figure 21 show a
layout example for two-layer boards.
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12 Device and Documentation Support
12.1 Device Support
12.1.1 Development Support
LMG5200 PSpice Transient Model
LMG5200 TINA-TI Transient Reference Design
LMG5200 TINA-TI Transient Spice Model
12.2 Documentation Support
12.2.1 Related Documentation
Layout Guidelines for LMG5200 GaN Power Stage Module
Using the LMG5200: GaN Half-Bridge Power Module Evaluation Module
12.3 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper
right corner, click on Alert me to register and receive a weekly digest of any product information that has
changed. For change details, review the revision history included in any revised document.
12.4 Community Resources
The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.
12.5 Trademarks
E2E is a trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
12.6 Electrostatic Discharge Caution
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
12.7 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
13 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
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13.1 Package Information
The LMG5200 device package is rated as an MSL3 package (Moisture Sensitivity Level 3). Refer to application
report AN-2029 Handling and Process Recommendations for specific handling and process recommendations of
an MSL3 package.
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PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
(4/5)
(6)
LMG5200MOFR
ACTIVE
QFM
MOF
9
2000
RoHS & Green
NIAU
Level-3-260C-168 HR
-40 to 125
LMG5200
513B
LMG5200MOFT
ACTIVE
QFM
MOF
9
250
RoHS & Green
NIAU
Level-3-260C-168 HR
-40 to 125
LMG5200
513B
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of
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