LMH0031VS

LMH0031 www.ti.com SNLS218A – JANUARY 2006 – REVISED APRIL 2013 LMH0031 SMPTE 292M/259M Digital Video Deserializer / Descrambler with Video and Ancillary Data FIFOs Check for Samples: LMH0031 FEATURES APPLICATIONS • • 1 2 • • • • • (1) • • • • • • • • • • SDTV/HDTV Serial Digital Video Standard Compliant Supports 270 Mbps, 360 Mbps, 540 Mbps, 1.483 Gbps and 1.485 Gbps Serial Video Data Rates with Auto-Detection LSB De-Dithering Option Uses Low-Cost 27MHz Crystal or Clock Oscillator Reference Fast VCO Lock Time: < 500 µs at 1.485 Gbps Built-in Self-Test (BIST) and Video Test Pattern Generator (TPG) SDTV/HDTV Serial-to-Parallel Digital Video Interfaces for: – Video Editing Equipment – VTRs – Standards Converters – Digital Video Routers and Switchers – Digital Video Processing and Editing Equipment – Video Test Pattern Generators and Digital Video Test Equipment – Video Signal Generators Patent Applications Made or Pending Automatic EDH/CRC Word and Flag Processing Ancillary Data FIFO with Extensive Packet Handling Options Adjustable, 4-Deep Parallel Output Video Data FIFO Flexible Control and Configuration I/O Port LVCMOS Compatible Control Inputs and Clock and Data Outputs LVDS and ECL-Compatible, Differential, Serial Inputs 3.3V I/O Power Supply and 2.5V Logic Power Supply Operation Low Power: Typically 850mW 64-Pin TQFP Package Commercial Temperature Range 0°C to +70°C DESCRIPTION The LMH0031 SMPTE 292M / 259M Digital Video Deserializer/Descrambler with Video and Ancillary Data FIFOs is a monolithic integrated circuit that deserializes and decodes SMPTE 292M, 1.485Gbps (or 1.483Gbps) serial component video data, to 20-bit parallel data with a synchronized parallel word-rate clock. It also deserializes and decodes SMPTE 259M, 270Mbps, 360Mbps and SMPTE 344M (proposed) 540Mbps serial component video data, to 10-bit parallel data. Functions performed by the LMH0031 include: clock/data recovery from the serial data, serial-to-parallel data conversion, SMPTE standard data decoding, NRZI-to-NRZ conversion, parallel data clock generation, word framing, CRC and EDH data checking and handling, Ancillary Data extraction and automatic video format determination. The parallel video output features a variable-depth FIFO which can be adjusted to delay the output data up to 4 parallel data clock periods. Ancillary Data may be selectively extracted from the parallel data through the use of masking and control bits in the configuration and control registers and stored in the on-chip FIFO. Reverse LSB dithering is also implemented. 1 2 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. All trademarks are the property of their respective owners. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright © 2006–2013, Texas Instruments Incorporated LMH0031 SNLS218A – JANUARY 2006 – REVISED APRIL 2013 www.ti.com DESCRIPTION (CONTINUED) The unique multi-functional I/O port of the LMH0031 provides external access to functions and data stored in the configuration and control registers. This feature allows the designer greater flexibility in tailoring the LMH0031 to the desired application. The LMH0031 is auto-configured to a default operating condition at power-on or after a reset command. Separate power pins for the PLL, deserializer and other functional circuits improve power supply rejection and noise performance. The LMH0031 has a unique Built-In Self-Test (BIST) and video Test Pattern Generator (TPG). The BIST enables comprehensive testing of the device by the user. The BIST uses the TPG as input data and includes SD and HD component video test patterns, reference black, PLL and EQ pathologicals and a 75% saturation, 8 vertical colour bar pattern, for all implemented rasters. The colour bar pattern has optional transition coding at changes in the chroma and luma bar data. The TPG data is output via the parallel data port. The LMH0030, SMPTE 292M / 259M Digital Video Serializer with Ancillary Data FIFO and Integrated Cable Driver, is the ideal complement to the LMH0031. The LMH0031's internal circuitry is powered from +2.5 Volts and the I/O circuitry from a +3.3 Volt supply. Power dissipation is typically 850mW. The device is packaged in a 64-pin TQFP. TYPICAL APPLICATION VDD 75: 1% SMPTE Video Data Input LMH0030 SD/HD Encoder/ Serializer/ Cable Driver Parallel Ancilliary Data Input SMPTE 292M or 259M Serial Data 1 PF 75: Coaxial Cable 1 PF LMH0034 Adaptive Cable Equalizer 75: 1% SMPTE Video Data Output LMH0031 SD/HD Decoder/ Deserializer Parallel Ancilliary Data Output 2 Submit Documentation Feedback Copyright © 2006–2013, Texas Instruments Incorporated Product Folder Links: LMH0031 LMH0031 www.ti.com SNLS218A – JANUARY 2006 – REVISED APRIL 2013 Block Diagram XTALi/Ext Clk REFERENCE CLOCK/OSCILLATOR XTALo PLL/CLOCK SYSTEM PCLK SDI INPUT DATA SAMPLERS CLOCK/DATA RECOVERY SDI BIST & TPG RBB RREF SDI BIAS SMPTE NRZI-NRZ CONVERTER DESCRAMBLER/ DESERIALIZER TRS & FORMAT DETECTOR PCLK EDH / CRC GENERATORS/CHECKERS ANCILLIARY DATA FIFO VIDEO DATA BUS AD[9:0] MASTER BUS DE-DITHERING FRAMING CONTROL ACLK RD / WR CONFIGURATION & CONTROL REGISTERS DV[19:10] ANC / CTRL VIDEO DATA FIFO & OUTPUT DV[9:0] I/O[7:0] VCLK MULTI-FUNCTION I/O PORT PCLK RESET RESET CONTROL INT. RESET SYSTEM MASTER CONTROLLER Submit Documentation Feedback Copyright © 2006–2013, Texas Instruments Incorporated Product Folder Links: LMH0031 3 LMH0031 SNLS218A – JANUARY 2006 – REVISED APRIL 2013 www.ti.com IO5 IO6 IO7 ACLK VDDD AD0 AD1 AD2 AD3 AD4 VSSD AD5 AD6 AD7 AD8 AD9 Connection Diagram 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 IO4 17 64 RD/WR IO3 18 63 ANC/CTRL IO2 19 62 V DDD VSSIO 20 61 XTALo DV19 21 60 XTALi/Ext Clk DV18 22 59 VSSIO DV17 23 58 V DDSI DV16 24 57 SDI LMH0031 DV15 25 56 SDI 35 36 37 38 39 40 41 42 43 44 45 46 47 48 VDDIO 34 VSSIO 33 IO0 49 RESET IO1 VSSD 32 DV0 50 VCLK DV1 DV10 31 DV2 51 VDDPLL DV3 DV11 30 DV4 52 VSSPLL VSSD DV12 29 DV5 53 R REF DV6 DV13 28 DV7 54 R BB DV8 DV14 27 DV9 55 VSSSI VDDD VDDIO 26 Figure 1. 64-Pin TQFP See Package Number PAG0064A 4 Submit Documentation Feedback Copyright © 2006–2013, Texas Instruments Incorporated Product Folder Links: LMH0031 LMH0031 www.ti.com SNLS218A – JANUARY 2006 – REVISED APRIL 2013 These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates. Absolute Maximum Ratings (1) (2) CMOS I/O Supply Voltage (VDDIO–VSSIO): 4.0V SDI Supply Voltage (VDDSI–VSSSI): 4.0V Digital Logic Supply Voltage (VDDD–VSSD): 3.0V PLL Supply Voltage (VDDPLL–VSSPLL): 3.0V CMOS Input Voltage (Vi): VSSIO −0.15V to VDDIO +0.15V CMOS Output Voltage (Vo): VSSIO −0.15V to VDDIO +0.15V CMOS Input Current (single input): Vi = VSSIO −0.15V: −5 mA Vi = VDDIO +0.15V: +5 mA CMOS Output Source/Sink Current: ±6 mA IBB Output Current: +300 μA IREF Output Current: +300 μA VSSSI −0.15V to VDDSI +0.15V SDI Input Voltage (Vi): Package Thermal Resistance θJA @ 0 LFM Airflow 40.1°C/W θJA @ 500 LFM Airflow 24.5°C/W θJC 5.23°C/W Storage Temp. Range: −65°C to +150°C Junction Temperature: +150°C Lead Temperature (Soldering 4 Sec): +260°C ESD Rating (HBM): 6.0 kV ESD Rating (MM): 400 V (1) (2) Absolute Maximum Ratings are those parameter values beyond which the life and operation of the device cannot be ensured. The stating herein of these maximums shall not be construed to imply that the device can or should be operated at or beyond these values. The table of “Electrical Characteristics” specifies acceptable device operating conditions. It is anticipated that this device will not be offered in a military qualified version. If Military/Aerospace specified devices are required, please contact the Texas Instruments Sales Office / Distributors for availability and specifications. Recommended Operating Conditions Symbol Parameter Conditions VDDIO CMOS I/O Supply Voltage VDDIO−VSSIO VDDSD SDI Supply Voltage VDDSI−VSSSI VDDD Digital Logic Supply Voltage VDDD–VSSD VDDPLL PLL Supply Voltage VDDPLL–VSSPLL TA Operating Free Air Temperature Reference Min Typ Max Units 3.150 3.300 3.450 V 2.375 2.500 2.625 V +70 °C 0 Submit Documentation Feedback Copyright © 2006–2013, Texas Instruments Incorporated Product Folder Links: LMH0031 5 LMH0031 SNLS218A – JANUARY 2006 – REVISED APRIL 2013 www.ti.com Required Input Conditions (1) (2) Symbol Parameter VIN Input Voltage Range tr, tf Rise Time, Fall Time Conditions 10%–90% Reference Min 1.0 SMPTE 259M, Level C Serial Input Data Rate SMPTE 344M VIN(SDI) SDI Serial Input Voltage, Single-ended VIN(SDI) SDI Serial Input Voltage, Differential tr, tf Rise Time, Fall Time fACLK Ancillary / Control Data Clock Frequency DCACLK Duty Cycle, Ancillary Clock tr, tf Ancillary / Control Clock and Data Rise Time, Fall Time tS Setup Time, ADN to ACLK or ION to ACLK Rising Edge tH Hold Time, Rising Edge ACLK to ADN or ACLK to ION RREF Bias Supply Reference Resistor fEXT External Clock Frequency CLK fXTAL (1) (2) 6 Crystal Frequency MBPS 1,485 VSSSI +1.0V SDI, SDI 20%–80%, SMPTE 259M Data Rates ACLK 10%–90% ION, ADN, ACLK Timing Diagram XTALo, XTALi V 800 880 mVP-P 125 800 880 mVP-P 0.4 1.0 1.5 ns 270 ps VCLK MHz 45 50 55 % 1.0 1.5 3.0 ns 3.0 1.5 ns 3.0 1.5 ns 4.75k Ω Tolerance 1% Ext Clk VDDSI −0.05V 125 20%–80%, SMPTE 292M Data Rates See Figure 7 ns 540 VIN = 125 mVP-P Control Data Input or I/O Bus Input V 3.0 1,483 SMPTE 292M Common Mode Voltage Units 360 SDI, SDI SMPTE 292M VCM(SDI) 1.5 Max VDDIO 270 SMPTE 259M, Level D BRSDI Typ VSSIO All LVCMOS Inputs −100 ppm 27.0 +100 ppm MHz Required Input Conditions are the electrical signal conditions or component values which shall be supplied by the circuit in which this device is used in order for it to produce the specified DC and AC electrical output characteristics. Functional and certain other parametric tests utilize a LMH0030 as the input source to the SDI inputs of the LMH0031. The LMH0030 is DC coupled to the inputs of the LMH0031. Typical VIN = 800 mV, VCM = 2.9 V. Submit Documentation Feedback Copyright © 2006–2013, Texas Instruments Incorporated Product Folder Links: LMH0031 LMH0031 www.ti.com SNLS218A – JANUARY 2006 – REVISED APRIL 2013 DC Electrical Characteristics Over Supply Voltage and Operating Temperature ranges, unless otherwise specified (1) (2). Symbol Parameter Conditions VIH Input Voltage High Level VIL Input Voltage Low Level IIH Input Current High Level VIH = VDDIO (3) IIL Input Current Low Level VIL = VSSIO VOH Output Voltage High Level IOH = −2 mA Reference All LVCMOS Inputs Min Typ 2.0 VDDIO VSSIO 0.8 +85 +150 −1 −20 2.4 2.7 VDDIO VSSIO VSSIO +0.3 VSSIO +0.5V VOL Output Voltage Low Level IOL = +2 mA VOHV Minimum Dynamic VOH IOH = −2 mA (4) VOLP Maximum Dynamic VOL IOL = +2 mA (4) VSDI Serial Data Input Voltage ISDI Serial Data Input Current VTH Input Thereshold Over VCM range IBB Bias Supply Output Current RBB = 8.66kΩ 1% −220 −188 IREF Reference Output Current RREF = 4.75kΩ 1% −290 −262 IDD (3.3V) Power Supply Current, 3.3V Supply, Total 270MBPS Data Rate IDD (2.5V) Power Supply Current, 2.5V Supply, Total 270MBPS Data Rate (1) (2) (3) (4) All LVCMOS Outputs V µA V VSSIO +0.4 125 1,485MBPS Data Rate Units VDDIO −0.5 SDI, SDI 1,485MBPS Data Rate Max 800 880 ±1 ±10 mVP-P Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Colour Bars 1 1 1 0 1 1 750 Line, 74.25 MHz, 60 Frame Progressive Component (SMPTE 296M) Ref. Black 1 1 1 1 0 0 PLL Path. 1 1 1 1 0 1 EQ Path. 1 1 1 1 1 0 Colour Bars 1 1 1 1 1 1 525 Line, 30 Frame, 27 MHz, NTSC 4x3 (SMPTE 125M) Ref. Black 0 0 0 0 0 0 PLL Path. 0 0 0 0 0 1 EQ Path. 0 0 0 0 1 0 Colour Bars (SD BIST) 0 0 0 0 1 1 625 Line, 25 Frame, 27 MHz, PAL 4x3 (ITU-T BT.601) Ref. Black 0 1 0 0 0 0 PLL Path. (SD BIST) 0 1 0 0 0 1 EQ Path. 0 1 0 0 1 0 Colour Bars 0 1 0 0 1 1 525 Line, 30 Frame, 36 MHz, NTSC 16x9 (SMPTE 125M) Ref. Black 0 0 0 1 0 0 PLL Path. 0 0 0 1 0 1 EQ Path. 0 0 0 1 1 0 Colour Bars 0 0 0 1 1 1 625 Line, 25 Frame, 36 MHz, PAL 16x9 (ITU-T BT.601) Ref. Black 0 1 0 1 0 0 PLL Path. 0 1 0 1 0 1 EQ Path. 0 1 0 1 1 0 Colour Bars 0 1 0 1 1 1 Ref. Black 0 0 1 0 0 0 PLL Path. 0 0 1 0 0 1 EQ Path. 0 0 1 0 1 0 Colour Bars 0 0 1 0 1 1 Ref. Black 0 1 1 0 0 0 PLL Path. 0 1 1 0 0 1 EQ Path. 0 1 1 0 1 0 Colour Bars 0 1 1 0 1 1 525 Line, 30 Frame, 54 MHz (NTSC) 625 Line, 25 Frame, 54 MHz (PAL) VIDEO INFO 0 REGISTER (Address 0Eh) Re-synchronization of the parallel video output data with the parallel rate clock is controlled by the functions Framing Enable, Framing Mode and NSP. For operating details about these control bits, refer to the preceeding section about Format Registers 0 and 1 and the Format Mode bit. Framing Enable may be assigned as an input on the multi-function I/O port. The NSP (New Sync Position) bit indicates that a new or out-of-place TRS character has been detected in the input data. This bit is set to a logic-1 and remains set for at least one horizontal line period or unless re-activated by a subsequent new or out-of-place TRS. It is reset by an EAV TRS character. The EAV (end of active video) and SAV (start of active video) bits track the occurrence of the corresponding TRS characters. Submit Documentation Feedback Copyright © 2006–2013, Texas Instruments Incorporated Product Folder Links: LMH0031 27 LMH0031 SNLS218A – JANUARY 2006 – REVISED APRIL 2013 www.ti.com The Lock Detect is a logic-1 when the loop is locked and the CDR has acquired a phase of the incoming serial data. This bit may be programmed as an output on the multi-function I/O bus. This bit is mapped to I/O port bit 4 in the default condition. The VPG Filter Enable bit when set enables operation of the Video Pattern Generator filter. Operation of this filter causes the insertion of transition codes in the chroma and luma data of colour bar test patterns where these patterns change from one bar to the next. This filter reduces the magnitude of out-of-band frequency products which are produced by abrupt transitions in the chroma and luma data when fed to D-to-A converters and picture monitors. The LMH0031 incorporates circuitry that implements a method for handling data that has been subjected to LSB dithering. Data from the de-scrambler is routed for de-dithering. Control of this circuitry is via the De-Dither Enable bit in the VIDEO INFO 0 control register. Recovery of data that has been dithered during the vertical blanking interval can be selectively enabled by use of the V De-Dither Enable bit in the VIDEO INFO 0 control register. The initial condition of De-Dither Enable and V De-Dither Enable is OFF. VIDEO CONTROL 0 (register address 55h) The EXTERNAL VCLK bit is a special application function which enables use of an external VCXO as a substitute for the internally generated VCLK. Additional circuitry is enabled within the LMH0031 which provides phasefrequency detection and control voltage output for the VCXO. An external loop filter and voltage amplifier are required to interface the control voltage output to the VCXO frequency control input. When this function is used, the RBB output function is changed from the bias supply output to the control voltage output of the phasefrequency detector. The VCLK output changes function, becoming the input for the VCXO signal. Use of this function and required external support circuitry is explained in the Application Information section. The SYNC DETECT ENABLE bit, when set, enables detection of TRS characters. This bit is normally set (ON). The LSB CLIP ENABLE bit, when set, causes the two LSBs of TRS characters to be set to 00b as described in ITU-R BT.601. This function is normally set (ON). The NRZI ENABLE bit, when set, enables data to be converted from NRZI to NRZ. This bit is normally set (ON). The DE-SCRAMBLE ENABLE bit, when set, enables de-scrambling of the incoming data according to requirements of SMPTE 259M or SMPTE 292M. This bit is normally set (ON). CAUTION The default state of this register is 36h. If any of the normal operating features of the descrambler are turned off, this register’s default data must be restored to resume normal device operation. REFERENCE CLOCK REGISTER (Address 67h) The Reference Clock register controls operation of the CDR reference clock source. The CLKEN bit when reset to a logic-0 enables the oscillator signal to be used by the LMH0031 as a reference. The default state of this bit at power-on is enabled. In general, this function and bit should not be disabled. The INT_OSC EN bit enables the internal crystal oscillator amplifier. By default this bit is a logic-0 and is therefore inactive at power-on. The device expects an external 27MHz reference reference clock source to be connected to the XTALi/Ext Clk pin and activated at power-on. I/O PIN 0 THROUGH 7 CONFIGURATION REGISTERS (Addresses 0Fh through 16h) The I/O Pin Configuration Registers are used to map individual bits of the multi-function I/O port to selected bits of the Configuration and Control Registers. Table 6 gives the pin select codes for the Configuration and Control register functions that may be mapped to the port. Pin[n] Select [5] controls whether the port pin is input or output. The port pin will be an input when this bit is set and an output when reset. Input-only functions may not be configured as outputs and vice versa. The remaining five Pin[n] Select [4:0] bits identify the particular Control Register bit to be mapped. 28 Submit Documentation Feedback Copyright © 2006–2013, Texas Instruments Incorporated Product Folder Links: LMH0031 LMH0031 www.ti.com SNLS218A – JANUARY 2006 – REVISED APRIL 2013 Example: Program, via the AD port, I/O port bit 0 as output for the CRC Luma Error bit in the control registers. 1. Set ANC/CTRL to a logic-low. 2. Set RD/WR to a logic-low. 3. Present 00Fh to AD[9:0] as the I/O PIN 0 CONFIG register address. 4. Toggle ACLK. 5. Present 310h to AD[9:0] as the register data, the bit address of the CRC Luma Error bit in the control registers. 6. Toggle ACLK. Table 6. Control Register Bit, Pin[n] SEL[5:0] Codes for I/O Port Pin Mapping (1) Pin[n] SEL[5:0] Codes [5] [4] [3] [2] [1] [0] HEX I/P or O/P reserved 0 0 0 0 0 0 00 O/P FF Flag Error 0 0 0 0 0 1 01 O/P AP Flag Error 0 0 0 0 1 0 02 O/P ANC Flag Error 0 0 0 0 1 1 03 O/P CRC Error (SD/HD) 0 0 0 1 0 0 04 O/P ANC FIFO 90% FULL 0 0 0 1 1 1 07 O/P SHORT MSG DETECT 0 0 1 0 0 0 08 O/P FULL MSG AVAIL 0 0 1 0 0 1 09 O/P SAV 0 0 1 1 0 1 0D O/P EAV 0 0 1 1 1 0 0E O/P NSP 0 0 1 1 1 1 0F O/P CRC Luma Error 0 1 0 0 0 0 10 O/P CRC Chroma Error 0 1 0 0 0 1 11 O/P F 0 1 0 0 1 0 12 O/P I/O Port Bit 0 V 0 1 0 0 1 1 13 O/P I/O Port Bit 1 H 0 1 0 1 0 0 14 O/P I/O Port Bit 2 Format[0] 0 1 0 1 0 1 15 O/P Format[1] 0 1 0 1 1 0 16 O/P Format[2] 0 1 0 1 1 1 17 O/P Format[3] 0 1 1 0 0 0 18 O/P Format[4] 0 1 1 0 0 1 19 O/P FIFO Full 0 1 1 0 1 0 1A O/P FIFO Empty 0 1 1 0 1 1 1B O/P I/O Port Bit 6 Lock Detect 0 1 1 1 0 0 1C O/P I/O Port Bit 4 Pass/Fail 0 1 1 1 0 1 1D O/P FIFO Overrun 0 1 1 1 1 0 1E O/P ANC Chksum Error 0 1 1 1 1 1 1F O/P EDH Force 1 0 0 0 0 0 20 I/P Test Pattern Select[0] 1 0 0 0 0 1 21 I/P Test Pattern Select[1] 1 0 0 0 1 0 22 I/P Test Pattern Select[2] 1 0 0 0 1 1 23 I/P Test Pattern Select[3] 1 0 0 1 0 0 24 I/P Test Pattern Select[4] 1 0 0 1 0 1 25 I/P Test Pattern Select[5] 1 0 0 1 1 0 26 I/P Register Bit Power-On Status I/O Port Bit 5 Addresses 05h and 06h are reserved Addresses 0Ah through 0Ch are reserved (1) I/O Port Bit 7 I/O Port Bit 3 (SD/HD) Note: All LVCMOS inputs have internal pull-down devices except VCLK and ACLK. Submit Documentation Feedback Copyright © 2006–2013, Texas Instruments Incorporated Product Folder Links: LMH0031 29 LMH0031 SNLS218A – JANUARY 2006 – REVISED APRIL 2013 www.ti.com Table 6. Control Register Bit, Pin[n] SEL[5:0] Codes for I/O Port Pin Mapping(1) (continued) Pin[n] SEL[5:0] Codes [5] [4] [3] [2] [1] [0] HEX I/P or O/P EDH Enable 1 0 0 1 1 1 27 I/P TPG Enable 1 0 1 0 0 0 28 I/P Register Bit Power-On Status Addresses 29h through 2Bh are reserved VPG Filter Enable 1 0 1 1 0 0 2C I/P De-Dither Enable 1 0 1 1 0 1 2D I/P Framing Enable 1 0 1 1 1 0 2E I/P FIFO Extract Enable 1 0 1 1 1 1 2F I/P PIN DESCRIPTIONS Pin 30 Name Description 1 AD9 Ancillary Data Output, Control Data Input 2 AD8 Ancillary Data Output, Control Data Input 3 AD7 Ancillary Data Output, Control Data Input 4 AD6 Ancillary Data Output, Control Data Input 5 AD5 Ancillary Data Output, Control Data Input 6 VSSD Negative Power Supply Input (2.5V supply, Digital Logic) 7 AD4 Ancillary Data Output, Control Data Input 8 AD3 Ancillary Data Output, Control Data Input 9 AD2 Ancillary Data Output, Control Data Input 10 AD1 Ancillary Data Output, Control Data Input 11 AD0 Ancillary Data Output, Control Data Input 12 VDDD Positive Power Supply Input (2.5V supply, Digital Logic) 13 ACLK ancillary/Control Clock Input 14 IO7 Multi-Function I/O Port 15 IO6 Multi-Function I/O Port 16 IO5 Multi-Function I/O Port 17 IO4 Multi-Function I/O Port 18 IO3 Multi-Function I/O Port 19 IO2 Multi-Function I/O Port 20 VSSIO Negative Power Supply Input (3.3V supply, I/O) 21 DV19 Parallel Video Output (HD=Luma) 22 DV18 Parallel Video Output (HD=Luma) 23 DV17 Parallel Video Output (HD=Luma) 24 DV16 Parallel Video Output (HD=Luma) 25 DV15 Parallel Video Output (HD=Luma) 26 VDDIO Positive Power Supply Input (3.3V supply, I/O) 27 DV14 Parallel Video Output (HD=Luma) 28 DV13 Parallel Video Output (HD=Luma) 29 DV12 Parallel Video Output (HD=Luma) 30 DV11 Parallel Video Output (HD=Luma) 31 DV10 Parallel Video Output (HD=Luma) 32 VSSD Negative Power Supply Input (2.5V supply, Digital Logic) 33 VDDD Positive Power Supply Input (2.5V supply, Digital Logic) 34 DV9 Parallel Video Output (HD=Chroma, SD=Luma & Chroma) 35 DV8 Parallel Video Output (HD=Chroma, SD=Luma & Chroma) 36 DV7 Parallel Video Output (HD=Chroma, SD=Luma & Chroma) Submit Documentation Feedback Copyright © 2006–2013, Texas Instruments Incorporated Product Folder Links: LMH0031 LMH0031 www.ti.com SNLS218A – JANUARY 2006 – REVISED APRIL 2013 PIN DESCRIPTIONS (continued) Pin Name Description 37 DV6 Parallel Video Output (HD=Chroma, SD=Luma & Chroma) 38 DV5 Parallel Video Output (HD=Chroma, SD=Luma & Chroma) 39 VSSD Negative Power Supply Input (2.5V supply, Digital Logic) 40 DV4 Parallel Video Output (HD=Chroma, SD=Luma & Chroma) 41 DV3 Parallel Video Output (HD=Chroma, SD=Luma & Chroma) 42 DV2 Parallel Video Output (HD=Chroma, SD=Luma & Chroma) 43 DV1 Parallel Video Output (HD=Chroma, SD=Luma & Chroma) 44 DV0 Parallel Video Output (HD=Chroma, SD=Luma & Chroma) 45 IO1 Multi-Function I/O Port 46 IO0 Multi-Function I/O Port 47 VSSIO Negative Power Supply Input (3.3V supply, I/O) 48 VDDIO Positive Power Supply Input (3.3V supply, I/O) 49 RESET Manual Reset Input (High True) 50 VCLK Parallel Video Data Clock Output 51 VDDPLL Positive Power Supply Input (2.5V supply, PLL) 52 VSSPLL Negative Power Supply Input (2.5V supply, PLL) 53 RREF Current Reference Resistor 54 RBB SDI Bias Supply Resistor 55 VSSSI Negative Power Supply Input (3.3V supply, Serial Input) 56 SDI Serial Data Complement Input 57 SDI Serial Data True Input 58 VDDSI Positive Power Supply Input (3.3V supply, Serial Input) 59 VSSIO Negative Power Supply Input (3.3V supply, I/O) 60 XTALi/EXT CLK Crystal or External 27MHz Clock Input 61 XTALo Crystal (Oscillator Output) 62 VDDD Positive Power Supply Input (2.5V supply, Digital Logic) 63 ANC/CTRL ancillary/Control Data Port Function Control Input 64 RD/WR ancillary/Control Data Port Read/Write Control Input Submit Documentation Feedback Copyright © 2006–2013, Texas Instruments Incorporated Product Folder Links: LMH0031 31 LMH0031 SNLS218A – JANUARY 2006 – REVISED APRIL 2013 www.ti.com Application Information A typical application circuit for the LMH0031 is shown in the Application Circuit diagram. This circuit demonstrates the capabilities of the LMH0031 and allows its evaluation in a native configuration. An assembled demonstration board is available, part number SD131EVK. The board may be ordered through any of TI's sales offices. Complete circuit board layouts and schematics for the SD131EVK are available on TI's WEB site. For latest availability information, please see: www.ti.com/appinfo/interface. PCB LAYOUT AND POWER SYSTEM BYPASS RECOMMENDATIONS Circuit board layout and stack-up for the LMH0031 should be designed to provide noise-free power to the device. Good layout practice also will separate high frequency or high-level inputs and outputs from low-level inputs to minimize unwanted stray noise pickup, feedback and interference. Power system performance may be greatly improved by using thin dielectrics (4 to 10 mils) for power/ground sandwiches. This increases the intrinsic capacitance of the PCB power system which improves power supply filtering, especially at high frequencies, and makes the value and placement of external bypass capacitors less critical. External bypass capacitors should include both RF ceramic and tantalum electrolytic types. RF capacitors may use values in the range 0.01 µF to 0.1 µF. Tantalum capacitors may be in the range 2.2 µF to 10 µF. Voltage rating for tantalum capacitors should be at least 5X the power supply voltage being used. It is recommended practice to use two vias at each power pin of the LMH0031 as well as all RF bypass capacitor terminals. Dual vias reduce the interconnect inductance by up to half, thereby extending the effective frequency range of the bypass components. The outer layers of the PCB may be flooded with additional VSS (ground) plane. These planes will improve shielding and isolation as well as increase the intrinsic capacitance of the power supply plane system. Naturally, to be effective, these planes must be tied to the VSS power supply plane at frequent intervals with vias. Frequent via placement also improves signal integrity on signal transmission lines by providing short paths for image currents which reduces signal distortion. The planes should be pulled back from all transmission lines and component mounting pads a distance equal to the width of the widest transmission line or the thickness of the dielectric separating the transmission line from the internal power or ground plane(s) whichever is greater. Doing so minimizes effects on transmission line impedances and reduces unwanted parasitic capacitances at component mounting pads. In especially noisy power supply environments, such as is often the case when using switching power supplies, separate filtering may be used at the LMH0031's PLL and serial input power pins. The LMH0031 was designed for this situation. The I/O, digital section, PLL and serial input power supply feeds are independent (see table and Block Diagram for details). Supply filtering may take the form of L-section or pi-section, L-C filters in series with these VDD inputs. Such filters are available in a single package from several manufacturers. Device power supplies must be either sequenced as described in POWER SUPPLIES, POWER-ON-RESET AND RESET INPUT and ideally should be applied simultaneously as from a common source. MAINTAINING OUTPUT DATA INTEGRITY The way in which the TRS and other video data characters are specified and are therefore output in parallel form can result in the simultaneous switching of many of the LMH0031’s CMOS outputs. Such switching can lead to the production of output high level droop or low level ground bounce. Given in the specifications, VOLP is the peak output LOW voltage or ground bounce and VOHV is the lowest output HIGH voltage or output droop that may occur under dynamic simultaneous output switching conditions. VOHV and VOLP are measured with respect to reference ground. Careful attention to PCB layout, power pin connections to the power planes and timing of the output data clocking can reduce these effects. Consideration must also be given to the timing allocated to external circuits which sample the outputs. The effects of simultaneous output switching on output levels may be minimized by adopting good PCB layout and data output timing practices, especially critical at HD data rates. The power pins feeding the I/O should have low inductance connections to the power and ground planes. It is recommended that these connections use at least two vias per power or ground pin. Short interconnecting traces consistent with good layout practices and soldering rules must be used. Sampling or clocking of data by external devices should be so timed as to take maximum advantage of the steady-state portion of the parallel output data interval. The LMH0031 is designed so that video data will be stable at the positive-going transition of VCLK. Data should not be sampled close to the data transition intervals associated with the negative-going clock edge. The specified propagation delay and clock to data timing parameters must be observed. When data is being sampled from the video data port together with the ANC port and/or I/O port, it is recommended that the sampling clocks be synchronized with the video clock, VCLK, to minimize possible effects from ground bounce or output droop on sampled signal levels. 32 Submit Documentation Feedback Copyright © 2006–2013, Texas Instruments Incorporated Product Folder Links: LMH0031 LMH0031 www.ti.com SNLS218A – JANUARY 2006 – REVISED APRIL 2013 PROCESSING NON-SUPPORTED RASTER FORMATS The number and type of HD raster formats has proliferated since the LMH0031 was designed. Though not specifically capable of fully or automatically processing these new formats, the LMH0031 may still be capable of deserializing them. The user is encouraged to experiment with processing these formats, keeping in mind that the LMH0031 has not been tested to handle formats other than those detailed in Table 4. Therefore, the results from attempts to process non-supported formats is not ensured. The following guidelines concerning device setup are provided to aid the user in configuring the LMH0031 to attempt limited processing of these other raster formats. In general, the device is configured to defeat its automatic format detection function and to limit operation to a general HD format. (The user should consult Table 4 for guidance on the format groups similar to the nonsupported one to be processed). Since most non-supported formats are in the HD group, the LMH0031 should be configured to operate in HD-ONLY mode by setting bit-5 of the FORMAT 0 register (address 0Bh). Also, the device should be further configured by loading the FORMAT SET[4:0] bits of this register with the general HD sub-format code. In addition, since control data is being written to the port, AD[9:8] must be driven as 11b. The complete data word for this general HD sub-format code with HD-ONLY bit set is 33Fh. Since this format differs from those in the table, the EAV/SAV indicators are disabled. Without these indicators, line numbering and CRC processing are disabled and ANC data extraction will not function. Output video chroma and luma data will be word-aligned. Post-processing of the parallel data output from the LMH0031 will be needed to implement CRC checking or line number tracking. USING EXTERNAL VCXO FOR VCLK The EXTERNAL VCLK bit of VIDEO CONTROL 0 (register address 55h) is a special application function which enables use of an external VCXO as a substitute for the internally generated VCLK. Additional circuitry is enabled within the LMH0031 which provides phase-frequency detection and control voltage output for the VCXO. An external loop filter and voltage amplifier are required to interface the control voltage output to the VCXO frequency control input. When this function is used, the RBB output function is changed from the bias supply output to the control voltage output of the phase-frequency detector. The VCLK output changes function, becoming the input for the VCXO signal. Figure 8 shows an example using dual VCXOs for VCLK to handle both standard and high definition video. Submit Documentation Feedback Copyright © 2006–2013, Texas Instruments Incorporated Product Folder Links: LMH0031 33 LMH0031 SNLS218A – JANUARY 2006 – REVISED APRIL 2013 www.ti.com +3.3V LMC7101 NC7SZ126 VCTRL + - 74.25 MHz VCXO FOUT OE 22.1: 100 k: +3.3V 182 k: NC7SZ125 VCTRL 27.00 MHz VCXO FOUT OE 22.1: CLC031 IO3 - SD/HD CLC031 IO4 - Lock Detect NC7SZ08 RB B VCLK LMH0031 22.1 k: 100 pF 10 nF RREF 4.75 k: To other logic or serializer DV[19:0] CAUTION! Read text before using this circuit. Figure 8. Using Dual VCXOs for VCLK Example The control voltage output from RBB is externally filtered by the loop filter consisting of a 22.1kΩ resistor in series with a 10nF capacitor, combined in parallel with a 100pF capacitor. This gives a loop bandwidth of 1.5kHz. Since the control voltage is limited to around 2.1V, it requires a level shifter to get the entire pull range on the VCXO. TI's LMC7101 is recommended with 100kΩ and 182kΩ resistors as shown in Figure 8 to provide a gain of 1.55, sufficient to drive a 3.3V VCXO. Recommended VCXOs from SaRonix (141 Jefferson Drive, Menlo Park, CA 94025, USA) include the ST1308AAB-74.25 for high definition and the ST1307BAB-27.00 for standard definition. Dual VCXOs require some supporting logic to select the appropriate VCXO. This requires the use of Format[4] (SD/HD) and Lock Detect, which are mapped at power-on to I/O Port Bit 3 and I/O Port Bit 4, respectively. These two signals pass through an AND gate (Fairchild Semiconductor's NC7SZ08 or similar). Its output is high when both Lock Detect and Format[4] are high, which indicates a valid high-definition signal is present. The VCXOs are buffered to control the transition times and to allow easy selection. The output of the AND gate is used to control the Output Enable (OE) function of the buffers. The 74.25MHz VCXO is buffered with the NC7SZ126 with the AND gate output connected to the OE pin of the NC7SZ126, and the 27.00MHz VCXO is buffered with the NC7SZ125 with the AND gate output connected to the OE pin of the NC7SZ125. This circuit uses the 27.00MHz VCXO as default and enables the 74.25MHz VCXO when a valid high-definition signal is present. The outputs from the buffers are daisy-chained together and sent to the LMH0031's VCLK in addition to other devices, such as the LMH0030 serializer. 34 Submit Documentation Feedback Copyright © 2006–2013, Texas Instruments Incorporated Product Folder Links: LMH0031 LMH0031 www.ti.com SNLS218A – JANUARY 2006 – REVISED APRIL 2013 REVISION HISTORY Changes from Original (April 2013) to Revision A • Page Changed layout of National Data Sheet to TI format .......................................................................................................... 34 Submit Documentation Feedback Copyright © 2006–2013, Texas Instruments Incorporated Product Folder Links: LMH0031 35 PACKAGE OPTION ADDENDUM www.ti.com 30-Sep-2021 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan (2) Lead finish/ Ball material MSL Peak Temp Op Temp (°C) Device Marking (3) (4/5) (6) LMH0031VS NRND TQFP PAG 64 160 Non-RoHS & Green Call TI Level-3-260C-168 HR 0 to 70 L031 LMH0031VS/NOPB ACTIVE TQFP PAG 64 160 RoHS & Green SN Level-3-260C-168 HR 0 to 70 L031 (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of