LMH0036
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LMH0036 SD SDI Reclocker with 4:1 Input Multiplexer
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FEATURES
APPLICATIONS
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Supports SMPTE 259M (C) Serial Digital Video
Standard
Supports 270 Mbps Serial Data Rate Operation
Supports DVB-ASI at 270 Mbps
Single 3.3V Supply Operation
360 mW Typical Power Consumption
Integrated 4:1 Multiplexed Input
Two Differential, Reclocked Outputs
Choice of Second Reclocked Output or LowJitter, Differential, Data-Rate Clock Output
Single 27 MHz External Crystal or Reference
Clock Input
Lock Detect Indicator Output
Output Mute Function for Data and Clock
Auto/Manual Reclocker Bypass
Differential LVPECL Compatible Serial Data
Inputs and Outputs
LVCMOS Control Inputs and Indicator Outputs
48-Pin WQFN Package
Industrial Temperature Range: -40°C to +85°C
Footprint Compatible with the LMH0056 and
LMH0356
SDTV Serial Digital Video Interfaces for:
– Digital Video Routers and Switchers
– Digital Video Processing and Editing
Equipment
– DVB-ASI Equipment
– Video Standards and Format Converters
DESCRIPTION
The LMH0036 SD SDI Reclocker with 4:1 Input
Multiplexer retimes serial digital video data
conforming to the SMPTE 259M (C) standard. The
LMH0036 operates at the serial data rate of 270
Mbps, and also supports DVB-ASI operation at 270
Mbps. The LMH0036 includes an integrated 4:1 input
multiplexer for selecting one of four input data
streams for retiming.
The LMH0036 retimes the incoming data to suppress
accumulated jitter. The LMH0036 recovers the serial
data-rate clock and optionally provides it as an
output. The LMH0036 has two differential serial data
outputs; the second output may be selected as a lowjitter, data-rate clock output. Controls and indicators
are: serial clock or second serial data output select,
manual rate select input, SD indicator output, lock
detect output, auto/manual data bypass, and output
mute. The serial data inputs, outputs, and serial datarate clock outputs are differential LVPECL
compatible. The CML serial data and serial data-rate
clock outputs are suitable for driving 100Ω
differentially terminated networks. The control logic
inputs and outputs are LVCMOS compatible.
The LMH0036 is powered from a single 3.3V supply.
Power dissipation is typically 360 mW. The device is
housed in a 48-pin WQFN package.
1
2
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
All trademarks are the property of their respective owners.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2008–2013, Texas Instruments Incorporated
LMH0036
SNLS254B – MARCH 2008 – REVISED APRIL 2013
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Typical Application
LMH0074
Equalizer
LMH0001
Cable Driver
LMH0036
Reclocker
Crosspoint
LMH0074
Equalizer
LMH0001
Cable Driver
LMH0074
Equalizer
Crosspoint
LMH0074
Equalizer
LMH0001
Cable Driver
LMH0036
Reclocker
LMH0074
Equalizer
LMH0001
Cable Driver
Crosspoint
LMH0074
Equalizer
LMH0074
Equalizer
Crosspoint
LMH0074
Equalizer
Block Diagram
SCO_EN
BYPASS/ AUTO BYPASS
SD
CONTROL LOGIC
LOCK DETECT
VCCO
BYPASS
50
50
XTAL IN/EXT CLK
XTAL OUT
LOOP FILTER 1
SCO/SDO2
VCO/PLL
SCO/SDO2
LOOP FILTER 2
O/P MUTE
VCCO
SDI0
SDI0
50
50
SDI1
SDI1
SDO
RETIMER/FIFO
SDO
SDI2
SDI2
SDI3
SDI3
SEL0
SEL1
2
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43
42
41
40
39
38
SCO_EN
LF1
44
VEE
LF2
45
VEE
NC
46
VEE
RSVD
47
VEE
SEL0
48
VEE
SEL1
Connection Diagram
37
SDI0
1
36
SD
SDI0
2
35
VCC
VCC
3
34
VCC
SDI1
4
33
SDO
SDI1
5
32
SDO
VCC
6
31
VCC
SDI2
7
30
VCC
SDI2
8
29
SCO/SDO2
VCC
9
28
SCO/SDO2
SDI3
10
27
VEE
SDI3
11
26
VEE
VCC
12
25
VEE
19
20
21
22
23
VEE
XTAL OUT
VEE
24
LOCK DET
18
VEE
BYPASS/
AUTOBYPASS
17
VEE
VCC
16
XTAL IN/
EXT CLK
15
VEE
14
O/P MUTE
13
VEE
LMH0036
(top view)
The exposed die attach pad is the primary negative electrical terminal for this device. It must be connected to the
negative power supply voltage.
Figure 1. 48-Pin WQFN
See Package Number RHS0048A
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PIN DESCRIPTIONS
Pin
Name
Description
1
SDI0
Data Input 0 True.
2
SDI0
Data Input 0 Complement.
4
SDI1
Data Input 1 True.
5
SDI1
Data Input 1 Complement
7
SDI2
Data Input 2 True.
8
SDI2
Data Input 2 Complement.
10
SDI3
Data Input 3 True.
11
SDI3
Data Input 3 Complement.
15
BYPASS/AUTO BYPASS
Bypass/Auto Bypass mode select. Bypasses reclocking when high. This pin has an internal
pulldown.
16
OUTPUT MUTE
Data and Clock Output Mute input. Mutes the output when low. This pin has an internal
pullup.
18
XTAL IN/EXT CLK
Crystal or External Oscillator input.
22
XTAL OUT
Crystal Oscillator output.
24
LOCK DETECT
PLL Lock Detect output (active high).
28
SCO/SDO2
Serial Clock or Serial Data Output 2 complement.
29
SCO/SDO2
Serial Clock or Serial Data Output 2 true.
32
SDO
Data Output complement.
33
SDO
Data Output true.
36
SD
SD indicator output. Output is high when locked to 270 Mbps.
37
SCO_EN
Serial Clock or Serial Data 2 Output select. Sets second output to output the clock when
high and the data when low. This pin has an internal pulldown.
43
LF1
Loop Filter.
44
LF2
Loop Filter.
45
NC
No Connect. Not bonded internally.
46
RSVD
Reserved. Do not connect or connect to ground.
47
SEL0
Data Input select input. This pin has an internal pulldown.
48
SEL1
Data Input select input. This pin has an internal pulldown.
3, 6, 12, 14,
30, 31, 34, 35 VCC
Positive power supply input.
DAP, 13, 17,
19, 20, 21,
23, 25, 26,
27, 38, 39,
40, 41, 42
Negative power supply input.
VEE
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
4
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ABSOLUTE MAXIMUM RATINGS (1) (2)
Supply Voltage (VCC–VEE)
4.0V
VEE−0.15V to VCC+0.15V
Logic Supply Voltage (Vi)
Logic Input Current (single input)
Vi = VEE−0.15V
−5 mA
Vi = VCC+0.15V
+5 mA
VEE−0.15V to VCC+0.15V
Logic Output Voltage (Vo)
Logic Output Source/Sink Current
±8 mA
VCC to VCC−2.0V
Serial Data Input Voltage (VSDI)
Serial Data Output Sink Current (ISDO)
24 mA
Package Thermal Resistance
θJA 48-pin WQFN
26.1°C/W
θJC 48-pin WQFN
1.9°C/W
−65°C to +150°C
Storage Temp. Range
Junction Temperature
+150°C
Lead Temperature (Soldering 4 Sec)
+260°C (Pb-free)
ESD Rating (HBM)
8 kV
ESD Rating (MM)
400V
ESD Rating (CDM)
(1)
(2)
1250V
“Absolute Maximum Ratings” are those parameter values beyond which the life and operation of the device cannot be ensured. The
stating herein of these maximums shall not be construed to imply that the device can or should be operated at or beyond these values.
DC ELECTRICAL CHARACTERISTICS and AC ELECTRICAL CHARACTERISTICS specify acceptable device operating conditions.
It is anticipated that this device will not be offered in a military qualified version. If Military/Aerospace specified devices are
required, please contact the Texas Instruments Sales Office/Distributors for availability and specifications.
RECOMMENDED OPERATING CONDITIONS
Supply Voltage (VCC–VEE)
3.3V ±5%
Logic Input Voltage
VEE to VCC
Differential Serial Input Voltage
800 mV ±10%
Serial Data or Clock Output Sink Current (ISO)
16 mA max.
−40°C to +85°C
Operating Free Air Temperature (TA)
DC ELECTRICAL CHARACTERISTICS
Over Supply Voltage and Operating Temperature ranges, unless otherwise specified. (1) (2)
Symbol
(2)
Conditions
Reference
Min
Logic level inputs
2
Typ
Max
Units
VCC
V
Input Voltage High Level
VIL
Input Voltage Low Level
0.8
V
IIH
Input Current High Level
VIH = VCC
47
65
µA
IIL
Input Current Low Level
VIL = VEE
−18
−25
µA
VEE
VOH
Output Voltage High Level IOH = −2 mA
VOL
Output Voltage Low Level
All logic level
outputs
IOL = +2 mA
VSDID
Serial Input Voltage,
Differential
VCMI
Input Common Mode
Voltage
VSDID = 200 mV
SDI
VSDOD
Serial Output Voltage,
Differential
100Ω differential load
SDO, SCO
VCMO
Output Common Mode
Voltage
100Ω differential load
SDO, SCO
Power Supply Current,
3.3V supply, Total
270 Mbps, NTSC color bar
pattern
ICC
(1)
Parameter
VIH
SDI
2
V
VEE + 0.6
V
200
1600
mVP-P
VEE+1.2
VCC−0.2
V
880
mVP-P
720
800
VCC −
VSDOD
109
V
mA
Current flow into device pins is defined as positive. Current flow out of device pins is defined as negative. All voltages are referenced to
VEE (equal to zero volts).
Typical values are stated for: VCC = +3.3V, TA = +25°C.
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AC ELECTRICAL CHARACTERISTICS
Over Supply Voltage and Operating Temperature ranges, unless otherwise specified. (1)
Symbol
Reference
BRSD
Serial Data Rate
SMPTE 259M (C)
SDI, SDO
Serial Input Jitter
Tolerance
270 Mbps (2) (3) (4)
SDI
TOLJIT
Serial Input Jitter
Tolerance
270 Mbps (2) (3) (5)
SDI
Serial Data Output Jitter
270 Mbps (3) (6)
SDO
Loop Bandwidth
270 Mbps,
0.6
UIP-P
0.02
0.08
UIP-P
300
kHz
270
MHz
2
SDO, SCO
Units
>6
SCO
Serial Clock Output
Alignment with respect to
Data Interval
Max
3
psRMS
40
60
%
45
55
%
15
ms
3
ns
(7) (8)
TACQ
Acquisition Time
See
tr, tf
Input rise/fall time
10%–90%
Logic inputs
tr, tf
Input rise/fall time
20%–80%
SDI
1500
ps
tr, tf
Output rise/fall time
10%–90%
Logic outputs
1.5
3
ns
tr, tf
Output rise/fall time
20%–80% (9)
SCO, SDO
90
130
ps
FREF
Reference Clock
Frequency
27
MHz
FTOL
Ref. Clock Freq.
Tolerance
±50
ppm
1.5
Typical values are stated for: VCC = +3.3V, TA = +25°C.
Peak-to-peak amplitude with sinusoidal modulation per SMPTE RP 184-1996 paragraph 4.1. The test data signal shall be color bars.
This parameter is ensured by characterization over voltage and temperature limits.
Refer to “A1” in Figure 1 of SMPTE RP 184-1996.
Refer to “A2” in Figure 1 of SMPTE RP 184-1996.
Serial Data Output Jitter is total output jitter with 0.2UIP-P input jitter.
Specification is ensured by design.
Measured from first SDI transition until Lock Detect (LD) output goes high (true).
RL = 100Ω differential.
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DEVICE DESCRIPTION
The LMH0036 SD SDI Reclocker with 4:1 Input Multiplexer is used in many types of digital video signal
processing equipment. The LMH0036 supports the SMPTE 259M (C) standard, with a corresponding serial data
rate of 270 Mbps. DVB-ASI data at 270 Mbps may also be retimed. The LMH0036 retimes the serial data stream
to suppress accumulated jitter. It provides two low-jitter, differential, serial data outputs. The second output may
be selected to output either serial data or a low-jitter serial data-rate clock. Controls and indicators are: serial
data-rate clock or second serial data output select, manual rate select input, SD indicator output, lock detect
output, auto/manual data bypass and output mute.
Serial data inputs are CML and LVPECL compatible. Serial data and data-rate clock outputs are differential CML
and produce LVPECL compatible levels. The output buffer design can drive AC or DC-coupled, terminated 100Ω
differential loads. The differential output level is 800 mVP-P ±10% into 100Ω AC or DC-coupled differential loads.
Logic inputs and outputs are LVCMOS compatible.
The device package is a 48–pin WQFN with an exposed die attach pad. The exposed die attach pad is
electrically connected to device ground (VEE) and is the primary negative electrical terminal for the device. This
terminal must be connected to the negative power supply or circuit ground.
Serial Data Inputs, Serial Data and Clock Outputs
SERIAL DATA INPUT AND OUTPUTS
The differential serial data inputs, SDI0-SDI3, accept 270 Mbps serial digital video data. The serial data inputs
are differential LVPECL compatible. These inputs are intended to be DC interfaced to devices such as the
LMH0074 adaptive cable equalizer. These inputs are not internally terminated or biased. The inputs may be ACcoupled if a suitable input bias voltage is provided.
The LMH0036 provides four independent, multiplexed data inputs. The active input channel is selected via the
SEL0 and SEL1 pins, as shown in Table 1. Figure 2 shows the equivalent input circuit for SDI[3:0] and SDI[3:0].
The LMH0036 has two, retimed, differential, serial data outputs, SDO and SCO/SDO2. These outputs provide
low jitter, differential, retimed data to devices such as the LMH0001 or LMH0002 cable driver. Output SCO/SDO2
is multiplexed and can provide either a second serial data output or a serial data-rate clock output. Figure 3
shows the equivalent output circuit for SDO, SDO, SCO/SDO2, and SCO/SDO2.
The SCO_EN input controls the operating mode for the SCO/SDO2 output. When the SCO_EN input is high the
SCO/SDO2 output provides a serial data-rate clock. When SCO_EN is low, the SCO/SDO2 output provides
retimed serial data.
Both differential serial data outputs, SDO and SCO/SDO2, are muted when the OUTPUT MUTE input is a logic
low level. SCO/SDO2 also mutes when the Bypass mode is activated when this output is operating as the serial
clock output. When muted, SDO and SDO (or SDO2 and SDO2) will assume opposite differential output levels.
The CML serial data outputs are differential LVPECL compatible. These outputs have internal 50Ω pull-ups and
are suitable for driving AC or DC-coupled, 100Ω center-tapped, AC grounded or 100Ω un-center-tapped,
differentially terminated networks.
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VCC
20 k:
1 pF
80 k:
VCC
2 k:
VCC
2 k:
SDI[3:0]
SDI[3:0]
Figure 2. Equivalent SDI Input Circuit (SDI[3:0], SDI[3:0])
VCC
VCC
VCC
50:
50:
SDO, SCO/SDO2
SDO, SCO/SDO2
Figure 3. Equivalent SDO Output Circuit (SDO, SDO, SCO/SDO2, SCO/SDO2)
SERIAL DATA CLOCK/SERIAL DATA 2 OUTPUT
The Serial Data Clock/Serial Data 2 Output is controlled by the SCO_EN input and provides either a second
retimed serial data output or a low jitter differential clock output appropriate to the serial data rate being
processed. When operating as a serial clock output, the rising edge of the clock will be positioned within the
corresponding serial data bit interval within 10% of the center of the data interval.
Differential output SCO/SDO2 functions as the second serial data output when the SCO_EN input is a logic-low
level. This output functions as the serial data-rate clock output when the SCO_EN input is a logic-high level. The
SCO_EN input has an internal pull-down device and the default state of SCO_EN is low (serial data output 2
enabled). SCO/SDO2 is muted when the OUTPUT MUTE input is a logic low level. When the Bypass mode is
activated and this output is functioning as a serial clock output, the output will also be muted. If an unsupported
data rate is used while in Auto Bypass mode with this output functioning as a serial clock output, the output is
invalid.
8
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Control Inputs and Indicator Outputs
SERIAL DATA INPUT SELECTOR
The Serial Data Input Selector (SEL [1:0]) allows the user to select the active input channel. Table 1 shows the
input selected for a given state of SEL [1:0].
Table 1. Data Input Select Codes
SEL [1:0] Code
Selected Input
00
SDI0
01
SDI1
10
SDI2
11
SDI3
LOCK DETECT
The Lock Detect (LD) output, when high, indicates that data is being received and the PLL is locked. LD may be
connected to the OUTPUT MUTE input to mute the data and clock outputs when no data signal is being
received. Note that when the Bypass/Auto Bypass input is set high, Lock Detect will remain low. See Table 2.
OUTPUT MUTE
The OUTPUT MUTE input, when low, mutes the serial data and clock outputs. It may be connected to Lock
Detect or externally driven to mute or un-mute the outputs. If OUTPUT MUTE is connected to LD, then the data
and clock outputs are muted when the PLL is not locked. This function overrides the Bypass function: see
Table 2. OUTPUT MUTE has an internal pull-up device to enable the output by default.
BYPASS/AUTO BYPASS
The Bypass/Auto Bypass input, when high, forces the device to output the data without reclocking it. When this
input is low, the device automatically bypasses the reclocking function when the device is in an unlocked
condition or the detected data rate is a rate which the device does not support. Note that when the Bypass/Auto
Bypass input is set high, Lock Detect will remain low. See Table 2. BYPASS/AUTO BYPASS has an internal pulldown device.
Table 2. Control Functionality
LOCK DETECT
OUTPUT MUTE
BYPASS/AUTO BYPASS
0
1
X
PLL unlocked, reclocker bypassed
DEVICE STATUS
1
1
0
PLL locked to supported data rate, reclocker not bypassed
X
0
X
Outputs muted
0
LOCK DETECT
X
Outputs muted
1
LOCK DETECT
0
PLL locked to supported data rate, reclocker not bypassed
SD
The SD output indicates that the LMH0036 is locked and processing SD data rates. It may be used to control
another device such as the LMH0002 cable driver. When this output is high it indicates that the data rate is 270
Mbps. The SD output is a registered function and is only valid when the PLL is locked and the Lock Detect
output is high. The SD output is undefined for a short time after lock detect assertion or de-assertion due to a
data change on the SDI input. See Figure 4 for a timing diagram showing the relationship between SDI, Lock
Detect, and SD.
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SDI
NO DATA
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270 MBPS DATA
NO DATA
T2
TACQ
270 MBPS DATA
NO DATA
TACQ
T2
Lock
Detect
T1
T1
T1
T1
SD
TACQ = Acquisition Time, defined in the AC Electrical Characteristics Table
T1 = Time from Lock Detect assertion or deassertion until SD output is valid, typically 37ns (one 27 MHz clock period)
T2 = Time from SDI input change until Lock Detect de-assertion, 1 ms maximum. SD output is not valid during this time.
Figure 4. SDI, Lock Detect, and SD Timing
SCO_EN
Input SCO_EN enables the SCO/SDO2 differential output to function either as a serial data-rate clock or second
serial data output. SCO/SDO2 functions as a serial data-rate clock when SCO_EN is high. This pin has an
internal pull-down device. The default state (low) enables the SCO/SDO2 output as a second serial data output.
CRYSTAL OR EXTERNAL CLOCK REFERENCE
The LMH0036 uses a 27 MHz crystal or external clock signal as a timing reference input. A 27 MHz parallel
resonant crystal and load network may be connected to the XTAL IN/EXT CLK and XTAL OUT pins.
Alternatively, a 27 MHz LVCMOS compatible clock signal may be input to XTAL IN/EXT CLK. Parameters for a
suitable crystal are given in Table 3.
Table 3. Crystal Parameters
Parameter
Value
Frequency
27 MHz
Frequency Stability
±100 ppm @ recommended drive level
Operating Mode
Fundamental mode, Parallel Resonant
Load Capacitance
20 pF
Shunt Capacitance
7 pF
Series Resistance
40Ω max.
Recommended Drive Level
100 µW
Maximum Drive Level
500 µW
Operating Temperature Range
−10°C to +60°C
10
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APPLICATION INFORMATION
Figure 5 shows a application circuit for the LMH0036.
SCO_EN
56 nF
SEL0
SEL1
44
43
LF1
42
VEE
41
VEE
40
VEE
39
VEE
38
VEE
37
SCO_EN
LF2
45
NC
RSVD
LOCK DET
VEE
VEE
VEE
36
35
34
33
32
SD
Data
Output
31
30
29
28
27
Clock Output or
2
nd
Data Output
26
25
DAP
24
VCC
22
23
SDI3
VCC
XTAL OUT
VEE
SDI3
VEE
Differential
Data Input 3
12
SCO/SDO2
VEE
21
11
100:
SCO/SDO2
20
10
VCC
SDI2
VCC
XTAL IN
VEE
9
Differential
Data Input 2
SDI2
19
8
LMH0036
17
18
100:
SDO
VCC
OP MUTE
VEE
7
SDI1
VCC
BP/ AUTO-BP
6
VCC
SDO
16
5
SD
VCC
SDI1
15
Differential
Data Input 1
4
VEE
100:
SDI0
VCC
VCC
3
SDI0
14
1
2
13
100:
Differential
Data Input 0
SEL0
SEL1
47
46
VCC
48
VCC
27 MHz
LOCK DET
BP/ AUTO-BP
OP MUTE
39 pF
39 pF
Figure 5. Application Circuit
BYPASS/AUTO BYPASS has an internal pulldown to enable Auto Bypass mode by default. This pin may be
pulled high to force the LMH0036 to bypass all data.
OUTPUT MUTE has an internal pullup to enable the outputs by default. This pin may be pulled low to mute the
outputs.
The XTAL IN/EXT CLK and XTAL OUT pins are shown with a 27 MHz crystal and the proper loading. The crystal
should match the parameters described in Table 3. Alternately, a 27MHz LVCMOS compatible clock signal may
be input to XTAL IN/EXT CLK.
The active high LOCK DETECT output provides an indication that proper data is being received and the PLL is
locked.
The SD output may be used to drive the SD/HD pin of an SDI cable driver (such as the LMH0002) in order to
properly set the cable driver’s edge rate for SMPTE compliance. It defaults to low when the LMH0036 is not
locked.
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SCO_EN has an internal pulldown to set the second output (SCO/SDO2) to output data. This pin may be pulled
high to set the second output as a serial clock.
The external loop filter capacitor (between LF1 and LF2) should be 56 nF. This is the only supported value; the
loop filter capacitor should not be changed.
SEL0 and SEL1 have internal pulldowns to select the SDI0 input by default.
The inputs are LVPECL compatible. The LMH0036 has a wide input common mode range and in most cases the
input should be DC coupled. For DC coupling, the inputs must be kept within the common mode range specified
in DC ELECTRICAL CHARACTERISTICS.
Figure 6 shows an example of a DC coupled interface between the LMH0074 cable equalizer and the LMH0036.
The LMH0074 output common mode voltage and voltage swing are within the range of the input common mode
voltage and voltage swing of the LMH0036. All that is required is a 100Ω differential termination as shown. The
resistor should be placed as close as possible to the LMH0036 input. If desired, this network may be terminated
with two 50Ω resisters and a center tap capacitor to ground in place of the single 100Ω resistor.
The outputs are LVPECL compatible. SDO is the primary data output and SCO/SDO2 is a second output that
may be set as the serial clock or a second data output. Both outputs are always active. The LMH0036 output
should be DC coupled to the input of the receiving device as long as the common mode ranges of both devices
are compatible.
Figure 7 shows an example of a DC coupled interface between the LMH0036 and LMH0001 cable driver. All that
is required is a 100Ω differential termination as shown. The resistor should be placed as close to the LMH0302
input as possible. If desired, this network may be terminated with two 50Ω resisters and a center tap capacitor to
ground in place of the single 100Ω resistor.
The LMH0036 has multiple ground connections, however; the primary ground connection is through the large
exposed DAP. The DAP must be connected to ground for proper operation of the LMH0036.
LMH0074
SD SDI Cable Equalizer
Coaxial Cable
1.0 PF
75:
SDI
SDO
1.0 PF
6.8 nH
SDI0
LMH0036
100:
SDI
SDI0
SDO
75:
37.4:
Figure 6. DC Input Interface
+3.3V
75:
LMH0001
SD SDI Cable Driver
75:
5.6 nH
75:
4.7 PF
Coaxial Cable
75:
4.7 PF
Coaxial Cable
SDI
SDO
SDO
LMH0036
100:
SDO
SDO
75:
SDI
75:
5.6 nH
Figure 7. DC Output Interface
12
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Copyright © 2008–2013, Texas Instruments Incorporated
Product Folder Links: LMH0036
LMH0036
www.ti.com
SNLS254B – MARCH 2008 – REVISED APRIL 2013
REVISION HISTORY
Changes from Revision A (April 2013) to Revision B
•
Page
Changed layout of National Data Sheet to TI format .......................................................................................................... 12
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Copyright © 2008–2013, Texas Instruments Incorporated
Product Folder Links: LMH0036
13
PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
(4/5)
(6)
LMH0036SQE/NOPB
ACTIVE
WQFN
RHS
48
250
RoHS & Green
SN
Level-3-260C-168 HR
-40 to 85
XL036
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of
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