LMH0070SQE/NOPB

LMH0040, LMH0050 LMH0070, LMH0340 www.ti.com SNLS271I – APRIL 2007 – REVISED APRIL 2013 3 Gbps, HD, SD, DVB-ASI SDI Serializer and Cable Driver With LVDS Interface Check for Samples: LMH0040, LMH0050, LMH0070, LMH0340 FEATURES DESCRIPTION • • • • • • • The LMH0340/0040/0070/0050 SDI Serializers are part of TI’s family of FPGA-Attach SER/DES products supporting 5-bit LVDS interfaces with FPGAs. An FPGA Host will format data with supplied IP such that the output of the LMH0340 is compliant with the requirements of DVB-ASI, SMPTE 259M-C, SMPTE 292M and SMPTE 424M standards. See Table 1 for details on which Standards are supported per device. 1 2 LVDS Interface to Host FPGA No External VCO or Clock Ref Required Integrated Variable Output Cable Driver 3.3V SMBus Configuration Interface Integrated TXCLK PLL Cleans Clock Noise Small 48-Pin WQFN Package Industrial Temperature range: -40°C to 85°C APPLICATIONS • SDI Unterfaces for: – Video Cameras – DVRs – Video Switchers – Video Editing Systems KEY SPECIFICATIONS • • • Output Compliant With SMPTE 424M, SMPTE 292M, SMPTE 259M-C and DVB-ASI (See Table 1) Typical Power Dissipation: 440 mW 30 ps Typical Output Jitter (HD, 3G) The interface between the SER (Serializer) and the FPGA consists of a 5 bit wide LVDS data bus, an LVDS clock and an SMBus interface. The LMH0340/0040/0070 SER devices include an integrated cable driver which is fully compliant with all of the SMPTE specifications listed above. The LMH0050 has a CML output driver that can drive a differential transmission line or interface to a cable driver. The FPGA-Attach SER/DES family is supported by a suite of IP which allows the design engineer to quickly develop video applications using the SER/DES products. The SER is packaged in a physically small 48-pin WQFN package. General Block Diagram SDA SCK SMB_CS LOCK SMBus Control GPIO[2:0] RESET DVB_ASI TX3 TX2 TX1 TX0 Parallel to Serial 5:1 Bypassable 8b10b Encode TX4 TXOUT SMPTE Cable Driver TXCLK LVDS Receivers PLL Clock Generation 1 2 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. All trademarks are the property of their respective owners. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright © 2007–2013, Texas Instruments Incorporated LMH0040, LMH0050 LMH0070, LMH0340 SNLS271I – APRIL 2007 – REVISED APRIL 2013 www.ti.com 37 TXCLK+ 38 TXCLK- 39 TX0+ 40 TX0- 41 TX1+ 42 TX1- 43 TX2+ 44 TX2- 45 TX3+ 46 TX3- 47 TX4+ 48 TX4- Connection Diagram VDD3V3 1 36 VDD3V3 RSVH_H 2 35 VDD2V5 GPIO_0 3 34 SMB_CS LMH0340, LMH0070, LMH0040, LMH0050, GPIO_1 4 RSVD_H 5 DVB_ASI 6 33 SCK 32 SDA TOP VIEW (not to scale) 31 LOCK GND 8 48-pin WQFN Package 29 GND GND 9 DAP = GND VDD2V5 7 30 RESET 28 VDDPLL GND 10 27 LF_CP GPIO_2 11 26 LF_REF GND 24 GND 23 GND 22 GND 21 DNC 20 DNC 19 VDD2V5 18 TXOUT- 17 TXOUT+ 16 VDD2V5 15 RSET 14 25 VDD2V5 GND 13 GND 12 Figure 1. Connection Diagram for 48L WQFN Package 2 Submit Documentation Feedback Copyright © 2007–2013, Texas Instruments Incorporated Product Folder Links: LMH0040 LMH0050 LMH0070 LMH0340 LMH0040, LMH0050 LMH0070, LMH0340 www.ti.com SNLS271I – APRIL 2007 – REVISED APRIL 2013 PIN DESCRIPTIONS Pin Name Type Description TX[4:0]+ TX[4:0]- Input, LVDS LVDS Data Input Pins Five channel wide DDR interface. Internal 100Ω termination. TXCLK+ TXCLK- Input, LVDS LVDS Clock Input Pins DDR Interface. Internal 100Ω termination. TXOUT+ Output, CML Serial Digital Interface Output Pin Non-Inverting Output TXOUT- Output, CML Serial Digital Interface Output Pin Inverting Output SDA I/O, LVCMOS SMBus Data I/O Pin SCK Input, LVCMOS SMBus Clock Input Pin SMB_CS Input, LVCMOS SMBus Chip Select Input Pin Device is selected when High. LVDS Input Interface Serial Output Interface SMBus Interface Control and Configuration Pins RESET Input, LVCMOS Reset Input Pin H = normal mode L = device in RESET LOCK Output, LVCMOS PLL LOCK Status Output H = unlock condition L = Device is Locked DVB_ASI Input, LVCMOS DVB_ASI Select Input H = DVB_ASI Mode enabled L = Normal Mode enabled GPIO[2:0] I/O, LVCMOS General Purpose Input / Output Software configurable I/O pins. RSVD_H Input, LVCMOS Configuration Input – Must tie High Pull High via 5 kΩ resistor to VDD3V3 RSET Input, analog Serial Output Amplitude Control Resistor connected from this pin to ground to set the signal amplitude. Nominally 8.06kΩ for 800mV output (SMPTE). LF_CP Input, analog Loop Filter Connection LF_REF Input, analog Loop Filter Reference Analog Inputs DNC Do Not Connect – Leave Open Power Supply and Ground VDD3V3 Power 3.3V Power Supply connection VDDPLL Power 3.3V PLL Power Supply connection VDD2V5 Power 2.5V Power Supply connection GND Ground Ground connection – The DAP (large center pad) is the primary GND connection for the device and must be connected to Ground along with the GND pins. Table 1. Feature Table Device SMPTE 424M Support (3G) SMPTE 292M Support (HD) SMPTE 259M Support (SD) DVB-ASI Support SMPTE compliant Cable Driver LMH0340 X X X X X X X X X X X X X X LMH0040 LMH0070 LMH0050 X Copyright © 2007–2013, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: LMH0040 LMH0050 LMH0070 LMH0340 3 LMH0040, LMH0050 LMH0070, LMH0340 SNLS271I – APRIL 2007 – REVISED APRIL 2013 www.ti.com These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates. Absolute Maximum Ratings (1) (2) −0.3V to +4.0V Supply Voltage (VDD3V3) −0.3V to +3.0V Supply Voltage (VDD2V5) LVCMOS input voltage −0.3V to (VDD3V3+0.3V) LVCMOS output voltage −0.3V to (VDD3V3+0.3V) SMBus I/O voltage -0.3V to +3.6V LVDS Input Voltage -0.3V to +3.6V Junction Temperature +150°C Storage Temperature −65° to 150°C Thermal Resistance— Junction to Ambient—θJA ESD Rating—Human Body Model, (1) (2) 25°C/W ≥±8kV 1.5 KΩ, 100 pF “Absolute Maximum Ratings” are limits beyond which the safety of the device cannot be ensured. It is not implied that the device will operate up to these limits. If Military/Aerospace specified devices are required, please contact the TI Sales Office/Distributors for availability and specifications. Recommended Operating Conditions Parameter Min Typ Max Units Supply Voltage (VDD3V3-GND) 3.135 3.3 3.465 V Supply Voltage (VDD2V5-GND) 2.375 2.5 2.625 V 100 mVP-P +85 °C Supply noise amplitude (10 Hz to 50 MHz) −40 Ambient Temperature +25 Case Temperature TXCLK input frequency 100 °C LMH0340 27 297 MHz LMH0040 27 149 MHz LMH0070 26.5 LMH0050 27 27 LVDS PCB board trace length (mismatch