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LMH0302
SNLS247H – APRIL 2007 – REVISED JUNE 2016
LMH0302 3-Gbps HD/SD SDI Cable Driver
1 Features
3 Description
•
•
•
•
•
•
•
•
•
•
The LMH0302 3-Gbps HD/SD SDI cable driver is
designed for use in ST 424, ST 292, ST 344, and ST
259 serial digital video applications. The LMH0302
drives 75-Ω transmission lines (Belden 1694A,
Belden 8281, or equivalent) at data rates up to
2.97 Gbps.
1
•
•
•
Supports ST 424 (3G), 292 (HD), and 259 (SD)
Data Rates up to 2.97 Gbps
Supports DVB-ASI at 270 Mbps
100-Ω Differential Input
75-Ω Single-Ended Outputs
Selectable Slew Rate
Output Driver Power-Down Control
Single 3.3-V Supply Operation
Industrial Temperature Range: −40°C to 85°C
Typical Power Consumption: 125 mW in SD Mode
and 165 mW in HD Mode
16-Pin WQFN Package
Footprint Compatible With the LMH0002SQ
Replaces the Gennum GS2978
The LMH0302 provides two selectable slew rates for
ST 259 and ST 424 or 292 compliance. The output
driver may be powered down through the output
driver enable pin.
The LMH0302 is powered from a single 3.3-V supply.
Power consumption is typically 125 mW in SD mode
and 165 mW in HD mode. The LMH0302 is available
in a 16-pin WQFN package.
Device Information(1)
PART NUMBER
LMH0302
2 Applications
•
•
•
PACKAGE
BODY SIZE (NOM)
WQFN (16)
4.00 mm × 4.00 mm
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
ST 424, ST 292, ST 344, and ST 259 Serial
Digital Interfaces
Digital Video Routers and Switches
Distribution Amplifiers
Typical Application
VCC
0.1 PF
75:
SD/HD
75:
ENABLE
6.8 nH
1.0 PF
4.7 PF
49.9:
ENABLE
SDI
SD/HD
LMH0302
Differential
Input
49.9:
1.0 PF
SDI
75:
SDO
SDO
75:
RREF
VCC
0.1 PF
4.7 PF
6.8 nH
750:
Copyright © 2016, Texas Instruments Incorporated
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
LMH0302
SNLS247H – APRIL 2007 – REVISED JUNE 2016
www.ti.com
Table of Contents
1
2
3
4
5
6
7
Features ..................................................................
Applications ...........................................................
Description .............................................................
Revision History.....................................................
Pin Configuration and Functions .........................
Specifications.........................................................
1
1
1
2
3
4
6.1
6.2
6.3
6.4
6.5
6.6
6.7
4
4
4
4
4
5
5
Absolute Maximum Ratings ......................................
ESD Ratings..............................................................
Recommended Operating Conditions.......................
Thermal Information .................................................
Electrical Characteristics – DC .................................
Electrical Characteristics – AC..................................
Typical Characteristics .............................................
Detailed Description .............................................. 6
7.1 Overview .................................................................. 6
7.2 Functional Block Diagram ........................................ 6
7.3 Feature Description .................................................. 6
7.4 Device Functional Modes.......................................... 7
8
Application and Implementation .......................... 8
8.1 Application Information ............................................ 8
8.2 Typical Application ................................................... 8
9 Power Supply Recommendations...................... 10
10 Layout................................................................... 10
10.1 Layout Guidelines ................................................ 10
10.2 Layout Example ................................................... 11
11 Device and Documentation Support ................. 12
11.1
11.2
11.3
11.4
Community Resources..........................................
Trademarks ...........................................................
Electrostatic Discharge Caution ............................
Glossary ................................................................
12
12
12
12
12 Mechanical, Packaging, and Orderable
Information ........................................................... 12
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision G (April 2013) to Revision H
•
Added ESD Ratings table, Feature Description section, Device Functional Modes, Application and Implementation
section, Power Supply Recommendations section, Layout section, Device and Documentation Support section, and
Mechanical, Packaging, and Orderable Information section .................................................................................................. 1
Changes from Revision F (April 2013) to Revision G
•
2
Page
Page
Changed layout of National Data Sheet to TI format ............................................................................................................. 1
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5 Pin Configuration and Functions
NC
NC
13
3
10
SD/HD
4
9
7
8
NC
RREF
14
SDO
NC
VEE
NC
11
GND
6
2
15
SDO
ENABLE
SDI
NC
12
5
1
NC
SDI
16
RUM Package
16-Pin WQFN
Top View
VCC
Not to scale
Pin Functions
PIN
NAME
NO.
TYPE (1)
DESCRIPTION
ENABLE
6
I
Output driver enable. When low, the SDO/SDO output driver is powered off. ENABLE has an
internal pullup. H = Normal operation. L = Output driver powered off.
EP
—
G
EP is the exposed pad at the bottom of the WQFN package. The exposed pad must be
connected to the ground plane through a via array. See Figure 6 for details.
NC
5, 7, 8, 13,
14, 15, 16
—
No connect. Not bonded internally.
RREF
4
I
Output driver level control. Connect a resistor to VCC to set output voltage swing.
SD/HD
10
I
Output slew rate control. Output rise/fall time complies with ST 424 or 292 when low and ST 259
when high.
SDI
1
I
Serial data true input.
SDI
2
I
Serial data complement input.
SDO
12
O
Serial data true output.
SDO
11
O
Serial data complement output.
VCC
9
P
Positive power supply (3.3 V).
VEE
3
G
Negative power supply (ground).
(1)
G = Ground, I = Input, O = Output, and P = Power
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6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted) (1)
MIN
MAX
UNIT
Supply voltage
–0.5
3.6
V
Input voltage (all inputs)
–0.3
VCC + 0.3
V
Output current
28
mA
Lead temperature, soldering (4 s)
260
°C
125
°C
150
°C
Junction temperature, TJ
Storage temperature, Tstg
(1)
–65
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
6.2 ESD Ratings
VALUE
V(ESD)
(1)
(2)
Electrostatic discharge
Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001 (1)
±4500
Charged-device model (CDM), per JEDEC specification JESD22-C101 (2)
±2000
Machine model (MM)
±250
UNIT
V
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
6.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
Supply voltage (VCC – VEE)
MIN
NOM
MAX
3.13
3.3
3.46
V
100
°C
85
°C
Operating junction temperature
Operating free air temperature, TA
–40
25
UNIT
6.4 Thermal Information
LMH0302
THERMAL METRIC
(1)
RUM (WQFN)
UNIT
16 PINS
RθJA
Junction-to-ambient thermal resistance
47.8
°C/W
RθJC(top)
Junction-to-case (top) thermal resistance
47.2
°C/W
RθJB
Junction-to-board thermal resistance
25.6
°C/W
ψJT
Junction-to-top characterization parameter
1.7
°C/W
ψJB
Junction-to-board characterization parameter
25.7
°C/W
RθJC(bot)
Junction-to-case (bottom) thermal resistance
14.5
°C/W
(1)
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report, SPRA953.
6.5 Electrical Characteristics – DC
Over supply voltage and operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
VCMIN
Input common mode voltage
SDI, SDI
VSDI
Input voltage swing
Differential, SDI, SDI
(1)
(2)
4
MIN
(1) (2)
TYP
MAX
1.1 + VSDI/2
VCC – VSDI/2
100
2200
UNIT
V
mVP−P
Current flow into device pins is defined as positive. Current flow out of device pins is defined as negative. All voltages are stated
referenced to VEE = 0 V.
Typical values are stated for VCC = 3.3 V and TA = 25°C.
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Electrical Characteristics – DC (continued)
Over supply voltage and operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
VCMOUT Output common mode voltage
SDO, SDO
VSDO
Output voltage swing
Single-ended, 75-Ω load,
RREF = 750 Ω 1%
VIH
Input voltage high level
SD/HD, ENABLE
VIL
Input voltage low level
SD/HD, ENABLE
ICC
Supply current
(1)(2)
MIN
TYP
MAX
UNIT
VCC – VSDO
720
V
800
880
mVP−P
2
V
0.8
SD/HD = 0, SDO/SDO enabled
50
59
SD/HD = 0, SDO/SDO disabled
26
33
SD/HD = 1, SDO/SDO enabled
38
48
SD/HD = 1, SDO/SDO disabled
15
22
V
mA
6.6 Electrical Characteristics – AC
Over supply voltage and operating free-air temperature range (unless otherwise noted)
PARAMETER
DRSDI
Input data rate
Tjit
Additive jitter
TEST CONDITIONS
(1)
MIN
tr,tf
Output rise time, fall time
TMATCH
Mismatch in rise time, fall time
2.97 Gbps, SDO, SDO
20
1.485 Gbps, SDO, SDO
18
270 Mbps, SDO, SDO
15
SD/HD = 0, 20% – 80%, SDO, SDO
90
SD/HD = 1, 20% – 80%, SDO, SDO
400
TOS
Output overshoot
RLSDO
(1)
(2)
(3)
Duty cycle distortion
UNIT
Mbps
psP-P
130
800
30
SD/HD = 1, SDO, SDO
50
SD/HD = 0, 1.485 Gbps, SDO, SDO
ps
ps
27
(2)
30
SD/HD = 1, SDO, SDO (2)
100
SD/HD = 0, SDO, SDO (2)
10%
SD/HD = 1, SDO, SDO (2)
Output return loss
MAX
2970
SD/HD = 0, SDO, SDO
SD/HD = 0, 2.97 Gbps, SDO, SDO (2)
TDCD
TYP
SDI, SDI
ps
8%
5 MHz to 1.5 GHz, SDO, SDO
(3)
15
1.5 GHz to 3.0 GHz, SDO, SDO (3)
10
dB
Typical values are stated for VCC = 3.3 V and TA = 25°C.
Specification is ensured by characterization.
Output return loss is dependent on board design. The LMH0302 meets this specification on the SD302 evaluation board.
6.7 Typical Characteristics
172 mV/DIV
172 mV/DIV
Typical device characteristics at TA = 25°C and VCC = 3.3 V (unless otherwise noted)
200 ps/DIV
100 ps/DIV
Figure 1. SDO PRBS10 at 2.97 Gbps
Figure 2. SDO PRBS10 at 1.485 Gbps
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7 Detailed Description
7.1 Overview
The LMH0302 ST 424, ST292, ST259 serial digital cable driver is a monolithic, high-speed cable driver designed
for use in serial digital video data transmission applications. The LMH0302 drives 75-Ω transmission lines
(Belden 8281, 1694A, Canare L-5CFB, or equivalent) at data rates up to 2.97 Gbps.
The LMH0302 provides two selectable slew rates for ST 259 and ST 292/424 compliance. The output voltage
swing is adjustable through a single external resistor ( RREF).
The LMH0302 is powered from a single 3.3-V supply. Power consumption is typically 125 mW in SD mode and
165 mW in HD mode. The LMH0302 is available in a 16-pin WQFN package.
7.2 Functional Block Diagram
SDO
SDO
SDI
+
+
-
-
SDI
RREF
Bias Generator
VCC
VEE
SD/HD
Enable
Control
Copyright © 2016, Texas Instruments Incorporated
7.3 Feature Description
The LMH0302 data path consists of several key blocks:
•
•
•
•
Input interfacing
Output interfacing
Output slew rate control
Output enable
7.3.1 Input Interfacing
The LMH0302 accepts either differential or single-ended input. The inputs are self-biased, allowing for simple AC
or DC coupling. DC-coupled inputs must be kept within the specified common-mode range.
7.3.2 Output Interfacing
The LMH0302 uses current mode outputs. Single-ended output levels are 800 mVP-P into 75-Ω AC-coupled
coaxial cable with an RREF resistor of 750 Ω. The RREF resistor is connected between the RREF pin and VCC.
6
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Feature Description (continued)
The RREF resistor must be placed as close as possible to the RREF pin. In addition, the copper in the plane layers
below the RREF network must be removed to minimize parasitic capacitance.
7.3.3 Output Slew Rate Control
The LMH0302 output rise and fall times are selectable for either ST 259, ST 424, or 292 compliance through the
SD/HD pin. For slower rise and fall times, or ST 259 compliance, SD/HD is set high. For faster rise and fall times,
ST 424 and ST 292 compliance, SD/HD is set low.
7.3.4 Output Enable
The SDO/SDO output driver are enabled or disabled with the ENABLE pin. When set low, the output driver is
powered off. ENABLE has an internal pullup.
7.4 Device Functional Modes
The LMH0302 features are programmed using pin mode only.
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8 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
8.1 Application Information
The LMH0302 is a single-channel SDI cable driver that supports different application spaces. The following
sections describe the typical use cases and common implementation practices.
8.1.1 General Guidance for All Applications
The SMPTE specifications define the use of AC-coupling capacitors for transporting uncompressed serial data
streams with heavy low-frequency content. This specification requires the use of a 4.7-µF AC-coupling capacitor
to avoid low frequency DC wander. The 75-Ω signal is also required to meet certain rise and fall timing to
facilitate highest eye opening for the receiving device.
SMPTE specifies the requirements for the Serial Digital Interface to transport digital video at SD, HD, 3 Gbps,
and higher data rates over coaxial cables. One of the requirements is meeting the required return loss. This
requirement specifies how closely the port resembles 75-Ω impedance across a specified frequency band.
Output return loss is dependent on board design. The LMH0302 supports these requirements.
8.2 Typical Application
VCC
0.1 PF
75:
SD/HD
75:
ENABLE
6.8 nH
1.0 PF
4.7 PF
49.9:
ENABLE
SDI
SD/HD
LMH0302
Differential
Input
49.9:
1.0 PF
SDI
75:
SDO
SDO
75:
RREF
VCC
0.1 PF
4.7 PF
6.8 nH
750:
Copyright © 2016, Texas Instruments Incorporated
Figure 3. Application Circuit
8
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Typical Application (continued)
8.2.1 Design Requirements
For the LMH0302 design example, Table 1 lists the design parameters.
Table 1. LMH0302 Design Parameters
PARAMETER
REQUIREMENT
Input termination
Required; 49.9 Ω are recommended (see Figure 3).
Output AC-coupling capacitors
Required; both SDO and SDO require AC-coupling capacitors. SDO AC-coupling capacitors
are expected to be 4.7 µF to comply with SMPTE wander requirement.
DC power supply coupling capacitors
To minimize power supply noise, place 0.1-µF capacitor as close to the device VCC pin as
possible.
Distance from device to BNC
Keep this distance as short as possible.
High speed SDI and SDI trace impedance
Design differential trace impedance of SDI and SDI with 100 Ω.
High speed SDO and SDO trace impedance
Single-ended trace impedance for SDO and SDO with 75 Ω.
8.2.2 Detailed Design Procedure
The following design procedure is recommended:
1.
2.
3.
4.
5.
Select a suitable power supply voltage for the LMH0302. It can be powered from a single 3.3-V supply.
Check that the power supply meets the DC requirements in Electrical Characteristics – DC.
Select the proper pull-high or pull-low for SD/HD to set the slew rate.
Select proper pull-high or pull-low for ENABLE to enable or disable the output driver.
Choose a high-quality 75-Ω BNC that is capable to support 2.97-Gbps applications. Consult a BNC supplier
regarding insertion loss, impedance specifications, and recommended BNC footprint for meeting SMPTE
return loss requirements.
6. Choose small 0402 surface-mount ceramic capacitors for the AC-coupling and bypass capacitors.
7. Use proper footprint for BNC and AC-coupling capacitors. Anti-pads are commonly used in power and
ground planes under these landing pads to achieve optimum return loss.
8.2.3 Application Curves
920
172 mV/DIV
SDO Amplitude (mVp-p)
900
880
860
840
820
800
780
760
660
1 ns/DIV
680
700
720
740
760
RREF Resistance (Ÿ)
Figure 4. SDO PRBS10 at 270 Mbps
780
C001
Figure 5. SDO Amplitude vs RREF Resistance
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9 Power Supply Recommendations
Follow these general guidelines when designing the power supply:
1. The power supply must be designed to provide the recommended operating conditions (see Recommended
Operating Conditions).
2. The maximum current draw for the LMH0302 is provided in Electrical Characteristics – DC. This figure can
be used to calculate the maximum current the supply must provide.
3. The LMH0302 does not require any special power supply filtering, provided the recommended operating
conditions are met. Only standard supply coupling is required.
10 Layout
10.1 Layout Guidelines
TI recommends the following layout guidelines for the LMH0302:
1. The RREF 1% tolerance resistor must be placed as close as possible to the RREF pin. In addition, the copper
in the plane layers below the RREF network must be removed to minimize parasitic capacitance.
2. Choose a suitable board stackup that supports 75-Ω single-ended trace and 100-Ω differential trace routing
on the top layer of the board. This is typically done with a Layer 2 ground plane reference for the 100-Ω
differential traces and a second ground plane at Layer 3 reference for the 75-Ω single-ended traces.
3. Use single-ended uncoupled trace designed with 75-Ω impedance for signal routing to SDO and SDO. The
trace width is typically 8-10 mil reference to a ground plane at Layer 3.
4. Use coupled differential traces with 100-Ω impedance for signal routing to SDI and SDI. They are usually
5-mil to 8-mil trace width reference to a ground plane at Layer 2.
5. Place anti-pad (ground relief) on the power and ground planes directly under the 4.7-μF AC-coupling
capacitor, return loss network, and IC landing pads to minimize parasitic capacitance. The size of the antipad depends on the board stackup and can be determined by a 3-dimension electromagnetic simulation tool.
6. Use a well-designed BNC footprint to ensure the BNC’s signal landing pad achieves 75-Ω characteristic
impedance. BNC suppliers usually provide recommendations on BNC footprint for best results.
7. Keep trace length short between the BNC and SDO. The trace routing for SDO and SDO must be
symmetrical, approximately equal lengths, and equal loading.
8. The exposed pad EP of the package must be connected to the ground plane through an array of vias. These
vias are solder-masked to avoid solder flow into the plated-through holes during the board manufacturing
process.
9. Connect each supply pin (VCC and VEE) to the power or ground planes with a short via. The via is usually
placed tangent to the landing pads of the supply pins with the shortest trace possible.
10. Power-supply bypass capacitors must be placed close to the supply pins.
10
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10.2 Layout Example
Figure 6 shows an example of proper layout requirements for the LMH0302.
BNC foot print
Anti-pad
GND stitch
> 5W
75
Anti-pad:
100
coupled trace
49.9
W=8
S = 10
W=8
6.8
0.1 µF
nH
VCC
4.7 µF
Zo = 75
0.1 µF
Solder
Paste
mask
75
4.7 µF
75
6.8
n
H
W = 10
> 5W
VCC
0.1 µF
750
VCC
EP
GND
GND
Figure 6. LMH0302 High-Speed Traces Layout Example
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11 Device and Documentation Support
11.1 Community Resources
The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.
11.2 Trademarks
E2E is a trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
11.3 Electrostatic Discharge Caution
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
11.4 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
12 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
12
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PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
(4/5)
(6)
LMH0302SQ/NOPB
ACTIVE
WQFN
RUM
16
1000
RoHS & Green
SN
Level-3-260C-168 HR
-40 to 85
L0302
LMH0302SQE/NOPB
ACTIVE
WQFN
RUM
16
250
RoHS & Green
SN
Level-3-260C-168 HR
-40 to 85
L0302
LMH0302SQX/NOPB
ACTIVE
WQFN
RUM
16
4500
RoHS & Green
SN
Level-3-260C-168 HR
-40 to 85
L0302
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of