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LMH0303
SNLS285H – APRIL 2008 – REVISED MAY 2016
LMH0303 3-Gbps HD/SD SDI Cable Driver With Cable Detect
1 Features
3 Description
•
•
•
•
•
•
•
The LMH0303 device is designed for use in ST 424,
ST 292, ST 344, and ST 259 serial digital video
applications. The LMH0303 drives 75-Ω transmission
lines (Belden 1694A, Belden 8281, or equivalent) at
data rates up to 2.97 Gbps.
1
•
•
•
•
•
•
•
•
Supports ST 424 (3G), 292 (HD), and 259 (SD)
Data Rates up to 2.97 Gbps
Supports DVB-ASI at 270 Mbps
Cable Detect on Output
Loss of Signal Detect at Input
Output Driver Power-Down Control
Typical Power Consumption: 130 mW in SD Mode
and 155 mW in HD Mode
Typical Power Consumption of the Power-Save
Mode: 4 mW
Single 3.3-V Supply Operation
75-Ω Single-Ended Outputs
100-Ω Differential Input
Selectable Slew Rate
Industrial Temperature Range: −40°C to 85°C
16-Pin WQFN Package
Footprint Compatible With the LMH0302
2 Applications
•
•
•
ST 424, ST 292, ST 344, and ST 259 Serial
Digital Interfaces
Digital Video Routers and Switches
Distribution Amplifiers
The LMH0303 includes intelligent sensing capabilities
to improve system diagnostics. The cable detect
feature senses near-end termination to determine if a
cable is correctly attached to the output BNC. Input
loss of signal (LOS) detects the presence of a valid
signal at the input of the cable driver. These sensing
features may be used to alert the user of a system
fault and activate a deep power-save mode, reducing
the power consumption of the cable driver to 4 mW.
These features are accessible through an SMBus
interface.
The LMH0303 provides two selectable slew rates for
ST 259 and ST 424 or 292. The output amplitude is
adjustable ±10% in 5-mV steps through the SMBus.
The LMH0303 is powered from a single 3.3-V supply.
Power consumption is typically 130 mW in SD mode
and 155 mW in HD mode. The LMH0303 is available
in a 16-pin WQFN package.
Device Information(1)
PART NUMBER
LMH0303
PACKAGE
WQFN (16)
BODY SIZE (NOM)
4.00 mm × 4.00 mm
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
Typical Application Schematic
SDI In
SD/HD
LMH0356
3G/HD/SD
SDI Reclocker
ENABLE
SDI
Clock or
Second
Data Output
SDI Out
LMH0303
3G/HD/SD
SDI Cable Driver
FAULT
SDA SCL
SMBus
Data
SMBus
Clock
Microcontroller
or
FPGA
Copyright © 2016, Texas Instruments Incorporated
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
LMH0303
SNLS285H – APRIL 2008 – REVISED MAY 2016
www.ti.com
Table of Contents
1
2
3
4
5
6
7
Features ..................................................................
Applications ...........................................................
Description .............................................................
Revision History.....................................................
Pin Configuration and Functions .........................
Specifications.........................................................
1
1
1
2
3
5
6.1
6.2
6.3
6.4
6.5
6.6
6.7
6.8
5
5
5
5
6
6
7
7
Absolute Maximum Ratings ......................................
ESD Ratings..............................................................
Recommended Operating Conditions.......................
Thermal Information ..................................................
Electrical Characteristics – DC .................................
Electrical Characteristics – AC..................................
Timing Requirements ................................................
Typical Characteristics ..............................................
Detailed Description .............................................. 8
7.1 Overview ................................................................... 8
7.2 Functional Block Diagram ......................................... 8
7.3 Feature Description................................................... 8
7.4 Device Functional Modes........................................ 11
7.5 Register Maps ......................................................... 12
8
Application and Implementation ........................ 16
8.1 Application Information............................................ 16
8.2 Typical Application .................................................. 17
9 Power Supply Recommendations...................... 18
10 Layout................................................................... 19
10.1 Layout Guidelines ................................................. 19
10.2 Layout Example .................................................... 19
11 Device and Documentation Support ................. 21
11.1
11.2
11.3
11.4
Community Resources..........................................
Trademarks ...........................................................
Electrostatic Discharge Caution ............................
Glossary ................................................................
21
21
21
21
12 Mechanical, Packaging, and Orderable
Information ........................................................... 21
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision G (April 2013) to Revision H
•
Added ESD Ratings table, Feature Description section, Device Functional Modes, Application and Implementation
section, Power Supply Recommendations section, Layout section, Device and Documentation Support section, and
Mechanical, Packaging, and Orderable Information section. ................................................................................................. 1
Changes from Revision F (April 2013) to Revision G
•
2
Page
Page
Changed layout of National Data Sheet to TI format ........................................................................................................... 15
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SNLS285H – APRIL 2008 – REVISED MAY 2016
5 Pin Configuration and Functions
RUM Package
16-Pin WQFN
Top View
Pin Functions
PIN
NO.
NAME
TYPE (1)
DESCRIPTION
1
SDI
I
Serial data true input.
2
SDI
I
Serial data complement input.
3
VEE
I
Negative power supply (ground)
4
RREF
I
Bias resistor. Connect a 750-Ω resistor to VCC.
5
RSTI
I
Reset input. RSTI has an internal pullup, LVCMOS, 2-state logic.
H = Normal operation.
L = Device reset. The device operates with default register settings. Forcing RSTI low
also forces RSTO low.
6
ENABLE
I
Output driver enable, LVCMOS, 2-state logic. ENABLE has an internal pullup.
H = Normal operation.
L = Output driver powered off.
7
SDA
I/O
8
SCL
I
SMBus clock input, LVCMOS, 2-state logic, open drain. SCL is input only. This pin
requires an external pullup.
9
VCC
P
Positive power supply (3.3 V)
10
SD/HD
I
Output slew rate control, LVCMOS, 2-state logic. SD/HD has an internal pulldown.
H = Output rise or fall time complies with ST 259.
L = Output rise or fall time complies with ST 424 or 292.
11
SDO
O
Serial data complement output.
(1)
SMBus bidirectional data pin, LVCMOS, 2-state logic, open drain. When functioning as
an output, it is open drain. This pin requires an external pullup.
G = Ground, I = Input, O = Output, and P = Power
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Pin Functions (continued)
PIN
NO.
NAME
TYPE (1)
DESCRIPTION
12
SDO
O
Serial data true output.
13
FAULT
O
Fault open drain output flag, LVCMOS, 2-state logic, open drain. Requires external
pullup resistor and may be wire ORed with multiple cable drivers.
H = Normal operation.
L = Loss of signal or termination fault for any output.
14
NC
—
No connect. Not bonded internally.
15
NC
—
No connect. Not bonded internally.
16
RSTO
O
Reset output, LVCMOS, 2-state logic. RSTO is automatically set to 1 when register 0 is
written. It can be reset back to zero by forcing RSTI to zero to reset the device. Used to
daisy chain multiple cable drivers on the same SMBus.
—
EP
G
EP is the exposed pad at the bottom of the WQFN package. The exposed pad must be
connected to the ground plane through a via array.
4
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6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted) (1)
MIN
MAX
UNIT
Supply voltage
–0.5
3.6
V
Input voltage (all inputs)
–0.3
VCC + 0.3
V
Output current
28
mA
Lead temperature (soldering, 4 s)
260
°C
125
°C
150
°C
Junction temperature
Storage temperature, Tstg
(1)
–65
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
6.2 ESD Ratings
VALUE
V(ESD)
(1)
(2)
Electrostatic
discharge
Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001 (1)
±8000
Charged-device model (CDM), per JEDEC specification JESD22-C101 (2)
±2000
Machine model (MM)
±400
UNIT
V
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. Pins listed as
±8000 V may actually have higher performance.
JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process. Pins listed as
±2000 V may actually have higher performance.
6.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
Supply voltage (VCC – VEE)
MIN
NOM
MAX
UNIT
3.13
3.3
3.46
V
100
°C
–40
25
85
°C
Operating junction temperature
Operating free air temperature, TA
6.4 Thermal Information
LMH0303
THERMAL METRIC (1)
RUM (WQFN)
UNIT
16 PINS
RθJA
Junction-to-ambient thermal resistance
40.7
°C/W
RθJC(top)
Junction-to-case (top) thermal resistance
39.5
°C/W
RθJB
Junction-to-board thermal resistance
18.5
°C/W
ψJT
Junction-to-top characterization parameter
0.6
°C/W
ψJB
Junction-to-board characterization parameter
18.5
°C/W
RθJC(bot)
Junction-to-case (bottom) thermal resistance
8
°C/W
(1)
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report, SPRA953.
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6.5 Electrical Characteristics – DC
Over supply voltage and operating temperature ranges (unless otherwise noted) (1) (2)
PARAMETER
TEST CONDITIONS
VCMIN
Input common mode voltage
SDI, SDI
VSDI
Input voltage swing
Differential (SDI, SDI)
VCMOUT
Output common mode voltage
SDO, SDO
VSDO
Output voltage swing (SDO, SDO)
Single-ended, 75-Ω load,
RREF = 750 Ω 1%
VIH
Input voltage high level
SD/HD, ENABLE
VIL
Input voltage low level
SD/HD, ENABLE
ICC
Supply current
MIN
TYP
MAX
1.6 + VSDI/2
VCC – VSDI/2
100
2200
UNIT
V
mVP−P
VCC – VSDO
720
V
800
880
mVP-P
2
V
0.8
SD/HD = 0,
SDO/SDO enabled
47
57
SD/HD = 1,
SDO/SDO enabled
40
47
SDO/SDO disabled
1.3
2.5
V
mA
SMBUS DC SPECIFICATIONS
VSIL
Data, clock input low voltage
VSIH
Data, clock input high voltage
ISPULLUP
Current through pullup resistor
or current source
VSDD
Nominal bus voltage
2.1
VOL = 0.4 V
(3)
ISLEAKB
Input leakage per bus segment
ISLEAKP
Input leakage per pin
CSI
Capacitance for SDA and SCL (3) (4)
(1)
(2)
(3)
(4)
0.8
V
VSDD
V
4
mA
3
3.6
V
–200
200
µA
–10
10
µA
10
pF
Current flow into device pins is defined as positive. Current flow out of device pins is defined as negative. All voltages are stated
referenced to VEE = 0 V.
Typical values are stated for VCC = 3.3 V and TA = 25°C.
Recommended value — Parameter not tested.
Recommended maximum capacitive load per bus segment is 400 pF.
6.6 Electrical Characteristics – AC
Over supply voltage and operating temperature ranges (unless otherwise noted) (1)
PARAMETER
DRSDI
Input data rate
Tjit
Additive output jitter
tr,tf
Output rise time and fall time
TMATCH
Mismatch in rise or fall time
TDCD
TOS
Output overshoot
RLSDO
(1)
(2)
(3)
6
Duty cycle distortion
Output return loss
TEST CONDITIONS
MIN
TYP
2.97 Gbps
20
1.485 Gbps
18
270 Mbps
15
SD/HD = 0, 20% to 80%
SD/HD = 1, 20% to 80%
90
400
MAX
UNIT
2970
Mbps
psP-P
130
800
SD/HD = 0
30
SD/HD = 1
50
SD/HD = 0, 2.97 Gbps (2)
27
SD/HD = 0, 1.485 Gbps (2)
30
SD/HD = 1 (2)
100
SD/HD = 0 (2)
10%
SD/HD = 1 (2)
ps
ps
ps
8%
5 MHz to 1.5 GHz (3)
15
1.5 GHz to 3 GHz (3)
10
dB
Typical values are stated for VCC = 3.3 V and TA = 25°C.
Specification is ensured by characterization.
Output return loss is dependent on board design. The LMH0303 meets this specification on the SD303EVK evaluation board.
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6.7 Timing Requirements
MIN
NOM
MAX
UNIT
100
kHz
fSMB
Bus operating frequency
10
tBUF
Bus free time between stop and start condition
4.7
µs
tHD:STA
Hold time after (repeated) start condition.
After this period, the first clock is generated; at ISPULLUP = MAX
4
µs
tSU:STA
Repeated start condition setup time
4.7
µs
tSU:STO
Stop condition setup time
4
µs
tHD:DAT
Data hold time
300
ns
tSU:DAT
Data setup time
250
ns
tLOW
Clock low period
4.7
µs
tHIGH
Clock high period
50
µs
tF
Clock or data fall time
300
ns
tR
Clock or data rise time
1000
ns
tPOR
Time in which device must be operational after power on
500
ms
4
tLOW
tHIGH
tR
SCL
tHD:STA
tBUF
tHD:DAT
tF
tSU:STA
tSU:DAT
tSU:STO
SDA
SP
ST
SP
ST
Figure 1. SMBus Timing Parameters
6.8 Typical Characteristics
187 mV/DIV
187 mV/DIV
Typical device characteristics at TA = 25°C and VCC = 3.3 V (unless otherwise noted)
200 ps/DIV
100 ps/DIV
Figure 2. SDO PRBS10 at 2.97 Gbps
Figure 3. SDO PRBS10 at 1.485 Gbps
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7 Detailed Description
7.1 Overview
The LMH0303 ST 424, ST292, ST259 serial digital cable driver is a monolithic, high-speed cable driver designed
for use in serial digital video data transmission applications. The LMH0303 drives 75-Ω transmission lines
(Belden 8281, 1694A, Canare L-5CFB, or equivalent) at data rates up to 2.97 Gbps.
The LMH0303 provides two selectable slew rates for ST 259 and ST 292/424 compliance. The output voltage
swing is adjustable through a single external resistor ( RREF) or SMBus interface in 5-mV steps.
The LMH0303 cable detect feature senses near-end termination to determine if a cable is attached to the output
BNC. The LMH0303 input loss of signal (LOS) detects the presence of a valid signal at the 100-Ω differential
input of the cable driver. These features can be used to activate power-save mode. These features are
accessible through an SMBus interface.
The LMH0303 is powered from a single 3.3 V supply. Power consumption is typically 130 mW in SD mode and
155 mW in HD mode. The LMH0303 is available in a 16-pin WQFN package.
7.2 Functional Block Diagram
SDO
SDO
Fault
Detect
LOS
SDI
+
+
SDI
-
-
RREF
Bias Generator
VEE
VCC
SCL
SDA
RSTO
RSTI
SD/HD
Enable
Control
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7.3 Feature Description
The LMH0303 data path consists of several key blocks as shown in the Functional Block Diagram. These key
circuits are:
•
•
•
•
•
•
8
Loss-of-signal detector
Input interfacing
Output interfacing
Output slew rate control
Cable fault detection
SMBus configuration
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Feature Description (continued)
7.3.1 Loss-of-Signal Detector
The LMH0303 detects when the input signal does not have a video-like pattern. Self-oscillation and low levels of
noise are rejected. This loss-of-signal detector allows a very sensitive input stage that is robust against coupled
noise without any degradation of jitter performance. Through the SMBus, the loss-of-signal detector can either
add an input offset or mute the outputs. An offset is added by default. Additionally, the loss-of-signal detector can
be linked to the ENABLE functionality so that when the LOS goes low, ENABLE also goes low.
7.3.2 Input Interfacing
The LMH0303 accepts either differential or single-ended input. For single-ended operation, the unused input
must be properly terminated.
7.3.3 Output Interfacing
The LMH0303 uses current mode outputs. Single-ended output levels are 800 mVP-P into 75-Ω AC-coupled
coaxial cable with an RREF resistor value of 750 Ω. The RREF resistor is connected between the RREF pin and
VCC.
The RREF resistor should be placed as close as possible to the RREF pin. In addition, the copper in the plane
layers below the RREF network should be removed to minimize parasitic capacitance.
7.3.4 Output Slew Rate Control
The LMH0303 output rise and fall times are selectable for either ST259 or ST 424 or 292 compliance through the
SD/HD pin. For slower rise and fall times, or ST 259 compliance, SD/HD is set high. For faster rise and fall times,
or ST 424 and ST 292 compliance, SD/HD is set low. SD/HD may also be controlled using the SMBus, provided
the SD/HD pin is held low. SD/HD has an internal pulldown.
7.3.5 Cable Fault Detection
The LMH0303 termination fault detection purpose is to provide an indication when no cable is connected to the
output (near end). The termination fault detection works by detecting reflections on the output. The device
measures the peak-to-peak output voltage. The output amplitude is normally 800 mVp-p. No termination results in
2x the output voltage (1600 mVp-p) due to the 100% reflection.
When a video signal (or AC test signal) is present on SDI, the device senses the SDO and SDO amplitudes. If
the output is not properly terminated (through a terminated cable or local termination), the amplitude will be
higher than expected, and the termination fault signal is asserted. The termination fault signal is deasserted
when the proper termination is applied. This feature allows the system designer the flexibility to react to cable
attachment and removal. Note that a long length of cable will look like a proper termination at the device output.
The cable driver must be enabled for the termination detection to operate. If the termination fault will be used to
power down the LMH0303, then periodic polling (enabling) is recommended to monitor the output termination.
For example, when a fault condition is triggered, ENABLE can be driven low to power down the device. The
LMH0303 should be re-enabled periodically to check the status of the output termination. The LMH0303 must be
powered on for at least 4 ms for termination fault detection to work.
7.3.6 SMBus Interface
The System Management Bus (SMBus) is a two-wire interface designed for the communication between various
system component chips. By accessing the control functions of the circuit through the SMBus, pin count is kept
to a minimum while allowing a maximum amount of versatility. The LMH0303 has several internal configuration
registers which may be accessed through the SMBus.
The 7-bit default address for the LMH0303 is 0x17. The LSB is set to 0'b for a WRITE and 1'b for a READ, so
the 8-bit default address for a WRITE is 0x2E and the 8-bit default address for a READ is 0x2F. The SMBus
address may be dynamically changed.
In applications where there might be several LMH0303s, the SDA, SCL, and FAULT pins can be shared. The
SCL, SDA, and FAULT pins are open drain and require external pullup resistors. Multiple LMH0303s may have
the FAULT pin wire ORed. This signal becomes active when either loss of signal is detected or any termination
faults are detected. The registers may be read in order to determine the cause. Additionally, each signal can be
masked from the FAULT pin.
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Feature Description (continued)
7.3.6.1 Transfer of Data through the SMBus
During normal operation the data on SDA must be stable during the time when SCL is High.
There are three unique states for the SMBus:
START: A High-to-Low transition on SDA while SCL is High indicates a message START condition.
STOP: A Low-to-High transition on SDA while SCL is High indicates a message STOP condition.
IDLE: If SCL and SDA are both High for a time exceeding tBUF from the last detected STOP condition or if they
are High for a total exceeding the maximum specification for tHIGH, then the bus will transfer to the IDLE state.
7.3.6.2 SMBus Transactions
The device supports WRITE and READ transactions. See Table 1 for register address, type (Read/Write, Read
Only), default value, and function information.
7.3.6.2.1 Writing a Register
To
1.
2.
3.
4.
5.
6.
7.
write a register, the following protocol is used (see SMBus 2.0 specification).
The Host drives a START condition, the 7-bit SMBus address, and a 0 indicating a WRITE.
The Device (Slave) drives the ACK bit (0).
The Host drives the 8-bit Register Address.
The Device drives an ACK bit (0).
The Host drives the 8-bit data byte.
The Device drives an ACK bit (0).
The Host drives a STOP condition.
The WRITE transaction is completed, the bus goes IDLE, and communication with other SMBus devices may
now occur.
7.3.6.2.2 Reading a Register
To read a register, the following protocol is used (see SMBus 2.0 specification).
1. The Host drives a START condition, the 7-bit SMBus address, and a 0 indicating a WRITE.
2. The Device (Slave) drives the ACK bit (0).
3. The Host drives the 8-bit Register Address.
4. The Device drives an ACK bit (0).
5. The Host drives a START condition.
6. The Host drives the 7-bit SMBus Address, and a 1 indicating a READ.
7. The Device drives an ACK bit 0.
8. The Device drives the 8-bit data value (register contents).
9. The Host drives a NACK bit 1 indicating end of the READ transfer.
10. The Host drives a STOP condition.
7.3.6.3 Communicating With Multiple LMH0303 Cable Drivers through the SMBus
A common application for the LMH0303 uses multiple cable driver devices. Even though the LMH0303 devices
all have the same default SMBus device ID (address), it is still possible for them share the SMBus signals as
shown in Figure 4. A third signal is required from the host to the first device. This signal acts as a Enable or
Reset signal. Additional LMH0303s are controlled from the upstream device. In this control scheme, multiple
LMH0303s may be controlled through the two-wire SMBus and the use of one General Purpose Output (GPO)
signal. Other SMBus devices may also be connected to the two wires, assuming they have their own unique
SMBus addresses.
10
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Feature Description (continued)
3.3V
RSTI
RSTO
SDA
RSTO
LMH0303
#N
SCL
RSTI
SDA
RSTO
SDA
GPO
SCL
LVCMOS GPIO
SMBus Interface
RSTI
LMH0303
#2
SCL
LMH0303
#1
Host
(for example,
FPGA)
SCL
SDA
Figure 4. SMBus Configuration for Multiple LMH0303 Cable Drivers
The RSTI pin of the first device is controlled by the system with a GPO pin from the host. The first LMH0303
RSTO pin is then daisy chained to the next device's RSTI pin. That device’s RSTO pin is connected to the next
device and so on.
The procedure at initialization is to:
1. Hold the host GPO pin Low in RESET, to the first device. RSTO output default is also Low which holds the
next device in RESET in the chain.
2. Raise the host GPO signal to LMH0303 #1 RSTI input pin.
3. Write to Address 0x2E Register 0 with the new address value (for example 0x2C).
4. Upon writing Register 0 in LMH0303 #1, its RSTO signal will switch High. Its new address is 0x2C, and the
next LMH0303 in the chain will now respond to the default address of 0x2E.
5. The process is repeated until all LMH0303 devices have a unique address loaded.
6. Direct SMBus writes and reads may now take place between the host and any addressed device.
The 7-bit address field allows for 128 unique addresses. The above procedure allows for the reprogramming of
the LMH0303 devices such that multiple devices may share the two-wire SMBus. Make sure all devices on the
bus have unique device IDs.
If power is toggled to the system, the SMBus address routine needs to be repeated.
7.4 Device Functional Modes
The LMH0303 features can be controlled through the pin or SMBus interface. SMBus Interface describes
detailed operation using SMBus interface.
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7.5 Register Maps
Table 1 lists the SMBus registers of the LMH0303 device.
Table 1. SMBus Registers
ADDRESS
R/W
0x00
R/W
0x01
R
0x02
12
R/W
NAME
BITS
FIELD
DEFAULT
ID
7:1
DEVID
0
RSVD
0
STATUS
7:3
RSVD
00000
MASK
0010111
DESCRIPTION
Device ID. Writing this register will force the
RSTO pin high. Further access to the device
must use this 7-bit address.
Reserved as 0. Always write 0 to this bit.
Reserved.
2
TFN
0
Termination Fault for SDI.
0: No Termination Fault Detected.
1: Termination Fault Detected.
1
TFP
0
Termination Fault for SDI.
0: No Termination Fault Detected.
1: Termination Fault Detected.
0
LOS
0
Loss Of Signal (LOS) detect at input.
0: No Signal Detected.
1: Signal Detected.
7
SD
0
SD Rate select bit. If the SD/HD pin is set to
VCC, it overrides this bit. With the SD/HD pin
set to ground, this bit selects the output edge
rate as follows:
0: HD edge rate.
1: SD edge rate.
6
RSVD
0
Reserved as 0. Always write 0 to this bit.
5
PD
0
Power Down for SDO output stage. If the
ENABLE pin is set to ground, it overrides this
bit. With the ENABLE pin set to VCC, PD
functions as follows:
0: SDO active.
1: SDO powered down.
4:3
RSVD
00
Reserved as 00. Always write 00 to these bits.
2
MTFN
0
Mask TFN from affecting FAULT pin.
0: TFN=1 will cause FAULT to be 0.
1: TFN=1 will not affect FAULT; the condition
is masked off.
1
MTFP
0
Mask TFP from affecting FAULT pin.
0: TFP=1 will cause FAULT to be 0.
1: TFP=1 will not affect FAULT; the condition
is masked off.
0
MLOS
0
Mask LOS from affecting FAULT pin.
0: LOS=0 will cause FAULT to be 0.
1: LOS=0 will not affect FAULT; the condition
is masked off.
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Register Maps (continued)
Table 1. SMBus Registers (continued)
ADDRESS
R/W
0x03
R/W
0x04
R/W
NAME
DIRECTION
OUTPUT
BITS
FIELD
DEFAULT
DESCRIPTION
7
HDTFThreshLSB
1
Least Significant Bit for HDTFThresh
detection threshold. Combines with
HDTFThresh bits in register 0x04.
6
SDTFThreshLSB
1
Least Significant Bit for SDTFThresh
detection threshold. Combines with
SDTFThresh bits in register 0x05.
5:3
RSVD
000
2
DTFN
0
Direction of TFN that affects FAULT pin (when
not masked).
0: TFN=1 will cause FAULT to be 0 (when the
condition is not masked off).
1: TFN=0 will cause FAULT to be 0 (when the
condition is not masked off).
1
DTFP
0
Direction of TFP that affects FAULT pin (when
not masked).
0: TFP=1 will cause FAULT to be 0 (when the
condition is not masked off).
1: TFP=0 will cause FAULT to be 0 (when the
condition is not masked off).
0
DLOS
0
Direction of LOS that affects FAULT pin
(when not masked).
0: LOS=0 will cause FAULT to be 0 (when the
condition is not masked off).
1: LOS=1 will cause FAULT to be 0 (when the
condition is not masked off).
100
Sets the Termination Fault threshold for SDO,
when SD is set to HD rates (0). Combines
with HDTFThreshLSB in register 0x03 (default
for combined value is 1001).
10000
SDO output amplitude in roughly 5 mV steps.
7:5
HDTFThresh
4:0
AMP
Reserved as 000. Always write 000 to these
bits.
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Register Maps (continued)
Table 1. SMBus Registers (continued)
ADDRESS
R/W
0x05
R/W
14
NAME
OUTPUTCTRL
BITS
FIELD
DEFAULT
DESCRIPTION
7
RSVD
0
Reserved as 0. Always write 0 to this bit.
6
FLOSOF
0
Force LOS to always OFF in regards to its
effect on the output signal. This forces the
device into either the mute or “add offset”
state. The LOS bit in register 0x01 still reflects
the correct state of LOS.
0: LOS operates normally, muting or adding
offset as specified by the MUTE bit.
1: Muting or adding offset is always in place
as specified by the MUTE bit.
5
FLOSON
0
Force LOS to always ON in regards to its
effect on the output signal. This prevents the
device from muting or adding offset. The LOS
bit in register 0x01 still reflects the correct
state of LOS.
0: LOS operates normally, muting or adding
offset as specified in the MUTE bit.
1: Muting or adding offset never occurs.
4
LOSEN
0
Configures LOS to be combined with the
ENABLE functionality.
0: Only the PD bit and ENABLE pin affect the
power down state of the output drivers.
1: If the ENABLE pin is set to ground, it
powers down the output drivers regardless of
the state of LOS or the PD bit. With the
ENABLE pin set to VCC, LOS=0 will power
down the output drivers, and LOS=1 will leave
the power down state dependent on the PD
bit.
3
MUTE
0
Selects whether the device will MUTE when
loss of signal is detected or add an offset to
prevent self oscillation. When an input signal
is detected (LOS=1), the device will operate
normally.
0: Loss of signal will force a small offset to
prevent self oscillation.
1: Loss of signal will force the channel to
MUTE.
010
Sets the Termination Fault threshold for SDO,
when SD is set to SD rate. Combines with
SDTFThreshLSB in register 0x03 (default for
combined value is 0101).
2:0
SDTFThresh
0x06
R/W
RSVD
7:0
RSVD
00000000
Reserved as 00000000. Always write
00000000 to these bits.
0x07
R/W
RSVD
7:0
RSVD
00000000
Reserved as 00000000. Always write
00000000 to these bits.
0x08
R/W
TEST
7:5
CMPCMD
4:0
RSVD
000
00000
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Compare command. Determines whether the
peak value or the current value of the
Termination Fault counters is read in registers
0x0A and 0x0B.
000: Resets compare value to 00; registers
0x0A and 0x0B show current counter values.
Sets detection to look for MAX peak values.
001: Capture counter 0. Register 0x0A shows
peak value.
010: Capture counter 1. Register 0x0B shows
peak value.
011, 100: Reserved.
101: Resets compare value to 0x1F. Sets
detection to look for MIN peak values.
110, 111: Reserved.
Reserved as 00000. Always write 00000 to
these bits.
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Register Maps (continued)
Table 1. SMBus Registers (continued)
ADDRESS
R/W
0x09
R
0x0A
0x0B
R
R
NAME
REV
TFPCOUNT
TFNCOUNT
BITS
FIELD
7:5
RSVD
4:3
2:0
7:5
RSVD
4:0
TFPCOUNT
7:5
RSVD
4:0
TFNCOUNT
DEFAULT
DESCRIPTION
000
Reserved.
DIREV
10
Die Revision.
PARTID
011
Part Identifier. Note that single output devices
(LMH0303) have the LSB=1. Dual output
devices (LMH0307) have the LSB=0.
000
Reserved.
00000
000
00000
This is either the current value of TFP
Counter, or the peak value of the counter,
depending on CMPCMD in register 0x08.
Reserved.
This is either the current value of TFN
Counter, or the peak value of the counter,
depending on CMPCMD in register 0x08.
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8 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
8.1 Application Information
The LMH0303 is a single-channel SDI cable driver that supports different application spaces. The following
sections describe the typical use cases and common implementation practices.
8.1.1 General Guidance for All Applications
The LMH0303 supports two modes of configuration: Pin control or SMBus mode. Once one of these two control
mechanism is chosen, pay attention to the PCB layout for the high-speed signals (see Layout Guidelines). The
SMPTE specifications also define the use of AC-coupling capacitors for transporting uncompressed serial data
streams with heavy low-frequency content. This specification requires the use of a 4.7-µF AC-coupling capacitor
to avoid low frequency DC wander. The 75-Ω signal is also required to meet certain rise and fall timing to
facilitate highest eye opening for the receiving device.
SMPTE specifies the requirements for the Serial Digital Interface to transport digital video at SD, HD, 3 Gb/s, and
higher data rates over coaxial cables. One of the requirements is meeting the required return loss. This
requirement specifies how closely the port resembles 75-Ω impedance across a specified frequency band.
Output return loss is dependent on board design. The LMH0303 supports these requirements. To gain additional
return loss margin, return loss network in Figure 5 can be optimized.
8.1.2 Cable Fault Detection Operation
The termination fault detection of the LMH0303 indicates when no cable is connected to the output (near end).
The termination fault detection works by detecting reflections on the output. The device measures the peak-topeak output voltage. The output amplitude is normally 800 mVp-p. No termination results in 2x the output voltage
(1600 mVp-p) due to the 100% reflection. At the lowest threshold settings, the LMH0303 detects fault even with
the amplitude down near 800 mVp-p (perfect termination). At the highest threshold settings, the LMH0303 will
detect no fault even as the amplitude approaches 1600 mVp-p (completely unterminated). With the default register
settings (HDTFThresh = 9) and with a 3G input, the cable driver will detect the unloaded condition if it sees an
amplitude greater than about 450 mVp-p below the maximum (that is, the output amplitude, including the
reflection, is about 1.15 Vp-p). Each step of the HD threshold register changes this decision voltage by
approximately 100 mV and this can range from 50 to 200 mV. These results are dependent on the board layout
and passive components.
Since the termination fault detection threshold is dependent on the PCB layout, the threshold may need to be
fine tuned for each design. To help in setting the termination fault threshold, the termination fault counters
(registers 0x0A and 0x0B) gauges how the cable driver is interpreting the output termination. The termination
fault counter counts the termination faults seen at the LMH0303 output. It counts up or down: up one tick when a
termination fault is detected, and down one tick when a proper termination is detected. The counter ranges from
0 to 31 (decimal). When there is no termination fault, the value will be near 0. When the count hits 31, the
termination fault indicator is asserted. These registers can be used to fine tune the termination fault threshold
setting. If there are many termination fault counts when the output is properly terminated, then the termination
fault threshold should be increased. If the register is not showing consistent counts of 31 when the output is
unterminated, then the termination fault threshold should be decreased.
16
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8.2 Typical Application
Figure 5 shows the application circuit for the LMH0303.
VCC
VCC
10 kΩ
FAULT
75 Ω
0.1 μF
75 Ω
RSTO
13
FAULT
14
NC
LMH0303
SD/HD
VEE
4.7 μF Coaxial Cable
75 Ω
4.7 μF Coaxial Cable
12
11
10
75 Ω
75 Ω
6.8 nH
RREF
6
5
RSTI
VCC
VCC
9
DAP
4
SDO
SCL
3
SDI
75 Ω
8
0.1 μF
SDO
SDA
2
SDI
7
49.9 Ω
ENABLE
1
Differential
Input
NC
RSTO
49.9 Ω
15
16
6.8 nH
750 Ω
RSTI
VCC
ENABLE
SDA
SCL
VCC
0.1 μF
10 kΩ
10 kΩ
SD/HD
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Figure 5. Application Circuit
8.2.1 Design Requirements
For the LMH0303 design example, Table 2 lists the design parameters.
Table 2. LMH0303 Design Parameters
PARAMETER
REQUIREMENT
Input termination
Required, 49.9 Ω are recommended (see Figure 5).
Output AC-coupling capacitors
Required. Both SDO and SDO require AC-coupling capacitors. SDO ACcoupling capacitors are expected to be 4.7 µF to comply with SMPTE
wander requirement.
DC power supply coupling capacitors
To minimize power supply noise, place 0.1-µF capacitor as close to the
device VCC pin as possible.
Distance from device to BNC
Keep this distance as short as possible.
High speed SDI and SDI trace impedance
Design differential trace impedance of SDI and SDI with 100 Ω.
High speed SDO and SDO trace impedance
Single-ended trace impedance for SDO and SDO with 75 Ω.
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8.2.2 Detailed Design Procedure
The following design procedure is recommended:
1. Select a suitable power supply voltage for the LMH0303. It can be powered from a single 3.3-V supply (see
Power Supply Recommendations).
2. Check that the power supply meets the DC requirements in Recommended Operating Conditions.
3. Select the proper pull-high or pull-low for SD/HD to set the slew rate.
4. Select proper pull-high or pull-low for ENABLE to enable or disable the output driver.
5. Choose a high quality 75-Ω BNC that is capable to support 2.97-Gbps applications. Consult a BNC supplier
regarding insertion loss, impedance specifications, and recommended BNC footprint for meeting SMPTE
return loss requirements.
6. Choose small 0402 surface mount ceramic capacitors for the AC-coupling and bypass capacitors.
7. Use proper footprint for BNC and AC-coupling capacitors. Anti-pads are commonly used in power and
ground planes under these landing pads to achieve optimum return loss.
8.2.3 Application Curves
920
187 mV/DIV
SDO Amplitude (mVp-p)
900
880
860
840
820
800
780
760
1 ns/DIV
660
680
700
720
740
760
RREF Resistance (Ÿ)
Figure 6. SDO PRBS10 at 270 Mbps
780
C001
Figure 7. SDO Amplitude vs RREF Resistance
9 Power Supply Recommendations
Follow these general guidelines when designing the power supply:
1. The power supply should be designed to provide the recommended operating conditions (see
Recommended Operating Conditions).
2. The maximum current draw for the LMH0303 is provided in Electrical Characteristics – DC. This figure can
be used to calculate the maximum current the supply must provide.
3. The LMH0303 does not require any special power supply filtering, provided the recommended operating
conditions are met. Only standard supply coupling is required.
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10 Layout
10.1 Layout Guidelines
TI recommends the following layout guidelines for the LMH0303:
1. The RREF 1% tolerance resistor should be placed as close as possible to the RREF pin. In addition, the copper
in the plane layers below the RREF network should be removed to minimize parasitic capacitance.
2. Choose a suitable board stackup that supports 75-Ω single-ended trace and 100-Ω differential trace routing
on the top layer of the board. This is typically done with a Layer 2 ground plane reference for the 100-Ω
differential traces and a second ground plane at Layer 3 reference for the 75-Ω single-ended traces.
3. Use single-ended uncoupled trace designed with 75-Ω impedance for signal routing to SDO and SDO. The
trace width is typically 8-10 mil reference to a ground plane at Layer 3.
4. Use coupled differential traces with 100-Ω impedance for signal routing to SDI and SDI. They are usually 5mil to 8-mil trace width reference to a ground plane at Layer 2.
5. Place anti-pad (ground relief) on the power and ground planes directly under the 4.7-μF AC-coupling
capacitor, return loss network, and IC landing pads to minimize parasitic capacitance. The size of the antipad depends on the board stackup and can be determined by a 3-dimension electromagnetic simulation tool.
6. Use a well-designed BNC footprint to ensure the BNC’s signal landing pad achieves 75-Ω characteristic
impedance. BNC suppliers usually provide recommendations on BNC footprint for best results.
7. Keep trace length short between the BNC and SDO. The trace routing for SDO and SDO should be
symmetrical, approximately equal lengths, and equal loading.
8. The exposed pad EP of the package should be connected to the ground plane through an array of vias.
These vias are solder-masked to avoid solder flow into the plated-through holes during the board
manufacturing process.
9. Connect each supply pin (VCC and VEE) to the power or ground planes with a short via. The via is usually
placed tangent to the landing pads of the supply pins with the shortest trace possible.
10. Power-supply bypass capacitors should be placed close to the supply pins.
10.2 Layout Example
Figure 8 shows an example of proper layout requirements for the LMH0303.
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Layout Example (continued)
BNC foot print
Anti-pad
GND stitch
> 5W
75
Anti-pad:
100
coupled trace
49.9
W=8
S = 10
W=8
6.8
0.1 µF
nH
VCC
4.7 µF
Zo = 75
0.1 µF
Solder
Paste
mask
75
4.7 µF
75
6.8
n
H
W = 10
> 5W
VCC
0.1 µF
750
VCC
EP
GND
GND
Figure 8. LMH0303 High-Speed Traces Layout Example
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11 Device and Documentation Support
11.1 Community Resources
The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.
11.2 Trademarks
E2E is a trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
11.3 Electrostatic Discharge Caution
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
11.4 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
12 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
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PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
(4/5)
(6)
LMH0303SQ/NOPB
ACTIVE
WQFN
RUM
16
1000
RoHS & Green
SN
Level-3-260C-168 HR
-40 to 85
L0303
LMH0303SQE/NOPB
ACTIVE
WQFN
RUM
16
250
RoHS & Green
SN
Level-3-260C-168 HR
-40 to 85
L0303
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of
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