LMH0307SQX/NOPB

LMH0307 www.ti.com SNLS286I – APRIL 2008 – REVISED APRIL 2013 3 Gbps HD/SD SDI Dual Output Cable Driver With Cable Detect Check for Samples: LMH0307 FEATURES DESCRIPTION • The LMH0307 3 Gbps HD/SD SDI Dual Output Cable Driver with Cable Detect is designed for use in SMPTE 424M, SMPTE 292M, SMPTE 344M, and SMPTE 259M serial digital video applications. The LMH0307 implements two complementary output drivers and drives 75Ω transmission lines (Belden 1694A, Belden 8281, or equivalent) at data rates up to 2.97 Gbps. 1 2 • • • • • • • • • • • • • SMPTE 424M, SMPTE 292M, SMPTE 344M, and SMPTE 259M Compliant Data Rates to 2.97 Gbps Supports DVB-ASI at 270 Mbps Cable Detect on Output Loss of Signal Detect at Input Output Driver Power Down Control Typical Power Consumption: 230 mW in SD Mode and 275 mW in HD Mode Power Save Mode Typical Power Consumption: 4 mW Single 3.3V Supply Operation Differential Input Dual Complementary 75Ω Outputs Selectable Slew Rate Industrial Temperature Range: −40°C to +85°C 16-Pin WQFN or 25-Ball CS-BGA package APPLICATIONS • • • SMPTE 424M, SMPTE 292M, SMPTE 344M, and SMPTE 259M Serial Digital Interfaces Digital Video Routers and Switches Distribution Amplifiers The LMH0307 includes intelligent sensing capabilities to improve system diagnostics. The cable detect feature senses near-end termination to determine if a cable is correctly attached to the output BNC. Input loss of signal (LOS) detects the presence of a valid signal at the input of the cable driver. These sensing features may be used to alert the user of a system fault and activate a deep power save mode, reducing the cable driver's power consumption to 4 mW. These features are accessible via an SMBus interface. The LMH0307 provides two selectable slew rates for SMPTE 259M and SMPTE 424M / 292M compliance. The output amplitude is adjustable ±10% in 5 mV steps via the SMBus. The LMH0307 is powered from a single 3.3V supply. Power consumption is typically 230 mW in SD mode and 275 mW in HD mode. The LMH0307 is available in two space-saving packages: a 4 x 4 mm 16-pin WQFN and even more space-efficient 3 x 3 mm 25ball CS-BGA package. Typical Application SDI In SD/HD SDI Out LMH0356 3G/HD/SD SDI Reclocker ENABLE SDI Clock or Second Data Output LMH0307 3G/HD/SD SDI Dual Cable Driver FAULT SDA SCL SMBus Data SMBus Clock Microcontroller or FPGA 1 2 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. All trademarks are the property of their respective owners. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright © 2008–2013, Texas Instruments Incorporated LMH0307 SNLS286I – APRIL 2008 – REVISED APRIL 2013 www.ti.com 2 VEE 3 RREF 4 SDO1 SDO1 FAULT 14 13 LMH0307SQ (top view) RSTI 5 6 7 8 SCL SDI 15 SDA 1 16 ENABLE SDI RSTO Connection Diagram 12 SDO0 11 SDO0 10 SD/HD 9 VCC The exposed die attach pad is a negative electrical terminal for this device. It should be connected to the negative power supply voltage. Figure 1. 16-Pin WQFN Package Number RUM A B C D E 1 2 3 4 5 SDI RSTO SDO1 SDO1 FAULT A1 A2 A3 A4 A5 SDI VEE NC VEE SDO0 B1 B2 B3 B4 B5 VEE VEE VEE VEE SDO0 C1 C2 C3 C4 C5 RREF RSTI NC VCC SD/HD D1 D2 D3 D4 D5 RREF ENABLE SDA SCL NC E1 E2 E3 E4 E5 LMH0307GR (top view) Figure 2. 25-Ball CS-BGA Package Number NYA 2 Submit Documentation Feedback Copyright © 2008–2013, Texas Instruments Incorporated Product Folder Links: LMH0307 LMH0307 www.ti.com SNLS286I – APRIL 2008 – REVISED APRIL 2013 PIN DESCRIPTIONS WQFN Pin CS-BGA Ball Name Description 1 A1 SDI Serial data true input. 2 B1 SDI Serial data complement input. 4 D1, E1 RREF Bias resistor. Connect a 750Ω resistor to VCC (also connect D1 to E1 on CS-BGA version). 5 D2 RSTI Reset input. RSTI has an internal pullup. H = Normal operation. L = Device reset. The device operates with default register settings. Forcing RSTI low also forces RSTO low. 6 E2 ENABLE Output driver enable. ENABLE has an internal pullup. H = Normal operation. L = Output driver powered off. 7 E3 SDA SMBus bidirectional data pin. When functioning as an output, it is open drain. This pin requires an external pullup. 8 E4 SCL SMBus clock input. SCL is input only. This pin requires an external pullup. 10 D5 SD/HD Output slew rate control. SD/HD has an internal pulldown. H = Output rise/fall time complies with SMPTE 259M. L = Output rise/fall time complies with SMPTE 424M / 292M. 11 C5 SDO0 Serial data output 0 complement output. 12 B5 SDO0 Serial data output 0 true output. 13 A5 FAULT Fault open drain output flag. Requires external pullup resistor and may be wire ORed with multiple cable drivers. H = Normal operation. L = Loss of signal or termination fault for any output. 14 A4 SDO1 Serial data output 1 true output. 15 A3 SDO1 Serial data output 1 complement output. 16 A2 RSTO Reset output. RSTO is automatically set to 1 when register 0 is written. It can be reset back to zero by forcing RSTI to zero to reset the device. Used to daisy chain multiple cable drivers on the same SMBus. 9 D4 VCC Positive power supply (+3.3V). DAP, 3 B2, B4, C1, C2, C3, C4 VEE Negative power supply (ground). — B3, D3, E5 NC No connect. Submit Documentation Feedback Copyright © 2008–2013, Texas Instruments Incorporated Product Folder Links: LMH0307 3 LMH0307 SNLS286I – APRIL 2008 – REVISED APRIL 2013 www.ti.com These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates. Absolute Maximum Ratings (1) −0.5V to 3.6V Supply Voltage −0.3V to VCC+0.3V Input Voltage (all inputs) Output Current 28 mA −65°C to +150°C Storage Temperature Range Junction Temperature +125°C Lead Temperature (Soldering 4 Sec) +260°C Package Thermal Resistance θJA 16-pin WQFN θJC 16-pin WQFN θJA 25-ball CS-BGA ESD Rating +7°C/W +67.6°C/W HBM 8 kV MM 400V CDM (1) +43°C/W 2 kV "Absolute Maximum Ratings" are those parameter values beyond which the life and operation of the device cannot be ensured. The stating herein of these maximums shall not be construed to imply that the device can or should be operated at or beyond these values. The table of Electrical Characteristics specifies acceptable device operating conditions. Recommended Operating Conditions Supply Voltage (VCC – VEE) 3.3V ±5% −40°C to +85°C Operating Free Air Temperature (TA) 4 Submit Documentation Feedback Copyright © 2008–2013, Texas Instruments Incorporated Product Folder Links: LMH0307 LMH0307 www.ti.com SNLS286I – APRIL 2008 – REVISED APRIL 2013 DC Electrical Characteristics Over Supply Voltage and Operating Temperature ranges, unless otherwise specified (1) (2). Symbol Parameter VCMIN Input Common Mode Voltage VSDI Input Voltage Swing VCMOUT Output Common Mode Voltage VSDO Output Voltage Swing VIH Input Voltage High Level VIL Input Voltage Low Level ICC Supply Current Conditions Reference SDI, SDI Differential Min Typ 1.6 + VSDI/2 100 SDO, SDO Single-ended, 75Ω load, RREF = 750Ω 1% Units VCC – VSDI/2 V 2200 mVP−P VCC – VSDO 720 SD/HD, ENABLE Max 800 V 880 2.0 mVP-P V 0.8 V 84 100 mA SD/HD = 1, SDO/SDO enabled 70 77 mA SDO/SDO disabled 1.3 2.5 mA 0.8 V VSDD V SD/HD = 0, SDO/SDO enabled SMBus DC Specifications VSIL Data, Clock Input Low Voltage VSIH Data, Clock Input High Voltage ISPULLUP Current through pullup resistor or current source VSDD Nominal Bus Voltage ISLEAKB Input Leakage per bus segment ISLEAKP Input Leakage per pin CSI Capacitance for SDA and SCL (1) (2) (3) (4) 2.1 VOL = 0.4V (3) (3) (4) 4 mA 3.0 3.6 V −200 200 µA −10 10 µA 10 pF Current flow into device pins is defined as positive. Current flow out of device pins is defined as negative. All voltages are stated referenced to VEE = 0 Volts. Typical values are stated for VCC = +3.3V and TA = +25°C. Recommended value — Parameter not tested. Recommended maximum capacitive load per bus segment is 400 pF. Submit Documentation Feedback Copyright © 2008–2013, Texas Instruments Incorporated Product Folder Links: LMH0307 5 LMH0307 SNLS286I – APRIL 2008 – REVISED APRIL 2013 www.ti.com AC Electrical Characteristics Over Supply Voltage and Operating Temperature ranges, unless otherwise specified (1). Symbol Parameter DRSDI Input Data Rate tjit Additive Jitter tr,tf Output Rise Time, Fall Time Conditions Reference Duty Cycle Distortion SDO, SDO Output Overshoot tSK SDO1 to SDO0 Skew Output Return Loss Units 2970 Mbps psP-P 1.485 Gbps 18 psP-P 270 Mbps 15 psP-P SD/HD = 0, 20% – 80%, 90 130 ps 800 ps SD/HD = 0 30 ps SD/HD = 1 50 ps SD/HD = 0, 2.97 Gbps (2) 27 ps SD/HD = 0, 1.485 Gbps (2) 30 ps 400 (2) 100 ps SD/HD = 0 (2) 10 % SD/HD = 1 (2) 8 % SD/HD = 0 (2) 8 ps SD/HD = 1 (2) RLSDO Max 20 SD/HD = 1 tOS Typ SDI, SDI 2.97 Gbps SD/HD = 1, 20% – 80% Mismatch in Rise/Fall Time Min 54 ps 5 MHz - 1.5 GHz (3) 15 dB 1.5 GHz - 3.0 GHz (3) 10 dB SMBus AC Specifications fSMB Bus Operating Frequency 10 tBUF Bus free time between Stop and Start Condition 100 kHz 4.7 µs tHD:STA Hold time after (repeated) Start Condition. After this period, the first clock is generated. 4.0 µs 4.7 µs At ISPULLUP = MAX tSU:STA Repeated Start Condition setup time tSU:STO Stop Condition setup time 4.0 µs tHD:DAT Data hold time 300 ns tSU:DAT Data setup time 250 ns tLOW Clock low period 4.7 µs tHIGH Clock high period 4.0 tF tR tPOR (1) (2) (3) 6 50 µs Clock/Data Fall Time 300 ns Clock/Data Rise Time 1000 ns Time in which device must be operational after power on 500 ms Typical values are stated for VCC = +3.3V and TA = +25°C. Specification is ensured by characterization. Output return loss is dependent on board design. The LMH0307 meets this specification on the SD307 evaluation board. Submit Documentation Feedback Copyright © 2008–2013, Texas Instruments Incorporated Product Folder Links: LMH0307 LMH0307 www.ti.com SNLS286I – APRIL 2008 – REVISED APRIL 2013 TIMING DIAGRAM tLOW tHIGH tR SCL tHD:STA tBUF tF tHD:DAT tSU:STA tSU:DAT tSU:STO SDA SP ST ST SP Figure 3. SMBus Timing Parameters DEVICE OPERATION INPUT INTERFACING The LMH0307 accepts either differential or single-ended input. For single-ended operation, the unused input must be properly terminated. OUTPUT INTERFACING The LMH0307 uses current mode outputs. Single-ended output levels are 800 mVP-P into 75Ω AC-coupled coaxial cable with an RREF resistor of 750Ω. The RREF resistor is connected between the RREF pin and VCC. The only resistor value that should be used for RREF is 750Ω. The RREF resistor should be placed as close as possible to the RREF pin. In addition, the copper in the plane layers below the RREF network should be removed to minimize parasitic capacitance. OUTPUT SLEW RATE CONTROL The LMH0307 output rise and fall times are selectable for either SMPTE 259M or SMPTE 424M / 292M compliance via the SD/HD pin. For slower rise and fall times, or SMPTE 259M compliance, SD/HD is set high. For faster rise and fall times, or SMPTE 424M and SMPTE 292M compliance, SD/HD is set low. SD/HD may also be controlled using the SMBus, provided the SD/HD pin is held low. SD/HD has an internal pulldown. OUTPUT ENABLE The SDO0/SDO0 and SDO1/SDO1output drivers can be enabled or disabled with the ENABLE pin. When set low, both output drivers are powered off and the LMH0307 enters a deep power save mode. ENABLE has an internal pullup. INPUT LOSS OF SIGNAL DETECTION (LOS) The LMH0307 detects when the input signal does not have a video-like pattern. Self oscillation and low levels of noise are rejected. This loss of signal detect allows a very sensitive input stage that is robust against coupled noise without any degradation of jitter performance. Via the SMBus, the loss of signal detect can either add an input offset or mute the outputs. An offset is added by default. Additionally, the loss of signal detect can be linked to the ENABLE functionality so that when the LOS goes low, ENABLE will also go low. OUTPUT CABLE DETECTION The LMH0307 detects when an output is locally terminated. When a video signal (or AC test signal) is present on SDI, the device senses the SDO and SDO amplitudes. If the output is not properly terminated (via a terminated cable or local termination), the amplitude will be higher than expected, and the Termination Fault signal is asserted. The Termination Fault signal is de-asserted when the proper termination is applied. This feature allows the system designer the flexibility to react to cable attachment and removal. Note that a long length of cable will look like a proper termination at the device output. Submit Documentation Feedback Copyright © 2008–2013, Texas Instruments Incorporated Product Folder Links: LMH0307 7 LMH0307 SNLS286I – APRIL 2008 – REVISED APRIL 2013 www.ti.com The cable driver must be enabled for the termination detection to operate. If the Termination Fault will be used to power down the LMH0307, then periodic polling (enabling) is recommended to monitor the output termination. For example, when a Fault condition is triggered, ENABLE can be driven low to power down the device. The LMH0307 should be re-enabled periodically to check the status of the output termination. The LMH0307 needs to be powered on for roughly 4 ms for Termination Fault detection to work. SMBUS INTERFACE The System Management Bus (SMBus) is a two-wire interface designed for the communication between various system component chips. By accessing the control functions of the circuit via the SMBus, pin count is kept to a minimum while allowing a maximum amount of versatility. The LMH0307 has several internal configuration registers which may be accessed via the SMBus. The 7-bit default address for the LMH0307 is 17h. The LSB is set to 0b for a WRITE and 1b for a READ, so the 8-bit default address for a WRITE is 2Eh and the 8-bit default address for a READ is 2Fh. The SMBus address may be dynamically changed. In applications where there might be several LMH0307s, the SDA, SCL, and FAULT pins can be shared. The SCL, SDA, and FAULT pins are open drain and require external pullup resistors. Multiple LMH0307s may have the FAULT pin wire ORed. This signal becomes active when either loss of signal is detected or any termination faults are detected. The registers may be read in order to determine the cause. Additionally, each signal can be masked from the FAULT pin. TRANSFER OF DATA VIA THE SMBus During normal operation the data on SDA must be stable during the time when SCL is High. There are three unique states for the SMBus: START: A High-to-Low transition on SDA while SCL is High indicates a message START condition. STOP: A Low-to-High transition on SDA while SCL is High indicates a message STOP condition. IDLE: If SCL and SDA are both High for a time exceeding tBUF from the last detected STOP condition or if they are High for a total exceeding the maximum specification for tHIGH then the bus will transfer to the IDLE state. SMBus TRANSACTIONS The device supports WRITE and READ transactions. See Table 1 for register address, type (Read/Write, Read Only), default value and function information. WRITING A REGISTER To 1. 2. 3. 4. 5. 6. 7. write a register, the following protocol is used (see SMBus 2.0 specification). The Host drives a START condition, the 7-bit SMBus address, and a “0” indicating a WRITE. The Device (Slave) drives the ACK bit (“0”). The Host drives the 8-bit Register Address. The Device drives an ACK bit (“0”). The Host drives the 8-bit data byte. The Device drives an ACK bit (“0”). The Host drives a STOP condition. The WRITE transaction is completed, the bus goes IDLE and communication with other SMBus devices may now occur. 8 Submit Documentation Feedback Copyright © 2008–2013, Texas Instruments Incorporated Product Folder Links: LMH0307 LMH0307 www.ti.com SNLS286I – APRIL 2008 – REVISED APRIL 2013 READING A REGISTER To read a register, the following protocol is used (see SMBus 2.0 specification). 1. The Host drives a START condition, the 7-bit SMBus address, and a “0” indicating a WRITE. 2. The Device (Slave) drives the ACK bit (“0”). 3. The Host drives the 8-bit Register Address. 4. The Device drives an ACK bit (“0”). 5. The Host drives a START condition. 6. The Host drives the 7-bit SMBus Address, and a “1” indicating a READ. 7. The Device drives an ACK bit “0”. 8. The Device drives the 8-bit data value (register contents). 9. The Host drives a NACK bit “1”indicating end of the READ transfer. 10. The Host drives a STOP condition. Submit Documentation Feedback Copyright © 2008–2013, Texas Instruments Incorporated Product Folder Links: LMH0307 9 LMH0307 SNLS286I – APRIL 2008 – REVISED APRIL 2013 www.ti.com APPLICATION INFORMATION Figure 4 shows the application circuit for the LMH0307. VCC 6.8 nH 0.1 PF 75: 75: 75: 4.7 PF Coaxial Cable 75: 4.7 PF Coaxial Cable 75: 75: 6.8 nH VCC VCC 10 k: FAULT 75: 0.1 PF 75: RSTO 14 15 13 FAULT 1 Differential Input SDO1 49.9: SDO1 RSTO 16 6.8 nH SDI SDO0 SDI SDO0 SD/HD 75: 4.7 PF Coaxial Cable 10 75: 75: DAP SCL 9 8 RSTI 5 VCC SDA RREF VCC 11 6.8 nH 7 4 LMH0307 VEE ENABLE 3 6 0.1 PF 4.7 PF Coaxial Cable 12 49.9: 2 75: 750: RSTI VCC ENABLE SDA SCL 0.1 PF VCC 10 k: 10 k: SD/HD Figure 4. Application Circuit 10 Submit Documentation Feedback Copyright © 2008–2013, Texas Instruments Incorporated Product Folder Links: LMH0307 LMH0307 www.ti.com SNLS286I – APRIL 2008 – REVISED APRIL 2013 COMMUNICATING WITH MULTIPLE LMH0307 CABLE DRIVERS VIA THE SMBus A common application for the LMH0307 will utilize multiple cable driver devices. Even though the LMH0307 devices all have the same default SMBus device ID (address), it is still possible for them share the SMBus signals as shown in Figure 5. A third signal is required from the host to the first device. This signal acts as a “Enable / Reset” signal. Additional LMH0307s are controlled from the upstream device. In this control scheme, multiple LMH0307s may be controlled via the two-wire SMBus and the use of one GPO (General Purpose Output) signal. Other SMBus devices may also be connected to the two wires, assuming they have their own unique SMBus addresses. 3.3V RSTO RSTI RSTO SDA RSTI LMH0307 #N SCL RSTO SCL GPO SCL LVCMOS GPIO SMBus Interface RSTI SDA Host (e.g. FPGA) LMH0307 #2 SDA LMH0307 #1 SCL SDA Figure 5. SMBus Configuration for Multiple LMH0307 Cable Drivers The RSTI pin of the first device is controlled by the system with a GPO pin from the host. The first LMH0307 RSTO pin is then daisy chained to the next device's RSTI pin. That device’s RSTO pin is connected to the next device and so on. The procedure at initialization is to: 1. Hold the host GPO pin Low in RESET, to the first device. RSTO output default is also Low which holds the next device in RESET in the chain. 2. Raise the host GPO signal to LMH0307 #1 RSTI input pin. 3. Write to Address 8’h2E (7’h17) Register 0 with the new address value (e.g. 8’h2C (7’h16). 4. Upon writing Register 0 in LMH0307 #1, its RSTO signal will switch High. Its new address is 8’h2C (7’h16), and the next LMH0307 in the chain will now respond to the default address of 8’h2E (7’h17). 5. The process is repeated until all LMH0307 devices have a unique address loaded. 6. Direct SMBus writes and reads may now take place between the host and any addressed device. The 7-bit address field allows for 128 unique addresses. The above procedure allows for the reprogramming of the LMH0307 devices such that multiple devices may share the two-wire SMBus. Make sure all devices on the bus have unique device IDs. If power is toggled to the system, the SMBus address routine needs to be repeated. Submit Documentation Feedback Copyright © 2008–2013, Texas Instruments Incorporated Product Folder Links: LMH0307 11 LMH0307 SNLS286I – APRIL 2008 – REVISED APRIL 2013 www.ti.com Table 1. SMBus Registers Address R/W Name Bits Field Default Description 00h R/W ID 7:1 DEVID 0010111 Device ID. Writing this register will force the RSTO pin high. Further accesses to the device must use this 7-bit address. 0 RSVD 0 01h R STATUS 7:5 RSVD 000 4 TF1N 0 Termination Fault for SDI1. 0: No Termination Fault Detected. 1: Termination Fault Detected. 3 TF1P 0 Termination Fault for SDI1. 0: No Termination Fault Detected. 1: Termination Fault Detected. 2 TF0N 0 Termination Fault for SDI0. 0: No Termination Fault Detected. 1: Termination Fault Detected. 1 TF0P 0 Termination Fault for SDI0. 0: No Termination Fault Detected. 1: Termination Fault Detected. 0 LOS 0 Loss Of Signal (LOS) detect at input. 0: No Signal Detected. 1: Signal Detected. 7 SD 0 SD Rate select bit. If the SD/HD pin is set to VCC, it overrides this bit. With the SD/HD pin set to ground, this bit selects the output edge rate as follows: 0: HD edge rate. 1: SD edge rate. 6 PD1 0 Power Down for SDO1 output stage. If the ENABLE pin is set to ground, it overrides this bit. With the ENABLE pin set to VCC, PD1 functions as follows: 0: SDO1 active. 1: SDO1 powered down. 5 PD0 0 Power Down for SDO0 output stage. If the ENABLE pin is set to ground, it overrides this bit. With the ENABLE pin set to VCC, PD0 functions as follows: 0: SDO0 active. 1: SDO0 powered down. 4 MTF1N 0 Mask TF1N from affecting FAULT pin. 0: TF1N=1 will cause FAULT to be 0. 1: TF1N=1 will not affect FAULT; the condition is masked off. 3 MTF1P 0 Mask TF1P from affecting FAULT pin. 0: TF1P=1 will cause FAULT to be 0. 1: TF1P=1 will not affect FAULT; the condition is masked off. 2 MTF0N 0 Mask TF0N from affecting FAULT pin. 0: TF0N=1 will cause FAULT to be 0. 1: TF0N=1 will not affect FAULT; the condition is masked off. 1 MTF0P 0 Mask TF0P from affecting FAULT pin. 0: TF0P=1 will cause FAULT to be 0. 1: TF0P=1 will not affect FAULT; the condition is masked off. 0 MLOS 0 Mask LOS from affecting FAULT pin. 0: LOS=0 will cause FAULT to be 0. 1: LOS=0 will not affect FAULT; the condition is masked off. 02h 12 R/W MASK Submit Documentation Feedback Reserved as 0. Always write 0 to this bit. Reserved. Copyright © 2008–2013, Texas Instruments Incorporated Product Folder Links: LMH0307 LMH0307 www.ti.com SNLS286I – APRIL 2008 – REVISED APRIL 2013 Table 1. SMBus Registers (continued) Address R/W Name 03h R/W DIRECTION 04h R/W OUTPUT0 Bits Field Default Description 7 HDTF0ThreshLSB 1 Least Significant Bit for HDTF0Thresh detection threshold. Combines with HDTF0Thresh bits in register 04h. 6 SDTF0ThreshLSB 1 Least Significant Bit for SDTF0Thresh detection threshold. Combines with SDTF0Thresh bits in register 05h. 5 RSVD 0 Reserved as 0. Always write 0 to this bit. 4 DTF1N 0 Direction of TF1N that affects FAULT pin (when not masked). 0: TF1N=1 will cause FAULT to be 0 (when the condition is not masked off). 1: TF1N=0 will cause FAULT to be 0 (when the condition is not masked off). 3 DTF1P 0 Direction of TF1P that affects FAULT pin (when not masked). 0: TF1P=1 will cause FAULT to be 0 (when the condition is not masked off). 1: TF1P=0 will cause FAULT to be 0 (when the condition is not masked off). 2 DTF0N 0 Direction of TF0N that affects FAULT pin (when not masked). 0: TF0N=1 will cause FAULT to be 0 (when the condition is not masked off). 1: TF0N=0 will cause FAULT to be 0 (when the condition is not masked off). 1 DTF0P 0 Direction of TF0P that affects FAULT pin (when not masked). 0: TF0P=1 will cause FAULT to be 0 (when the condition is not masked off). 1: TF0P=0 will cause FAULT to be 0 (when the condition is not masked off). 0 DLOS 0 Direction of LOS that affects FAULT pin (when not masked). 0: LOS=0 will cause FAULT to be 0 (when the condition is not masked off). 1: LOS=1 will cause FAULT to be 0 (when the condition is not masked off). 100 Sets the Termination Fault threshold for SDO0, when SD is set to HD rates (0). Combines with HDTF0ThreshLSB in register 03h (default for combined value is 1001). 7:5 HDTF0Thresh 4:0 AMP0 10000 SDO0 output amplitude in roughly 5 mV steps. Submit Documentation Feedback Copyright © 2008–2013, Texas Instruments Incorporated Product Folder Links: LMH0307 13 LMH0307 SNLS286I – APRIL 2008 – REVISED APRIL 2013 www.ti.com Table 1. SMBus Registers (continued) Address R/W Name 05h R/W OUTPUT0CTRL 06h 07h 14 R/W R/W OUTPUT1 OUTPUT1CTRL Bits Field Default 7 RSVD 0 Description Reserved as 0. Always write 0 to this bit. 6 FLOSOF 0 Force LOS to always OFF in regard to its effect on the output signal. This forces the device into either the mute or “add offset” state. The LOS bit in register 01h still reflects the correct state of LOS. 0: LOS operates normally, muting or adding offset as specified by the MUTE bit. 1: Muting or adding offset is always in place as specified by the MUTE bit. 5 FLOSON 0 Force LOS to always ON in regard to its effect on the output signal. This prevents the device from muting or adding offset. The LOS bit in register 01h still reflects the correct state of LOS. 0: LOS operates normally, muting or adding offset as specified in the MUTE bit. 1: Muting or adding offset never occurs. 4 LOSEN 0 Configures LOS to be combined with the ENABLE functionality. 0: Only the PD bits and ENABLE pin affect the power down state of the output drivers. 1: If the ENABLE pin is set to ground, it powers down the output drivers regardless of the state of LOS or the PD bits. With the ENABLE pin set to VCC, LOS=0 will power down the output drivers, and LOS=1 will leave the power down state dependent on the PD bits. 3 MUTE 0 Selects whether the device will MUTE when loss of signal is detected or add an offset to prevent self oscillation. When an input signal is detected (LOS=1), the device will operate normally. 0: Loss of signal will force a small offset to prevent self oscillation. 1: Loss of signal will force the channel to MUTE. 2:0 SDTF0Thresh 010 Sets the Termination Fault threshold for SDO0, when SD is set to SD rates (1). Combines with SDTF0ThreshLSB in register 03h (default for combined value is 0101). 7:5 HDTF1Thresh 100 Sets the Termination Fault threshold for SDO1, when SD is set to HD rates (0). Combines with HDTF1ThreshLSB in register 07h (default for combined value is 1001). 4:0 AMP1 10000 SDO1 output amplitude in roughly 5 mV steps. 7 HDTF1ThreshLSB 1 Least Significant Bit for HDTF1Thresh detection threshold. Combines with HDTF1Thresh bits in register 06h. 6 SDTF1ThreshLSB 1 Least Significant Bit for SDTF1Thresh detection threshold. Combines with SDTF1Thresh bits in register 07h. 5:3 RSVD 011 Reserved as 011. Always write 011 to these bits. 2:0 SDTF1Thresh 010 Sets the Termination Fault threshold for SDO1, when SD is set to SD rates (1). Combines with SDTF1ThreshLSB in bit 6 (default for combined value is 0101). Submit Documentation Feedback Copyright © 2008–2013, Texas Instruments Incorporated Product Folder Links: LMH0307 LMH0307 www.ti.com SNLS286I – APRIL 2008 – REVISED APRIL 2013 Table 1. SMBus Registers (continued) Address R/W Name Bits Field 08h R/W TEST 7:5 CMPCMD 4:0 09h 0Ah 0Bh 0Ch 0Dh R R R R R REV TF0PCOUNT TF0NCOUNT TF1PCOUNT TF1NCOUNT Default Description 000 Compare command. Determines whether the peak value or the current value of the Termination Fault counters is read in registers 0Ah-0Dh. 000: Resets compare value to 00; registers 0Ah-0Dh all show current counter values. Sets detection to look for MAX peak values. 001: Capture counter 0. Register 0Ah shows peak value. 010: Capture counter 1. Register 0Bh shows peak value. 011: Capture counter 2. Register 0Ch shows peak value. 100: Capture counter 3. Register 0Dh shows peak value. 101: Resets compare value to 1Fh. Sets detection to look for MIN peak values. 110, 111: Reserved. RSVD 00000 Reserved as 00000. Always write 00000 to these bits. 7:5 RSVD 000 Reserved. 4:3 DIEREV 10 Die Revision. 2:0 PARTID 010 Part Identifier. Note that single output devices (LMH0303) have the LSB=1. Dual output devices (LMH0307) have the LSB=0. 7:5 RSVD 000 Reserved. 4:0 TF0PCOUNT 7:5 RSVD 4:0 TF0NCOUNT 7:5 RSVD 4:0 TF1PCOUNT 7:5 RSVD 4:0 TF1NCOUNT 00000 000 00000 000 00000 000 00000 This is either the current value of TF0P Counter, or the peak value of the counter, depending on CMPCMD in register 08h. Reserved. This is either the current value of TF0N Counter, or the peak value of the counter, depending on CMPCMD in register 08h. Reserved. This is either the current value of TF1P Counter, or the peak value of the counter, depending on CMPCMD in register 08h. Reserved. This is either the current value of TF1N Counter, or the peak value of the counter, depending on CMPCMD in register 08h. Submit Documentation Feedback Copyright © 2008–2013, Texas Instruments Incorporated Product Folder Links: LMH0307 15 LMH0307 SNLS286I – APRIL 2008 – REVISED APRIL 2013 www.ti.com REVISION HISTORY Changes from Revision H (April 2013) to Revision I • 16 Page Changed layout of National Data Sheet to TI format .......................................................................................................... 15 Submit Documentation Feedback Copyright © 2008–2013, Texas Instruments Incorporated Product Folder Links: LMH0307 PACKAGE OPTION ADDENDUM www.ti.com 10-Dec-2020 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan (2) Lead finish/ Ball material MSL Peak Temp Op Temp (°C) Device Marking (3) (4/5) (6) LMH0307GRE/NOPB ACTIVE csBGA NYA 25 250 RoHS & Green SNAGCU Level-1-260C-UNLIM -40 to 85 307G LMH0307SQ/NOPB ACTIVE WQFN RUM 16 1000 RoHS & Green SN Level-3-260C-168 HR -40 to 85 L0307 LMH0307SQE/NOPB ACTIVE WQFN RUM 16 250 RoHS & Green SN Level-3-260C-168 HR -40 to 85 L0307 LMH0307SQX/NOPB ACTIVE WQFN RUM 16 4500 RoHS & Green SN Level-3-260C-168 HR -40 to 85 L0307 (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of