LMH0324RTWR

Order Now Product Folder Support & Community Tools & Software Technical Documents Reference Design LMH0324 SNLS531B – APRIL 2016 – REVISED JUNE 2018 LMH0324 3G/HD/SD SDI Dual Output Adaptive Cable Equalizer 1 Features 3 Description • The LMH0324 is a low-power, dual-output, extended reach adaptive cable equalizer. It is designed to equalize SDI data transmitted over 75-Ω coax cable. The equalizer operates over a wide range of data rates from 125 Mbps to 2.97 Gbps. The equalizer includes an active sensing circuitry that ensures robust performance and enhanced immunity to variations in the input signal launch amplitude. 1 • • • • • • • • • • • • • • • • Supports ST 424(3G), ST 292(HD), and ST 259(SD) Compatible with DVB-ASI and AES10 (MADI) Adaptive Cable Equalizer Cable Reach (Belden 1694A): – 200 m at 2.97 Gbps – 280 m at 1.485 Gbps – 600 m at 270 Mbps Low Power: 78 mW (typical) Power Save Mode: 15 mW On-chip Input Termination (75 Ω single-ended) Integrated Input Return Loss Network Dual 100-Ω Output Drivers With De-Emphasis Independent Output Power-Down Control Supports Signal Splitter Mode (–6 dB Launch Amplitude) Cable Length Indicator Digital MUTEREF Threshold Powers from 2.5-V or 1.8-V Supply Configurable by Control Pins, SPI, or SMBus Interface 4-mm × 4-mm 24-pin QFN Package Operating Temperature Range: –40°C to +85°C The LMH0324 provides extended cable reach with low power consumption. It offers power management to reduce power consumption further when no input signal is present. The LMH0324 has two differential serial data outputs, which provide flexibility for fan-out buffering. The output drivers offer programmable de-emphasis to compensate for board trace losses at the LMH0324 outputs. The operating state of the LMH0324 can be set via pin control. Additional settings of the device can be programmed via SPI or SMBus interface. The LMH0324 is pin-compatible to the LMH1219 (12Gbps adaptive cable equalizer with integrated reclocker). The pin compatibility allows ease of upgrade from a 3-Gbps equalizer to a 12-Gbps equalizer with integrated reclocker. Device Information(1) PART NUMBER PACKAGE LMH0324 2 Applications • • • • QFN (24) BODY SIZE (NOM) 4.00 mm × 4.00 mm (1) For all available packages, see the orderable addendum at the end of the data sheet. SMPTE Compatible Serial Digital Interface (SDI) Broadcast Video Routers, Switchers, and Monitors DVB-ASI and Distribution Amplifiers Digital Video Processing and Editing Simplified Block Diagram Low Power Adaptive Cable Equalizer VOD_DE EQ Bypass 2 IN0± SE 75 Ÿ Term and RL Network 100 Ÿ Driver Cable EQ Carrier Detector 2 OUT0± VOD_DE OUT_MUX 100 Ÿ Driver 2 OUT1± CD_N LDO VDD_LDO Power Management Single 2.5 V or 1.8 V Control Logic Control Pins Carrier Detect Serial Interface SPI or SMBus 1 An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. PRODUCTION DATA. LMH0324 SNLS531B – APRIL 2016 – REVISED JUNE 2018 www.ti.com Table of Contents 1 2 3 4 5 6 Features .................................................................. Applications ........................................................... Description ............................................................. Revision History..................................................... Pin Configuration and Functions ......................... Specifications......................................................... 1 1 1 2 3 5 6.1 6.2 6.3 6.4 6.5 6.6 Absolute Maximum Ratings ...................................... 5 ESD Ratings.............................................................. 5 Recommended Operating Conditions....................... 5 Thermal Information .................................................. 6 Electrical Characteristics........................................... 6 Recommended SMBus Interface AC Timing Specifications ............................................................. 9 6.7 Serial Parallel Interface (SPI) AC Timing Specifications ............................................................. 9 6.8 Typical Characteristics ............................................ 10 7 Detailed Description ............................................ 12 7.1 Overview ................................................................. 12 7.2 Functional Block Diagram ....................................... 12 7.3 Feature Description................................................. 13 7.4 Device Functional Modes........................................ 16 7.5 LMH0324 Register Map .......................................... 21 8 Application and Implementation ........................ 26 8.1 Application Information............................................ 26 8.2 Typical Application ................................................. 26 9 Power Supply Recommendations...................... 30 10 Layout................................................................... 31 10.1 Layout Guidelines ................................................. 31 10.2 Layout Example .................................................... 31 11 Device and Documentation Support ................. 32 11.1 11.2 11.3 11.4 11.5 Receiving Notification of Documentation Updates Community Resources.......................................... Trademarks ........................................................... Electrostatic Discharge Caution ............................ Glossary ................................................................ 32 32 32 32 32 12 Mechanical, Packaging, and Orderable Information ........................................................... 32 4 Revision History Changes from Revision A (May 2016) to Revision B • Page Added top navigator link for reference design; first public release of data sheet ................................................................. 1 Changes from Original (April 2016) to Revision A Page • Deleted min and max VOD_DE amplitude specification when VOD_DE = Level F ............................................................. 8 • Changed typical VOD_DE amplitude specifications for Levels F, R, and L .......................................................................... 8 • Changed DEM value and DEM register settings in Table 4 to match correct VOD_DE pin logic levels ............................. 14 • Added new row for VOD = 5, DEM = 5 setting in Table 9 .................................................................................................. 28 2 Submit Documentation Feedback Copyright © 2016–2018, Texas Instruments Incorporated Product Folder Links: LMH0324 LMH0324 www.ti.com SNLS531B – APRIL 2016 – REVISED JUNE 2018 5 Pin Configuration and Functions VIN VDD_LDO VDDIO SCK_SCL MISO_ADDR1 OUT_CTRL 24 23 22 21 20 19 RTW Package 24-Pin QFN Top View IN0+ 1 18 OUT0+ IN0- 2 17 OUT0- VSS 3 16 VSS RSV1 4 15 OUT1+ RSV2 5 14 OUT1- MODE_SEL 6 13 RSV_L LMH0324 8 9 10 11 12 IN_OUT_SEL VSS MOSI_SDA VOD_DE CD_N SS-N_ADDR0 7 EP = VSS Pin Functions PIN NAME NO. I/O (1) DESCRIPTION High Speed Differential I/Os IN0+ 1 I, Analog IN0- 2 I Analog RSV1 4 RSV2 5 OUT0+ 18 O, Analog OUT0- 17 O, Analog OUT1+ 15 O, Analog OUT1- 14 O, Analog Single-ended complementary inputs, 75-Ω internal termination from IN0+ or IN0- to internal common mode voltage and return loss compensation network. Requires external 4.7-µF AC coupling capacitors for SMPTE video applications. Reserved pins. Do not connect. Differential complementary outputs with 100-Ω internal termination. Requires external 4.7-µF AC coupling capacitors. Output driver OUT0± can be disabled under user control. Differential complementary outputs with 100-Ω internal termination. Requires external 4.7-µF AC coupling capacitors. Output driver OUT1± can be disabled under user control. Control Pins CD_N is the carrier detect. CD_N is pulled LOW when signal is detected and adaptation is completed. CD_N is an open drain output. It requires an external resistor to logic supply. CD_N is tolerant to 3.3 V when VDDIO is powered from 2.5 V supply. CD_N 12 O, LVCMOS, OD IN_OUT_SEL 8 I, 4-LEVEL IN_OUT_SEL selects the signal flow at input port IN0 to output ports. See Table 2 for details. This pin setting can be overridden by register control. OUT_CTRL 19 I, 4-LEVEL OUT_CTRL selects the equalized or un-equalized signal from IN0 to OUT0± and OUT1±. See Table 3 for details. This pin setting can be overridden by register control. VOD_DE 11 I, 4-LEVEL VOD_DE selects the driver output amplitude and de-emphasis level for both OUT0± and OUT1±. See Table 4 for details. This pin setting can be overridden by register control. MODE_SEL 6 I, 4-LEVEL MODE_SEL enables SPI or SMBus serial control interface. See Table 5 for details. (1) Note: I = Input, O=Output, IO=Input or Output, OD=Open Drain, LVCMOS=2-State Logic, 4-LEVEL=4-State Logic Submit Documentation Feedback Copyright © 2016–2018, Texas Instruments Incorporated Product Folder Links: LMH0324 3 LMH0324 SNLS531B – APRIL 2016 – REVISED JUNE 2018 www.ti.com Pin Functions (continued) PIN NAME NO. I/O (1) DESCRIPTION Serial Control Interface (SPI Mode), MODE_SEL = F (Float) SS_N 7 I, LVCMOS SS_N is the Slave Select. When SS_N is at logic Low, it enables SPI access to the LMH0324 slave device. SS_N is a LVCMOS input referenced to VDDIO. MISO 20 O, LVCMOS MISO is the SPI serial data output from the LMH0324 slave device. MISO is a LVCMOS output referenced to VDDIO. MOSI 10 I, LVCMOS MOSI is used as the SPI serial data input to the LMH0324 slave device. MOSI is LVCMOS input referenced to VDDIO. SCK 21 I, LVCMOS SCK is the SPI serial input clock to the LMH0324 slave device. SCK is LVCMOS referenced to VDDIO. Serial Control Interface (SMBus MODE) , MODE_SEL = L (1 kΩ to VSS) ADDR0 7 Strap, 4-LEVEL ADDR1 20 Strap, 4-LEVEL SDA 10 SCL IO, LVCMOS, OD ADDR[1:0] are SMBus address straps to select one of the 16 supported SMBus addresses. ADDR[1:0] are 4-level straps and are read into the device at power up. SMBus bi-directional open drain data line to or from the LMH0324 slave device. SDA is an open drain IO and requires an external 2 kΩ to 5 kΩ pull-up resistor to the SMBus termination voltage. SDA is 3.3 V tolerant when VDDIO is powered from 2.5 V. SMBus input clock to the LMH0324 slave device. It is driven by a LVCMOS open drain driver from the SMBus master. SCL requires an external 2 kΩ to 5 kΩ pull-up resistor to the SMBus termination voltage. SCL is 3.3 V tolerant when VDDIO is powered from 2.5 V. 21 I, LVCMOS, OD 3, 9, 16 I, Ground Ground reference. Power VSS VIN 24 I, Power VIN is connected to an external power supply. It accepts either 2.5 V ± 5% or 1.8 V ± 5%. When VIN is powered from 2.5 V, VDD_LDO is the output of an on-chip LDO regulator and requires a bypass capacitor to VSS. When VIN is powered from 1.8 V, for lower power operation, both VIN and VDD_LDO should be connected to 1.8 V supply. VDDIO 22 I, Power VDDIO powers the LVCMOS IO and 4-level input logic. VDDIO should be connected to 2.5 V ± 5% or 1.8 V ± 5%. VDDIO must always be greater than or equal to VIN. For SMBus access, VDDIO must be 2.5 V ± 5%. VDD_LDO is the output of the internal 1.8 V LDO regulator when VIN is connected to 2.5 V supply. VDD_LDO output requires external 1-µF and 0.1-µF bypass capacitors to VSS. The internal LDO is designed to power internal circuitry only. VDD_LDO is an input when VIN is powered from 1.8 V for lower power operation. When VIN is connected to a 1.8 V supply, both VIN and VDD_LDO should be connected to the 1.8 V supply. VDD_LDO 23 IO, Power RSV_L 13 I EP 4 I, Ground For pin compatibility with the LMH1219 (11.88 Gbps Ultra-HD adaptive cable equalizer with integrated reclocker), connect RSV_L to a 2.5 V supply with a 0.1-µF bypass capacitor. For low power operation, tie RSV_L to VSS. See Power Supply Recommendations for details. EP is the exposed pad at the bottom of the QFN package. The exposed pad must be connected to the ground plane through a via array. See Figure 26 for details. Submit Documentation Feedback Copyright © 2016–2018, Texas Instruments Incorporated Product Folder Links: LMH0324 LMH0324 www.ti.com SNLS531B – APRIL 2016 – REVISED JUNE 2018 6 Specifications 6.1 Absolute Maximum Ratings over operating free-air temperature range (unless otherwise noted) (1) MIN MAX UNIT Supply Voltage for 2.5-V Mode (VIN, VDDIO) –0.5 2.75 V Supply Voltage for 1.8-V Mode (VIN, VDD_LDO, VDDIO) –0.5 2.0 V 4-Level Input/Output Voltage for 2.5 V Supply (IN_OUT_SEL, OUT_CTRL, VOD_DE, MODE_SEL, ADDR0, ADDR1) –0.5 2.75 V 4-Level Input/Output Voltage for 1.8 V Supply (IN_OUT_SEL, OUT_CTRL, VOD_DE, MODE_SEL, ADDR0, ADDR1) -0.5 2.0 V (2) –0.5 4.0 V –0.5 2.75 V V SMBus Input/Output Voltage (SDA, SCL) SPI Input/Output Voltage for 2.5 V Supply (SS_N, MISO, MOSI, and SCK) SPI Input/Output Voltage for 1.8 V Supply (SS_N, MISO, MOSI, and SCK) -0.5 2.0 Input Voltage (IN0±) –0.5 2.75 V Input Current (IN0±) –30 30 mA 125 °C 150 °C Junction Temperature Storage temperature (1) (2) -65 Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. SDA and SCL is 3.3 V tolerant when VDDIO is 2.5 V. 6.2 ESD Ratings VALUE V(ESD) (1) (2) Electrostatic discharge Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001 (1) ±4500 Charged-device model (CDM), per JEDEC specification JESD22-C101 (2) ±1500 UNIT V JEDEC document JEP155 states that 500 V HBM allows safe manufacturing with a standard ESD control process. Manufacturing with less than 500 V HBM is possible with the necessary precautions. Pins listed as ±4500 V may actually have higher performance. JEDEC document JEP157 states that 250 V CDM allows safe manufacturing with a standard ESD control process. Manufacturing with less than 250 V CDM is possible with the necessary precautions. Pins listed as ±1500 V may actually have higher performance. 6.3 Recommended Operating Conditions over operating free-air temperature range (unless otherwise noted) 2.5 V Supplies VIN, VDDIO to VSS 1.8 V Supplies VIN, VDDIO , VDD_LDO to VSS VDDSMBUS SMBus: SDA, SCL Open Drain Termination Voltage, VDDIO = 2.5 V VLAUNCH MAX UNIT 2.5 2.625 V 1.71 1.8 1.89 V 3.6 V 2.375 0.72 0.8 0.88 Splitter Mode 0.36 0.4 0.44 –40 25 Operating Junction Temperature TAMBIENT Ambient Temperature (1) NOM Source Launch Amplitude before Coax TJUNCTION NPS (1) MIN 2.375 Supply Noise 50 Hz to 1 MHz, Sinusoidal