LMH0366SQX/NOPB

LMH0366 www.ti.com SNAS585D – APRIL 2012 – REVISED APRIL 2013 LMH0366 3 Gbps HD/SD SDI Low Power Reclocker with Integrated Eye Monitor Check for Samples: LMH0366 FEATURES DESCRIPTION • The LMH0366 3 Gbps HD/SD SDI Low Power Reclocker with Integrated Eye Monitor retimes serial digital video data conforming to the SMPTE ST 424, SMPTE ST 292, and SMPTE ST 259-C standards. The reclocker operates at serial data rates of 125 Mbps, 270 Mbps, 1.4835 Gbps, 1.485 Gbps, 2.967 Gbps, and 2.97 Gbps. 1 2 • • • • • • • • • • • • • SMPTE ST 424, SMPTE ST 292, and SMPTE ST 259-C Compliant Supports 125 Mbps, 270 Mbps, 1.4835 Gbps, 1.485 Gbps, 2.967 Gbps, and 2.97 Gbps Serial Data Rate Operation Supports DVB-ASI at 270 Mbps and MADI at 125 Mbps 100 mW Typical Power Consumption (145 mW with Both Output Drivers Enabled) Input Equalization (0-60” FR4) and Input Signal Detection Two Differential, Reclocked Outputs with Option of Recovered Clock Output De-Emphasis to Compensate for up to 40” of FR4 Trace Losses 64 x 64 Point Eye Opening Monitor 27 MHz External Reference or Referenceless Operation Internally Terminated 100Ω Input with Rail-toRail Input Common Mode Voltage Internally Terminated 100Ω LVDS Outputs with Programmable Output Common Mode Voltage and Swing Single 2.5V Supply Operation Power Save Mode with Device Power Down Control Industrial Temperature Range: -40°C to +85°C APPLICATIONS • • The LMH0366 automatically detects the data rate and retimes the data to accumulated jitter. The reclocker recovers data-rate clock and optionally provides output. incoming suppress the serial it as an The LMH0366 input has an FR4 equalizer capable of equalizing 0-60” of FR4 trace length, and also includes signal detection with a programmable threshold. The LMH0366 has two differential serial data outputs and offers flexibility in selecting the output signals between the reclocked data, recovered clock, or bypassed data. The output drivers offer programmable de-emphasis for up to 40” of FR4 trace losses, in addition to programmable common mode voltage and swing for flexible interfacing. The LMH0366 provides a 64 x 64 point eye monitor for analyzing the eye quality of the incoming signal. The LMH0366 supports two modes of operation. In pin mode, the LMH0366 operates with control pins to set its operating state. In SPI mode, an optional SPI serial interface can be used to configure and monitor multiple LMH0366 devices in a daisy-chain configuration. SMPTE ST 424, SMPTE ST 292, and ST SMPTE 259 Serial Digital Interfaces Broadcast Video Routers, Switchers, and Distribution Amplifiers TYPICAL APPLICATION LMH0394 Cable Equalizer LMH0366 Reclocker LMH030x Cable Driver 1 2 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. All trademarks are the property of their respective owners. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright © 2012–2013, Texas Instruments Incorporated LMH0366 SNAS585D – APRIL 2012 – REVISED APRIL 2013 www.ti.com Block Diagram SPI Interface Control Pins Control Logic Eye Monitor Recovered Clock Bypassed Data SDI Clock and Data Recovery FR4 EQ SDO1 Output Select SDO1 SDO0 Output Select SDO0 Reclocked Data Bypassed Data LF1 VEE 23 22 21 20 SCO_EN LF2 24 VEE RATE0 Connection Diagram 19 RATE1 1 18 SD/HD SDI 2 17 SDO0 SDI 3 16 SDO0 ENABLE 4 15 VCC BYPASS 5 14 SDO1 MUTE 6 13 SDO1 7 8 9 10 11 12 SPI_EN XTAL_IN VEE XTAL_OUT LOCK_DETECT VEE LMH0366 (top view) DAP = VEE Figure 1. Pin Mode (non-SPI) / SPI_EN = GND 2 Submit Documentation Feedback Copyright © 2012–2013, Texas Instruments Incorporated Product Folder Links: LMH0366 LMH0366 LF2 LF1 VEE MISO SS SNAS585D – APRIL 2012 – REVISED APRIL 2013 GPIO0 www.ti.com 24 23 22 21 20 19 GPIO1 1 18 SD/HD SDI 2 17 SDO0 SDI 3 16 SDO0 ENABLE 4 15 VCC MOSI 5 14 SDO1 SCK 6 13 SDO1 7 8 9 10 11 12 SPI_EN XTAL_IN VEE XTAL_OUT LOCK_DETECT VEE LMH0366 (top view) DAP = VEE The exposed die attach pad is the primary negative electrical terminal for this device. It must be connected to the negative power supply voltage. Figure 2. SPI Mode / SPI_EN = VCC 24-Pin See Package Number RTW0024A PIN DESCRIPTIONS – PIN MODE (NON-SPI) / SPI_EN = GND Pin Name I/O, Type Description 1, 24 RATE1, RATE0 I, LVCMOS Data rate select inputs. RATE0 and RATE1 each has an internal pulldown. 2, 3 SDI, SDI I, SDI Serial data differential input. 4 ENABLE I, LVCMOS Device enable. This pin has an internal pullup. H = Device enabled (normal operation). L = Device powered down. 5 BYPASS I, LVCMOS Reclocker bypass. This pin has an internal pulldown. H = Reclocking bypassed. L = Normal operation. 6 MUTE I, LVCMOS Output mute. This pin has an internal pullup. H = Normal operation. L = SDO0 and SDO1 outputs are muted. 7 SPI_EN I, LVCMOS SPI register access enable. This pin has an internal pulldown. H = SPI register access mode. L = Pin mode. 8 XTAL_IN I, ANALOG External crystal or clock input for optional 27 MHz external reference. When not used (i.e. referenceless mode), connect to ground. 10 XTAL_OUT O, ANALOG External crystal or clock output. 11 LOCK_DETECT O, LVCMOS PLL lock detect status. H = PLL locked. L = PLL not locked. 13, 14 SDO1, SDO1 O, LVDS Serial data differential output 1. 16, 17 SDO0, SDO0 O, LVDS Serial data differential output 0. SD/HD O, LVCMOS Data rate range indication. H = Locked data rate is SD. L = Locked data rate is 3G or HD (or PLL unlocked). 18 Submit Documentation Feedback Copyright © 2012–2013, Texas Instruments Incorporated Product Folder Links: LMH0366 3 LMH0366 SNAS585D – APRIL 2012 – REVISED APRIL 2013 www.ti.com PIN DESCRIPTIONS – PIN MODE (NON-SPI) / SPI_EN = GND (continued) Pin Name I/O, Type Description 19 SCO_EN I, LVCMOS Serial clock output enable for SDO1. This pin has an internal pulldown. H = SDO1 output is serial clock. L = SDO1 output is serial data. 22, 23 LF1, LF2 I, Analog Loop filter. Connect a 56 nF capacitor between LF1 and LF2. 15 VCC Power Positive power supply (2.5V). DAP, 9, 12, 20, 21 VEE Ground Negative power supply (ground). Name I/O, Type Description 1, 24 GPIO1, GPIO0 I/O, LVCMOS General purpose input/output pins, selectable via the SPI. Pins 24 and 1 will operate as RATE0 and RATE1 inputs (the same as while in pin mode), with internal pulldowns, unless configured differently via the SPI. 2, 3 SDI, SDI I, SDI Serial data differential input. 4 ENABLE I, LVCMOS Device enable. This pin has an internal pullup. H = Device enabled (normal operation). L = Device powered down. 5 MOSI (SPI) I, LVCMOS SPI master output / slave input. LMH0366 data receive. This pin has an internal pullup. 6 SCK (SPI) I, LVCMOS SPI serial clock input. 7 SPI_EN I, LVCMOS SPI register access enable. This pin has an internal pulldown. H = SPI register access mode. L = Pin mode. 8 XTAL_IN I, ANALOG External crystal or clock input for optional 27 MHz external reference. When not used (i.e. referenceless mode), connect to ground. 10 XTAL_OUT O, ANALOG External crystal or clock output. 11 LOCK_DETECT O, LVCMOS PLL lock detect status. H = PLL locked. L = PLL not locked. 13, 14 SDO1, SDO1 O, LVDS Serial data differential output 1. 16, 17 SDO0, SDO0 O, LVDS Serial data differential output 0. 18 SD/HD O, LVCMOS Data rate range indication. H = Locked data rate is SD. L = Locked data rate is 3G or HD (or PLL unlocked). 19 SS (SPI) I, LVCMOS SPI slave select. This pin has an internal pullup. 20 MISO (SPI) O, LVCMOS SPI master input / slave output. LMH0366 data transmit. LF1, LF2 I, Analog Loop filter. Connect a 56 nF capacitor between LF1 and LF2. VCC Power Positive power supply (2.5V). Ground Negative power supply (ground). PIN DESCRIPTIONS – SPI MODE / SPI_EN = VCC Pin 22, 23 15 DAP, 9, 12, 21 VEE These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates. 4 Submit Documentation Feedback Copyright © 2012–2013, Texas Instruments Incorporated Product Folder Links: LMH0366 LMH0366 www.ti.com Absolute Maximum Ratings SNAS585D – APRIL 2012 – REVISED APRIL 2013 (1) (2) Supply Voltage (VCC) 3.1V −0.3V to VCC+0.3V Input Voltage (any input) −65°C to +150°C Storage Temperature Range Junction Temperature +125°C Package Thermal Resistance θJA 24-pin WQFN 42.7°C/W θJC 24-pin WQFN 8.7°C/W ESD Ratings HBM (std: JESD22-A114-F) ≥±6 kV MM (std: JESD22-A115-C) ≥±250V ≥±1250V CDM (std: JESD22-C101-E) (1) (2) “Absolute Maximum Ratings” indicate limits beyond which damage to the device my occur, including inoperability and degradation of device reliability and/or performance. Functional operation of the device and/or non-degradation at the Absolute Maximum Ratings or other conditions beyond those indicated in the Recommended Operating Conditions is not implied. The Recommended Operating Conditions indicate conditions at which the device is functional and the device should not be operated beyond such conditions. If Military/Aerospace specified devices are required, please contact the Texas Instruments Sales Office/Distributors for availability and specifications. Recommended Operating Conditions Supply Voltage (VCC) 2.5V ±5% Input Voltage 0V to VCC −40°C to +85°C Operating Free Air Temperature (TA) DC Electrical Characteristics Over recommended supply voltage and operating temperature ranges, unless otherwise specified. Symbol Parameter Conditions Logic inputs Max Units V Input Voltage High Level 1.7 VCC Input Voltage Low Level VEE 0.7 V IIN Input Current −55 55 µA VOH Output Voltage High Level IOH = −2 mA VOL Output Voltage Low Level IOL = +2 mA (3) VCMI Input Common Mode Voltage (3) VSSP-P VOD ΔVOD VOS ΔVOS IOS (3) (4) Typ VIL Serial Input Voltage, Differential (2) Min VIH VSDID (1) Reference (1) (2) Differential Output Voltage, P-P Differential Output Voltage 100Ω load, default register settings (4), Figure 3 Logic outputs 2.0 0.2 V SDI 200 1600 mVP-P 0 VCC V SDO0, SDO1 V 700 800 1000 mVP-P 350 400 500 mVP-P 50 mV Change in Magnitude of VOD for Complimentary Output States Offset Voltage 1.375 V Change in Magnitude of VOS for Complimentary Output States 1.1 1.2 50 mV Output Short Circuit Current 30 mA The Electrical Characteristics tables list ensured specifications under the listed Recommended Operating Conditions except as otherwise modified or specified by the Electrical Characteristics Conditions and/or Notes. Typical specifications are estimations only and are not ensured. Typical values represent most likely parametric norms at VCC = +2.5V, TA = +25°C, and at the Recommended Operating Conditions at the time of product characterization and are not ensured. Specification is ensured by characterization and is not tested in production. The differential output voltage and offset voltage are adjustable via the SPI. Submit Documentation Feedback Copyright © 2012–2013, Texas Instruments Incorporated Product Folder Links: LMH0366 5 LMH0366 SNAS585D – APRIL 2012 – REVISED APRIL 2013 www.ti.com DC Electrical Characteristics (continued) Over recommended supply voltage and operating temperature ranges, unless otherwise specified. (1)(2) Symbol ICC Parameter Conditions Supply Current Normal operation, two output drivers Reference Min Normal operation, one output driver and low power settings (5) Device disabled (ENABLE = 0) (5) Typ Max Units 58 75 mA 40 55 mA 7 14 mA Low power mode with one output driver is achieved by powering down the second output driver, setting the amplitude of the active output driver to the lowest setting, disabling input signal detection, and disabling signal detection and equalization for input channels not present on the LMH0366. This can be configured with the following SPI register settings: write “1” to register 0x20 bit 7 (SIG_DET_PRESET) to force the reclocker to assume an input signal is present (so input signal detection can be turned off), write “1” to register 0x11 bit 3 (SDO1_PD) to power down the SDO1 output driver, write “00” to register 0x12 bits 7:6 (SDO0_VOD) to set the SDO0 VOD to 400 mVP-P, and write “11111110” (0xFE) to register 0x15 to power down the input signal detection as well as power down the signal detection and the equalization for input channels not present on the LMH0366. AC Electrical Characteristics Over recommended supply voltage and operating temperature ranges, unless otherwise specified. Symbol DRSDI TOLJIT Parameter Serial Input Data Rate (for reclocking) Conditions MADI Reference Min (1) (2) Typ SDI Max 125 Mbps 270 Mbps SMPTE ST 292 1483.5, 1485 Mbps SMPTE ST 424 2967, 2970 Mbps SMPTE ST 259-C, DVB-ASI (3) (4) (5) Serial Input Jitter Tolerance > UIP-P 6 (3) (4) (6) tJIT Serial Data Output Intrinsic Jitter 270 Mbps >0.6 (3) SDO0, SDO1 0.02 UIP-P 0.02 0.05 UIP-P (3) 0.04 0.1 UIP-P 270 Mbps,