LMH0376SQ/NOPB

LMH0376 www.ti.com SNAS583A – APRIL 2012 – REVISED JULY 2013 LMH0376 3 Gbps HD/SD SDI Low Power Reclocker with Integrated Eye Monitor and 4:1 Input Mux Check for Samples: LMH0376 FEATURES DESCRIPTION • The LMH0376 3 Gbps HD/SD SDI Low Power Reclocker with Integrated Eye Monitor and 4:1 Input Mux retimes serial digital video data conforming to the SMPTE ST 424, SMPTE ST 292, and SMPTE ST 259-C standards. The reclocker operates at serial data rates of 125 Mbps, 270 Mbps, 1.4835 Gbps, 1.485 Gbps, 2.967 Gbps, and 2.97 Gbps. 1 • • • • • • • • • • • • • • • SMPTE ST 424, SMPTE ST 292, and SMPTE ST 259-C Compliant Supports 125 Mbps, 270 Mbps, 1.4835 Gbps, 1.485 Gbps, 2.967 Gbps, and 2.97 Gbps Serial Data Rate Operation Supports DVB-ASI at 270 Mbps and MADI at 125 Mbps 100 mW Typical Power Consumption (145 mW with Both Output Drivers Enabled) Integrated 4:1 Multiplexed Input with 0-60” FR4 Equalizer and Independent Signal Detect on Each Channel Two Differential, Reclocked Outputs with Option of Recovered Clock Output De-Emphasis to Compensate for up to 40” of FR4 Trace Losses 64 x 64 Point Eye Opening Monitor 27 MHz External Reference or Reference-less Operation Internally Terminated 100Ω Inputs with Rail-toRail Input Common Mode Voltage Internally Terminated 100Ω LVDS Outputs with Programmable Output Common Mode Voltage and Swing Single 2.5V Supply Operation Power Save Mode with Device Power Down Control 48-Pin WQFN Package (7 x 7 mm) Industrial Temperature Range: -40°C to +85°C Footprint Compatible with the LMH0356 in Pin Mode APPLICATIONS • • The LMH0376 automatically detects the data rate and retimes the data to accumulated jitter. The reclocker recovers data-rate clock and optionally provides output. incoming suppress the serial it as an The LMH0376 includes an integrated 4:1 input multiplexer for selecting one of four input data streams for retiming. Each of the four inputs has an FR4 equalizer capable of equalizing 0-60” of FR4 trace length. Each input also includes independent signal detection with a programmable threshold. The LMH0376 has two differential serial data outputs and offers flexibility in selecting the output signals between the reclocked data, recovered clock, bypassed data, or the bypassed data from an independently selected input channel. The output drivers offer programmable de-emphasis for up to 40” of FR4 trace losses, in addition to programmable common mode voltage and swing for flexible interfacing. The LMH0376 provides a 64 x 64 point eye monitor for analyzing the eye quality of the incoming signal. The LMH0376 supports two modes of operation. In pin mode, the LMH0376 operates with control pins to set its operating state, and is footprint compatible with the LMH0356 reclocker. In SPI mode, an optional SPI serial interface can be used to configure and monitor multiple LMH0376 devices in a daisy-chain configuration. SMPTE ST 424, SMPTE ST 292, and SMPTE ST 259 Serial Digital Interfaces Broadcast Video Routers, Switchers, and Distribution Amplifiers 1 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright © 2012–2013, Texas Instruments Incorporated LMH0376 SNAS583A – APRIL 2012 – REVISED JULY 2013 www.ti.com Typical Application LMH030x Cable Driver LMH0395 Equalizer LMH0376 Reclocker LMH030x Cable Driver LMH0395 Equalizer LMH030x Cable Driver LMH0395 Equalizer LMH0376 Reclocker LMH030x Cable Driver LMH0395 Equalizer SVA-30149001 Block Diagram SPI Interface Control Pins Control Logic Eye Monitor Secondary Input Select FR4 EQ SDI1 FR4 EQ SDI2 FR4 EQ SDI3 FR4 EQ Primary Input Select Reclocked Data SDI0 Recovered Clock Bypassed Data Clock and Data Recovery SDO1 Output Select SDO1 SDO0 Output Select SDO0 Bypassed Data SVA-30149003 2 Submit Documentation Feedback Copyright © 2012–2013, Texas Instruments Incorporated Product Folder Links: LMH0376 LMH0376 www.ti.com SNAS583A – APRIL 2012 – REVISED JULY 2013 43 42 41 40 39 38 SCO_EN LF1 44 VEE LF2 45 VEE RATE0 46 VEE RATE1 47 VEE SEL0 48 VEE SEL1 Connection Diagrams 37 SDI0 1 36 SD/HD SDI0 2 35 VCC VCC 3 34 VCC SDI1 4 33 SDO0 SDI1 5 32 SDO0 VCC 6 31 VCC SDI2 7 30 VCC SDI2 8 29 SDO1 ENABLE 9 28 SDO1 SDI3 10 27 VEE SDI3 11 26 VEE VCC 12 25 VEE 13 14 15 16 17 18 19 20 21 22 23 24 VEE VCC BYPASS MUTE SPI_EN XTAL_IN VEE VEE VEE XTAL_OUT VEE LOCK_DETECT LMH0376SQ (top view) DAP = VEE SVA-30149002 Figure 1. Pin Mode (non-SPI) / SPI_EN = GND / LMH0356 Compatible Submit Documentation Feedback Copyright © 2012–2013, Texas Instruments Incorporated Product Folder Links: LMH0376 3 LMH0376 43 42 41 40 39 SS 44 MISO LF1 45 VEE LF2 46 VEE GPIO0 47 VEE GPIO1 48 VEE GPIO2 www.ti.com GPIO3 SNAS583A – APRIL 2012 – REVISED JULY 2013 38 37 SDI0 1 36 SD/HD SDI0 2 35 VCC VCC 3 34 VCC SDI1 4 33 SDO0 SDI1 5 32 SDO0 VCC 6 31 VCC SDI2 7 30 VCC SDI2 8 29 SDO1 ENABLE 9 28 SDO1 SDI3 10 27 VEE SDI3 11 26 VEE VCC 12 25 VEE 13 14 15 16 17 18 19 20 21 22 23 24 VEE VCC MOSI SCK SPI_EN XTAL_IN VEE VEE VEE XTAL_OUT VEE LOCK_DETECT LMH0376SQ (top view) DAP = VEE SVA-30149013 NOTE: The exposed die attach pad is the primary negative electrical terminal for this device. It must be connected to the negative power supply voltage. Figure 2. SPI Mode / SPI_EN = VCC 48-Pin WQFN See Package Number RHS 48 4 Submit Documentation Feedback Copyright © 2012–2013, Texas Instruments Incorporated Product Folder Links: LMH0376 LMH0376 www.ti.com SNAS583A – APRIL 2012 – REVISED JULY 2013 Table 1. PIN DESCRIPTIONS – Pin Mode (non-SPI) / SPI_EN = GND / LMH0356 Compatible Pin Name I/O, Type Description 1, 2 SDI0, SDI0 I, SDI Serial data differential input 0. 4, 5 SDI1, SDI1 I, SDI Serial data differential input 1. 7, 8 SDI2, SDI2 I, SDI Serial data differential input 2. ENABLE I, LVCMOS Device enable. This pin has an internal pullup. H = Device enabled (normal operation). L = Device powered down. 9 10, 11 SDI3, SDI3 I, SDI Serial data differential input 3. 15 BYPASS I, LVCMOS Reclocker bypass. This pin has an internal pulldown. H = Reclocking bypassed. L = Normal operation. 16 MUTE I, LVCMOS Output mute. This pin has an internal pullup. H = Normal operation. L = SDO0 and SDO1 outputs are muted. 17 SPI_EN I, LVCMOS SPI register access enable. This pin has an internal pulldown. H = SPI register access mode. L = Pin mode. 18 XTAL_IN I, ANALOG External crystal or clock input for optional 27 MHz external reference. When not used (i.e. referenceless mode), connect to ground. 22 XTAL_OUT O, ANALOG External crystal or clock output. 24 LOCK_DETECT O, LVCMOS PLL lock detect status. H = PLL locked. L = PLL not locked. 28, 29 SDO1, SDO1 O, LVDS Serial data differential output 1. 32, 33 SDO0, SDO0 O, LVDS Serial data differential output 0. 36 SD/HD O, LVCMOS Data rate range indication. H = Locked data rate is SD. L = Locked data rate is 3G or HD (or PLL unlocked). 37 SCO_EN I, LVCMOS Serial clock output enable for SDO1. This pin has an internal pulldown. H = SDO1 output is serial clock. L = SDO1 output is serial data. 43, 44 LF1, LF2 I, Analog Loop filter. Connect a 56 nF capacitor between LF1 and LF2. 45, 46 RATE0, RATE1 I, LVCMOS Data rate select inputs. RATE0 and RATE1 each has an internal pulldown. 47, 48 SEL0, SEL1 I, LVCMOS Input channel select inputs. SEL0 and SEL1 each has an internal pulldown. VCC Power Positive power supply (2.5V). Ground Negative power supply (ground). 3, 6, 12, 14, 30, 31, 34, 35 DAP, 13, 19, 20, VEE 21, 23, 25, 26, 27, 38, 39, 40, 41, 42 Submit Documentation Feedback Copyright © 2012–2013, Texas Instruments Incorporated Product Folder Links: LMH0376 5 LMH0376 SNAS583A – APRIL 2012 – REVISED JULY 2013 www.ti.com Table 2. PIN DESCRIPTIONS – SPI Mode / SPI_EN = VCC Pin Name I/O, Type Description 1, 2 SDI0, SDI0 I, SDI Serial data differential input 0. 4, 5 SDI1, SDI1 I, SDI Serial data differential input 1. 7, 8 SDI2, SDI2 I, SDI Serial data differential input 2. ENABLE I, LVCMOS Device enable. This pin has an internal pullup. H = Device enabled (normal operation). L = Device powered down. 10, 11 SDI3, SDI3 I, SDI Serial data differential input 3. 15 MOSI (SPI) I, LVCMOS SPI master output / slave input. LMH0376 data receive. This pin has an internal pullup. 16 SCK (SPI) I, LVCMOS SPI serial clock input. 17 SPI_EN I, LVCMOS SPI register access enable. This pin has an internal pulldown. H = SPI register access mode. L = Pin mode. 18 XTAL_IN I, ANALOG External crystal or clock input for optional 27 MHz external reference. When not used (i.e. referenceless mode), connect to ground. 22 XTAL_OUT O, ANALOG External crystal or clock output. 24 LOCK_DETECT O, LVCMOS PLL lock detect status. H = PLL locked. L = PLL not locked. 28, 29 SDO1, SDO1 O, LVDS Serial data differential output 1. 32, 33 SDO0, SDO0 O, LVDS Serial data differential output 0. 36 SD/HD O, LVCMOS Data rate range indication. H = Locked data rate is SD. L = Locked data rate is 3G or HD (or PLL unlocked). 37 SS (SPI) I, LVCMOS SPI slave select. This pin has an internal pullup. 38 MISO (SPI) O, LVCMOS SPI master input / slave output. LMH0376 data transmit. LF1, LF2 I, Analog Loop filter. Connect a 56 nF capacitor between LF1 and LF2. GPIO0, GPIO1, GPIO2, GPIO3 I/O, LVCMOS General purpose input/output pins, selectable via the SPI. Pins 45-48 will operate as RATE0, RATE1, SEL0, and SEL1 inputs (the same as while in pin mode), with internal pulldowns, unless configured differently via the SPI. VCC Power Positive power supply (2.5V). Ground Negative power supply (ground). 9 43, 44 45, 46, 47, 48 3, 6, 12, 14, 30, 31, 34, 35 DAP, 13, 19, 20, VEE 21, 23, 25, 26, 27, 39, 40, 41, 42 6 Submit Documentation Feedback Copyright © 2012–2013, Texas Instruments Incorporated Product Folder Links: LMH0376 LMH0376 www.ti.com SNAS583A – APRIL 2012 – REVISED JULY 2013 These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates. ABSOLUTE MAXIMUM RATINGS (1) (2) MIN MAX Supply Voltage, VCC UNIT 3.1 V Input Voltage (any input) –0.3 VCC + 0.3 V Storage Temperature Range –65 150 °C Junction Temperature Package Thermal Resistance θJA 48-pin WQFN θJC 48-pin WQFN ESD Rating (2) °C 31.3 °C/W 8.5 °C/W HBM, STD - JESD22-A114F ≥ ±6 kV MM, STD - JESD22-A115-A ≥ ±250 V ≥ ±1250 V CDM, STD - JESD22-C101-D (1) 125 "Absolute Maximum Ratings” indicate limits beyond which damage to the device may occur, including inoperability and degradation of device reliability and/or performance. Functional operation of the device and/or non-degradation at the Absolute Maximum Ratings or other conditions beyond those indicated in the Recommended Operating Conditions is not implied. If Military/Aerospace specified devices are required, please contact the Texas Instruments Sales Office/Distributors for availability and specifications. RECOMMENDED OPERATING CONDITIONS (1) Supply Voltage, VCC Input Voltage NOM MAX UNIT 2.5 2.625 V VCC V 85 °C 0 Operating Free Air Temperature, TA (1) MIN 2.375 –40 25 The Recommended Operating Conditions indicate conditions at which the device is functional and the device should not be operated beyond such conditions. Absolute Maximum Numbers are ensured for a junction temperature range of -40°C to +125°C. Models are validated to Maximum Operating Voltages only. Submit Documentation Feedback Copyright © 2012–2013, Texas Instruments Incorporated Product Folder Links: LMH0376 7 LMH0376 SNAS583A – APRIL 2012 – REVISED JULY 2013 www.ti.com DC ELECTRICAL CHARACTERISTICS Over recommended supply voltage and operating temperature ranges, unless otherwise specified. (1) (2) Symbol Parameter VIH Input Voltage High Level VIL Input Voltage Low Level IIN Input Current −55 VOH Output Voltage High Level IOH = −2 mA VOL Output Voltage Low Level IOL = +2 mA VSDID Serial Input Voltage, Differential See (3) VCMI Input Common Mode Voltage See (3) RIN Input Termination Resistor Between SDI and SDI (4) VSSP-P Differential Output Voltage, P-P VOD Differential Output Voltage 100Ω load, default register settings (5), Figure 3 ΔVOD Change in Magnitude of VOD for Complimentary Output States VOS Offset Voltage ΔVOS Change in Magnitude of VOS for Complimentary Output States IOS Output Short Circuit Current ICC Supply Current (1) (2) (3) (4) (5) (6) 8 Conditions Reference Logic inputs Min Typ Max Units 1.7 VCC V VEE 0.7 V 55 µA Logic outputs 2.0 V 0.2 V SDI0, SDI1, SDI2, SDI3 200 1600 mVP-P 0 VCC V Ω 100 SDO0, SDO1 700 800 1000 mVP-P 350 400 500 mVP-P 50 mV 1.375 V 50 mV 1.1 1.2 30 mA Normal operation, two output drivers 58 75 mA Normal operation, one output driver and low power settings (6) 40 55 mA Device disabled (ENABLE = 0) 7 14 mA The Electrical Characteristics tables list ensures specifications under the listed Recommended Operating Conditions except as otherwise modified or specified by the Electrical Characteristics Conditions and/or Notes. Typical specifications are estimations only. Typical values represent most likely parametric norms at VCC = +2.5V, TA = +25°C, and at the Recommended Operating Conditions at the time of product characterization and are not specified. Specified by characterization and not tested in production. The LMH0376 provides an integrated 100Ω input termination resistor for each serial data input pair. The differential output voltage and offset voltage are adjustable via the SPI. Low power mode with one output driver is achieved by powering down the second output driver, setting the amplitude of the active output driver to the lowest setting, disabling signal detection for all input channels, and disabling equalization for all input channels except SDI0. This can be configured with the following SPI register settings: write “1” to register 0x20 bit 7 (SIG_DET_PRESET) to force the reclocker to assume an input signal is present (so input signal detection can be turned off), write “1” to register 0x11 bit 3 (SDO1_PD) to power down the SDO1 output driver, write “00” to register 0x12 bits 7:6 (SDO0_VOD) to set the SDO0 VOD to 400 mVP–P, and write “11111110” (0xFE) to register 0x15 to power down the input signal detection for all input channels and power down the input equalization for all input channels except SDI0. Submit Documentation Feedback Copyright © 2012–2013, Texas Instruments Incorporated Product Folder Links: LMH0376 LMH0376 www.ti.com SNAS583A – APRIL 2012 – REVISED JULY 2013 AC ELECTRICAL CHARACTERISTICS Over recommended supply voltage and operating temperature ranges, unless otherwise specified. (1) (2) Symbol Parameter Conditions Reference DRSDI Serial Input Data Rate (for reclocking) MADI SDI0, SDI1, SDI2, SDI3 TOLJIT tJIT Serial Input Jitter Tolerance Serial Data Output Intrinsic Jitter BWLOOP FCO Loop Bandwidth Serial Clock Output Frequency Min Typ Max Units 125 Mbps 270 Mbps SMPTE ST 292 1483.5, 1485 Mbps SMPTE ST 424 2967, 2970 Mbps SMPTE ST 259-C, DVB-ASI See (3) (4) (5) See (3) (4) (6) 270 Mbps (3) >6 UIP-P >0.6 UIP-P 0.01 0.02 UIP-P 1483.5 or 1485 Mbps (3) 0.02 0.05 UIP-P 2967 or 2970 Mbps (3) 0.04 0.1 UIP-P 270 Mbps,