LMH1981MTX/NOPB

LMH1981 www.ti.com SNLS214H – APRIL 2006 – REVISED MARCH 2013 LMH1981 Multi-Format Video Sync Separator Check for Samples: LMH1981 FEATURES DESCRIPTION • The LMH1981 is a high performance multi-format sync separator ideal for use in a wide range of video applications, such as broadcast and professional video equipment and HDTV/DTV systems. 1 2 • • • • • • • Standard Analog Video Sync Separation for NTSC, PAL, 480I/P, 576I/P, 720P, and 1080I/P/PsF from Composite Video (CVBS), S-Video (Y/C), and Component Video (YPBPR/GBR) Interfaces Bi-Level & Tri-Level Sync Compatible Composite, Horizontal, and Vertical Sync Outputs Burst/Back Porch Timing, Odd/Even Field, and Video Format Outputs Superior Jitter Performance on Leading Edge of HSync Automatic Video Format Detection 50% Sync Slicing for Video Inputs from 0.5 VPP to 2 VPP 3.3V to 5V Supply Operation APPLICATIONS • • • • • • Broadcast and Professional Video Equipment HDTV/DTV Systems Genlock Circuits Video Capture Devices Set-Top Boxes (STB) & Digital Video Recorders (DVR) Video Displays The input accepts standard analog SD/ED/HD video signals with either bi-level or tri-level sync, and the outputs provide all of the critical timing signals in CMOS logic, which swing from rail-to-rail (VCC and GND) including Composite, Horizontal, and Vertical Syncs, Burst/Back Porch Timing, Odd/Even Field, and Video Format Outputs. HSync features very low jitter on its leading (falling) edge, minimizing external circuitry needed to clean and reduce jitter in subsequent clock generation stages. The LMH1981 automatically detects the input video format, eliminating the need for programming using a microcontroller, and applies precise 50% sync slicing to ensure accurate sync extraction at OH, even for inputs with irregular amplitude from improper termination or transmission loss. Its unique Video Format Output conveys the total horizontal line count per field as an 11-bit binary serial data stream, which can be decoded by the video system to determine the input video format and enable dynamic adjustment of system parameters, i.e.: color space or scaler conversions. The LMH1981 is available in a 14-pin TSSOP package and operates over a temperature range of −40°C to +85°C. Connection Diagram REXT 1 14 OEOUT GND 2 13 BPOUT VCC1 3 12 CSOUT VIN 4 GND 5 10 GND VCC2 6 9 VFOUT HSOUT 7 8 VSOUT LMH1981 11 VCC3 Figure 1. 14-Pin TSSOP - Top View See PW Package 1 2 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. All trademarks are the property of their respective owners. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright © 2006–2013, Texas Instruments Incorporated LMH1981 SNLS214H – APRIL 2006 – REVISED MARCH 2013 www.ti.com PIN DESCRIPTIONS Pin No. Pin Name Pin Description 1 REXT Bias Current External Resistor 2, 5, 10 GND Ground 3, 6, 11 VCC Supply Voltage 4 VIN Video Input 7 HSOUT Horizontal Sync Output 8 VSOUT Vertical Sync Output 9 VFOUT Video Format Output 12 CSOUT Composite Sync Output 13 BPOUT Burst/Back Porch Timing Output 14 OEOUT Odd/Even Field Output These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates. Absolute Maximum Ratings ESD Tolerance (4) (1) (2) (3) Human Body Model Machine Model Charge-Device Model Supply Voltage, VCC −65°C to +150°C Lead Temperature (soldering 10 sec.) Junction Temperature (TJMAX) 300°C (5) +150°C Thermal Resistance (θJA) (4) (5) 52°C/W Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for which the device is intended to be functional, but specific performance is not ensured. For ensured specifications and the test conditions, see the Electrical Characteristics Tables. All voltages are measured with respect to GND, unless otherwise specified. If Military/Aerospace specified devices are required, please contact the Texas Instruments Sales Office/ Distributors for availability and specifications. Human Body Model, applicable std. MIL-STD-883, Method 3015.7. Machine Model, applicable std. JESD22-A115-A (ESD MM std. of JEDEC)Field-Induced Charge-Device Model, applicable std. JESD22-C101-C (ESD FICDM std. of JEDEC). The maximum power dissipation is a function of TJ(MAX), θJA. The maximum allowable power dissipation at any ambient temperature is PD = (TJ(MAX) - TA)/θJA . All numbers apply for packages soldered directly onto a PC board. Operating Ratings Temperature Range (1) (2) −40°C to +85°C 3.3V −5% to 5V +5% VCC Input Amplitude, VIN-AMPL (1) (2) 2 1.0 kV −0.3V to VCC + 0.3V Storage Temperature Range (2) (3) 350V 0V to 5.5V Video Input, VIN (1) 3.5 kV 140 mV to VCC–VIN-CLAMP Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for which the device is intended to be functional, but specific performance is not ensured. For ensured specifications and the test conditions, see the Electrical Characteristics Tables. The maximum power dissipation is a function of TJ(MAX), θJA. The maximum allowable power dissipation at any ambient temperature is PD = (TJ(MAX) - TA)/θJA . All numbers apply for packages soldered directly onto a PC board. Submit Documentation Feedback Copyright © 2006–2013, Texas Instruments Incorporated Product Folder Links: LMH1981 LMH1981 www.ti.com SNLS214H – APRIL 2006 – REVISED MARCH 2013 Electrical Characteristics (1) Unless otherwise specified, all limits are ensured for TA = 25°C, VCC = VCC1 = VCC2 = VCC3 = 3.3V, REXT = 10 kΩ 1%, RL = 10 kΩ, CL < 10 pF.Boldface limits apply at the temperature extremes. See Figure 2. Symbol ICC Parameter Supply Current Conditions No input signal Min (2) Typ (3) Max (2) VCC = 3.3V 9.5 11.5 VCC = 5V 11 13.5 Units mA Video Input Specifications VIN-SYNC Input Sync Amplitude Amplitude from negative sync tip to video blanking level for SD/EDTV bi-level sync 0.14 0.30 0.60 Amplitude from negative to positive sync tips for HDTV tri-level sync (4) (7) (6) 0.30 0.60 1.20 (4) (5) (6) VIN-CLAMP Input Sync Tip Clamp Level VIN-SLICE Input Sync Slice Level Logic Output Specifications VOL Level between video blanking & sync tip for SD/EDTV and between negative & positive sync tips for HDTV 0.7 V 50 % (8) Output Logic 0 VOH VPP Output Logic 1 See output load conditions above VCC = 3.3V 0.3 VCC = 5V 0.5 See output load conditions above VCC = 3.3V 3.0 VCC = 5V 4.5 V V TSYNC-LOCK Sync Lock Time Time for the output signals to be correct after the video signal settles at VIN following a significant input change. See START-UP TIME for more information 2 V periods TVSOUT Vertical Sync Output Pulse Width See Figure 3, Figure 4, Figure 5, Figure 6, Figure 7, and Figure 8 for SDTV, EDTV & HDTV Vertical Interval Timing 3 H periods (1) (2) (3) (4) (5) (6) (7) (8) Electrical Table values apply only for factory testing conditions at the temperature indicated. Factory testing conditions result in very limited self-heating of the device such that TJ = TA. No ensured specification of parametric performance is indicated in the electrical tables under conditions of internal self-heating where TJ > TA. Limits are 100% production tested at 25°C. Limits over the operating temperature range are ensured through correlations using the Statistical Quality Control (SQC) method. Typical values represent the most likely parametric norm at the time of characterization. Actual typical values may vary over time and will also depend on the application and configuration. The typical values are not tested and are not ensured on shipped production material. VIN-AMPL plus VIN-CLAMP should not exceed VCC. Tested with 480I signal. Maximum voltage offset between 2 consecutive input horizontal sync tips must be less than 25 mVPP. Tested with 720P signal. Outputs are negative-polarity logic signal, except for odd/even field and video format outputs. Submit Documentation Feedback Copyright © 2006–2013, Texas Instruments Incorporated Product Folder Links: LMH1981 3 LMH1981 SNLS214H – APRIL 2006 – REVISED MARCH 2013 www.ti.com LMH1981 Test Circuit 1 REXT 10 k:, 1% + C4 4.7 PF 2 C1 0.1 PF 3 VCC CVBS/Y/G VIDEO INPUT CIN 1 PF RT 75: 5 C2 0.1 PF 6 VCC HORIZONTAL SYNC OUTPUT 4 RS 7 REXT OEOUT GND BPOUT CSOUT VCC1 LMH1981 VIN VCC3 GND GND VCC2 VFOUT HSOUT VSOUT 14 RS 13 RS 12 RS 11 8 BURST/BACK PORCH TIMING OUTPUT COMPOSITE SYNC OUTPUT VCC C3 0.1 PF 10 9 ODD/EVEN FIELD OUTPUT RS RS VIDEO FORMAT OUTPUT VERTICAL SYNC OUTPUT Figure 2. Test Circuit The LMH1981 test circuit is shown in Figure 2. The video generator should provide a low-noise, broadcastquality signal over 75Ω coaxial cable which should be impedance-matched with a 75Ω load termination resistor to prevent unwanted signal distortion. The output waveforms should be monitored using a low-capacitance probe on an oscilloscope with at least 500 MHz bandwidth. See PCB LAYOUT CONSIDERATIONS for more information about signal and supply trace routing and component placement. 4 Submit Documentation Feedback Copyright © 2006–2013, Texas Instruments Incorporated Product Folder Links: LMH1981 LMH1981 www.ti.com SNLS214H – APRIL 2006 – REVISED MARCH 2013 SDTV Vertical Interval Timing (NTSC, PAL, 480I, 576I) START OF FIELD 1 3H 3H H H 3H VERTICAL SYNC SERRATION COLOR BURST ½H VIN LINE # 525 1 2 3 4 5 6 7 8 9 10 11 CSOUT HSOUT BPOUT TVSOUT = 3H VSOUT OEOUT ODD FIELD Figure 3. NTSC Odd Field Vertical Interval START OF FIELD 2 3H 3H 3H ½H VIN LINE # 263 264 265 266 267 268 269 270 271 272 273 CSOUT HSOUT BPOUT TVSOUT = 3H VSOUT OEOUT EVEN FIELD Figure 4. NTSC Even Field Vertical Interval Submit Documentation Feedback Copyright © 2006–2013, Texas Instruments Incorporated Product Folder Links: LMH1981 5 LMH1981 SNLS214H – APRIL 2006 – REVISED MARCH 2013 www.ti.com EDTV Vertical Interval Timing (480P, 576P) START OF FRAME 6H 6H H H VERTICAL SYNC SERRATION | VIN 525 1 6 | LINE # 7 8 9 10 11 12 13 14 26 (42) 27 (43) CSOUT | HSOUT | BPOUT | TVSOUT = 3H VSOUT | OEOUT LOGIC HIGH FOR PROGRESSIVE VIDEO FORMATS OEOUT Figure 5. 480P Vertical Interval HDTV Vertical Interval Timing (720P, 1080P) START OF FRAME 20H (36H) H | VIN 750 (1125) 1 3 2 4 5 6 7 8... 25 (41) | LINE # CSOUT | HSOUT | BPOUT TVSOUT = 3H | OEOUT | VSOUT OEOUT LOGIC HIGH FOR PROGRESSIVE VIDEO FORMATS Figure 6. 720P (1080P) Vertical Interval 6 Submit Documentation Feedback Copyright © 2006–2013, Texas Instruments Incorporated Product Folder Links: LMH1981 LMH1981 www.ti.com SNLS214H – APRIL 2006 – REVISED MARCH 2013 HDTV Vertical Interval Timing (1080I) START OF FIELD 1 15H VERTICAL SYNC SERRATION H ½H | VIN 1125 1 2 3 4 5 6 7 20 21 22 584 585 586 | LINE # CSOUT | HSOUT | BPOUT OEOUT FIELD 1 | TVSOUT = 3H | VSOUT Figure 7. 1080I Field 1 Vertical Interval ½H START OF FIELD 2 5H 15H | VIN LINE # 563 564 565 566 567 568 569 570... 583 | CSOUT | HSOUT | BPOUT TVSOUT = 3H OEOUT FIELD 2 | VSOUT | Figure 8. 1080I Field 2 Vertical Interval Submit Documentation Feedback Copyright © 2006–2013, Texas Instruments Incorporated Product Folder Links: LMH1981 7 LMH1981 SNLS214H – APRIL 2006 – REVISED MARCH 2013 www.ti.com SD/EDTV Horizontal Interval Timing WHITE LEVEL VIDEO INPUT RANGE 0.5 VPP to 2 VPP VIDEO 1 VPP (typ.) VIN NTSC/PAL COLOR BURST ENVELOPE OH BLANKING LEVEL SYNC 50% SLICE SYNC TIP LEVEL CSOUT tdCSOUT HSOUT tdHSOUT THSOUT BPOUT tdBPOUT TBPOUT Figure 9. SD/EDTV Horizontal Interval with Bi-level Sync 8 Submit Documentation Feedback Copyright © 2006–2013, Texas Instruments Incorporated Product Folder Links: LMH1981 LMH1981 www.ti.com SNLS214H – APRIL 2006 – REVISED MARCH 2013 Table 1. SDTV Horizontal Interval Timing Characteristics (NTSC, PAL, 480I, 576I) (1) (2) Symbol tdCSOUT Parameter Conditions Composite Sync Output Propagation Delay from Input Sync See Figure 9 Reference (OH) Typ NTSC, 480I 475 PAL, 576I 525 NTSC, 480I 40 PAL, 576I 60 Units ns Horizontal Sync Output Propagation Delay from Input Sync Reference (OH) See Figure 9 (1) tdBPOUT Burst/Back Porch Timing Output Propagation Delay from Input Sync Trailing Edge See Figure 9 300 ns THSOUT Horizontal Sync Output Pulse Width See Figure 9 2.5 µs TBPOUT Burst/Back Porch Timing Output Pulse Width See Figure 9 3.2 µs tdHSOUT (1) (2) ns Note: HSync propagation delay variation less than ±3 ns (typ) over 0°C to 70°C temperature range. VCC = 3.3V , TA = 25°C Table 2. EDTV Horizontal Interval Timing Characteristics (480P, 576P) Symbol Parameter Conditions Typ Units tdCSOUT Composite Sync Output Propagation Delay from Input Sync Reference (OH) See Figure 9 450 ns tdHSOUT Horizontal Sync Output Propagation Delay from Input Sync Reference (OH) See Figure 9 35 ns tdBPOUT Burst/Back Porch Timing Output Propagation Delay from Input Sync Trailing Edge See Figure 9 500 ns THSOUT Horizontal Sync Output Pulse Width See Figure 9 2.3 µs TBPOUT Burst/Back Porch Timing Output Pulse Width See Figure 9 350 ns HDTV Horizontal Interval Timing WHITE LEVEL VIDEO INPUT RANGE 0.5 VPP to 2 VPP VIDEO 1 VPP (typ.) 50% OH TRAILING EDGE + SYNC VIN LEADING EDGE 50% 50% SLICE BLANKING LEVEL - SYNC CSOUT tdCSOUT HSOUT tdHSOUT THSOUT BPOUT tdBPOUT TBPOUT Figure 10. HDTV Horizontal Interval with Tri-level Sync Submit Documentation Feedback Copyright © 2006–2013, Texas Instruments Incorporated Product Folder Links: LMH1981 9 LMH1981 SNLS214H – APRIL 2006 – REVISED MARCH 2013 www.ti.com Table 3. HDTV Horizontal Interval Timing Characteristics (720P, 1080I) (1) Symbol Parameter Conditions Typ Units tdCSOUT Composite Sync Output Propagation Delay from Input Sync Leading Edge See Figure 10 150 ns tdHSOUT Horizontal Sync Output Propagation Delay from Input Sync Reference (OH) See Figure 10 30 ns tdBPOUT Burst/Back Porch Timing Output Propagation Delay from Input Sync Trailing Edge See Figure 10 Horizontal Sync Output Pulse Width See Figure 10 THSOUT TBPOUT (1) 10 Burst/Back Porch Timing Output Pulse Width See Figure 10 720P 400 1080I, 1080P 300 720P 525 1080I, 1080P 475 350 ns ns ns VCC = 3.3V , TA = 25°C Submit Documentation Feedback Copyright © 2006–2013, Texas Instruments Incorporated Product Folder Links: LMH1981 LMH1981 www.ti.com SNLS214H – APRIL 2006 – REVISED MARCH 2013 APPLICATION INFORMATION GENERAL DESCRIPTION The LMH1981 is designed to extract the timing information from various video formats with vertical serration and output the syncs and relevant timing signals in CMOS logic. Its high performance, advanced features and easy application make it ideal for broadcast and professional video systems where low jitter is a crucial parameter. The device can operate from a supply voltage between 3.3V and 5V. The only required external components are bypass capacitors at the power supply pins, an input coupling capacitor at pin 4, and a precision REXT resistor at pin 1. Refer to the test circuit in Figure 2. REXT Resistor The REXT external resistor establishes the internal bias current and precise reference voltage for the LMH1981. For optimal performance, REXT should be a 10 kΩ 1% precision resistor with a low temperature coefficient to ensure proper operation over a wide temperature range. Using a REXT resistor with less precision may result in reduced performance (like worse jitter performance, increased propagation delay variation, or reduced input sync amplitude range) against temperature, supply voltage, input signal, or part-to-part variations. NOTE The REXT resistor serves a different function than the “RSET resistor” used in the LM1881 sync separator. In the older LM1881, the RSET value was adjusted to accommodate different input line rates. For the LMH1981, the REXT value is fixed, and the device automatically detects the input line rate to support various video formats without electrical or physical intervention. Automatic Format Detection and Switching Automatic format detection eliminates the need for external programming via a microcontroller or RSET resistor. The device outputs will respond correctly to video format switching after a sufficient start-up time has been satisfied. Unlike other sync separators, the LMH1981 does not require the power to be cycled in order to ensure correct outputs after a significant change to the input signal. See START-UP TIME for more details. 50% Sync Slicing The LMH1981 features 50% sync slicing on HSync to provide accurate sync separation for video input amplitudes from 0.5 VPP to 2 VPP, which enables excellent HSync jitter performance even for improperly terminated or attenuated source signals and stability against variations in temperature. The sync separator is compatible with SD/EDTV bi-level and HDTV tri-level sync inputs. Bi-level syncs will be sliced at the 50% point between the video blanking level and negative sync tip, indicated by the input's sync timing reference or “OH” in Figure 9. Tri-level syncs will be sliced at the 50% point between the negative and positive sync tips (or positive zero-crossing), indicated by OH in Figure 10. VIDEO INPUT The LMH1981 supports sync separation for CVBS, Y (luma) from Y/C and YPBPR and G (sync on green) from GBR with either bi-level or tri-level sync, as specified in the following video standards. • Composite Video (CVBS) and S-Video (Y/C): – SDTV: SMPTE 170M (NTSC), ITU-R BT.470 (PAL) • Component Video (YPBPR/GBR): – SDTV: SMPTE 125M, SMPTE 267M, ITU-R BT.601 (480I, 576I) – EDTV: ITU-R BT.1358 (480P, 576P) – HDTV: SMPTE 296M (720P), SMPTE 274M (1080I/P), SMPTE RP 211 (1080PsF) The LMH1981 does not support RGB formats that conform to VESA standards used for PC graphics. Submit Documentation Feedback Copyright © 2006–2013, Texas Instruments Incorporated Product Folder Links: LMH1981 11 LMH1981 SNLS214H – APRIL 2006 – REVISED MARCH 2013 www.ti.com Input Termination The video source should be load terminated with a 75Ω resistor to ensure correct video signal amplitude and minimize signal distortion due to reflections. In extreme cases, the LMH1981 can handle unterminated or doubleterminated input conditions, assuming 1 VPP signal amplitude for normal terminated video. Input Coupling Capacitor The input signal should be AC coupled to the VIN (pin 4) of the LMH1981 with a properly chosen coupling capacitor, CIN. The primary consideration in choosing CIN is whether the LMH1981 will interface with video sources using an AC-coupled output stage. If AC-coupled video sources are expected in the end-application, then it’s recommended to choose a small CIN value such as 0.01 µF as prescribed in the next section. Other considerations such as HSync jitter performance and start-up time are practically fixed by the limited range of small CIN values. It’s important to note that video sources with AC-coupled outputs will introduce videodependent jitter that cannot be remedied by the sync separator; moreover, this type of jitter is not prevalent in sources with DC-coupled input/output stages. When only DC-coupled video sources are expected, a larger CIN value can be chosen to minimize voltage droop and thus improve HSync jitter at the expense of increased start-up time as explained in START-UP TIME. A typical CIN value such as 1 µF will give excellent jitter performance and reasonable start-up time using a broadcast-quality DC-coupled video generator. For applications where low HSync jitter is not critical, CIN can be a small value to reduce start-up time. START-UP TIME When there is a significant change to the video input signal, such as sudden signal switching, signal attenuation (i.e.: additional termination via loop through) or signal gain (i.e.: disconnected end-of-line termination), the quiescent operation of the LMH1981 will be disrupted. During this dynamic input condition, the LMH1981 outputs may not be correct but will recover to valid signals after a predictable start-up time, which consists of an adjustable input settling time and a predetermined “sync lock time”. Input Settling Time and Coupling Capacitor Selection Following a significant input condition, the negative sync tip of the AC-coupled signal settles to the input clamp voltage as the coupling capacitor, CIN, recovers a quiescent DC voltage via the dynamic clamp current. Because CIN determines the input settling time, its capacitance value is critical when minimizing overall start-up time. For example, a settling time of 8 ms can be expected for a typical CIN value of 1 µF when switching in a standard NTSC signal with no prior input. A smaller value yields shorter settling time at the expense of increased line droop voltage and consequently higher HSync jitter, whereas a larger one gives lower jitter but longer settling time. Settling time is proportional to the value of CIN, so doubling CIN will also double the settling time. The value of CIN is a tradeoff between start-up time and jitter performance and therefore should be evaluated based on the application requirements. Figure 11 shows a graph of typical input-referred HSync jitter vs. CIN values to use as a guideline. Refer to Horizontal Sync Output for more about jitter performance. 12 Submit Documentation Feedback Copyright © 2006–2013, Texas Instruments Incorporated Product Folder Links: LMH1981 LMH1981 www.ti.com SNLS214H – APRIL 2006 – REVISED MARCH 2013 HSYNC JITTER (PSPP) 2500 2000 1500 PAL 1000 500 1080I 0 0 2 4 6 CIN (PF) 8 10 Figure 11. Typical HSync Jitter vs. CIN Values Sync Lock Time In addition to settling time, the LMH1981 has a predetermined sync lock time, TSYNC-LOCK, before the outputs are correct. Once the AC-coupled input has settled enough, the LMH1981 needs time to detect the valid video signal and resolve the blanking & sync tip levels for 50% sync slicing before the output signals are correct. For practical values of CIN, TSYNC-LOCK is typically less than 1 or 2 video fields in duration starting from the 1st valid VSync output pulse to the valid HSync pulses beginning thereafter. VSync and HSync pulses are considered valid when they align correctly with the input's vertical and horizontal sync intervals. Note that the start-up time may vary depending on the video duty cycle, average picture level variations, and start point of video relative to the vertical sync interval. It is recommended for the outputs to be applied to the system after the start-up time is satisfied and outputs are valid. For example, the oscilloscope screenshot in Figure 12 shows a typical start-up time of about 13.5 ms from when an NTSC signal is switched in (no previous input) to when the LMH1981 outputs are valid. Signal Before CIN Settling Time AC Coupled Signal (VIN) Sync Lock Time HSync Start- up Time VSync Figure 12. Typical Start-Up Time for NTSC Input to LMH1981 via 1 µF Coupling Capacitor Submit Documentation Feedback Copyright © 2006–2013, Texas Instruments Incorporated Product Folder Links: LMH1981 13 LMH1981 SNLS214H – APRIL 2006 – REVISED MARCH 2013 www.ti.com LOGIC OUTPUTS In the absence of a video input signal, the LMH1981 outputs are logic high except for the odd/even field and video format outputs, which are both undefined, and the composite sync output. Composite Sync Output CSOUT (pin 12) simply reproduces the video input sync pulses below the video blanking level. This is obtained by clamping the video signal sync tip to the internal clamp voltage at VIN and extracting the resultant composite sync signal, or CSync. For both bi-level and tri-level syncs, CSync's negative-going leading edge is derived from the input's negative-going leading edge with a propagation delay. Horizontal Sync Output HSOUT (pin 7) produces a negative-polarity horizontal sync signal, or HSync, with very low jitter on its negativegoing leading edge (reference edge) using precise 50% sync slicing. For bi-level and tri-level sync signals, the horizontal sync leading edge is triggered from the input's sync reference, OH, with a propagation delay. HSync was optimized for excellent jitter performance on its leading edge because most video systems are negative-edge triggered. When HSync is used in a positive-edge triggered system, like an FPGA PLL input, it must be inverted beforehand to produce positive-going leading edges. The trailing edge of HSync should never be used as the reference or triggered edge. This is because the trailing edges of HSync are reconstructed for the broad serration pulses during the vertical interval. HSync's typical peak-to-peak jitter can be measured using the input-referred jitter test methodology on a realtime digital oscilloscope by triggering at or near the input's OH reference and monitoring HSync's leading edge with 4-sec. variable persistence. This is one way to measure HSync's typical peak-to-peak jitter in the time domain. Figure 13 and Figure 14 show oscilloscope screenshots demonstrating very low jitter on HSync's leading edge for 1080I tri-level sync and PAL Black Burst inputs, respectively, from a Tek TG700-AWVG7/AVG7 video generator with DC-coupled outputs and with LMH1981 VCC = 3.3V. Figure 13. Typical HSync Jitter for 1080I Input Upper: Horizontal Sync Leading Edge (Reference) Lower: Zoomed In — 400 ps/DIV, 25 mV/DIV Figure 14. Typical HSync Jitter for PAL Input Upper: Horizontal Sync Leading Edge (Reference) Lower: Zoomed In — 1000 ps/DIV, 25 mV/DIV Vertical Sync Output VSOUT (pin 8) produces a negative-polarity vertical sync signal, or VSync. VSync's negative-going leading edge is derived from the 50% point of the first vertical serration pulse with a propagation delay, and its output pulse width, TVSOUT, spans approximately three horizontal periods (3H). Burst/Back Porch Timing Output BPOUT (pin 13) provides a negative-polarity burst/back porch signal, which is pulsed low for a fixed width during the back porch interval following the input's sync pulse. The burst/back porch timing pulse is useful as a burst gate signal for NTSC/PAL color burst synchronization and as a clamp signal for black level clamping (DC restoration) and sync stripping applications. 14 Submit Documentation Feedback Copyright © 2006–2013, Texas Instruments Incorporated Product Folder Links: LMH1981 LMH1981 www.ti.com SNLS214H – APRIL 2006 – REVISED MARCH 2013 For SDTV formats, the back porch pulse's negative-going leading edge is derived from the input's positive-going sync edge with a propagation delay, and the pulse width spans an appropriate duration of the color burst envelope for NTSC/PAL. During the vertical interval, its pulse width is shorter to correspond with the narrow serration pulses. For EDTV formats, the back porch pulse behaves similar to the SDTV case except that the shorter pulse width is always maintained. For HDTV formats, the pulse's leading edge is derived from the input's negative-going trailing sync edge with a propagation delay, and the pulse width is even narrower to correspond with the shortest back porch duration of HDTV formats. Odd/Even Field Output OEOUT (pin 14) provides an odd/even field output signal, which facilitates identification of odd and even fields for interlaced or segmented frame (sF) formats. For interlaced or segmented frame formats, the odd/even output is logic high during an odd field (field 1) and logic low during an even field (field 2). The odd/even output edge transitions align with VSync's leading edge to designate the start of odd and even fields. For progressive (noninterlaced) video formats, the output is held constantly at logic high. Video Format Output (Lines-per-Field Data) The LMH1981 counts the number of HSync pulses per field to approximate the total horizontal line count per field (vertical resolution). This can be used to identify the video format and enable dynamic adjustment of video system parameters, such as color space or scaler conversions. The line count per field is output to VFOUT (pin 9) as an 11-bit binary data stream. The video format data stream is clocked out on the 11 consecutive leading edges of HSync, starting at the 3rd HSync after each VSync leading edge. Outside of these active 11-bits of data, the video format output can be either 0 or 1 and should be treated as undefined. Refer to Figure 15 to see the VFOUT data timing for the 480P progressive format and Figure 16 and Figure 17 for the 1080I interlaced format. See Table 4 for a summary of VFOUT data for all supported formats. A FPGA/MCU can be used to decode the 11-bit VFOUT data stream by using HSync as the clock source signal and VSync as the enable signal. Using the FPGA's clock delay capability, a delayed clock derived from HSync can be used as the sampling clock to latch the VFOUT data in the middle of the horizontal line period rather than near the VFOUT data-bit transitions in order to avoid setup time requirements. Table 4. VFOUT Data Summary (1) (1) TV Format (Total Lines per Field) VFOUT Data Field 1 VFOUT Data Field 2 NTSC/480I (262.5) 00100000100b 260d 00100000011b 259d PAL/576I (312.5) 00100110110b 310d 00100110101b 309d 480P (525) 01000001010b 522d N/A 576P (625) 01001101110b 622d N/A 720P (750) 01011101011b 747d N/A 1080I (562.5) 01000110000b 560d 01000101111b 559d 1080P (1125) 10001100010b 1122d N/A Note: VFOUT Data has an average offset of −3 lines due to the HSync pulses uncounted during the VSync pulse interval. Submit Documentation Feedback Copyright © 2006–2013, Texas Instruments Incorporated Product Folder Links: LMH1981 15 LMH1981 SNLS214H – APRIL 2006 – REVISED MARCH 2013 www.ti.com 11H VIN LINE # 9 11 10 12 13 14 15 16 17 18 19 20 21 0 1 0 22 CSOUT HSOUT (CLOCK) 3rd HSync after VSync leading edge VSOUT 11- BIT BINARY DATA STREAM VFOUT (DATA) 0 0 1 START 0 0 0 0 1 01000001010b = 522 HORIZONTAL LINES PER FIELD END Figure 15. Video Format Output for Progressive Format, 480P 11H VIN LINE # 3 4 5 6 7 8 9 10 11 12 13 0 0 14 15 CSOUT HSOUT (CLOCK) 3rd HSync after VSync leading edge VSOUT 11-BIT BINARY DATA STREAM VFOUT (DATA) 0 START 1 0 0 0 1 1 0 01000110000b = 560 HORIZONTAL LINES PER FIELD 0 END Figure 16. Video Format Output for Interlaced Format, 1080I Field 1 16 Submit Documentation Feedback Copyright © 2006–2013, Texas Instruments Incorporated Product Folder Links: LMH1981 LMH1981 www.ti.com SNLS214H – APRIL 2006 – REVISED MARCH 2013 11H VIN LINE# 567 566 568 569 570 571 572 573 574 575 576 577 1 1 1 578 CSOUT HSOUT (CLOCK) 3rd HSync after VSync leading edge VSOUT 11-BIT BINARY DATA STREAM VFOUT (DATA) 0 1 START 0 0 0 1 0 1 01000101111b = 559 HORIZONTAL LINES PER FIELD END Figure 17. Video Format Output for Interlaced Format, 1080I Field 2 OPTIONAL CONSIDERATIONS Optional Input Filtering An external filter may be necessary if the video signal has considerable high-frequency noise or has large chroma amplitude that extends near the sync tip. A simple RC low-pass filter with a series resistor (RS) and a capacitor (CF) to ground can be used to improve the overall signal-to-noise ratio and sufficiently attenuate chroma such that minimum peak of its amplitude is above the 50% sync slice level. To achieve the desired filter cutoff frequency, it’s advised to vary CF and keep RS small (ie. 100Ω) to minimize sync tip clipping due to the voltage drop across RS. Note that using an external filter will increase the propagation delay from the input to the outputs. In applications where the chroma filter needs to be disabled when non-composite video (ie: ED/HD video) is input, it is possible to use a transistor to switch open CF’s connection to ground as shown in Figure 18. This transistor can be switched off/on by logic circuitry to decode the lines-per-field data output (VFOUT). As shown in Table 4, NTSC and PAL both have 1 (logic high) for the 3rd bit of VFOUT. If the logic circuitry detects 0 (logic low) for this bit, indicating non-composite video, the transistor can be turned off to disable the chroma filter. VIDEO IN CIN RS VIN LMH1981 75: CF 10 k: LOGIC CIRCUIT VFOUT HSOUT VSOUT ED/HD = ³0´ NTSC/PAL = ³1´ Figure 18. External Chroma Filter with Control Circuit AC-Coupled Video Sources An AC coupled video source typically has a 100 µF or larger output coupling capacitor (COUT) for protection and to remove the DC bias of the amplifier output from the video signal. When the video source is load terminated, the average value of the video signal will shift dynamically as the video duty cycle varies due to the averaging effect of the COUT and termination resistors. The average picture level or APL of the video content is closely related to the duty cycle. Submit Documentation Feedback Copyright © 2006–2013, Texas Instruments Incorporated Product Folder Links: LMH1981 17 LMH1981 SNLS214H – APRIL 2006 – REVISED MARCH 2013 www.ti.com For example, a significant decrease in APL such as a white-to-black field transition will cause a positive-going shift in the sync tips characterized by the source’s RC time constant, tRC-OUT (150Ω*COUT). The LMH1981’s input clamp circuitry may have difficulty stabilizing the input signal under this type of shifting; consequently, the unstable signal at VIN may cause missing sync output pulses to result, unless a proper value for CIN is chosen. To avoid this potential problem when interfacing AC-coupled sources to the LMH1981, it’s necessary to introduce a voltage droop component via CIN to compensate for video signal shifting related to changes in the APL. This can be accomplished by selecting CIN such that the effective time constant of the LMH1981’s input circuit, tRC-IN, is less than tRC-OUT. The effective time constant of the input circuit can be approximated as: tRC-IN = (RS+RI)*CIN*TLINE/TCLAMP, where RS = 150Ω, RI = 4000Ω (input resistance), TLINE ∼ 64 μs for NTSC, and TCLAMP = 250 ns (internal clamp duration). A white-to-black field transition in NTSC video through COUT will exhibit the maximum sync tip shifting due to its long line period (TLINE). By setting tRC-IN < tRC-OUT, the maximum value of CIN can be calculated to ensure proper operation under this worst-case condition. For instance, tRC-OUT is about 33 ms for COUT = 220 µF. To ensure tRC-IN < 33 ms, CIN must be less than 31 nF. By choosing CIN = 0.01 μF, the LMH1981 will function properly with AC-coupled video sources using COUT ≥ 220 μF. PCB LAYOUT CONSIDERATIONS LMH1981 IC Placement The LMH1981 should be placed such that critical signal paths are short and direct to minimize PCB parasitics from degrading the high-speed video input and logic output signals. Ground Plane A two-layer, FR-4 PCB is sufficient for this device. One of the PCB layers should be dedicated to a single, solid ground plane that runs underneath the device and connects the device GND pins together. The ground plane should be used to connect other components and serve as the common ground reference. It also helps to reduce trace inductances and minimize ground loops. Try to route supply and signal traces on another layer to maintain as much ground plane continuity as possible. Power Supply Pins The power supply pins should be connected together using short traces with minimal inductance. When routing the supply traces, be careful not to disrupt the solid ground plane. For high frequency bypassing, place 0.1 µF SMD ceramic bypass capacitors with very short connections to power supply and GND pins. Two or three ceramic bypass capacitors can be used depending on how the supply pins are connected together. Place a 4.7 µF SMD tantalum bypass capacitor nearby all three power supply pins for low frequency supply bypassing. REXT Resistor The REXT resistor should be a 10 kΩ 1% SMD precision resistor. Place REXT as close as possible to the device and connect to pin 1 and the ground plane using the shortest possible connections. All input and output signals must be kept away from this pin to prevent unwanted signals from coupling into this pin. Video Input The input signal path should be routed using short, direct traces between video source and input pin. Use a 75Ω input termination and a SMD capacitor for AC coupling the video input to pin 4. Output Routing The output signal paths should be routed using short, direct traces to minimize parasitic effects that may degrade these high-speed logic signals. All output signals should have a resistive load of about 10 kΩ and capacitive load of less than 10 pF, including parasitic capacitances for optimal signal quality. This is especially important for the horizontal sync output, in which it is critical to minimize timing jitter. Each output can be protected by current limiting with a small series resistor, like 100Ω. 18 Submit Documentation Feedback Copyright © 2006–2013, Texas Instruments Incorporated Product Folder Links: LMH1981 LMH1981 www.ti.com SNLS214H – APRIL 2006 – REVISED MARCH 2013 REVISION HISTORY Changes from Revision G (March 2013) to Revision H • Page Changed layout of National Data Sheet to TI format .......................................................................................................... 18 Submit Documentation Feedback Copyright © 2006–2013, Texas Instruments Incorporated Product Folder Links: LMH1981 19 PACKAGE OPTION ADDENDUM www.ti.com 10-Dec-2020 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan (2) Lead finish/ Ball material MSL Peak Temp Op Temp (°C) Device Marking (3) (4/5) (6) LMH1981MT/NOPB ACTIVE TSSOP PW 14 94 RoHS & Green SN Level-1-260C-UNLIM -40 to 85 LMH19 81MT LMH1981MTX/NOPB ACTIVE TSSOP PW 14 2500 RoHS & Green SN Level-1-260C-UNLIM -40 to 85 LMH19 81MT (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of