LMH2190
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SNAS473H – JUNE 2009 – REVISED MAY 2013
LMH2190 Quad Channel 27 MHz Clock Tree Driver with I2C Interface
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FEATURES
DESCRIPTION
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The LMH2190 is a quad channel configurable clock
tree driver which supplies a digital system clock to
peripherals in mobile handsets or other applications.
It provides a solution to clocking issues such as
limited drive capability for fanout or longer traces,
protection of the master clock from varying loads and
frequency pulling effects, isolation buffering from
noisy modules, and crosstalk isolation. It has very low
phase noise which enables it to drive sensitive
modules such as Wireless LAN and Bluetooth.
1
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1 Input Clock, 4 Output Clocks
Supports both Square or Sine Wave Input
1.8V Square Wave Clock Outputs
Skewed Clock Outputs
Independent Clock Request
High Isolation of Supply Noise to Clock Input
High Output to Output Isolation
Output Drive up to 50 pF
EMI Controlled Output Edges and EMI Filtering
Integrated 1.8V Low-Dropout Regulator
– Low Output Noise Voltage
– 10 mA load Current
I2C Configurable up to 400 kHz (Fast Mode)
Ultra Low Standby Current
VBAT Range = 2.5V to 5.5V
APPLICATIONS
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Mobile Handsets
PDAs
Portable Equipment
The LMH2190 can be clocked up to 27 MHz, and has
an independent clock request pin for each clock
output which allows the peripheral to control the
clock. It features an integrated LDO which provides
an ultra low noise voltage supply with 10 mA external
load current which can be used to supply the TCXO
or other clock source.
The I2C serial interface can be used to override the
default configuration of the device to optimize the
LMH2190 for the application. Some of these
programmable features include setting the polarity of
both the clock and the clock request inputs. In
addition, the clock outputs have programmable output
drive current to optimize for the connected load. EMI
switching noise can be controlled by configuring
output drive and skew settings.
The LMH2190 quad clock distributor is offered in a
tiny 1.61mm x 1.61mm 16 bump DSBGA package. Its
small size and low supply current make it ideal for
portable applications.
1
2
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
All trademarks are the property of their respective owners.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2009–2013, Texas Instruments Incorporated
LMH2190
SNAS473H – JUNE 2009 – REVISED MAY 2013
www.ti.com
Typical Application
VBAT
CBAT
VBAT
1 PF
A1
VOUT B1
1.8V LDO, 10 mA
COUT
2.2 PF
A3
CLK1
PERIPHERAL
A4
CIN
CCLK
10 nF
470 pF
VDD
CLOCK
GND
EN
SCLK_IN
C1
SCLK_REQ
C2
CLOCK
TREE
DRIVER
CLK2
PERIPHERAL
D4
CLK3
PERIPHERAL
D3
CLK4
CONTROL
LOGIC
PERIPHERAL
R1,2
5.1 k:
ENABLE
CPU/
BASE
BAND
A2
SCL
D2
SDA
D1
CLOCK
REQUEST
2
I C
LMH2190
B3
CLK_REQ1
B4
CLK_REQ2
C4
CLK_REQ3
C3
CLK_REQ4
B2
VSS
2
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These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
ABSOLUTE MAXIMUM RATINGS
(1) (2)
Supply Voltage
VBAT - VSS
-0.3V to 6V
LVCMOS port IO voltage
-0.3V to (VOUT + 0.3V)
Current on CLKx pins
ESD Tolerance
+/- 65 mA
(3)
Human Body Model
2000V
Machine Model
200V
−65°C to 150°C
Storage Temperature Range
Junction Temperature
(4)
150°C
Maximum Lead Temperature
(Soldering,10 sec)
(1)
(2)
(3)
(4)
230°C
Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for
which the device is intended to be functional, but performance is not specified. For specifications and the test conditions, see the
Electrical Characteristics Tables.
If Military/Aerospace specified devices are required, please contact the Texas Instruments Sales Office/ Distributors for availability and
specifications.
Human body model, applicable std. MIL-STD-883, Method 3015.7. Machine model, applicable std. JESD22–A115–A (ESD MM std of
JEDEC). Field-Induced Charge-Device Model, applicable std. JESD22–C101–C. (ESD FICDM std. of JEDEC)
The maximum power dissipation is a function of TJ(MAX) , θJA and TA. The maximum allowable power dissipation at any ambient
temperature is PD = (TJ(MAX) - TA)/θJA. All numbers apply for packages soldered directly onto a PC board.
OPERATING RATINGS
(1)
Supply Voltage (VBAT - VSS)
2.5V to 5.5V
VENABLE
0 to 2V
Input Clock, SCLK_IN
DC Mode
32 kHz to 27 MHz
AC Mode
13 MHz to 27 MHz
Duty Cycle
45% to 55%
Temperature Range
-40°C to +85°C
Package Thermal Resistance θJA (2)
(1)
(2)
113.6°C/W
Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for
which the device is intended to be functional, but performance is not specified. For specifications and the test conditions, see the
Electrical Characteristics Tables.
The maximum power dissipation is a function of TJ(MAX) , θJA and TA. The maximum allowable power dissipation at any ambient
temperature is PD = (TJ(MAX) - TA)/θJA. All numbers apply for packages soldered directly onto a PC board.
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3.5 V DC AND AC ELECTRICAL CHARACTERISTICS
(1) (2)
Unless otherwise specified, all limits are specified at TA = 25°C, VBAT = 3.5V, fSCLK_IN = 26 MHz, COUT = 2.2 µF, VDD_IO = 1.8V
(See Figure 6 ) (3), IOUT = 1 mA, Registers are in default setting. Boldface limits apply at the temperature extremes.
Symbol
Parameter
Supply Current
IDD
Active Supply Current
Shutdown Supply Current
IDDQ
Quiescent Supply Current
IDDEN
Current to Enable pin
CPD
Condition
Min
(4)
Typ
(5)
Max
(4)
Units
(6)
Power Dissipation Capacitance
per CLK output, (7)
Clock outputs toggling at 26 MHz
without external capacitors on
CLK1/2/3/4, LDO is ON, IOUT = 0 mA
3
In Shutdown. No clocks toggling. LDO
is OFF
0.1
1
In Shutdown. Input CLK toggling, no
Clock outputs toggling. LDO is OFF
0.1
1
No Clock outputs toggling. LDO is ON,
IOUT = 0 mA
36
60
No Clock outputs toggling, LDO is ON,
IOUT = 10 mA
50
80
mA
μA
μA
I2C port is operational
300
I2C port is idle
0.1
Defined with respect to VOUT = 1.8V
μA
15.7
17.5
pF
6.5
10
ns
7.5
11
ns
Clock Outputs (CLK1/2/3/4)
tpLH
Propagation Delay SCLK_IN to
CLK1 - Low to High, Figure 1 (7)
50% to 50%
tpHL
Propagation Delay SCLK_IN to
CLK1 - High to Low, Figure 1 (7)
50% to 50%
tSKEW
Skew Between Outputs (Either
Edge), Figure 1, (7)
CLK1 to CLK2, 50% to 50%
3
6
8.5
CLK2 to CLK3 and CLK3 to CLK4,
50% to 50%
1
3.5
7.3
CL = 10 pF to 50 pF, 20% to 80%
3
6
CL = 10 pF to 50 pF, 80% to 20%
2.5
5
50
58
tRISE
Rise Time, Figure 3,
(7) (8)
(7) (8)
tFALL
Fall Time, Figure 3
CLK_DC
Output Clock Duty Cycle,
Figure 3, (7)
CL = 10 pF to 50 pF
JitterRMS
Additive RMS period Jitter
BW = 100 Hz to 1 MHz
(1)
(2)
(3)
(4)
(5)
(6)
(7)
(8)
4
42
CLK1
100
CLK2
240
CLK3
330
CLK4
400
ns
ns
%
fs
Electrical Table values apply only for factory testing conditions at the temperature indicated. Factory testing conditions result in very
limited self-heating of the device such that TJ = TA. No specification of parametric performance is indicated in the electrical tables under
conditions of internal self-heating where TJ > TA.
CBAT, COUT: Low-ESR Surface-Mount Ceramic Capacitors (MLCCs) used in setting electrical characteristics.
VDD_IO is equal to VOUT when the LDO is enabled and it is equal to VENABLE when it is disabled.
Limits are 100% production tested at 25°C. Limits over temperature range are specified through correlations using statistical quality
control (SQC) method.
Typical values represent the most likely parametric norm as determined at the time of characterization. Actual typical values may vary
over time and will also depend on the application and configuration. The typical values are not tested and are not specified on shipped
production material.
IDD current depends on switching frequency and load.
This parameter is specified by design and/or characterization and is not tested in production.
Appropriate output load register must be set.
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3.5 V DC AND AC ELECTRICAL CHARACTERISTICS (1)(2) (continued)
Unless otherwise specified, all limits are specified at TA = 25°C, VBAT = 3.5V, fSCLK_IN = 26 MHz, COUT = 2.2 µF, VDD_IO = 1.8V
(See Figure 6 ) (3), IOUT = 1 mA, Registers are in default setting. Boldface limits apply at the temperature extremes.
Symbol
Phase
Noise
Parameter
CLK1 Additive Phase Noise with
all Outputs toggling
CLK2 Additive Phase Noise with
all Outputs toggling
CLK3 Additive Phase Noise with
all Outputs toggling
CLK4 Additive Phase Noise with
all Outputs toggling
Condition
Min
(4)
Typ
(5)
f = 100 Hz
-130
f = 1 kHz
-144
f = 10 kHz
-152
f = 100 kHz
-158
f = 1 MHz
-165
f = 100 Hz
-128
f = 1 kHz
-139
f = 10 kHz
-146
f = 100 kHz
-151
f = 1 MHz
-153
f = 100 Hz
-127
f = 1 kHz
-138
f = 10 kHz
-144
f = 100 kHz
-148
f = 1 MHz
-150
f = 100 Hz
-125
f = 1 kHz
-135
f = 10 kHz
-142
f = 100 kHz
-147
f = 1 MHz
-148
VOH
CLK1/2/3/4 Output Voltage High
Level
CLK1/2/3/4 = -2 mA
VOL
CLK1/2/3/4 Output Voltage Low
Level
CLK1/2/3/4 = 2 mA
ROFF
Output Impedance when disabled
LDO enabled
grounded
LDO disabled
diode to ground
Max
(4)
Units
dBc/Hz
1.6
V
0.2
System Clock Input (SCLK_IN)
VIH
SCLK_IN Input Voltage High Level DC Mode
AC Mode
VIL
SCLK_IN Input Voltage Low Level
DC Mode
AC Mode
IIH
SCLK_IN Input Current High Level SCLK_IN = 1.8V, Clock path disabled
IIL
SCLK_IN Input Current Low Level
SCLK_IN = VSS, Clock path disabled
2.0
1.2
1.8
0
0.35 x
VOUT
0
0.6
0
-0.1
(9)
CIN
Input Capacitance
VBIAS
DC Bias Voltage
AC Mode
RIN
Input Resistance
AC Mode, Clock path enabled.
(9)
0.65 x
VOUT
7.5
21
0.1
0
V
V
µA
µA
10
pF
0.805
V
30
kΩ
This parameter is specified by design and/or characterization and is not tested in production.
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3.5 V DC AND AC ELECTRICAL CHARACTERISTICS (1)(2) (continued)
Unless otherwise specified, all limits are specified at TA = 25°C, VBAT = 3.5V, fSCLK_IN = 26 MHz, COUT = 2.2 µF, VDD_IO = 1.8V
(See Figure 6 ) (3), IOUT = 1 mA, Registers are in default setting. Boldface limits apply at the temperature extremes.
Symbol
Parameter
Condition
Min
(4)
Typ
(5)
Max
(4)
Units
Clock Request Output (SCLK_REQ)
tpLH
Propagation Delay, Push-Pull and
Open Source, Figure 2, (10)
50% to 50%
tpHL
Propagation Delay, Push-Pull and
Open Drain, Figure 2, (10)
50% to 50%
VOH
SCLK_REQ Output Voltage High
Level
SCLK_REQ = -500 µA, Push-Pull
Output
1.52
SCLK_REQ = -500 µA, Open Source
Output
1.52
VOL
SCLK_REQ Output Voltage Low
Level
21
32
15
21
ns
V
SCLK_REQ = 500 µA, Push-Pull Output
0.2
SCLK_REQ = 500 µA, Open Drain
Output
0.2
V
Clock Request Inputs (CLK_REQ1/2/3/4)
tSET
Setup Time from CLK_REQx to
SCLK_IN, to enable CLKx,
Figure 4, (10)
16
ns
VIH
CLK_REQ1/2/3/4 Input Voltage
High Level
0.8 x
VDD_IO
V
VIL
CLK_REQ1/2/3/4 Input Voltage
Low Level
IIH
CLK_REQ1/2/3/4 Input Current
High Level
0.2 x
VDD_IO
200 kΩ internal pull down resistor.
CLK_REQ1/2/3/4 = 1.8V
CLK_REQ1/2/3/4 Input Current
Low Level
SCL and SDA Inputs, VENABLE = 1.8V
VIL = VSS
12.7
0
0.1
µA
Without internal / external pull down
resistor. CLK_REQ1/2/3/4 = 1.8V
IIL
8.3
V
-0.1
0
µA
(11)
VIH
SCL and SDA Input Voltage High
Level
0.8 x
VENABLE
VIL
SCL and SDA Input Voltage Low
Level
IIH
SCL and SDA Input Current High
Level
SCL/SDA = VENABLE
IIL
SCL and SDA Input Current Low
Level
100 kΩ internal Pull-up resistor,
SCL/SDA = VSS
VOL
SDA Output Voltage Low Level
SDA = 3 mA
V
0
-28
0.2 x
VENABLE
V
0.1
µA
-18
µA
0.2
V
2
V
ENABLE Input
VIH
ENABLE Input Voltage High Level
VIL
ENABLE Input Voltage Low Level
1.65
IIH
ENABLE Input Current High Level
ENABLE = VOUT
IIL
ENABLE Input Current Low Level
ENABLE = VSS
-0.1
0.5
V
0.1
µA
µA
(10) This parameter is specified by design and/or characterization and is not tested in production.
(11) I2C interface uses IO cells specified at 1.8V typical supply (1.6V Min - 2.0V Max).
6
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3.5 V DC AND AC ELECTRICAL CHARACTERISTICS (1)(2) (continued)
Unless otherwise specified, all limits are specified at TA = 25°C, VBAT = 3.5V, fSCLK_IN = 26 MHz, COUT = 2.2 µF, VDD_IO = 1.8V
(See Figure 6 ) (3), IOUT = 1 mA, Registers are in default setting. Boldface limits apply at the temperature extremes.
Symbol
Parameter
Condition
Min
(4)
Typ
(5)
Max
(4)
Units
LDO
VOUT
Output Voltage
ILOAD
Load Current
IOUT = 1 mA
VDO
Dropout Voltage
ISC
Short Circuit Current Limit
PSRR
Power Supply Rejection Ratio
(12)
1.78
VOUT > 1.74V
(13)
1.805
0
VOUT = 1.7V, IOUT = 10 mA
100
VBAT ripple = 200 mVPP,
IOUT = 10 mA
f = 100 Hz
93
f = 217.5 Hz
90
f = 1 kHz
78
f = 10 kHz
62
f = 50 kHz
54
f = 100 kHz
50
f = 1 MHz
42
f = 3.25 MHz
35
Output Noise Voltage
BW = 10Hz to 100 kHz, VBAT = 4.2V,
COUT = 2.2 µF, All Outputs are Off
10
TSHTDWN
Thermal Shutdown
Temperature
160
Hysteresis
20
(14)
Line Transient
VBAT = (VOUT (NOM) + 1.0V) to (VOUT
(NOM) + 1.6V) in 30 µs
(14)
ROUT
IOUT = 0 mA to 10 mA in 10 µs
TON
mA
dB
µVRMS
°C
-70
30
100
DC Output Resistance
Turn on Time
mV
mV
(14)
(14)
150
1
IOUT = 10 mA to 0 mA in 10 µs
Overshoot on Startup
mA
-1
VBAT = (VOUT (NOM) + 1.6V) to (VOUT
(NOM) + 1.0V) in 30 µs
Load Transient
V
10
300
EN
ΔVOUT
1.82
185
mV
Ω
5
to 95% of VOUT (NOM)
mV
270
µs
(12) The device maintains stable, regulated output voltage without a load.
(13) Dropout voltage is the voltage difference between the supply voltage and the output voltage at which the output voltage drops to 100
mV below its nominal value.
(14) This parameter is specified by design and/or characterization and is not tested in production.
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TIMING WAVEFORMS
50%
50%
SCLK_IN
tpLH
tpHL
50%
50%
CLK1
Skew
Skew
50%
50%
CLK2
Figure 1. Clock Output Timing Waveforms
50%
50%
CLK_REQx
tpLH
tpHL
50%
50%
SCLK_REQ
Figure 2. Clock Request Timing Waveforms
CLK_DC
80%
CLKx
80%
20%
20%
tRISE
50%
tFALL
Figure 3. Rise / Fall Time and Duty Cycle Waveform for Clock Outputs
50%
CLK_REQx
tSET
50%
SCLK_IN
Figure 4. Setup Time from SCLK_IN to CLK_REQ
8
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Connection Diagram
4
CLK2
CLK_
REQ2
CLK_
REQ3
CLK3
3
CLK1
CLK_
REQ1
CLK_
REQ4
CLK4
2
Enable
VSS
SCLK_
REQ
SCL
1
VBAT
VOut
SCLK_IN
SDA
A
B
C
D
Figure 5. 16-Bump DSBGA
See YFQ0016 Package
PIN DESCRIPTIONS (1)
Pin Name
Port/Direction
Type
C1
Pin
SCLK_IN
Host
I
Source Clock Input
C2
SCLK_RQ
Host
O
Source Clock Request
A3
CLK1
Peripheral
O
Clock Output 1
B3
CLK_REQ1
Peripheral
I
Clock Request Input 1
A4
CLK2
Peripheral
O
Clock Output 2
B4
CLK_REQ2
Peripheral
I
Clock Request Input2
D4
CLK3
Peripheral
O
Clock Output 3
C4
CLK_REQ3
Peripheral
I
Clock Request Input 3
D3
CLK4
Peripheral
O
Clock Output 4
C3
CLK_REQ4
Peripheral
I
Clock Request Input 4
A2
ENABLE
Host
I
Enable Device, Active High
D2
SCL
Host
I
I2C Clock Input, 100 kΩ Pull-up to ENABLE
D1
SDA
Host/Bidrectional
I/O
A1
VBAT
Battery/Input
Power
Power Supply
B1
VOUT
LDO/Output
Power
Power Supply to Clock Source and Clock Outputs
B2
VSS
Ground
Ground
Ground Pin
(1)
DESCRIPTION
I2C Data I/O, 100 kΩ Pull-up to ENABLE
I = Input, O = Output, I/O = Input / Output
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VBAT
A1
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VOUT
B1
1.8V LDO
1
VDD_IO
0
SD LOGIC
SCLK_IN
C1
VBAT
ENABLE
SCL
SDA
CLOCK
TREE
DRIVER
A3
CLK1
A4
CLK2
D4
CLK3
D3
CLK4
A2
D2
2
I C
CONTROL
LOGIC
VDD_IO
D1
B3
SCLK_REQ
VOUT
CLOCK
REQUEST
C2
LMH2190
CLK_REQ1
B4
CLK_REQ2
C4
CLK_REQ3
C3
CLK_REQ4
B2
VSS
Figure 6. LMH2190 Block Diagram
10
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TYPICAL PERFORMANCE CHARACTERISTICS
Unless otherwise specified, TA = 25°C, VBAT = 3.5V, fSCLK_IN = 26 MHz, COUT = 2.2 µF, VDD_IO = 1.8V (See Figure 19),
Registers are in default configuration.
Supply Current
vs.
Supply Voltage
Supply Current
vs.
Input Clock Frequency
7.40
7.45
7.35
7.40
7.35
7.30
7.30
7.25
7.25
7.20
7.20
7.15
7.10
7.15
7.05
85°C
25°C
7.10
7.05
6
- All Clocks Toggling
- 22.5 pF Capacitive Load per CLK
- No external Capacitor on CLK1/2/3/4
- SCLK_IN = 0 to 1.8V Square Wave
6
5 - DC Mode
SUPPLY CURRENT (mA)
SUPPLY CURRENT (mA)
7.45
5
4
4
2
2
1
3.0
3.5
4.0
4.5
CLK1 Only Toggling
01
-40°C
2.5
All CLK's Toggling
33
5.0
0
5.5
0
10
VBAT (V)
Figure 8.
Supply Current
vs.
Capacitive Load
LDO Output Voltage
vs.
Supply Voltage
-40°C
1.80
25°C
1.78
1.78
All CLK's Toggling
6
6
40
1.80
- Appropriate Drive Strength Setting
15 - SCLK_IN = 0 to 1.8V Square Wave
12 - DC Mode
12
VOUT (V)
SUPPLY CURRENT (mA)
30
Figure 7.
15
9
9
20
FREQUENCY (MHz)
CLK1 Only Toggling
1.76
1.76
1.74
1.74
3
1.72
3
0
1.72
1.70
0
1.70
85°C
IOUT = 10 mA
0
1.82
10
20
30
40
50
3.0
3.5
4.0
4.5
CAPACITIVE LOAD (pF)
VBAT (V)
Figure 9.
Figure 10.
LDO Output Voltage
vs.
LDO Output Current
LDO Output Voltage
vs.
Time
5.0
5.5
2.0
1.82
1.8
-40°C
1.80
1.80
1.6
AMPLITUDE (V)
25°C
VOUT (V)
2.5
1.78
1.78
1.76
1.76
85°C
1.74
1.74
1.72
1.4
1.2
ENABLE
VOUT
1.0
0.8
0.6
0.4
0.2
1.72
0
2
4
6
8
10
IOUT (mA)
0.0
COUT = 2.2 PF
TIME (50 Ps/DIV)
Figure 11.
Figure 12.
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TYPICAL PERFORMANCE CHARACTERISTICS (continued)
Unless otherwise specified, TA = 25°C, VBAT = 3.5V, fSCLK_IN = 26 MHz, COUT = 2.2 µF, VDD_IO = 1.8V (See Figure 19),
Registers are in default configuration.
Additive Phase Noise
vs.
Frequency Offset
CLK1 Response, CL = 10 pF
-110
SCLK_IN
-120
-130
CLK3
0.5 V/DIV
ADDITIVE PHASENOISE (dBc/Hz)
-100
CLK4
-140
CLK1
-150
CLK1
CLK2
-160
-170
-180
100
DRIVE STRENGTH = 10 - 15 pF
1k
10k
100k
1M
FREQUENCY OFFSET (Hz)
TIME (5 ns/DIV)
Figure 13.
Figure 14.
CLK1 Response, CL = 22pF
CLK1 Response, CL = 33 pF
0.5 V/DIV
SCLK_IN
0.5 V/DIV
SCLK_IN
CLK1
CLK1
DRIVE STRENGTH = 15 - 22.5 pF
DRIVE STRENGTH = 22.5 - 33.5 pF
TIME (5 ns/DIV)
TIME (5 ns/DIV)
Figure 15.
Figure 16.
CLK1 Response, CL = 50 pF
Power Supply Rejection Ratio
vs.
Frequency
100
80
CLK1
PSRR (dB)
0.5 V/DIV
SCLK_IN
60
40
20
DRIVE STRENGTH = 33.5 - 50 pF
0
100
TIME (5 ns/DIV)
1k
10k
100k
1M
FREQUENCY (Hz)
Figure 17.
12
IOUT = 10 mA
VBAT: No capacitors
VOUT: 2.2 #F and 100 nF
Figure 18.
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APPLICATION INFORMATION
The LMH2190 is a quad channel configurable clock distribution device which supplies a digital system clock to
peripherals in mobile handsets or other applications. Examples of peripherals are Bluetooth, Wireless LAN,
and/or Digital Video Broadcast-H (DVB-H).
The LMH2190 provides a solution to clocking issues such as limited drive capability, frequency pulling and
crosstalk. The drive capability of a TCXO can be insufficient when traces are long and/ or multiple peripherals
are connected to one TCXO. The LMH2190’s clock outputs can be configured independently to drive capacitive
loads up to 50 pF per channel. The buffer function of the LMH2190 prevents frequency pulling of the TCXO.
Frequency pulling can occur when the TCXO observes varying loads. A peripheral device that shuts down can
cause this load variation for instance. Crosstalk between peripheral devices is minimal since each peripheral has
its own LMH2190 digital clock output. Also isolation from peripheral to TCXO is specified by use of the LMH2190.
Adding a component in the clock path inherently means adding noise. The LMH2190 though has excellent phase
noise specifications in order to minimize degradation of the clock quality. A typical LMH2190 application is
depicted in Figure 19.
The LMH2190 clock tree driver can be divided into 4 blocks:
• Clock tree driver
– The clock tree driver provides a clean clock to a maximum of 4 separately connected peripheral devices.
• Clock request logic
– Independent clock request inputs allow the peripheral to control when the particular clock should be
enabled. Further, the clock request inputs control the source clock request (SCLK_REQ) and enabling of
the LDO.
• Low Dropout regulator (LDO)
– The LDO provides a low noise, high PSRR supply voltage that enables low phase noise on the clock
outputs, and low quiescent current for portable applications. It can also be used to provide a low noise
supply to the TCXO eliminating the need for a separate LDO.
2
• I C Control logic
– An I2C control port enables re-configuration of settings of many features of the device in order to optimize
the device performance based on the application. For these settings see Table 2, Table 3, Table 4,
Table 5, and Table 6 in I2C Registers.
All the blocks can be switched into a low power-consumption mode to save energy. This functionality is
controlled via the ENABLE pin.
The following sections provide an explanation on PHASE NOISE and a detailed description of each block.
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VBAT
CBAT
VBAT
1 PF
A1
VOUT B1
1.8V LDO, 10 mA
COUT
2.2 PF
A3
CLK1
PERIPHERAL
A4
CIN
VDD
CCLK
10 nF
470 pF
CLOCK
GND
EN
SCLK_IN
C1
SCLK_REQ
C2
CLK2
PERIPHERAL
CLOCK
TREE
DRIVER
D4
CLK3
PERIPHERAL
D3
CLK4
CONTROL
LOGIC
PERIPHERAL
R1,2
5.1 k:
ENABLE
CPU/
BASE
BAND
A2
SCL
D2
SDA
D1
CLOCK
REQUEST
2
I C
LMH2190
B3
CLK_REQ1
B4
CLK_REQ2
C4
CLK_REQ3
C3
CLK_REQ4
B2
VSS
Figure 19. Typical LMH2190 Setup
PHASE NOISE
An important specification for oscillators and clock buffers is phase noise. It determines the timing and thus
accuracy of various peripheral devices in a cell phone such as Bluetooth, WLAN and DVB-H.
Phase noise is expressed in the frequency domain and is usually specified at a number of offset frequencies
from the carrier frequency. The phase noise of the oscillator and the LMH2190 together determine the phase
noise of the clock that is distributed to the peripheral devices. Therefore an additive phase noise is specified for
the LMH2190 rather than its total output phase noise since that depends on the TCXO connected to the
LMH2190.
Knowing the TCXO phase noise and the additive phase noise of the LMH2190, the total phase noise to the
peripheral can be calculated:
PN_TCXO
PN = 10 LOG 10
10
add.PN_LMH2190
+ 10
10
Where, PN is the total phase noise at the output of the LMH2190, PN_TCXO is the TCXO’s phase noise and
add.PN_LMH2190 is the additive phase noise of the LMH2190, all in dBc/Hz.
CLOCK TREE DRIVER
The clock tree driver consists of one input that drives 4 outputs (Figure 20). It is supplied by the highly accurate
1.8V LDO. In default configuration the outputs are switched on when the clock request inputs are high. The input
as well as the output can be configured in several ways though I2C programming.
14
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Clock Tree Driver Input
The source clock input (SCLK_IN) is the input for the clock tree driver. It can be configured to DC or AC coupled
mode. In shutdown mode, the input stage is completely switched off to prevent unnecessary power consumption
when the source clock is still present.
In the DC coupled mode, the clock input may range from 32 kHz to 27 MHz. DC coupling mode requires that the
input is a square wave.
In AC mode an external capacitor needs to be connected in series with the clock source and the SCLK_IN pin to
block external DC. Internally, a DC bias network centers it at about VOUT/2. This enables the use of a sine wave
clock source with a amplitude between 0.8 VPP and 1.8 VPP. The bias voltage is enabled only when the clock
request output is activated in order to eliminate the DC power. In the AC coupled mode, the clock input may
range from 13 MHz up to 27 MHz. It is assumed to be a sine wave. Signals with sharp edges, such as square
wave signals, should be prevented as the DC control loop will not be able to maintain its internal DC level.
Clock Tree Driver Outputs
The LMH2190's clock tree driver outputs have many modes of operation to reduce power consumption and
minimize EMI. The output drive strength of the LMH2190 can be selected in 4 steps based on the load
capacitance it needs to drive. The configuration can be done via the I2C interface.
There are two dedicated methods for reducing EMI that can be selected through the I2C interface. As shown in
Figure 21 and Figure 22 the first method (default) skews all of the clock edges individually, so that the EMI
generated by the switching is spread out over time. The second method inverts two of the outputs and also
skews one pair from the other.
CLK1 ENABLE
CLK1
CLK INPUT TYPE
REG00-Bit4
CLK2 ENABLE
CLK1 LOAD
REG01-Bit0:1
CLK2
DC
1
SCLK_IN
AC
0
SKEW
SETTING
CLK3 ENABLE
CLK2 LOAD
REG02-Bit0:1
CLK3
CLK TREE
REG00-Bit0
CLK4 ENABLE
CLK3 LOAD
REG03-Bit0:1
CLK4
CLK4 LOAD
REG04-Bit0:1
Figure 20. Clock Tree Driver
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SCLK_IN
SCLK_IN
CLK1
CLK1
CLK2
CLK2
CLK3
CLK3
CLK4
CLK4
Figure 21. Clock Outputs Timing: With Skew only
Figure 22. Clock Outputs Timing: With Skew and
Inversion
CLOCK REQUEST LOGIC
The clock request logic enables an independent control of the clock tree driver outputs (CLK1 to CLK4) as well
as an overall source clock request (SCLK_REQ) and LDO enabling. Since the clock request logic always needs
to be active, it is supplied by either the output of the LDO (VOUT) or by the external ENABLE. Further details
about the selection between VOUT and ENABLE can be found in the LOW DROPOUT REGULATOR section later
in the datasheet.
Clock Request Inputs
A clock request input is provided for each clock output (Figure 23). This allows the peripheral device to control
the LMH2190 when it wants to receive a clock. In case the peripheral device does not have clock request
functionality, the CLKx_REQ can be wired to a logic high level to enable the clock output (in default register
setting). Alternatively, it can be controlled through I2C. The CLKx_REQ input can be configured to be active high
or active low. When the LDO is off, the clock request logic still need to be powered such that it can turn on the
LDO. This is why the ENABLE input is used to power the Clock Request Logic in case the LDO is off. Although
the CLK_REQ logic is supplied with 1.8V LDO voltage (or ENABLE), the CLKx_REQ input can tolerate voltages
up to VBAT.
To prevent glitches on CLK outputs, enabling of the outputs is done synchronously. A latch is used to ensure that
the CLK outputs will be enabled on the falling edge of the source clock input (SCLK_IN).
16
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CLK_REQx INPUT POLARITY
REG0x-Bit2
CLK_REQx_FORCE ON
REG0x-Bit3
CLKx ENABLE
CLK_REQx
CLK_REQx INPUT VALUE
REG05-Bitx
1
0
200 kÖ
CLK_REQx_FORCE OFF
REG0x-Bit4
CLK_REQx PULL DOWN RESISTOR
REG0x-Bit5
Figure 23. Clock Request Input
System Clock Request Output
In the typical mode of operation, the clock request output will be enabled if one of the 4 CLK_REQ inputs is high
(Figure 24). However, this can be overridden via the I2C interface which has a register bit that forces the output
to be enabled, independent of the CLK_REQ input. The polarity of the output can be controlled via I2C
(CLK_REQ Output Polarity) along with whether the output is configured as push/pull, open drain or open source.
For the open drain case, there needs to be an external resistor that pulls the SCLK_REQ to a high level. This
high level may be greater than the LDO voltage of 1.8V, but not more than the supply voltage (VBAT) of the
LMH2190.
CLK_REQ OUTPUT TYPE
REG00-Bit1
CLK_REQ OUTPUT POLARITY
REG00-Bit2
VDD_IO
CLKx_ENABLE
0
SCLK_REQ
1
CLK_REQ OUTPUT MODE
REG00-Bit3
SCLK_REQ OUTPUT VALUE
REG05-Bit5
Figure 24. System Clock Request Output
The System Clock Request Output pin can be used to enable or disable an external TCXO to save power
consumption. See Figure 25. The LDO powers the TCXO, while the SCLK_REQ enables or disables the TCXO.
If the TXCO doesn't have an enable pin, power savings can be realized by switching off the LMH2190's LDO and
therewith the TCXO.
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VOUT
LMH2190
VDD
EN
SCLK_REQ
TCXO
CLK_OUT
SCLK_IN
GND
Figure 25. TCXO Powered from LMH2190's LDO
Note that the LMH2190 initializes to its default settings when VBAT is powered-up. As a consequence, the
LMH2190 is in it's default state until it is configured through I2C. Because of this configuration the CLK1/2/3/4
outputs may transmit the clock to a peripheral upon startup when it is not requested by the peripheral and before
the device is initialized through the I2C port. This may happen for instance when the default settings of the device
for SCLK_REQ and CLK_REQ1/2/3/4 polarities do not correspond to what is expected by the TCXO and the
peripheral. Care must be taken to prevent any unwanted behavior in the peripheral device until the I2C port
correctly configures the device. The setting of the registers is maintained as long as the VBAT voltage is present.
LOW DROPOUT REGULATOR
The linear and low dropout regulator (LDO) is used to regulate the input voltage, VBAT, to generate an accurate
1.8V supply voltage. This allows the LMH2190 to suppress VBAT voltage ripples. A voltage ripple would distort
clock edges causing phase noise on the distributed clock signal.
In default mode the LDO is powered-up when one or more Clock Request inputs are high. Therefore the Clock
Request Logic needs to be powered continuously such that it can wake-up the LMH2190 and its LDO. The
VDD_IO voltage that takes care of supplying the Clock Request Logic can therefore be driven by either the LDO
output voltage or the ENABLE signal. Normally the VDD_IO signal is connected to the LDO output, unless the LDO
is in a low power shutdown mode. In that case the ENABLE signal will drive VDD_IO (Figure 26). As soon as there
is a clock request, the built in LDO will power up and takes over the sourcing of VDD_IO from the ENABLE signal.
LDO
VBAT
VBAT
VOUT
VOUT
LDO_EN
1
LDO MODE
REG00-Bit5:6
0
VDD_IO
OFF
SD LOGIC
00
01
10
11
CLKx ENABLE
ENABLE
ON
THERMAL
SHUTDOWN
TSD
REG05-Bit0
Figure 26. Linear Regulator Block Diagram
The LDO contains thermal overheating detection. If it does overheat, the LMH2190 (except the register logic) will
shutdown and sets a status bit in the I2C status register.
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The LDO can be configured to be always ON for the case when it needs to supply power to the TCXO even
when the LMH2190 is not requesting any clocks to be distributed.
It is possible to use an external 1.8V supply connected to VOUT and shut off the internal LDO, although it is highly
recommended to use the internally generated 1.8V. If an external supply is used, care should be taken during
startup as the default configuration is for the internal LDO to be enabled. In this case, there could be contention
between the two supplies which could cause excessive current flow.
I2C CONTROL LOGIC
The LMH2190 can be controlled by a I2C host device. The I2C address of the LMH2190 is 38h. It can configure
the registers inside the LMH2190 to change the default configuration. The I2C communication is based on a
READ/WRITE structure, following the I2C transmission protocol. According to the I2C specification one set of pullup resistors needs to be present on the I2C bus.
Some of the features are for instance setting the polarity of the clock request inputs and outputs and setting the
drive strength of the clock outputs. It also allows direct control of the clock request signals and the LDO via the
I2C. The I2C interface is powered by the ENABLE, while the control logic and registers are powered by the VBAT.
I2C Data Validity
The data on SDA line must be stable during the HIGH period of the clock signal (SCL). In other words, the state
of the data line should only change when SCL is LOW (Figure 27).
SCL
SDA
data
change
allowed
data
valid
data
change
allowed
data
valid
data
change
allowed
Figure 27. I2C Signals: Data Validity
I2C Start and Stop Condition
START and STOP bits classify the beginning and the end of the I2C session. START condition is defined as SDA
signal transitioning from HIGH to LOW while SCL line is HIGH (Figure 28). STOP condition is defined as the
SDA transitioning from LOW to HIGH while SCL is HIGH. The I2C master always generates START and STOP
bits. The I2C bus is considered to be busy after START condition and free after STOP condition. During data
transmission, I2C master can generate repeated START conditions. First START and repeated START
conditions are equivalent, function-wise.
SDA
SCL
S
P
START condition
STOP condition
Figure 28. I2C Start and Stop Conditions
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Transferring Data
Every frame on the SDA line must be eight bits long, with the most significant bit (MSB) being transferred first.
Each byte of data has to be followed by an acknowledge bit. The acknowledge related clock pulse is generated
by the master. The transmitter releases the SDA line (HIGH) during the acknowledge clock pulse. The receiver
must pull down the SDA line during the 9th clock pulse, signifying an acknowledge. A receiver which has been
addressed must generate an acknowledge after each byte has been received.
After the START condition, the I2C master sends a chip address (Figure 29). This address is seven bits long
followed by an eight bit which is a data direction bit (R/W). For the eighth bit, a “0” indicates a WRITE and a “1”
indicates a READ. The second byte selects the register to which the data will be written. The third byte contains
data to write to the selected register.
MSB
LSB
ADR6
Bit7
ADR5
bit6
ADR4
bit5
ADR3
bit4
ADR2
bit3
ADR1
bit2
ADR0
bit1
R/W
bit0
2
I C SLAVE address (chip address)
Figure 29. I2C Chip Address
Register changes take effect at the SCL rising edge during the last ACK from slave. An example of a WRITE
cycle is given in Figure 30. When a READ function is to be accomplished, a WRITE function must precede the
READ function, as shown in the Read Cycle waveform (Figure 31).
ack from slave
ack from slave
start
MSB Chip Address LSB
w
ack MSB Register 0x02h LSB ack
start
slave address =
38h or 01110002
w
ack
MSB
ack from slave
Data
LSB
ack
stop
ack
stop
SCL
SDA
register address = 0x02h
ack
register 0x02h data
Figure 30. Example I2C Write Cycle
ack from slave
ack from slave repeated start
start MSB Chip Address LSB w ack MSB Register 0x00h LSB ack rs
ack from slave data from slave ack from master
MSB Chip Address LSB r ack MSB
Data
LSB ack stop
SCL
SDA
start
slave address =
38h or 01110002
w ack register address = 0x05h ack
rs
slave address =
38h or 01110002
r ack
register 0x05h data
ack stop
Figure 31. Example I2C Read Cycle
I2C Timing
The timing of the SDA and SCL signals is depicted in Figure 32 and the parameters are given in Table 1.
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SDA
10
8
7
6
1
8
2
7
SCL
5
1
4
3
9
Figure 32. I2C Timing Diagram
Table 1. I2C Timing
Symbol
fSCL
Limit
Parameter
Min
Max
Clock Frequency
400
1
Hold Time (repeated) START Condition
2
3
Units
kHz
0.6
µs
Clock Low Time
1.3
ns
Clock High Time
600
ns
4
Setup Time for a Repeated START Condition
600
ns
5
Data Hold Time (Output direction, delay generated by
LMH2190)
300
900
µs
5
Data Hold Time (Input direction, delay generated by the
Master)
0
900
ns
6
Data Setup Time
7
Rise Time of SDA and SCL
20+0.1 Cb
300
ns
8
Fall Time of SDA and SCL
10+0.1 Cb
300
ns
9
Set-up Time for STOP condition
600
10
Bus Free Time between a STOP and a START Condition
1.3
Cb
Capacitive Load for Each Bus Line
10
100
ns
ns
µs
200
pF
I2C Registers
Table 2. Configuration Register (1)
Field
Bits
Description
Output Mode
[0]
Sets the timing relationship of the clock
outputs (Figure 21 and Figure 22).
0 - All 4 outputs are skewed from each
other
1 - Two pair of outputs where one output of
the pair is the inversion of the other and the
second pair is skewed from the first pair.
Clock Request Output Type
[1]
Sets whether the output is push-pull or open
drain.
0 - Push-Pull Output
1 - Open Drain/Source Output (Open drain
with Active low output, Open source with
Active high output).
Clock Request Output Polarity
[2]
Sets whether the clock request output is
active low or active high.
0 - Active low output
1 - Active high output
Clock Request Output Mode
[3]
Sets how the clock request output operates.
0 - Use clock request inputs
1 - Force the clock request output to be
asserted.
(1)
Address = 00H, type = R/W, reset value = 44H, 0100_0100, Bold face settings are the default configuration.
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Table 2. Configuration Register(1) (continued)
Field
Bits
Clock Input Type
Description
[4]
LDO Mode
[6-5]
Reserved
[7]
Sets whether the input is AC or DC coupled.
0 - AC coupled
1 - DC coupled
Sets the regulator mode of operation.
00 - OFF
01 - Reserved
10 - Track Clock Requests
11 - Force ON
Table 3. CLK1 Output Register (1)
Field
Bits
Description
CLK1 Load
[1-0]
Sets the drive strength of the clock output
based on the capacitive load.
00 - 10pF to 15pF
01 - 15pF to 22.5pF
10 - 22.5pF to 33.5pF
11 - 33.5pF to 50pF
CLK_REQ1 Input Polarity
[2]
Sets whether a logic low or high enables the
clock output.
0 - Logic low enables the clock output.
1 - Logic high enables the clock output.
CLK_REQ1 Force ON Control
[3]
Selects whether to use a clock request or
I2C logic to enable the output.
0 - Use the clock request pin to control
the output.
1 - Force the clock output to be enabled
(Force ON).
CLK_REQ1 Force OFF Control
[4]
Selects whether to use a clock request or
I2C logic to disable the output.
0 - Use the clock request pin to control
the output.
1 - Force the clock output to be disabled
(Force OFF). ”Force OFF" overrides ”Force
ON".
CLK_REQ1 Pull down Resistor
[5]
Selects whether an internal 200 kΩ pull
down resistor on the clock request input to
GND is present.
0 - No internal pull down resistor is
present.
1 - Internal 200 kΩ pull-down resistor is
present.
Reserved
[6]
Reserved
[7]
(1)
Address = 01H, type = R/W, reset value = 06H, 0000_0110, Bold face settings are the default configuration.
Table 4. CLK2 Output Register (1)
Field
Bits
Description
CLK2 Load
[1-0]
Sets the drive strength of the clock output
based on the capacitive load.
00 - 10pF to 15pF
01 - 15pF to 22.5pF
10 - 22.5pF to 33.5pF
11 - 33.5pF to 50pF
CLK_REQ2 Input Polarity
(1)
22
[2]
Sets whether a logic low or high enables the
clock output.
0 - Logic low enables the clock output.
1 - Logic high enables the clock output.
Address = 02H, type = R/W, reset value = 06H, 0000_0110, Bold face settings are the default configuration.
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Table 4. CLK2 Output Register(1) (continued)
Field
Bits
Description
CLK_REQ2 Force ON Control
[3]
Selects whether to use a clock request or
I2C logic to enable the output.
0 - Use the clock request pin to control
the output.
1 - Force the clock output to be enabled
(Force ON).
CLK_REQ2 Force OFF Control
[4]
Selects whether to use a clock request or
I2C logic to disable the output.
0 - Use the clock request pin to control
the output.
1 - Force the clock output to be disabled
(Force OFF). ”Force OFF" overrides ”Force
ON".
CLK_REQ2 Pull down Resistor
[5]
Selects whether an internal 200 kΩ pull
down resistor on the clock request input to
GND is present.
0 - No internal pull down resistor is
present.
1 - Internal 200 kΩ pull-down resistor is
present.
Reserved
[6]
Reserved
[7]
Table 5. CLK3 Output Register (1)
Field
Bits
Description
CLK3 Load
[1-0]
Sets the drive strength of the clock output
based on the capacitive load.
00 - 10pF to 15pF
01 - 15pF to 22.5pF
10 - 22.5pF to 33.5pF
11 - 33.5pF to 50pF
CLK_REQ3 Input Polarity
[2]
Sets whether a logic low or high enables the
clock output.
0 - Logic low enables the clock output.
1 - Logic high enables the clock output.
CLK_REQ3 Force ON Control
[3]
Selects whether to use a clock request or
I2C logic to enable the output.
0 - Use the clock request pin to control
the output.
1 - Force the clock output to be enabled
(Force ON).
CLK_REQ3 Force OFF Control
[4]
Selects whether to use a clock request or
I2C logic to disable the output.
0 - Use the clock request pin to control
the output.
1 - Force the clock output to be disabled
(Force OFF). ”Force OFF" overrides ”Force
ON".
CLK_REQ3 Pull down Resistor
[5]
Selects whether an internal 200 kΩ pull
down resistor on the clock request input to
GND is present.
0 - No internal pull down resistor is
present.
1 - Internal 200 kΩ pull-down resistor is
present.
Reserved
[6]
Reserved
[7]
(1)
Address = 03H, type = R/W, reset value = 06H, 0000_0110, Bold face settings are the default configuration.
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Table 6. CLK4 Output Register (1)
Field
Bits
Description
CLK4 Load
[1-0]
Sets the drive strength of the clock output
based on the capacitive load.
00 - 10pF to 15pF
01 - 15pF to 22.5pF
10 - 22.5pF to 33.5pF
11 - 33.5pF to 50pF
CLK_REQ4 Input Polarity
[2]
Sets whether a logic low or high enables the
clock output.
0 - Logic low enables the clock output.
1 - Logic high enables the clock output.
CLK_REQ4 Force ON Control
[3]
Selects whether to use a clock request or
I2C logic to enable the output.
0 - Use the clock request pin to control
the output.
1 - Force the clock output to be enabled
(Force ON).
CLK_REQ4 Force OFF Control
[4]
Selects whether to use a clock request or
I2C logic to disable the output.
0 - Use the clock request pin to control
the output.
1 - Force the clock output to be disabled
(Force OFF). ”Force OFF" overrides ”Force
ON".
CLK_REQ4 Pull down Resistor
[5]
Selects whether an internal 200 kΩ pull
down resistor on the clock request input to
GND is present.
0 - No internal pull down resistor is
present.
1 - Internal 200 kΩ pull-down resistor is
present.
Reserved
[6]
Reserved
[7]
(1)
Address = 04H, type = R/W, reset value = 06H, 0000_0110, Bold face settings are the default configuration.
Table 7. Status Register (1)
Field
Bits
Description
Thermal Shutdown (TSD)
[0]
Indicates if a thermal shutdown event has occurred.
0 - Thermal shutdown has not occurred.
1 - Thermal shutdown has occurred
CLK_REQ1 Input Value
[1]
Captures the state of the generated clock request
input value.
0 - Generated clock request is low.
1 - Generated clock request is high.
CLK_REQ2 Input Value
[2]
Captures the state of the generated clock request
input value.
0 - Generated clock request is low.
1 - Generated clock request is high.
CLK_REQ3 Input Value
[3]
Captures the state of the generated clock request
input value.
0 - Generated clock request is low.
1 - Generated clock request is high.
CLK_REQ4 Input Value
[4]
Captures the state of the generated clock request
input value.
0 - Generated clock request is low.
1 - Generated clock request is high.
SCLK_REQ Output Value
[5]
Captures the state of the system clock request output
value.
0 - System clock request is low.
1 - System clock request is high.
Reserved
[6]
(1)
24
Address = 05H, type = R
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LMH2190
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SNAS473H – JUNE 2009 – REVISED MAY 2013
Table 7. Status Register(1) (continued)
Field
Bits
Reserved
Description
[7]
LAYOUT RECOMMENDATIONS
As with any other device, careful attention must be paid to the board layout. If the board isn't properly designed,
the performance of the device can be less than might be expected. Especially the input clock trace (SCLK_IN)
and output traces (CLK1/2/3/4) should be as short as possible to reduce the capacitive load observed by the
clock outputs. Also proper decoupling close to the device is necessary. Beside a capacitor in the µF range (See
Table 8), a capacitor of 100 nF on VBAT and VOUT is recommended close to device. The equivalent series
resistance (ESR) of the capacitors should be sufficiently low. A standard capacitor is usually adequate. Advised
values are given in Table 8. An evaluation board is available to ease evaluation and demonstrate a proper board
layout.
Table 8. Recommended Component Values
Symbol
Parameter
Min
Typ
CBAT (1)
Capacitor on VBAT
0.47
1
COUT (1)
Capacitor on VOUT
1
2.2
ESR
Equivalent Series Resistance
5
CSCLK_IN
Input AC Coupling Capacitor
330
(1)
470
Max
Units
µF
500
mΩ
10000
pF
CBAT, COUT: Low-ESR Surface-Mount Ceramic Capacitors (MLCC's) used in setting electrical characteristics.
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REVISION HISTORY
Changes from Revision G (April 2013) to Revision H
•
26
Page
Changed layout of National Data Sheet to TI format .......................................................................................................... 25
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PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
(4/5)
(6)
LMH2190TM-38/NOPB
ACTIVE
DSBGA
YFQ
16
250
RoHS & Green
SNAGCU
Level-1-260C-UNLIM
-20 to 85
AA
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of
