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LMH5401
SBOS710D – OCTOBER 2014 – REVISED FEBRUARY 2018
LMH5401 8-GHz, Low-Noise, Low-Power, Fully-Differential Amplifier
1 Features
3 Description
•
•
The LMH5401 device is a very high-performance,
differential amplifier optimized for radio frequency
(RF), intermediate frequency (IF), or high-speed, dccoupled, time-domain applications. The device is
ideal for dc- or ac-coupled applications that may
require
a
single-ended-to-differential
(SE-DE)
conversion when driving an analog-to-digital
converter (ADC). The LMH5401 generates very low
levels of second- and third-order distortion when
operating in SE-DE or differential-to-differential (DEDE) mode.
1
•
•
•
•
•
•
•
•
Gain Bandwidth Product (GBP): 8 GHz
Excellent Linearity Performance:
DC to 2 GHz, G = 12 dB
Slew Rate: 17,500 V/µs
Low HD2, HD3 Distortion
(1 VPP, 200 Ω, DE-DE, G = 12 dB):
– 100 MHz: HD2 at –104 dBc, HD3 at –96 dBc
– 200 MHz: HD2 at –95 dBc, HD3 at –92 dBc
– 500 MHz: HD2 at –80 dBc, HD3 at –77 dBc
– 1 GHz: HD2 at –64 dBc, HD3 at –58 dBc
Low IMD2, IMD3 Distortion
(2 VPP, 200 Ω, DE-DE, G = 12 dB):
– 200 MHz: IMD2 at –96 dBc, IMD3 at –95 dBc
– 500 MHz: IMD2 at –80 dBc, IMD3 at –83 dBc
– 1 GHz: IMD2 at –70 dBc, IMD3 at –63 dBc
Input Voltage Noise: 1.25 nV/√Hz
Input Current Noise: 3.5 pA/√Hz
Supports Single- and Dual-Supply Operation
Power Consumption: 55 mA
Power-Down Feature
2 Applications
•
•
•
•
•
•
•
•
GSPS ADC Drivers
ADC Drivers for High-Speed Data Acquisition
ADC Drivers for 1-GBPS Ethernet over Microwave
DAC Buffers
IF, RF, and Baseband Gain Blocks
SAW Filter Buffers and Drivers
Balun Replacement DC to 2 GHz
Level Shifters
Distortion versus Frequency
(G = 12 dB, SE-DE, RL = 200 Ω, VPP = 2 V)
0
A common-mode reference input pin aligns the
amplifier output common-mode with the ADC input
requirements. Power supplies between 3.3 V and 5 V
can be selected and dual-supply operation is
supported when required by the application. A powerdown feature is also available for power savings.
This level of performance is achieved at a very low
power level of 275 mW when a 5-V supply is used.
The device is fabricated in Texas Instruments'
advanced complementary BiCMOS process and is
available in a space-saving, UQFN-14 package for
higher performance.
Device Information(1)
DEVICE NAME
PACKAGE
LMH5401
BODY SIZE
UQFN (14)
2.50 mm × 2.50 mm
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
LMH5401 Driving an ADC12J4000
HD2
HD3
±20
RT
50-:,
Single-Ended
Input
RF
RG
FB+
25 :
10 :
IN-
+
±40
LMH5401
IN+
RM
RF
OUT+ RO
OUT_AMP
10 :
RG
±60
+
RO
+
Distortion (dBc)
The amplifier is optimized for use in both SE-DE and
DE-DE systems. The device has unprecedented
usable bandwidth from DC to 2 GHz. The LMH5401
can be used for SE-DE conversions in the signal
chain without external baluns in a wide range of
applications such as test and measurement,
broadband communications, and high-speed data
acquisition.
FB-
Filter
IN+
ADC
IN-
OUT
25 :
CM
±80
±100
±120
10
100
Frequency (MHz)
1k
C014
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
LMH5401
SBOS710D – OCTOBER 2014 – REVISED FEBRUARY 2018
www.ti.com
Table of Contents
1
2
3
4
5
6
Features ..................................................................
Applications ...........................................................
Description .............................................................
Revision History.....................................................
Pin Configuration and Functions .........................
Specifications.........................................................
6.1
6.2
6.3
6.4
6.5
6.6
6.7
6.8
6.9
7
1
1
1
2
4
5
Absolute Maximum Ratings ...................................... 5
ESD Ratings.............................................................. 5
Recommended Operating Conditions....................... 5
Thermal Information .................................................. 5
Electrical Characteristics: VS = 5 V........................... 6
Electrical Characteristics: VS = 3.3 V........................ 8
Typical Characteristics: 5 V .................................... 10
Typical Characteristics: 3.3 V ................................. 15
Typical Characteristics: 3.3-V to 5-V Supply
Range....................................................................... 19
Parameter Measurement Information ................ 20
7.1
7.2
7.3
7.4
7.5
7.6
7.7
7.8
Output Reference Points......................................... 20
ATE Testing and DC Measurements ...................... 20
Frequency Response .............................................. 20
S-Parameters .......................................................... 21
Frequency Response with Capacitive Load............ 21
Distortion ................................................................. 21
Noise Figure............................................................ 21
Pulse Response, Slew Rate, and Overdrive Recovery
................................................................................. 21
7.9 Power Down............................................................ 22
7.10 VCM Frequency Response .................................... 22
7.11 Test Schematics.................................................... 22
8
Detailed Description ............................................ 24
8.1
8.2
8.3
8.4
9
Overview .................................................................
Functional Block Diagram .......................................
Feature Description.................................................
Device Functional Modes........................................
24
24
25
31
Application and Implementation ........................ 32
9.1 Application Information............................................ 32
9.2 Typical Application .................................................. 35
9.3 Do's and Don'ts ...................................................... 43
10 Power Supply Recommendations ..................... 44
10.1
10.2
10.3
10.4
Supply Voltage ......................................................
Single-Supply ........................................................
Split-Supply ...........................................................
Supply Decoupling ................................................
44
44
44
44
11 Layout................................................................... 45
11.1 Layout Guidelines ................................................. 45
11.2 Layout Example .................................................... 46
12 Device and Documentation Support ................. 48
12.1
12.2
12.3
12.4
12.5
12.6
12.7
Device Support......................................................
Documentation Support ........................................
Receiving Notification of Documentation Updates
Community Resources..........................................
Trademarks ...........................................................
Electrostatic Discharge Caution ............................
Glossary ................................................................
48
48
48
48
49
49
49
13 Mechanical, Packaging, and Orderable
Information ........................................................... 49
4 Revision History
Changes from Revision C (October 2017) to Revision D
Page
•
Added table note to Pin Functions table to distinguish pin types........................................................................................... 4
•
Changed GND and PD pin descriptions in Pin Functions table ............................................................................................. 4
•
Changed VOUT_AMP value from 2 VPP to 1 VPP in condition statement of HD2 and HD3 curve ....................................... 15
•
Changed VOUT_AMP value from 2 VPP to 1 VPP in condition statement of HD2 and HD3 Differential curve..................... 16
•
Changed VOUT_AMP value from 2 VPP to 1 VPP in condition statement of HD2 and HD3 vs Output Voltage curve ......... 16
•
Changed VOUT_AMP value from 2 VPP to 1 VPP in condition statement of HD2 and HD3 vs Input Common-Mode
Voltage curve........................................................................................................................................................................ 16
•
Changed VOUT_AMP value from 2 VPP to 1 VPP in condition statement of HD2 and HD3 vs Output Common-Mode
Voltage curve........................................................................................................................................................................ 16
•
Corrected and deleted note from Functional Block Diagram................................................................................................ 24
•
Added Power Down and Ground Pins subsection to Feature Description section .............................................................. 25
Changes from Revision B (January 2015) to Revision C
Page
•
Added Input, VIO, IIB, and IIO parameters to 5-V Electrical Characteristics table ................................................................... 6
•
Changed RT and RG2 values in first row of Table 2 ............................................................................................................. 21
•
Changed Functional Block Diagram graphic ........................................................................................................................ 24
•
Changed Device Comparison Table to be a separate sub-section within Feature Description section............................... 30
•
Added Driving Unmatched Loads For Lower Loss section .................................................................................................. 36
2
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•
SBOS710D – OCTOBER 2014 – REVISED FEBRUARY 2018
Changed 8 MHz to 8 GHz in first sentence of Layout Guidelines section .......................................................................... 45
Changes from Revision A (October 2014) to Revision B
Page
•
Added dc-coupled to first sentence of Description section ................................................................................................... 1
•
Changed second sentence of second paragraph in Description section ............................................................................... 1
•
Updated ESD Ratings table to current standards ................................................................................................................. 5
•
Changed AC Performance, IMD3 and IMD2 parameter test conditions in 5-V Electrical Characteristics table ................... 6
•
Changed Input, VICL parameter maximum specification in 5-V Electrical Characteristics table ............................................. 6
•
Changed Input, VICL parameter maximum specification in 3.3-V Electrical Characteristics table ......................................... 8
•
Changed Output, VOCRH parameter test condition from Output voltage range low to TA = –40°C to 85°C in 3.3-V
Electrical Characteristics table .............................................................................................................................................. 9
•
Changed Typical Characteristics curves: updated color scheme, grammatical edits throughout curves ........................... 10
•
Added Large-Signal to title of Figure 2, Figure 4, and Figure 6 .......................................................................................... 10
•
Added Large-Signal to title of Figure 8 ................................................................................................................................ 10
•
Changed Differential-Ended to Differential in title of Figure 11 ........................................................................................... 10
•
Added Large-Signal to titles of Figure 30, Figure 32, and Figure 34 .................................................................................. 15
•
Added Large-Signal to title of Figure 36 .............................................................................................................................. 15
•
Changed correction to reduction in second paragraph of Output Reference Points section ............................................... 20
•
Changed header for last column in Table 1 ........................................................................................................................ 21
•
ChangedFigure 56 through Figure 59: modifications to figures, added AV = 4 V/V to titles ................................................ 22
•
Deleted last sentence from first paragraph of the Fully-Differential Amplifier section.......................................................... 25
•
Changed 1.2 V to the specified minimum voltage in the third paragraph of the Fully-Differential Amplifier section............ 25
•
Added sixth sentence stating the feedback path must always be DC-coupled to the AC-Coupled Signal Path
Considerations section ......................................................................................................................................................... 25
•
Added AV = 4 V/V to title of Figure 62 ................................................................................................................................. 30
•
Deleted example from the Operation with a Single Supply section ..................................................................................... 31
•
Added Stability section ........................................................................................................................................................ 32
•
Changed 15 dB to 19 dB in third paragraph of SFDR Considerations section ................................................................... 38
•
Added Figure 75 to the Active Balun section ...................................................................................................................... 42
Changes from Original (October 2014) to Revision A
Page
•
Changed Output Common-Mode Control Pin, VCM voltage range low and high parameter typical specifications in 5-V
Electrical Characteristics ........................................................................................................................................................ 7
•
Changed Output Common-Mode Control Pin, VCM voltage range low and high parameter specifications in 3.3-V
Electrical Characteristics table ............................................................................................................................................... 9
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SBOS710D – OCTOBER 2014 – REVISED FEBRUARY 2018
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5 Pin Configuration and Functions
RMS Package
14-Pin UQFN
Top View
VS
CM
VS+
3
2
1
LMH5401
25 :
FB+
4
IN
5
IN+
6
FB
7
14
GND
13
OUT+
12
OUT
11
GND
10 :
10 :
+
25 :
8
9
10
VS
PD
VS+
Pin Functions
PIN
NAME
NO.
TYPE
DESCRIPTION
CM
2
I
Input pin to set amplifier output common-mode voltage
FB–
7
O
Negative output feedback component connection
FB+
4
O
Positive output feedback component connection
GND
11, 14
P
Power down ground. See Power Down and Ground Pins
IN–
5
I
Negative input pin
IN+
6
I
Positive input pin
OUT–
12
O
Negative output pin
OUT+
13
O
Positive output pin
PD
9
I
Power-down (logic 1 = power down). See Power Down and Ground Pins
VS–
3, 8
P
Negative supply voltage
VS+
1, 10
P
Positive supply voltage
4
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SBOS710D – OCTOBER 2014 – REVISED FEBRUARY 2018
6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted) (1)
MIN
MAX
UNIT
5.5
V
Power supply
Input voltage range
(VS+) + 0.7
V
Input current
(VS–) – 0.7
10
mA
Output current (sourcing or sinking) OUT+, OUT–
100
mA
Continuous power dissipation
See Thermal Information table
Maximum junction temperature, TJ
150
°C
Maximum junction temperature, continuous operation, long-term reliability
125
°C
Operating free-air temperature, TA
–40
85
°C
Storage temperature, Tstg
–40
150
°C
(1)
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
6.2 ESD Ratings
VALUE
V(ESD)
(1)
(2)
Electrostatic discharge
Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001 (1)
±3500
Charged-device model (CDM), per JEDEC specification JESD22-C101 (2)
±1000
UNIT
V
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
6.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
MIN
NOM
MAX
Supply voltage (VS = VS+ – VS–)
3.15
5
5.25
V
Operating junction temperature, TJ
–40
125
°C
Ambient operating air temperature, TA
–40
85
°C
25
UNIT
6.4 Thermal Information
LMH5401
THERMAL METRIC (1)
RMS (UQFN)
UNIT
14 PINS
RθJA
Junction-to-ambient thermal resistance
101
°C/W
RθJC(top)
Junction-to-case (top) thermal resistance
51
°C/W
RθJB
Junction-to-board thermal resistance
61
°C/W
ψJT
Junction-to-top characterization parameter
4.2
°C/W
ψJB
Junction-to-board characterization parameter
61
°C/W
RθJC(bot)
Junction-to-case (bottom) thermal resistance
N/A
°C/W
(1)
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
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SBOS710D – OCTOBER 2014 – REVISED FEBRUARY 2018
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6.5 Electrical Characteristics: VS = 5 V
at TA = 25°C, VS+ = 2.5 V, VS– = –2.5 V, VCM = 0 V, RL = 200-Ω differential, G = 12 dB (4 V/V), single-ended input,
differential output, and RS = 50 Ω, (unless otherwise noted) (1)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
TEST
LEVEL (2)
AC PERFORMANCE
GBP
Gain bandwidth product
G = 30 dB (32 V/V)
8
GHz
C
SSBW
Small-signal, –3-dB bandwidth
VO = 200 mVPP
6.2
GHz
C
LSBW
Large-signal, –3-dB bandwidth
VO = 2 VPP
4.8
GHz
C
Bandwidth for 0.1-dB flatness
VO = 2 VPP
800
MHz
C
Slew rate
2-V step
17500
V/µs
C
Rise and fall time
1-V step, 10% to 90%
80
ps
C
Overdrive recovery
Overdrive = ±0.5 V
300
ps
C
Output balance error
f = 1 GHz
47
dBc
C
Output impedance
At DC, differential
0.1% settling time
2 V, RL = 200 Ω
SR
zo
Second-order harmonic
distortion
HD2
HD3
Third-order harmonic distortion
IMD3
IMD2
Third-order intermodulation
Second-order intermodulation
16
20
24
1
Ω
A
ns
C
f = 100 MHz, VO = 2 VPP
–99
dBc
C
f = 200 MHz, VO = 2 VPP
–92
dBc
C
f = 500 MHz, VO = 2 VPP
–75
dBc
C
f = 1 GHz, VO = 2 VPP
–56
dBc
C
f = 100 MHz, VO = 2 VPP
–94
dBc
C
f = 200 MHz, VO = 2 VPP
–90
dBc
C
f = 500 MHz, VO = 2 VPP
–75
dBc
C
f = 1 GHz, VO = 2 VPP
–58
dBc
C
f = 100 MHz, VO = 1 VPP per tone
–95
dBc
C
f = 200 MHz, VO = 1 VPP per tone
–91
dBc
C
f = 500 MHz, VO = 1 VPP per tone
–75
dBc
C
f = 1 GHz, VO = 1 VPP per tone
–60
dBc
C
f = 100 MHz, VO = 1 VPP per tone
–95
dBc
C
f = 200 MHz, VO = 1 VPP per tone
–89
dBc
C
f = 500 MHz, VO = 1 VPP per tone
–71
dBc
C
f = 1 GHz, VO = 1 VPP per tone
–52
dBc
C
1.25
nV/√Hz
C
3.5
pA/√Hz
C
9.6
dB
C
NOISE PERFORMANCE
en
Input voltage noise density
in
Input noise current
NF
Noise figure
RS = 50 Ω, SE-DE, 200 MHz
(see Figure 59)
INPUT
VOS
Input offset voltage
±0.5
±5
mV
A
IB
Input bias current
70
150
µA
A
IOS
Input offset current
±1
±10
µA
A
Ω
C
V
A
V
A
dBc
C
Differential resistance
VICL
Input common-mode
low voltage
VICH
Input common-mode
high voltage
CMRR
Common-mode rejection ratio
(1)
(2)
6
Open-loop
4600
VS–
(VS+) – 1.41
Differential, 1-VPP input shift, DC
(VS+) – 1.2
72
(VS–) + 0.41
The input resistance and corresponding gain are obtained with the external resistance added.
Test levels: (A) 100% tested at 25°C. Overtemperature limits by characterization and simulation. (B) Limits set by characterization and
simulation. (C) Typical value only for information.
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Electrical Characteristics: VS = 5 V (continued)
at TA = 25°C, VS+ = 2.5 V, VS– = –2.5 V, VCM = 0 V, RL = 200-Ω differential, G = 12 dB (4 V/V), single-ended input,
differential output, and RS = 50 Ω, (unless otherwise noted)(1)
PARAMETER
TEST CONDITIONS
UNIT
TEST
LEVEL (2)
(VS+) – 1.1
V
A
(VS+) – 1.2
V
C
(VS–) + 1.1
V
A
(VS–) + 1.2
V
C
5.8
VPP
C
50
mA
A
MIN
TYP
(VS+) – 1.3
MAX
OUTPUT
VOCRH
Output voltage range, high
Measured
single-ended
VOCRL
Output voltage range, low
Measured
single-ended
VOD
Differential output voltage swing Differential
IOD
Differential output current
TA = 25°C
TA = –40°C to
+85°C
TA = 25°C
(VS–) + 1.3
TA = –40°C to
+85°C
VO = 0 V (3)
40
POWER SUPPLY
VS
Supply voltage
PSRR
IQ
Power-supply rejection ratio
Quiescent current
V
A
VS–
3.15
–50
–80
5.25
dB
A
VS+
–60
–82
dB
A
Power down = 0
50
55
62
mA
A
Power down = 1
1
3
6
mA
A
OUTPUT COMMON-MODE CONTROL PIN (VCM)
SSBW
VOCM
Small-signal bandwidth
VOCM = 100 mVPP
1.2
GHz
C
VCM slew rate
VOCM = 500 mVPP
2900
V/µs
C
VCM voltage range low
Differential gain shift < 1 dB
V
A
VCM voltage range high
Differential gain shift < 1 dB
V
A
VCM gain
VCM = 0 V
V/V
A
VOCM output common-mode
offset from VCM input voltage
VCM = 0 V
–27
mV
C
Common-mode offset voltage
Output-referred
0.4
mV
A
V
A
(VS–) + 1.4
(VS+) – 2
(VS+) – 1.4
0.98
1
(VS–) + 2
1.01
POWER DOWN (PD PIN)
VT
Enable or disable voltage
threshold
Device powers on below 0.8 V
Device powers down above 1.2 V
Power down quiescent current
(3)
0.9
1
1.1
1.2
3
6
mA
A
Power down bias current
Power down = 2.5 V
10
±100
µA
C
Turnon time delay
Time to VO = 90% of final value
10
ns
C
Turnoff time delay
Time to VO = 10% of original value
10
ns
C
This test shorts the outputs to ground (midsupply) then sources or sinks 60 mA and measures the deviation from the initial condition.
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6.6 Electrical Characteristics: VS = 3.3 V
at TA = 25°C, VS+ = 1.65 V, VS– = –1.65 V, VCM = 0 V, RL = 200-Ω differential, G = 12 dB (4 V/V), single-ended input and
differential output, and input and output referenced to midsupply, (unless otherwise noted.) Measured using an EVM as
discussed in the Parameter Measurement Information section.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
TEST
LEVEL (1)
AC PERFORMANCE
GBP
Gain bandwidth product
G = 30 dB (32 V/V)
8
MHz
C
SSBW
Small-signal, –3-dB bandwidth
VO = 200 mVPP
6
GHz
C
LSBW
Large-signal, –3-dB bandwidth
VO = 2 VPP
4.4
GHz
C
Bandwidth for 0.1-dB flatness
VO = 2 VPP
700
MHz
C
Slew rate
2-V step
17500
V/µs
C
Rise and fall time
1-V step, 10% to 90%
90
ps
C
Overdrive recovery
Overdrive = ±0.5 V
400
ps
C
Output balance error
f = 1 GHz
47
dBc
C
Output impedance
At DC
0.1% settling time
2 V, RL = 200 Ω
SR
zo
Second-order harmonic
distortion
HD2
HD3
Third-order harmonic distortion
IMD2
IMD3
Second-order intermodulation
distortion
Third-order intermodulation
distortion
16
20
24
1
Ω
A
ns
C
f = 100 MHz, VO = 1 VPP
–100
dBc
C
f = 200 MHz, VO = 1 VPP
–94
dBc
C
f = 500 MHz, VO = 1 VPP
–78.5
dBc
C
f = 1 GHz, VO = 1 VPP
–58
dBc
C
f = 100 MHz, VO = 1 VPP
–86
dBc
C
f = 200 MHz, VO = 1 VPP
–78
dBc
C
f = 500 MHz, VO = 1 VPP
–64
dBc
C
f = 1 GHz, VO = 1 VPP
–52
dBc
C
f = 100 MHz, VO = 0.5 VPP per tone
–95
dBc
C
f = 200 MHz, VO = 0.5 VPP per tone
–95
dBc
C
f = 500 MHz, VO = 0.5 VPP per tone
–81
dBc
C
f = 1 GHz, VO = 0.5 VPP per tone
–66
dBc
C
f = 100 MHz, VO = 0.5 VPP per tone
–101
dBc
C
f = 200 MHz, VO = 0.5 VPP per tone
–95
dBc
C
f = 500 MHz, VO = 0.5 VPP per tone
–82
dBc
C
f = 1 GHz, VO = 0.5 VPP per tone
–66
dBc
C
1.25
nV/√Hz
C
3.5
pA/√Hz
C
9.6
dB
C
4600
Ω
C
V
A
V
A
dBc
C
NOISE PERFORMANCE
en
Input voltage noise density
in
Input noise current
NF
Noise figure
RS = 50 Ω, SE-DE, G = 12 dB,
200 MHz
INPUT
Zid
Differential impedance
VICL
Input common-mode
low voltage
VICH
Input common-mode
high voltage
CMRR
Common-mode rejection ratio
(1)
8
(VS–)
(VS+) – 1.41
Differential, 1-VPP input shift, DC
(VS+) – 1.2
–72
(VS–) + 0.41
Test levels: (A) 100% tested at 25°C. Overtemperature limits by characterization and simulation. (B) Limits set by characterization and
simulation. (C) Typical value only for information.
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Electrical Characteristics: VS = 3.3 V (continued)
at TA = 25°C, VS+ = 1.65 V, VS– = –1.65 V, VCM = 0 V, RL = 200-Ω differential, G = 12 dB (4 V/V), single-ended input and
differential output, and input and output referenced to midsupply, (unless otherwise noted.) Measured using an EVM as
discussed in the Parameter Measurement Information section.
PARAMETER
TEST CONDITIONS
UNIT
TEST
LEVEL (1)
(VS+) – 1.1
V
A
(VS+) – 1.2
V
C
(VS–) + 1.1
V
A
(VS–) + 1.2
V
C
2.8
VPP
C
40
mA
A
MIN
TYP
(VS+) – 1.3
MAX
OUTPUT
VOCRH
Output voltage range, high
Measured
single-ended
VOCRL
Output voltage range, low
Measured
single-ended
VOD
Differential output voltage swing Differential
IOD
Differential output current
TA = 25°C
TA = –40°C to
+85°C
TA = 25°C
(VS–) + 1.3
TA = –40°C to
+85°C
VO = 0 V (2)
30
POWER SUPPLY
VS
Supply voltage
PSRR
IQ
Power-supply rejection ratio
Quiescent current
V
A
VS–
3.15
–50
–80
5.25
dB
A
VS+
–60
–84
dB
A
Power down = 0
49
54
62
mA
A
Power down = 1
1
1.6
5
mA
A
GHz
C
V
A
V
A
V/V
A
OUTPUT COMMON-MODE CONTROL PIN (VCM)
SSBW
VOCM
Small-signal bandwidth
VOCM = 200 mVPP
VCM voltage range low
Differential gain shift < 1 dB
3
VCM voltage range high
Differential gain shift < 1 dB
VCM gain
VCM = 0 V
VOCM output common-mode
offset from VCM input voltage
VCM = 0 V
–27
mV
C
Common-mode offset voltage
Output-referred
0.4
mV
A
V
A
(VS–) + 1.35
(VS+) – 1.55
(VS+) – 1.35
0.98
1
(VS–) + 1.55
1.01
POWER DOWN (PD PIN)
VT
Enable or disable voltage
threshold
Device powers on below 0.8 V,
device powers down above 1.2 V
Power down quiescent current
(2)
0.9
1
1.1
1.2
3
6
mA
A
Power down bias current
Power down = 2.5 V
10
±100
µA
C
Turnon time delay
Time to VO = 90% of final value
10
ns
C
Turnoff time delay
Time to VO = 10% of original value
10
ns
C
This test shorts the outputs to ground (midsupply) then sources or sinks 60 mA and measures the deviation from the initial condition.
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6.7 Typical Characteristics: 5 V
5
5
0
0
Normalized Gain (dB)
Normalized Gain (dB)
at TA = 25°C, split supplies, VCM = 0 V, RL = 200-Ω differential (RO = 40 Ω each), G = 12 dB (4 V/V), single-ended input and
differential output, and input and output pins referenced to midsupply, (unless otherwise noted.) Measured using an EVM as
discussed in the Parameter Measurement Information section (see Figure 56 to Figure 59).
±5
±10
2 V/V
4 V/V
±15
±5
±10
2 V/V
4 V/V
8 V/V
10 V/V
±15
8 V/V
10 V/V
±20
1
10
100
1k
±20
10k
Frequency (MHz)
1
0
0
Normalized Gain (dB)
Normalized Gain (dB)
5
±5
±10
4 V/V
8 V/V
10 V/V
10
10k
C002
Figure 2. Large-Signal Frequency Response vs Gain
5
1
1k
VOUT_AMP = 2 VPP, RL = 200 Ω
Figure 1. Small-Signal Frequency Response vs Gain
±20
100
Frequency (MHz)
VS = ±2.5 V, VOUT_AMP = 0.2 VPP, RL = 200 Ω
±15
10
C001
±5
±10
4 V/V
±15
8 V/V
10 V/V
±20
100
1k
10k
Frequency (MHz)
1
10
100
1k
Frequency (MHz)
C003
VOUT_AMP = 0.2 VPP, RL = 200 Ω
10k
C004
VOUT_AMP = 2 VPP, RL = 200 Ω
Figure 3. Differential Input Small-Signal Frequency
Response vs Gain
Figure 4. Differential Input Large-Signal Frequency
Response vs Gain
10
2
5
±2
Normalized Gain (dB)
Normalized Gain (dB)
0
0
±5
±10
±4
±6
±8
±10
±12
±14
±15
±16
±20
±18
1
10
100
1k
10k
Frequency (MHz)
VS = ±2.5 V, VOUT_AMP = 2 VPP, G = 12 dB, SE-DE
Figure 5. Small-Signal Frequency Response vs Load
10
1
10
100
1k
Frequency (MHz)
C005
10k
C006
VS = ±2.5 V, VOUT_AMP = 2 VPP, G = 12 dB, SE-DE
Figure 6. Large-Signal Frequency Response vs Load
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Typical Characteristics: 5 V (continued)
10
10
5
5
0
0
Normalized Gain (dB)
Normalized Gain (dB)
at TA = 25°C, split supplies, VCM = 0 V, RL = 200-Ω differential (RO = 40 Ω each), G = 12 dB (4 V/V), single-ended input and
differential output, and input and output pins referenced to midsupply, (unless otherwise noted.) Measured using an EVM as
discussed in the Parameter Measurement Information section (see Figure 56 to Figure 59).
±5
±10
±15
±20
±25
1 pF
2.2 pF
4.7 pF
No Cap
±30
±35
±40
1
±5
±10
±15
±20
±25
1 pF
2.2 pF
4.7 pF
No Cap
±30
±35
±40
10
100
1k
10k
Frequency (MHz)
1
10
VS = ±2.5 V, VOUT_AMP = 0.2 VPP, capacitance at DUT output
pins, G = 12 dB, SE-DE
Figure 7. Small-Signal Frequency Response vs Capacitive
Load
100
1k
10k
Frequency (MHz)
C007
C008
VS = ±2.5 V, VOUT_AMP = 2 VPP, capacitance at DUT output
pins, G = 12 dB, SE-DE
Figure 8. Large-Signal Frequency Response vs Capacitive
Load
30
4
20
2
S Parameters (dB)
Normalized Gain (dB)
10
0
±2
±4
±6
±40ƒC
±8
±20
±30
±40
±50
Sss11
Sdd22
Sds21
Ssd12
±60
25°C
±10
0
±10
±70
85°C
±12
±80
10
100
1k
10
8.5k
Frequency (MHz)
100
1k
Frequency (MHz)
C009
VS = ±2.5 V, VOUT_AMP = 2 VPP, G = 12 dB, SE-DE
10k
C010
VS = ±2.5 V, VOUT_AMP = 200 mVPP, ±2.5-V supply
Figure 9. Bandwidth vs Temperature
Figure 10. S-Parameters Single-Ended Input
0
30
20
±10
0
Balance Error (dBc)
S Parameters (dB)
10
±10
±20
±30
±40
±50
Sdd11
Sdd22
Sdd12
Sdd21
±60
±70
±80
10
100
1k
Frequency (MHz)
±20
±30
±40
±50
±60
±70
10k
10
C011
VS = ±2.5 V, VOUT_AMP = 200 mVPP
100
1k
Frequency (MHz)
10k
C012
VS = ±2.5 V, VOUT_AMP = 200 mVPP
Figure 11. S-Parameters Differential Input (±2.5-V Supply)
Figure 12. Balance Error
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Typical Characteristics: 5 V (continued)
at TA = 25°C, split supplies, VCM = 0 V, RL = 200-Ω differential (RO = 40 Ω each), G = 12 dB (4 V/V), single-ended input and
differential output, and input and output pins referenced to midsupply, (unless otherwise noted.) Measured using an EVM as
discussed in the Parameter Measurement Information section (see Figure 56 to Figure 59).
0
10
Distortion (dBc)
0
Gain (dB)
HD2
HD3
±20
±10
±20
±30
±40
±60
±80
±100
±120
±40
10
100
1k
10
10k
Frequency (MHz)
C013
0
0
HD2
HD3
HD2
HD3
±20
Distortion (dBc)
±20
Distortion (dBc)
C014
Figure 14. HD2 and HD3 vs Frequency
Figure 13. Common-Mode Frequency Response
±40
±60
±80
±100
±40
±60
±80
±100
±120
±120
10
100
1k
Frequency (MHz)
10
100
Figure 16. HD2 and HD3 vs Frequency
0
HD2
HD3
±10
C016
VS = ±2.5 V, VOUT_AMP = 2 VPP, (SE-DE, RL = 100 Ω)
Figure 15. HD2 and HD3 vs Frequency
0
1k
Frequency (MHz)
C015
VS = ±2.5 V, VOUT_AMP = 2 VPP
(Differential to Differential, RL = 200 Ω)
HD2
±10
HD3
±20
Distortion (dBc)
±20
Distortion (dBc)
1k
VS = ±2.5 V, VOUT_AMP = 2 VPP, SE-DE, RL = 200 Ω
VS = ±2.5 V, VOUT_AMP = 200 mVPP
±30
±40
±50
±30
±40
±50
±60
±60
±70
±70
±80
±80
±90
±50
±25
0
25
50
75
100
Temperature (ƒC)
125
0
100
Figure 17. HD2 and HD3 vs Temperature
200
300
400
Load Resistance (
C017
VS = ±2.5 V, VOUT_AMP = 2 VPP, RL = 200 Ω, f = 500 MHz
12
100
Frequency (MHz)
500
C018
VS = ±2.5 V, VOUT_AMP = 2 VPP, f = 500 MHz
Figure 18. HD2 and HD3 vs Load Resistance
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Typical Characteristics: 5 V (continued)
at TA = 25°C, split supplies, VCM = 0 V, RL = 200-Ω differential (RO = 40 Ω each), G = 12 dB (4 V/V), single-ended input and
differential output, and input and output pins referenced to midsupply, (unless otherwise noted.) Measured using an EVM as
discussed in the Parameter Measurement Information section (see Figure 56 to Figure 59).
0
0
HD2
HD3
±20
HD3
±20
Distortion (dBc)
Distortion (dBc)
HD2
±10
±40
±60
±80
±30
±40
±50
±60
±70
±80
±100
±90
±120
±100
0
1
2
3
4
5
Output Voltage (V)
±3
VS = ±2.5 V, f = 500 MHz
±1
0
1
2
C020
VS = ±2.5 V, VOUT_AMP = 2 VPP, f = 500 MHz
Figure 19. HD2 and HD3 vs Output Voltage
0
Figure 20. HD2 and HD3 vs Input Common-Mode Voltage
0
HD2
HD3
Harmonic Distrotion (dBc)
±10
±20
±30
Distortion (dBc)
±2
Input Common Mode (V)
C019
±40
±50
±60
±70
±80
IMD2
IMD3
±20
±40
±60
±80
±100
±90
±120
±100
±2
0
±1
1
2
Output Common Mode (V)
10
100
1k
Frequency (MHz)
C021
VS = ±2.5 V, f = 500 MHz , VOUT_AMP = 2 VPP
2k
C022
VS = ±2.5 V, VOUT_AMP = 1 VPP per tone
Figure 21. HD2 and HD3 vs Output Common-Mode Voltage
Figure 22. Intermodulation vs Frequency
100
16
12
Noise Figure (dB)
Voltage Noise (nV / Hz )
14
10
1
10
8
6
4
2
0.1
0
100
1k
10k
100k
1M
Frequency (Hz)
10M
10
C023
VS = ±2.5 V
100
1k
Frequency (MHz)
3k
C024
VS = ±2.5 V
Figure 23. Input-Referred Voltage Noise
Figure 24. Noise Figure vs Frequency
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Typical Characteristics: 5 V (continued)
1.5
0.04
1.0
0.02
0.5
0.00
VO (V)
VO (V)
at TA = 25°C, split supplies, VCM = 0 V, RL = 200-Ω differential (RO = 40 Ω each), G = 12 dB (4 V/V), single-ended input and
differential output, and input and output pins referenced to midsupply, (unless otherwise noted.) Measured using an EVM as
discussed in the Parameter Measurement Information section (see Figure 56 to Figure 59).
0.0
±0.5
±0.02
±0.04
±1.0
1-Vpp Pulse
2-Vpp Pulse
±1.5
0
5
10
15
±0.06
20
Time (ns)
1-Vpp Pulse
2-Vpp Pulse
±0.08
0
5
10
15
VS = ±2.5 V, VOUT_AMP
Figure 26. Pulse Response Common-Mode for Various VO
6
2.5
2.0
VO Ideal
4
Output Voltage (V)
1.5
Output Voltage (V)
C026
VS = ±2.5 V, VOUT_AMP, VCM = (VO+ + VO–) / 2
Figure 25. Pulse Response for Various VO
1.0
0.5
0.0
±0.5
±1.0
±2.0
0
10
20
VO Measured
2
0
±2
±4
Vout
V
O
PD
±1.5
±6
30
40
50
60
70
80
Time (ns)
90
100
0.0
C027
0.5
1.0
1.5
2.0
Time (ns)
2.5
C028
VS = ±2.5 V
VS = ±2.5 V
Figure 28. Overdrive Recovery
Figure 27. Power-Down Timing
14
20
Time (ns)
C025
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6.8 Typical Characteristics: 3.3 V
5
5
0
0
Normalized Gain (dB)
Normalized Gain (dB)
at TA = 25°C, split supplies, VCM = 0 V, RL = 200-Ω differential (RO = 40 Ω each), G = 12 dB, single-ended input and
differential output, and input and output pins referenced to midsupply, (unless otherwise noted). Measured using an EVM as
discussed in the Parameter Measurement Information section (see Figure 56 to Figure 59).
±5
±10
2 V/V
4 V/V
±15
±5
±10
2 V/V
4V/V
8 V/V
10 V/V
±15
8 V/V
10 V/V
±20
1
10
100
1k
±20
10k
Frequency (MHz)
1
10
100
1k
Frequency (MHz)
C029
VS = ±1.65 V, VOUT_AMP = 0.2 VPP, RL = 200 Ω
10k
C030
VS = ±1.65 V, VOUT_AMP = 2 VPP, RL = 200 Ω
Figure 29. Small-Signal Frequency Response vs Gain
Figure 30. Large-Signal Frequency Response vs Gain
5
2
0
±2
Normalized Gain (dB)
Normalized Gain (dB)
0
±5
±10
±15
1
±6
±8
±10
±12
4 V/V
±14
8 V/V
±16
10 V/V
±20
±4
10
±18
100
1k
10k
Frequency (MHz)
1
100
1k
Frequency (MHz)
VS = ±1.65 V, VOUT_AMP = 0.2 VPP, G = 12 dB
10k
C032
VS = ±1.65 V, VOUT_AMP = 2 VPP, G = 12 dB
Figure 31. Small-Signal Frequency Response vs RL
Figure 32. Large-Signal Frequency Response vs RL
10
5
5
0
Normalized Gain (dB)
Normalized Gain (dB)
10
C031
0
±5
±10
±5
±10
4 V/V
±15
±15
±20
±20
8 V/V
10 V/V
1
10
100
1k
10k
Frequency (MHz)
1
100
1k
Frequency (MHz)
C033
10k
C034
VS = ±1.65 V, VOUT_AMP = 2 VPP
VS = ±1.65 V, VOUT_AMP = 0.2 VPP, G = 12 dB
Figure 33. Small-Signal Differential Input Frequency
Response vs RL
10
Figure 34. Large-Signal Differential Input Frequency
Response vs RL
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Typical Characteristics: 3.3 V (continued)
10
10
5
5
0
0
Normalized Gain (dB)
Normalized Gain (dB)
at TA = 25°C, split supplies, VCM = 0 V, RL = 200-Ω differential (RO = 40 Ω each), G = 12 dB, single-ended input and
differential output, and input and output pins referenced to midsupply, (unless otherwise noted). Measured using an EVM as
discussed in the Parameter Measurement Information section (see Figure 56 to Figure 59).
±5
±10
±15
±20
±25
1 pF
2.2 pF
4.7 pF
No Cap
±30
±35
±40
1
±15
±20
±25
1 pF
2.2 pF
4.7 pF
No Cap
±30
±35
±40
10
100
1k
10k
Frequency (MHz)
1
10
10k
C036
Figure 36. Large-Signal Frequency Response with
Capacitive Load
20
20
10
10
0
S Parameters (dB)
0
±10
±20
±30
±40
±50
Sss11
Sdd22
Sds21
Ssd12
±60
±70
±80
10
100
1k
±10
±20
±30
±40
±50
Sdd11
Sdd22
Sdd12
Sdd21
±60
±70
±80
±90
10
10k
Frequency (MHz)
100
1000
10000
Frequency (MHz)
C037
C038
VS = ±1.65 V, VOUT_AMP = 200 mVPP
VS = ±1.65 V, VOUT_AMP = 200 mVPP
Figure 38. Differential Input, S-Parameters
Figure 37. Single-Ended Input, S-Parameters
10
0
0
±20
Distortion (dBc)
Gain (dB)
1k
VS = ±1.65 V, VOUT_AMP = 2 VPP, capacitance at DUT output
pins
Figure 35. Small-Signal Frequency Response with
Capacitive Load
±10
±20
±30
HD2
HD3
±40
±60
±80
±100
±120
±40
10
100
1k
10k
Frequency (MHz)
10
100
Frequency (MHz)
C039
VS = ±1.65 V, VOUT_AMP = 200 mVPP
1k
C040
VS = ±1.65 V, VOUT_AMP = 1 VPP, RL = 200 Ω, G = 12 dB,
single-ended input
Figure 39. Common-Mode Frequency Response
16
100
Frequency (MHz)
C035
VS = ±1.65 V, VOUT_AMP = 2 VPP, capacitance at DUT output
pins,
S Parameters (dB)
±5
±10
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Figure 40. HD2 and HD3
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Typical Characteristics: 3.3 V (continued)
at TA = 25°C, split supplies, VCM = 0 V, RL = 200-Ω differential (RO = 40 Ω each), G = 12 dB, single-ended input and
differential output, and input and output pins referenced to midsupply, (unless otherwise noted). Measured using an EVM as
discussed in the Parameter Measurement Information section (see Figure 56 to Figure 59).
0
HD2
±10
HD3
±20
HD3
±20
±30
Distortion (dBc)
Distortion (dBc)
0
HD2
±40
±60
±80
±40
±50
±60
±70
±80
±100
±90
±120
±100
10
100
0
1k
Frequency (MHz)
VS = ±1.65 V, VOUT_AMP = 1 VPP, RL = 200 Ω, G = 12 dB,
differential input
VS = ±1.65, VOUT_AMP = 1 VPP, f = 500 MHz, RL = 200 Ω, G =
12 dB
±10
HD3
±20
±20
±30
±30
Distortion (dBc)
Distortion (dBc)
0
HD2
±40
±50
±60
±70
±50
±60
±70
±80
±90
±90
±0.5
0.0
0.5
Input Common Mode (V)
1.0
Figure 43. HD2 and HD3 vs Input Common-Mode Voltage
0
±100
±1.00 ±0.75 ±0.50 ±0.25
0.00
0.25
0.50
0.75
1.00
C044
VS = ±1.65 V, VOUT_AMP = 1 VPP, f = 500 MHz, RL = 200 Ω, G =
12 dB
Figure 44. HD2 and HD3 vs Output Common-Mode Voltage
1.5
IMD2
IMD3
±20
HD2
HD3
Output Common Mode (V)
C043
VS = ±1.65 V, VOUT_AMP = 1 VPP, f = 500 MHz, RL = 200 Ω, G =
12 dB
1.0
0.5
±40
VO (V)
Distortion (dBc)
±40
±80
±1.0
3
C042
Figure 42. HD2 and HD3 vs Output Voltage
±10
±1.5
2
Output Voltage (V)
Figure 41. HD2 and HD3 Differential
0
±100
±2.0
1
C041
±60
0.0
±80
±0.5
±100
±1.0
±120
±1.5
10
100
Frequency (MHz)
1k
2k
1-Vpp Pulse
2-Vpp Pulse
0
C045
VS = ±1.65 V, VOUT_AMP = 0.5 VPP per tone, RL = 200 Ω, G = 12
dB
Figure 45. Intermodulation Distortion vs Frequency
5
10
15
Time (ns)
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C046
VS = ±1.65 V, VOUT_AMP
Figure 46. Pulse Response for Various VO
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Typical Characteristics: 3.3 V (continued)
at TA = 25°C, split supplies, VCM = 0 V, RL = 200-Ω differential (RO = 40 Ω each), G = 12 dB, single-ended input and
differential output, and input and output pins referenced to midsupply, (unless otherwise noted). Measured using an EVM as
discussed in the Parameter Measurement Information section (see Figure 56 to Figure 59).
2.5
0.04
2.0
0.02
1.5
Output Voltage (V)
0.06
VO (V)
0.00
±0.02
±0.04
±0.06
1.0
0.5
0.0
±0.5
±1.0
±0.08
1-Vpp Pulse
2-Vpp Pulse
±0.10
0
5
10
15
±2.0
20
Time (ns)
Vout
V
O
PD
±1.5
0
10
20
30
40
50
60
70
80
Time (ns)
C047
VS = ±1.65 V, VOUT_AMP, VCM = (VO+ + VO–) / 2
90
100
C027
VS = ±2.5 V
Figure 47. Pulse Response Common-Mode
Figure 48. Power-Down Timing
6
VO Ideal
Output Voltage (V)
4
VO Measured
2
0
±2
±4
±6
0.0
0.5
1.0
1.5
2.0
Time (ns)
2.5
C028
VS = ±2.5 V
Figure 49. Overdrive Recovery
18
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6.9 Typical Characteristics: 3.3-V to 5-V Supply Range
at TA = 25°C, split supplies, VCM = 0 V, RL = 200-Ω differential (RO = 40 Ω each), G = 12 dB, single-ended input and
differential output, and input and output pins referenced to midsupply, (unless otherwise noted). Measured using an EVM as
discussed in the Parameter Measurement Information section (see Figure 56 to Figure 59).
0
80
3.3 V
5V
±10
Balance Error (dB)
±20
CMRR (dB)
3.3 V
5V
70
±30
±40
±50
±60
60
50
40
30
20
10
0
±70
1
10
100
1k
10k
Frequency (MHz)
1
10
Differential input, differential output, (Sdc21)
1k
10k
C051
Differential input, differential output
Figure 50. CMRR
Figure 51. Balance Error
1k
65
3.3 V
5V
3.3 V
63
5V
61
Supply Current (mA)
Closed Loop RO |Z| ( )
100
Frequency (MHz)
C050
100
10
59
57
55
53
51
49
47
1
45
10
100
1k
10k
Frequency (MHz)
±50
±25
0
Differential output impedance, response includes board parasitics
75
0.8
0.6
0.4
0.2
0.0
125
C053
20
3.3 V
5V
100
Figure 53. Supply Current vs Temperature
Output Offset Voltage (mV) @ DC
Output Offset Voltage (mV) at DC
50
VS = ±2.5 V
Figure 52. Differential Output Impedance vs Frequency
1.0
25
Temperature (ƒC)
C052
3.3 V
15
5V
10
5
0
±5
±10
±15
±20
±25
±30
±50
±25
0
25
50
75
Temperature (ƒC)
100
125
±50
±25
0
25
50
75
100
Temperature (ƒC)
C054
At DC
125
C055
At DC
Figure 54. Differential Offset Voltage vs Temperature
Figure 55. Common-Mode Offset Voltage vs Temperature
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7 Parameter Measurement Information
7.1 Output Reference Points
The LMH5401 is a fully-differential amplifier (FDA) configurable with external resistors for noise gain greater than
2 V/V or 6 dB (GBP = 8 GHz). For most of this document, data is collected for G = 12 dB for single-ended-todifferential (SE-DE) and differential-to-differential (DE-DE) conversions in the diagrams shown in the Test
Schematics section. When matching the output to a 100-Ω load, the evaluation module (EVM) uses external
40-Ω resistors to complete the output matching. Having on-chip output resistors creates two potential reference
points for measuring the output voltage. The amplifier output pins create one output reference point (OUT_AMP).
The other output reference point is the point at the matched 100-Ω load (OUT_LOAD). These points are shown
in Figure 56 to Figure 59; see the Test Schematics section.
Most measurements in the Electrical Characteristics tables and in the Typical Characteristics sections are
measured with reference to the OUT_AMP reference point. The conversion between reference points is a
straightforward reduction of 3 dB for power and 6 dB for voltage, as shown in Equation 1. The measurements are
referenced to OUT_AMP when not specified.
VOUT_LOAD = (VOUT_AMP – 6 dB) and POUT_LOAD = (POUT_AMP – 3 dB)
(1)
7.2 ATE Testing and DC Measurements
All production testing and ensured DC parameters are measured on automated test equipment capable of DC
measurements only. Measurements such as output current sourcing and sinking are made in reference to the
device output pins. Some measurements (such as voltage gain) reference the output of the internal amplifier and
do not include losses attributed to the on-chip output resistors. The Electrical Characteristics table conditions
specify these conditions. When the measurement refers to the amplifier output, then the output resistors are not
included in the measurement. If the measurement refers to the device pins, then the output resistor loss is
included in the measurement.
7.3 Frequency Response
This test is run with single-ended inputs and differential inputs.
For tests with single-ended inputs, the standard EVM is used with no changes; see Figure 56. To provide a
matched input, the unused input requires a broadband 50-Ω termination to connect. When using a four-port
network analyzer, the unused input can be terminated with a broadband load, or can connect to the unused input
on the four-port analyzer. The network analyzer provides proper termination. A network analyzer connects to the
input and output of the EVM with 50-Ω coaxial cables and measures the forward transfer function (s21). The
input signal frequency is swept with the signal level set for the required output amplitude.
The LMH5401 is fully symmetrical. Either input (IN+ or IN–) can be used for single-ended inputs. The unused
input must be terminated. RF, RG1, and RG2 determine the gain. RT and RM enable matching to the source
resistance. See the Test Schematics section for more information on setting these resistors per gain and source
impedance requirements. Bandwidth is dependant on gain settings because this device is a voltage feedback
amplifier. With a GBP of 8 GHz, the approximate bandwidth is calculated for a specific application requirement,
as shown in Equation 2. Figure 57 shows a test schematic for differential input and output.
GBP (Hz) = BW (Hz) × Noise Gain
20
(2)
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Frequency Response (continued)
For tests with differential inputs, the same setup for single-ended inputs is used except all four connectors are
connected to a network analyzer port. Measurements are made in true differential mode on the Rohde &
Schwarz® network analyzer or in calculated differential mode. In each case, the differential inputs are each driven
with a 50-Ω source. Table 1 and Table 2 lists the resistor values used in frequency response sweeps.
Table 1. Differential Input/Output
AV (V/V)
RG1, RG2 (Ω)
RF (TOTAL / EXTERNAL, Ω)
RT (Ω)
2
100
199 / 174
100
4
49.9
199 / 174
N/A
6
49.9
300 / 274
N/A
8
49.9
400 / 375
N/A
10
49.9
500 / 475
N/A
Table 2. SE Input
RG2 (Ω)
RF (TOTAL / EXTERNAL,
Ω)
76.8
121
200 / 175
357
66.5
152 / 127
12.1
1100
60.4
250 / 225
9.76
1580
57.6
300 / 275
AV (V/V)
RG1 (Ω)
RT (Ω)
2
90.9
4
22.6
8
10
7.4 S-Parameters
The standard EVM is used for all s-parameter measurements. All four ports are used or are terminated with
50 Ω; see the Frequency Response section.
7.5 Frequency Response with Capacitive Load
The standard EVM is used and the capacitive load is soldered to the inside pads of the 40-Ω matching resistors
(on the DUT side). In this configuration, the on-chip, 10-Ω resistors isolate the capacitive load from the amplifier
output pins. The test schematic for capacitive load measurements is shown in Figure 58.
7.6 Distortion
The standard EVM is used for measuring single-tone harmonic distortion and two-tone intermodulation distortion.
All distortion is measured with single-ended input signals; see Figure 59. To interface with single-ended test
equipment, external baluns are required between the EVM output ports and the test equipment. The Typical
Characteristics plots are created with Marki™ baluns, model number BAL-0010. These baluns combine two
tones in the two-tone test plots. For distortion measurements, the same termination must be used on both input
pins. When a filter is used on the driven input port, the same filter and a broadband load terminate the other
input. When the signal source is a broadband controlled impedance, only a broadband-controlled impedance is
required to terminate the unused input.
7.7 Noise Figure
The standard EVM is used with a single-ended input matched to 50-Ω and the Marki balun on the output similar
to the harmonic distortion test setup.
7.8 Pulse Response, Slew Rate, and Overdrive Recovery
The standard EVM is used for time-domain measurements. The input is single-ended with the differential outputs
routed directly to the oscilloscope inputs. The differential signal response is calculated from the two separate
oscilloscope inputs (Figure 25 to Figure 46). In addition, the common-mode response is captured in this
configuration.
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7.9 Power Down
The standard EVM is used with the shorting block on jumper JPD removed completely. A high-speed, 50-Ω pulse
generator drives the PD pin when the output signal is measured by viewing the output signal (such as a 250-MHz
sine-wave input).
7.10 VCM Frequency Response
The standard EVM is used with RCM+ and RCM– removed and a new resistor installed at RTCM = 49.9 Ω. The
49.9-Ω resistor is placed at C17 on the EVM schematic. A network analyzer is connected to the VCM input of the
EVM and the EVM outputs are connected to the network analyzer with 50-Ω coaxial cables. Set the network
analyzer analysis settings to single-ended input and differential output. Measure the output common-mode with
respect to the single-ended input (Scs21). The input signal frequency is swept with the signal level set for
100 mV (–16 dBm). Note that the common-mode control circuit gain is one.
7.11 Test Schematics
RT = 357 :
LMH5401
50-:
Single-Ended
Input
+
RG2 = 66.5 :
10 :
IN-
-
IN+
10 :
RF = 127 :
OUT+ 40 :
+ OUT_AMP
-
+
Test Equipment
With 50-:
Outputs
RG1 = 22.6 :
Differential
Load = 200 :
25 :
RF = 127 :
40 :
+
OUT_LOAD
OUT-
25 :
CM
1 Test Equipment
With 50-:
2
Inputs
Test Equipment
Load = 100 :
PD
Figure 56. Test Schematic: Single-Ended Input, Differential Output, AV = 4 V/V
RT = NA
LMH5401
100-:
DifferentialEnded Input
+
RG2 = 50 :
10 :
IN-
-
IN+
10 :
RF = 174 :
OUT+ 40 :
+ OUT_AMP
-
+
Test Equipment
With 50-:
Outputs
RG1 = 50 :
Differential
Load = 200 :
25 :
RF = 174 :
40 :
+
OUT_LOAD
OUT-
25 :
Test Equipment
Load = 100 :
RT = NA
CM
1 Test Equipment
With 50-:
2
Inputs
PD
Figure 57. Test Schematic: Differential Input, Differential Output, AV = 4 V/V
22
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Test Schematics (continued)
RT = 357 :
LMH5401
50-:
Single-Ended
Input
+
-
10 :
IN-
-
IN+
OUT+ 40 :
+
OUT_AMP
-
+ OUT_LOAD
-
CO
+
Test Equipment
With 50-:
Outputs
R1 = 22.6 :
Differential
Load = 200 :
25 :
RF = 127 :
R2 = 66.5 :
10 :
RF = 127 :
OUT-
40 :
25 :
CM
1 Test Equipment
With 50-:
2
Inputs
Test Equipment
Load = 100 :
PD
Figure 58. Test Schematic: Capacitive Load, AV = 4 V/V
LMH5401
357 :
50-:
Single-Ended
Input
22.6 :
IN-
10 :
+
+
IN+
OUT+
Differential
Load = 200 :
40 :
+
OUT_AMP
+
Test Equipment
With 50-:
Outputs
25 :
127 :
10 :
66.5 :
127 :
OUT-
40 :
BAL
0010
Test Equipment
With 50-:
Inputs
OUT_LOAD
25 :
CM
PD
Figure 59. Test Schematic for Noise Figure and Single-Ended Harmonic Distortion, AV = 4 V/V
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8 Detailed Description
8.1 Overview
The LMH5401 is a very high-performance, differential amplifier optimized for radio frequency (RF) and
intermediate frequency (IF) or high-speed, time-domain applications for wide bandwidth applications as the GBP
is 8 GHz. The device is designed for DC- or AC-coupled applications that may require a single-ended-todifferential (SE-DE) conversion when driving an analog-to-digital converter (ADC). The required external
feedback (RF) and gain set (RG) resistors configure the gain of the device. For the EVM the standard gain is set
to G = 12 dB (for DE and SE conversions) with RF = 127 Ω and RG = 22.6 Ω.
A common-mode reference input pin aligns the amplifier output common-mode with the ADC input requirements.
Power supplies between 3.3 V and 5 V are selected and dual-supply operation is supported when required by
the application. A power-down feature is available for power savings.
The LMH5401 offers two on-chip termination resistors, one for each output with values of 10 Ω each. For most
load conditions the 10-Ω resistors are a partial termination. Consequently, external termination resistors are
required in most applications. See Table 4 for some common load values and the matching resistors.
8.2 Functional Block Diagram
V+
+FB
25
+OUT
-IN
±
+
High-Aol
Differential I/O
Amplifier
±
+IN
2.5 k
10
2.5 k
+
-OUT
10
-FB
25
V+
±
Vcm
Error
Amplifier
+
PD
VCM
Comparator
GND
V±
V– and GND are isolated.
24
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8.3 Feature Description
The LMH5401 includes the following features:
• Fully-differential amplifier
• Flexible gain configurations using external resistors
• Output common-mode control
• Single- or split-supply operation
• Gain bandwidth product (GBP) of 8 GHz
• Linear bandwidth of 2 GHz (G = 12 dB)
• Power down
8.3.1 Fully-Differential Amplifier
The LMH5401 is a voltage feedback (VFA)-based fully-differential amplifier (FDA) offering a GBP of 8 GHz with
flexible gain options using external resistors. The core differential amplifier is a slightly decompensated voltage
feedback design with a high slew rate and best-in-class linearity up to 2 GHz for G = 12 dB (SE-DE, DE-DE).
As with all FDA devices, the output average voltage (common-mode) is controlled by a separate common-mode
loop. The target for this output average is set by the VCM input pin. The VOCM range extends from 1.1 V below the
midsupply voltage to 1.1 V above the midsupply voltage when using a 5-V supply. Note that on a 3.3-V supply
the output common-mode range is quite small. For applications using a 3.3-V supply voltage, the output
common-mode must remain very close to the midsupply voltage.
The input common-mode voltage offers more flexibility than the output common-mode voltage. The input
common-mode range extends from the negative rail to approximately 1 V above the midsupply voltage when
powered with a 5-V supply.
8.3.1.1 Power Down and Ground Pins
A power-down pin is included. This pin is referenced to the GND pins with a threshold voltage of approximately
1 V. Setting the PD pin voltage to more than the specified minimum voltage turns the device off, which places the
LMH5401 into a very low quiescent current state. Note that when disabled, the signal path is still present through
the passive external resistors. Input signals applied to a disabled LMH5401 device still appear at the outputs at
some level through this passive resistor path, as with any disabled FDA device. The power-down pin is biased to
the logic-low state with a 50-kΩ internal resistor.
8.3.2 Operations for Single-Ended to Differential Signals
One of the most useful features supported by the FDA device is a simple conversion from a single-ended input to
a differential output centered on a user-controlled, common-mode level. Although the output side is relatively
straightforward, the device input pins move in a common-mode sense with the input signal. This feature
increases the apparent input impedance to be greater than the RG value. However, this feature can cause input
clipping if this common-mode signal moves beyond the input range. This input active impedance issue applies to
AC- and DC-coupled designs, and requires somewhat more complex solutions for the resistors to account for this
active impedance, as shown in this section.
8.3.2.1 AC-Coupled Signal Path Considerations for Single-Ended Input to Differential Output Conversion
When the signal path is AC coupled, the DC biasing for the LMH5401 becomes a relatively simple task. In all
designs, start by defining the output common-mode voltage. The AC-coupling issue can be separated for the
input and output sides of an FDA design. The input can be AC-coupled and the output DC coupled, or the output
can be AC-coupled and the input DC-coupled, or they can both be AC-coupled. One situation where the output
can be DC-coupled (for an AC-coupled input), is when driving directly into an ADC where the VOCM control
voltage uses the ADC common-mode reference to directly bias the FDA output common-mode to the required
ADC input common-mode. The feedback path must always be DC-coupled. In any case, the design starts by
setting the desired VOCM. When an AC-coupled path follows the output pins, the best linearity is achieved by
operating VOCM at midsupply. The VOCM voltage must be within the linear range for the common-mode loop, as
specified in the headroom specifications. If the output path is AC-coupled, letting the VOCM control pin float is
usually preferred to obtain a midsupply default VOCM bias with no external elements. To limit noise, place a 0.1µF decoupling capacitor on the VOCM pin to ground. After VOCM is defined, check the target output voltage swing
to ensure that the VOCM positive or negative output swing on each side does not clip into the supplies. If the
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Feature Description (continued)
desired output differential swing is defined as VOPP, divide by 4 to obtain the ±VP swing around VOCM at each of
the two output pins (each pin operates 180° out of phase with the other). Check that VOCM ±VP does not exceed
the output swing of this device. Going to the device input pins side, because both the source and balancing
resistor on the non-signal input side are DC blocked (see Figure 61), no common-mode current flows from the
output common-mode voltage, thus setting the input common-mode equal to the output common-mode voltage.
This input headroom sets a limit for higher VOCM voltages. The minimum headroom for the input pins to the
positive supply overrides the headroom limit for the output VOCM because the input VICM is the output VOCM for
AC-coupled sources. The input signal moves this input VICM around the DC bias point, as shown in the Resistor
Design Equations for Single-to-Differential Applications subsection of the Fully-Differential Amplifier section.
8.3.2.2 DC-Coupled Input Signal Path Considerations for SE-DE Conversions
The output considerations remain the same as for the AC-coupled design. The input can be DC-coupled when
the output is AC-coupled. A DC-coupled input with an AC-coupled output can have some advantages to move
the input VICM down if the source is ground referenced. When the source is DC-coupled into the LMH5401 (as
shown in Figure 60), both sides of the input circuit must be DC coupled to retain differential balance. Normally,
the non-signal input side has an RG element biased to an expected source midrange value. Providing this
midscale reference provides a balanced differential swing around VOCM at the outputs. Often, RG2 is grounded for
DC-coupled, bipolar-input applications. This configuration provides a balanced differential output if the source
swings around ground. If the source swings from ground to some positive voltage, grounding RG2 results in a
unipolar output differential swing from both outputs at VOCM (when the input is at ground) to one polarity of swing.
Biasing RG2 to an expected midpoint for the input signal creates a differential output swing around VOCM. One
significant consideration for a DC-coupled input is that VOCM sets up a common-mode bias current from the
output back through RF and RG to the source on both sides of the feedback. Without input-balancing networks,
the source must sink or source this DC current. After the input signal range and biasing on the other RG element
is set, check that the voltage divider from VOCM to VI through RF and RG (and possibly RS) establishes an input
VICM at the device input pins that is in range.
50-: Input Match Gain of 4 V/V
from RT, Single-Ended Source to
Differential Output
LMH5401
RT = 357 :
25 :
RF = 127 :
50-:
Source
RG1 = 22.6 :
+
-
IN-
10 :
-
+
-
IN+
OUT+
OUT_AMP
+
RG2 = 66.5 :
10 :
40 :
Differential
Load = 200 :
40 :
+
100 :
-
OUT-
RF = 127 :
25 :
CM
PD
Figure 60. DC-Coupled, Single-Ended-to-Differential, Gain of 4 V/V
8.3.2.3 Resistor Design Equations for Single-to-Differential Applications
Being familiar with the FDA resistor selection criteria is still important because the LMH5401 gain is configured
through external resistors. The design equations for setting the resistors around an FDA to convert from a singleended input signal to a differential output can be approached in several ways. In this section, several critical
assumptions are made to simplify the results:
• The feedback resistors are selected first and are set to be equal on the two sides of the device.
• The DC and AC impedances from the summing junctions back to the signal source and ground (or a bias
voltage on the non-signal input side) are set equal to retain the feedback divider balance on each side of the
FDA.
26
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Feature Description (continued)
Both of these assumptions are typical and are aimed to deliver the best dynamic range through the FDA signal
path.
After the feedback resistor values are selected, the aim is to solve for RT (a termination resistor to ground on the
signal input side), RG1 (the input gain resistor for the signal path), and RG2 (the matching gain resistor on the
non-signal input side); see Figure 61. This example uses the LMH5401, which is an external resistor FDA. The
same resistor solutions can be applied to AC- or DC-coupled paths. Adding blocking capacitors in the inputsignal chain is a simple option. Adding these blocking capacitors after the RT element (see Figure 61) has the
advantage of removing any DC currents in the feedback path from the output VOCM to ground.
50-: Input Match Gain of 4 V/V from RT,
Single-Ended Source to Differential Output
LMH5401
RT = 357 :
25 :
RF = 127 :
50-:
Source
RG1 = 22.6 :
C1 = 0.1 PF
IN-
-
RG2 = 66.5 :
C2 = 0.1 PF
OUT+ 40 :
+
OUT_AMP
-
IN+
+
+
-
10 :
10 :
40 :
Differential
Load = 200 :
+
100 :
-
OUT-
RF = 127 :
25 :
CM
PD
Figure 61. AC-Coupled, Single-Ended Source to a Differential Gain of a 4-V/V
Most FDA amplifiers use external resistors and have complete flexibility in the selected RF. However, the
LMH5401 has small on-chip feedback resistors that are fixed at 25 Ω. The equations used in this section apply
with an additional 25 Ω to add to the external RF resistors.
After the feedback resistor values are selected, solve for RT (a termination resistor to ground on the signal input
side), RG1 (the input gain resistor for the signal path), and RG2 (the matching gain resistor on the non-signal input
side). The same resistor solutions are applied to AC- or DC-coupled paths. Adding blocking capacitors in the
input-signal chain is a simple option. Adding these blocking capacitors after the RT element has the advantage of
removing any DC currents in the feedback path from the output VOCM to ground.
Earlier approaches to the solutions for RT and RG1 (when the input must be matched to a source impedance, RS)
follow an iterative approach. This complexity arises from the active input impedance at the RG1 input. When the
FDA converts a single-ended signal to a differential signal, the common-mode input voltage at the FDA inputs
must move with the input signal to generate the inverted output signal as a current in the RG2 element. A more
recent solution is shown as Equation 3, where a quadratic in RT is solved for an exact required value. This
quadratic emerges from the simultaneous solution for a matched input impedance and target gain. The only
required inputs are:
1. The selected RF value.
2. The target voltage gain (AV) from the input of RT to the differential output voltage.
3. The desired input impedance at the junction of RT and RG1 to match RS.
Solving this quadratic for RT starts the solution sequence, as shown in Equation 3:
RS
§
·
2R S ¨ 2R F
A V2 ¸
2R F R S2 A V
2
©
¹
R T2 RT
0
2RF 2 A V
R S A V (4 A V ) 2RF 2 A V
R S A V (4 A V )
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Feature Description (continued)
Because this equation is a quadratic, there are limits to the range of solutions. Specifically, after RF and RS are
selected, there is physically a maximum gain beyond which Equation 3 starts to solve for negative RT values (if
input matching is a requirement). With RF selected, use Equation 4 to verify that the maximum gain is greater
than the desired gain.
Av max
28
RF
RS
ª
«
2 ‡ «1
«
«
¬«
4
1
(
RF
RS
º
»
»
2 »
2) »
¼»
RF
RS
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Feature Description (continued)
If the achievable AVmax is less than desired, increase the RF value. After RT is derived from Equation 3, the RG1
element is shown in Equation 5:
R
2 F RS
AV
R G1
RS
1
RT
(5)
Then, the simplest approach is to use a single RG2 = RT || RS + RG1 on the non-signal input side. Often, this
approach is shown as the separate RG1 and RS elements. This approach can provide a better divider match on
the two feedback paths, but a single RG2 is often acceptable. A direct solution for RG2 is shown as Equation 6:
R
2 F
AV
R G2
RS
1
RT
(6)
This design proceeds from a target input impedance matched to RS, signal gain AV, and a selected RF value. The
nominal RF value selected for the LMH5401 characterization is 152 Ω (RFExternal + RFInternal, where RFInternal is
always 25 Ω). As discussed previously, this resistance is on-chip and cannot be changed. See Table 1 and
Table 2 in the Frequency Response section, which lists the value of resistors used for characterization in this
document.
8.3.2.4 Input Impedance Calculations
The designs so far have included a source impedance (RS) that must be matched by RT and RG1. The total
impedance with respect to the input at RG1 for the circuit of Figure 60 is the parallel combination of RT to ground
and ZA (active impedance) presented by the amplifier input at RG1. That expression (assuming RG2 is set to
obtain a differential divider balance) is shown in Equation 7:
ZA
R G1
§
¨1
©
R G1 ·§
RF ·
¸¨ 1
¸
R G2 ¹©
R G1 ¹
RF
2
R G2
(7)
For designs that do not require impedance matching (but instead come from the low-impedance output of
another amplifier, for instance), RG1 = RG2 is the single-to-differential design used without RT to ground. Setting
RG1 = RG2 = RG in Equation 7 shows the input impedance of a simple input FDA driving from a low-impedance,
single-ended source to a differential output.
8.3.3 Differential-to-Differential Signals
The LMH5401 can amplify differential input signals to differential output signals. In many ways, this method is a
much simpler way to operate the FDA from a design equations perspective. Again, assuming the two sides of the
circuit are balanced with equal RF and RG elements, the differential input impedance is the sum of the two RG
elements to a differential inverting summing junction. In these designs, the input common-mode voltage at the
summing junctions does not move with the signal, but must be DC biased in the allowable range for the input
pins with consideration given to the voltage headroom required to each supply. Slightly different considerations
apply to ac- or DC-coupled, differential-in to differential-out designs, as shown in this section.
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Feature Description (continued)
8.3.3.1 AC-Coupled, Differential-Input to Differential-Output Design Issues
When using the LMH5401 with an AC-coupled differential source, the input can be coupled in through two
blocking capacitors. An optional input differential termination resistor (RM) can be included to allow the input RG
resistors to be scaled up while still delivering lower differential input impedance to the source. In Figure 62, the
RG elements sum to show a 200-Ω differential impedance and the RM element combines in parallel to give a net
100-Ω, AC, differential impedance to the source. Again, the design proceeds by selecting the RF element values,
then the RG to set the differential gain, then an RM element (if required) to achieve a target input impedance.
Alternatively, the RM element can be eliminated, the RG elements set to the desired input impedance, and RF set
to the get the differential gain (= RF / RG). The DC biasing in Figure 62 is simple. The output VOCM is set by the
input control voltage and, because there is no DC current path for the output common-mode voltage, that DC
bias sets the input pins common-mode operating points.
RF1 = 402 :
C1
Downconverter Mixer
Differential
Output
RG1 = 100 :
RM = 200 :
C1
VOCM
FDA
RL = 200 :
RG2 = 100 :
RF2 = 402 :
Figure 62. Downconverting Mixer AC-Coupled to the LMH5401 (AV = 4 V/V)
8.3.3.2 DC-Coupled, Differential-Input to Differential-Output Design Issues
Operating the LMH5401 with a DC-coupled input source simply requires that the input pins stay in range of the
DC common-mode operating voltage. Only RG values that are equal to the differential input impedance and that
set the correct RF values for the gain desired are required.
8.3.4 Output Common-Mode Voltage
The CM input controls the output common-mode voltage. CM has no internal biasing network and must be driven
by an external source or resistor divider network to the positive power supply. The CM input impedance is very
high and bias current is not critical. The CM input has no internal reference and must be driven from an external
source. Using a bypass capacitor is required. A capacitor value of 0.01 µF is recommended. For best harmonic
distortion, maintain the CM input within ±1 V of the midsupply voltage using a 5-V supply and within ±0.5 V when
using a 3.3-V supply. The CM input voltage can operate outside this range if a lower output swing is used or
distortion degradation is allowed. For more information, see Figure 21 and Figure 22.
8.3.5 LMH5401 Comparison
Table 3 lists several fully differential amplifiers with similar applications to the LMH5401.
Table 3. Device Family Comparison
30
DEVICE
BW (AV = 12 dB)
DISTORTION
NOISE (nV/√Hz)
LMH3401
7 GHz, G = 16 dB
–79-dBc HD2, –77-dBc HD3 at 500 MHz
1.4
LMH6554
1.6 GHz
–79-dBc HD2, –70-dBc HD3 at 250 MHz
0.9
LMH6552
0.8 GHz
–74-dBc HD2, –84-dBc HD3 at 70 MHz
1.1
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8.4 Device Functional Modes
8.4.1 Operation With a Split Supply
The LMH5401 operates using split supplies. One of the most common supply configurations is ±2.5 V. In this
case, VS+ is connected to 2.5 V, VS– is connected to –2.5 V, and the GND pins are connected to the system
ground. As with any device, the LMH5401 is impervious to what the levels are named in the system. In essence,
using split supplies is simply a level shift of the power pins by –2.5 V. If everything else is level-shifted by the
same amount, the device does not detect any difference. With a ±2.5-V power supply, the CM range is 0 V ±1 V;
the input has a slightly larger range of –2.5 V to 1 V. This design has certain advantages in systems where
signals are referenced to ground, and as shown in the ADC Input Common-Mode Voltage Considerations : DCCoupled Input section, for driving ADCs with low input common-mode voltage requirements in DC-coupled
applications. With the GND pin connected to the system ground, the power-down threshold is 1.2 V, which is
compatible with most logic levels from 1.5-V CMOS to 2.5-V CMOS.
As noted previously, the absolute supply voltage values are not critical. For example, using a 4-V VS+ and a
–1-V VS– still results in a 5-V supply condition. As long as the input and output common-mode voltages remain
in the optimum range, the amplifier can operate on any supply voltages from 3.3 V to 5.25 V. When considering
using supply voltages near the 3.3-V total supply, take care to ensure that the amplifier performance is adequate.
Setting appropriate common-mode voltages for large-signal swing conditions becomes difficult when the supply
voltage is below 4 V.
8.4.2 Operation With a Single Supply
As with split supplies, the LMH5401 can operate from single-supply voltages from 3.3 V to 5.25 V. Single-supply
operation is most appropriate when the signal path is AC-coupled and the input and output common-mode
voltages are set to midsupply by the CM pin and are preserved by coupling capacitors on the input and output.
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9 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
9.1 Application Information
9.1.1 Stability
Two types of gain are associated with amplifiers: noise and signal gain. Noise gain (NG) is what is used to best
determine the stability of an amplifier. The noise gain is the inverse of the voltage divider from the outputs back
to the differential inputs. This gain is calculated by NG = (RF / RIN) + 1. For the LMH5401, NG values greater
than three creates a stable circuit independent on how the signal gain is set. In Figure 63, for optimal
performance choose RF within the values noted in this document (see the Parameter Measurement Information
section for further information). Using too large of a resistance in the feedback path adds noise and can possibly
have a negative affect on bandwidth, depending on the parasitic capacitance of the board; too low of a
resistance can load the output, thus affecting distortion performance. When low gain stability is required, alter the
noise gain by adding a dummy resistor (that is, RT in the differential configuration of Figure 63). By manipulating
the noise gain with this addition, the amplifier can be stabilized without affecting signal gain. Evaluate the system
at lower signal gains (G less than or equal to 2) if SNR can be tolerated with the higher noise gain configuration.
In Figure 63, RS and RT in parallel combination affects the noise gain of the amplifier. RG and RF are the main
gain-setting resistors and the addition of RT adjusts the noise gain for stability. Much of this stability can be
simulated using the LMH5401 TINA model, depending on the amplifier configuration. The example in Figure 63 (
listed in row 1 of Table 1) uses the LMH5401, a signal gain of two , and a noise gain of five.
LMH5401
25 Ÿ
RF = 75 Ÿ
RG = 50 Ÿ
IN
RT = 100 Ÿ
10 Ÿ
-
OUT+
+ OUT_AMP
IN+
40 Ÿ
+
RG = 50 Ÿ
10 Ÿ
RF = 75 Ÿ
40 Ÿ
+ Differential
Load = 200 Ÿ
OUT
25 Ÿ
CM
PD
Figure 63. Differential Stability
9.1.2 Input and Output Headroom Considerations
The starting point for most designs is to assign an output common-mode voltage. For AC-coupled signal paths,
this starting point is often the default midsupply voltage to retain the most available output swing around the
output operating point, which is centered with VCM equal to the midsupply point. For DC-coupled designs, set this
voltage considering the required minimum headroom to the supplies listed in the Electrical Characteristics tables
for VCM control. From that target output, VCM, the next step is to verify that the desired output differential VPP
stays within the supplies. For any desired differential output voltage (VOPP) check the maximum possible signal
swing for each output pin. Make sure that each pin can swing to the voltage required by the application.
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Application Information (continued)
For instance, when driving the ADC12D1800RF with a 1.25-V common-mode and 0.8-VPP input swing, the
maximum output swing is set by the negative-going signal from 1.25 V to 0.2 V. The negative swing of the signal
is right at the edge of the output swing capability of the LMH5401. To set the output common-mode to an
acceptable range, a negative power supply of at least –1 V is recommended. The designed negative supply
voltage is the ADC VCM – 2.5 V for the negative supply and the ADC VCM + 2.5 V for the input swing. To use the
existing supply rails, deviating from the designed voltage may be required.
With the output headroom confirmed, the input junctions must stay within the operating range. Because the input
range extends approximately to the negative supply voltage, input range limitations only appear when
approaching the positive supply where a maximum 1.5-V headroom is required.
The input pins operate at voltages set by the external circuit design, the required output (VOCM), and the input
signal characteristics. The operating voltage of the input pins depends on the external circuit design. With a
differential input, the input pins operate at a fixed input VICM, and the differential input signal does not influence
this common-mode operating voltage.
AC-coupled differential input designs have a VICM equal to the output VOCM. DC-coupled differential input designs
must check the voltage divider from the source VCM to the LMH5401 CM setting. That result solves to an input
VICM within the specified range. If the source VCM can vary over some voltage range, the validation calculations
must include this variation.
9.1.3 Noise Analysis
The first step in the output noise analysis is to reduce the application circuit to the simplest form with equal
feedback and gain setting elements to ground (as shown in Figure 64) and considering FAD and resistor noise
terms.
enRG2
enRF2
RG
RF
r
r
In+2
+
In±2
eno2
±
eni2
enRG2
enRF2
RG
RF
r
r
Figure 64. FDA Noise-Analysis Circuit
Figure 64 shows the noise powers for each term. When the RF and RG terms are matched on each side, the total
differential output noise is the root sum of squares (RSS) of these separate terms. Using NG (noise gain) ≡ 1 +
RF / RG, the total output noise is shown in Equation 8. Each resistor noise term is a 4-kTR power.
eno
eniNG
2
2 inR F
2
2 4kTR FNG
(8)
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Application Information (continued)
The first term is the differential input spot noise times the noise gain. The second term is the input current noise
terms times the feedback resistor (and because there are two terms, the power is two times one of the terms).
The last term is the output noise resulting from the RF and RG resistors (again times two) for the output noise
power of each side added together. Using the exact values for a 50-Ω, matched, single-ended to differential gain,
sweep with 127 Ω (plus an internal 25 Ω) and the intrinsic noise eni = 1.25 nV and in = 3.5 pA for the LMH5401,
which gives an output spot noise from Equation 8. Then, dividing by the signal gain set through internal resistors
(AV), gives the input-referred, spot-noise voltage (ei) of 1.35 nV/√Hz. Note that for the LMH5401 the current noise
is an insignificant noise contributor because of the low value of RF.
9.1.4 Noise Figure
Noise figure (NF) is a helpful measurement in an RF system design. The basis of this calculation is to define how
much thermal noise the system (or even on the component) adds to this input signal. All systems are assumed to
have a starting thermal noise power of –174 dBm/√Hz at room temperature calculated from P(dBW) = 10 × log
(kTB), where T is temperature in Kelvin (290k), B is bandwidth in Hertz (1 Hz), and k is Boltzmann's constant
1.38 × 10–23 (J / K). Whenever an element is placed in a system, additional noise is added beyond the thermal
noise floor. The noise factor (NF) helps calculate the noise figure and is the ratio between the input SNR and the
output SNR. Input SNR includes the noise contribution from the resistive part of the source impedance, ZS. NF is
relative to the source impedance used in the measurement or calculation because capacitors and inductors are
known to be noiseless. Equation 9 calculates NF:
NF = 10 log (eno2 / enZs)
where
•
•
en(Zs) is the thermal noise of the source resistance and equal to 4 kTRS (GDT)2,
G is the voltage gain of the amplifier.
(9)
From Equation 10, NF is approximately equal to 10 dB which is the just above the actual value of 9.6 dB
measured on the bench at 200 MHz when referenced to 50 Ω and as shown in Figure 59.
RT
DT =
RS + RT
(10)
For thermal noise calculations with different source resistances, Equation 11 can be used to calculate the NF
change with a new source resistance. For example, Equation 9 uses a source resistance of 50 Ω. By using a
source of 100 Ω, the new noise figure calculation (Equation 11) yields an NF of 6.6 dB, which provides a 3-dB
improvement that results from the increase in Zs.
en(Zs) = kTRs
(11)
9.1.5 Thermal Considerations
The LMH5401 is packaged in a space-saving UQFN package that has a thermal coefficient (RθJA) of 101°C/W.
Limit the total power dissipation to keep the device junction temperature below 150°C for instantaneous power
and below 125°C for continuous power.
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9.2 Typical Application
The LMH5401 is designed as a single-ended-to-differential (SE-DE) and differential-to-differential (DE-DE) gain
block configured with external resistors and gain-stable single-ended to differential for NG ≥ 2 V/V . The
LMH5401 has no low-end frequency cutoff and has 8-GHz gain product bandwidth. The LMH5401 is a substitute
for a balun transformer in many applications.
The RO resistors serve to match the filter impedance to the 20-Ω amplifier differential output impedance. If no
filter is used, these resistors may not be required if the ADC is located very close to the LMH5401. If there is a
transmission line between the LMH5401 and the ADC, then the RO resistors must be sized to match the
transmission line impedance. A typical application driving an ADC is shown in Figure 65.
RT
50-:,
Single-Ended
Input
RF
RG
FB+
25 :
IN-
+
LMH5401
OUT_AMP
RO
10 :
RG
RM
+
OUT+ RO
+
IN+
10 :
RF
FB-
Filter
IN+
ADC
IN-
OUT
25 :
CM
Figure 65. Single-Ended Input ADC Driver
9.2.1 Design Requirements
The main design requirements are to keep the amplifier input and output common-mode voltages compatible
with the ADC requirements and the amplifier requirements. Using split power supplies may be required.
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Typical Application (continued)
9.2.2 Detailed Design Procedure
9.2.2.1 Driving Matched Loads
The LMH5401 has on-chip output resistors, however, for most load conditions additional resistance must be
added to the output to match a desired load. Table 4 lists the matching resistors for some common load
conditions.
Table 4. Load Component Values (1)
RO+ AND RO– FOR A MATCHED TOTAL LOAD RESISTANCE AT
TERMINATION
AMPLIFIER OUTPUT
LOAD (RL)
(1)
TERMINATION LOSS
50 Ω
15 Ω
100 Ω
6 dB
100 Ω
40 Ω
200 Ω
6 dB
200 Ω
90 Ω
400 Ω
6 dB
400 Ω
190 Ω
800 Ω
6 dB
1 kΩ
490 Ω
2000 Ω
6 dB
The total load includes termination resistors.
9.2.2.2 Driving Unmatched Loads For Lower Loss
When the LMH5401 and the load can be placed very close together, back-terminated transmission lines are not
required. In this case, the 6-dB loss can be reduced significantly. One example is shown in Figure 66.
VIN
Low-Pass Filter
175 :
36.5 :
8.4 nF
LMH5401
137 :
ADC12J4000
0.7 pF
8.4 nF
73.2 :
0.7 pF
175 :
NOTE: Amplifier gain = 12 dB and net gain to ADC = 10.5 dB.
Figure 66. Low-Loss ADC
9.2.2.3 Driving Capacitive Loads
With high-speed signal paths, capacitive loading is highly detrimental to the signal path, as shown in Figure 67.
Designers must make every effort to reduce parasitic loading on the amplifier output pins. The device on-chip
resistors are included to isolate the parasitic capacitance associated with the package and the PCB pads that the
device is soldered to. The LMH5401 is stable with most capacitive loads ≤ 10 pF; however, bandwidth suffers
with capacitive loading on the output.
10
5
Normalized Gain (dB)
0
±5
±10
±15
±20
±25
1 pF
2.2 pF
4.7 pF
No Cap
±30
±35
±40
1
10
100
Frequency (MHz)
1k
10k
C008
Figure 67. Frequency Response with Capacitive Load
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9.2.2.4 Driving ADCs
The LMH5401 is designed and optimized for the highest performance to drive differential input ADCs. Figure 68
shows a generic block diagram of the LMH5401 driving an ADC. The primary interface circuit between the
amplifier and the ADC is usually a filter of some type for antialias purposes, and provides a means to bias the
signal to the input common-mode voltage required by the ADC. Filters range from single-order real RC poles to
higher-order LC filters, depending on the requirements of the application. Output resistors (RO) are shown on the
amplifier outputs to isolate the amplifier from any capacitive loading presented by the filter.
RF
RG
FB+
25 :
10 :
IN-
+ 100-:
Differential Input
LMH5401
+
OUT_AMP
RG
10 :
RF
RO
Filter
RO
+
IN+
OUT+
FB-
IN+
ADC
IN-
OUT-
25 :
CM
Figure 68. Differential ADC Driver Block Diagram
The key points to consider for implementation are the SNR, SFDR, and ADC input considerations, as shown in
this section.
9.2.2.4.1 SNR Considerations
The signal-to-noise ratio (SNR) of the amplifier and filter can be calculated from the amplitude of the signal and
the bandwidth of the filter. The noise from the amplifier is band-limited by the filter with the equivalent brick-wall
filter bandwidth. The amplifier and filter noise can be calculated using Equation 12:
SNRAMP+FILTER = 10 ´ log
V2O
e2FILTEROUT
= 20 ´ log
VO
eFILTEROUT
where:
•
•
•
•
eFILTEROUT = eNAMPOUT × √ENB,
eNAMPOUT = the output noise density of the LMH5401,
ENB = the brick-wall equivalent noise bandwidth of the filter, and
VO = the amplifier output signal.
(12)
For example, with a first-order (N = 1) band-pass or low-pass filter with a 30-MHz cutoff, the ENB is 1.57 × f–3dB
= 1.57 × 30 MHz = 47.1 MHz. For second-order (N = 2) filters, the ENB is 1.22 × f–3dB. When filter order
increases, the ENB approaches f–3dB (N = 3 → ENB = 1.15 × f–3dB; N = 4 → ENB = 1.13 × f–3dB). Both VO and
eFILTEROUT are in RMS voltages. For example, with a 2-VPP (0.707 VRMS) output signal and a 30-MHz first-order
filter, the SNR of the amplifier and filter is 70.7 dB with eFILTEROUT = 5.81 nV/√Hz × √47.1 MHz = 39.9 μVRMS.
The SNR of the amplifier, filter, and ADC sum in RMS fashion is as shown in Equation 13 (SNR values in dB):
-SNRAMP+FILTER
SNRSYSTEM = -20 ´ log
10
10
-SNRADC
+ 10
10
(13)
This formula shows that if the SNR of the amplifier and filter equals the SNR of the ADC, the combined SNR is
3 dB lower (worse). Thus, for minimal degradation (< 1 dB) on the ADC SNR, the SNR of the amplifier and filter
must be ≥ 10 dB greater than the ADC SNR. The combined SNR calculated in this manner is usually accurate to
within ±1 dB of the actual implementation.
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9.2.2.4.2 SFDR Considerations
The SFDR of the amplifier is usually set by the second-order or third-order harmonic distortion for single-tone
inputs, and by the second-order or third-order intermodulation distortion for two-tone inputs. Harmonics and
second-order intermodulation distortion can be filtered to some degree, but third-order intermodulation spurs
cannot be filtered. The ADC generates the same distortion products as the amplifier, but as a result of the
sampling and clock feedthrough, additional spurs (not linearly related to the input signal) are included.
When the spurs from the amplifier and filter are known, each individual spur can be directly added to the same
spur from the ADC, as shown in Equation 14, to estimate the combined spur (spur amplitudes in dBc):
-HDxADC
-HDxAMP+FILTER
HDxSYSTEM = -20 ´ log 10
20
+ 10
20
(14)
This calculation assumes the spurs are in phase, but usually provides a good estimate of the final combined
distortion.
For example, if the spur of the amplifier and filter equals the spur of the ADC, then the combined spur is 6 dB
higher. To minimize the amplifier contribution (< 1 dB) to the overall system distortion, the spur from the amplifier
and filter must be approximately 19 dB lower in amplitude than that of the converter. The combined spur
calculated in this manner is usually accurate to within ±6 dB of the actual implementation; however, higher
variations can be detected as a result of phase shift in the filter, especially in second-order harmonic
performance.
This worst-case spur calculation assumes that the amplifier and filter spur of interest is in phase with the
corresponding spur in the ADC, such that the two spur amplitudes can be added linearly. There are two phaseshift mechanisms that cause the measured distortion performance of the amplifier-ADC chain to deviate from the
expected performance calculated using Equation 14: common-mode phase shift and differential phase shift.
Common-mode phase shift is the phase shift detected equally in both branches of the differential signal path
including the filter. Common-mode phase shift nullifies the basic assumption that the amplifier, filter, and ADC
spur sources are in phase. This phase shift can lead to better performance than predicted when the spurs
become phase shifted, and there is the potential for cancellation when the phase shift reaches 180°. However, a
significant challenge exists in designing an amplifier-ADC interface circuit to take advantage of a common-mode
phase shift for cancellation: the phase characteristic of the ADC spur sources are unknown, thus the necessary
phase shift in the filter and signal path for cancellation is also unknown.
Differential phase shift is the difference in the phase response between the two branches of the differential filter
signal path. Differential phase shift in the filter as a result of mismatched components caused by nominal
tolerance can severely degrade the even-order distortion of the amplifier-ADC chain. This effect has the same
result as mismatched path lengths for the two differential traces, and causes more phase shift in one path than
the other. Ideally, the phase response over frequency through the two sides of a differential signal path are
identical, such that even-order harmonics remain optimally out of phase and cancel when the signal is taken
differentially. However, if one side has more phase shift than the other, then the even-order harmonic
cancellation is not as effective.
Single-order RC filters cause very little differential phase shift with nominal tolerances of 5% or less, but higherorder LC filters are very sensitive to component mismatch. For instance, a third-order Butterworth band-pass
filter with a 100-MHz center frequency and a 20-MHz bandwidth creates as much as 20° of differential phase
imbalance in a SPICE Monte Carlo analysis with 2% component tolerances. Therefore, although a prototype may
work, production variance is unacceptable. In ac-coupled applications that require second- and higher-order
filters between the LMH5401 and the ADC, a transformer or balun is recommended at the ADC input to restore
the phase balance. For DC-coupled applications where a transformer or balun at the ADC input cannot be used,
using first- or second-order filters is recommended to minimize the effect of differential phase shift because of the
component tolerance.
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9.2.2.4.3 ADC Input Common-Mode Voltage Considerations : AC-Coupled Input
The input common-mode voltage range of the ADC must be respected for proper operation. In an AC-coupled
application between the amplifier and the ADC, the input common-mode voltage bias of the ADC is
accomplished in different ways depending on the ADC. Some ADCs use internal bias networks such that the
analog inputs are automatically biased to the required input common-mode voltage if the inputs are AC-coupled
with capacitors (or if the filter between the amplifier and ADC is a band-pass filter). Other ADCs supply the
required input common-mode voltage from a reference voltage output pin (often called CM or VCM). With these
ADCs, the AC-coupled input signal can be re-biased to the input common-mode voltage by connecting resistors
from each input to the CM output of the ADC, as Figure 69 shows. However, the signal is attenuated because of
the voltage divider created by RCM and RO.
RO
RCM
AIN+
Amp
ADC
AIN-
RCM
CM
RO
Figure 69. Biasing AC-Coupled ADC Inputs Using the ADC CM Output
The signal can be re-biased when ac coupling; thus, the output common-mode voltage of the amplifier is a don’t
care for the ADC.
9.2.2.4.4 ADC Input Common-Mode Voltage Considerations : DC-Coupled Input
DC-coupled applications vary in complexity and requirements, depending on the ADC. One typical requirement is
resolving the mismatch between the common-mode voltage of the driving amplifier and the ADC. Devices such
as the ADS5424 require a nominal 2.4-V input common-mode, whereas other devices such as the ADS5485
require a nominal 3.1-V input common-mode; still others such as the ADS6149 and the ADS4149 require 1.5 V
and
0.95 V, respectively. As shown in Figure 70, a resistor network can be used to perform a common-mode level
shift. This resistor network consists of the amplifier series output resistors and pull-up or pull-down resistors to a
reference voltage. This resistor network introduces signal attenuation that may prevent the use of the full-scale
input range of the ADC. ADCs with an input common-mode closer to the typical 2.5-V LMH5401 output commonmode are easier to DC-couple, and require little or no level shifting.
VREF
VAMP+
RO
RP
ADC
VADC+
Amp
RIN
VAMP-
RO
RP
CIN
VADC-
VREF
Figure 70. Resistor Network to DC Level-Shift Common-Mode Voltage
For common-mode analysis of the circuit in Figure 70, assume that VAMP± = VCM and VADC± = VCM (the
specification for the ADC input common-mode voltage). VREF is chosen to be a voltage within the system higher
than VCM (such as the ADC or amplifier analog supply) or ground, depending on whether the voltage must be
pulled up or down, respectively; RO is chosen to be a reasonable value, such as 24.9 Ω. With these known
values, RP can be found by using Equation 15:
RP = RO
VADC - VREF
VAMP - VADC
(15)
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Shifting the common-mode voltage with the resistor network comes at the expense of signal attenuation.
Modeling the ADC input as the parallel combination of a resistance (RIN) and capacitance (CIN) using values
taken from the ADC data sheet, the approximate differential input impedance (ZIN) for the ADC can be calculated
at the signal frequency. The effect of CIN on the overall calculation of gain is typically minimal and can be ignored
for simplicity (that is, ZIN = RIN). The ADC input impedance creates a divider with the resistor network; the gain
(attenuation) for this divider can be calculated by Equation 16:
GAIN =
2RP || ZIN
2RO + 2RP || ZIN
(16)
With ADCs that have internal resistors that bias the ADC input to the ADC input common-mode voltage, the
effective RIN is equal to twice the value of the bias resistor. For example, the ADS5485 has a 1-kΩ resistor tying
each input to the ADC VCM; therefore, the effective differential RIN is 2 kΩ.
The introduction of the RP resistors modifies the effective load that must be driven by the amplifier. Equation 17
shows the effective load created when using the RP resistors.
RL = 2RO + 2RP || ZIN
(17)
The RP resistors function in parallel to the ADC input such that the effective load (output current) at the amplifier
output is increased. Higher current loads limit the LMH5401 differential output swing.
By using the gain and knowing the full-scale input of the ADC (VADC
with the network can be calculated using Equation 18:
V
VAMP PP = ADC FS
GAIN
FS),
the required amplitude to drive the ADC
(18)
As with any design, testing is recommended to validate whether the specific design goals are met.
9.2.2.5 GSPS ADC Driver
The LMH5401 can drive the full Nyquist bandwidth of ADCs with sampling rates up to 4 GSPS, as shown in
Figure 71. If the front-end bandwidth of the ADC is more than 2 GHz, use a simple noise filter to improve SNR.
Otherwise, the ADC can be connected directly to the amplifier output pins. Matching resistors may not be
required, however allow space for matching resistors on the preliminary design.
LMH5401
RT
50-:
Single-Ended
Input
25 :
RF
RG
IN-
10 :
-
OUT+ R
O
+
+
IN+
OUT_AMP
10 :
RG
RM
RO
+
IN+
Filter
IN-
GSPS ADC
OUT-
RF
25 :
CM
Figure 71. GSPS ADC Driver
40
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9.2.2.6 Common-Mode Voltage Correction
The LMH5401 can set the output common-mode voltage to within a typical value of ±30 mV. If greater accuracy
is desired, a simple circuit can improve this accuracy by an order of magnitude. A precision, low-power
operational amplifier is used to sense the error in the output common-mode of the LMH5401 and corrects the
error by adjusting the voltage at the CM pin. In Figure 72, the precision of the op amp replaces the less accurate
precision of the LMH5401 common-mode control circuit while still using the LMH5401 common-mode control
circuit speed. The op amp in this circuit must have better than a 1-mV input-referred offset voltage and low noise.
Otherwise the specifications are not very critical because the LMH5401 is responsible for the entire differential
signal path.
OUT+
IN±
±
FB+
5k
+
CM
LMH5401
±
IN+
+
5k
FB-
OUT-
10 nF
±
LMV771
+
Desired
VOCM
Figure 72. Common-Mode Correction Circuit
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9.2.2.7 Active Balun
The LMH5401 is designed to convert single-ended signals to a differential output with high bandwidth and
linearity, as shown in Figure 73. The LMH5401 can support DC coupling as well as AC coupling. The LMH5401
is smaller than any balun with low-frequency response and has balance errors that are excellent over a wide
frequency range. As shown in Figure 74, the LMH5401 balance error is better than
–40 dBc up to 1 GHz when used with a 5-V supply. Figure 75 plots the input return loss. The s-parameters
demonstrate the performance of the configuration, which is comparable (or even better) to a balun.
LMH5401
RT
Single-Ended
Input
FB+
RF
RG
25 :
+ OUT_AMP
RO
+
IN+
RG
10 :
RF
RO
-
+
RM
OUT+
10 :
IN-
Differential
Output
OUT-
25 :
FB-
CM
Figure 73. Active Balun
0
30
20
10
±20
S Parameters (dB)
Balance Error (dBc)
±10
±30
±40
±50
0
±10
±20
±30
±40
±50
Sss11
Sdd22
Sds21
Ssd12
±60
±60
±70
±70
±80
10
100
1k
Frequency (MHz)
10k
10
C012
Figure 74. Balance Error
42
100
1k
Frequency (MHz)
10k
C010
Figure 75. Input Return Loss
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9.2.3 Application Curves
7
17
6
16
15
5
Gain (dB)
Resistor Loss (dB)
The LMH5401 has on-chip series output resistors to facilitate board layout. These resistors provide the LMH5401
extra phase margin in most applications. When the amplifier is used to drive a terminated transmission line or a
controlled impedance filter, extra resistance is required to match the transmission line of the filter. In these
applications, there is a 6 dB loss of gain. When the LMH5401 is used to drive loads that are not back-terminated
there is a loss in gain resulting from the on-chip resistors. Figure 76 shows that loss for different load conditions.
In most cases the loads are between 50 Ω and 200 Ω, where the on-chip resistor losses are 1.6 dB and 0.42 dB,
respectively. Figure 77 shows the net gain realized by the amplifier for a large range of load resistances when
the LMH5401 is configured for 16-dB gain.
4
3
2
14
13
12
11
1
10
0
9
10
100
1k
External Load (Ÿ)
10k
10
Figure 76. Gain Loss Resulting from On-Chip Output
Resistors
100
1k
External Load (Ÿ)
C072
10k
C073
Figure 77. Net Gain versus Load Resistance
9.3 Do's and Don'ts
9.3.1 Do:
• Include a thermal design at the beginning of the project.
• Use well-terminated transmission lines for all signals.
• Use solid metal layers for the power supplies.
• Keep signal lines as straight as possible.
• Use split supplies where required.
9.3.2 Don't:
• Use a lower supply voltage than necessary.
• Use thin metal traces to supply power.
• Forget about the common-mode response of filters and transmission lines.
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10 Power Supply Recommendations
The LMH5401 can be used with either split or single-ended power supplies. The ideal supply voltage is a 5-V
total supply, split around the desired common-mode of the output signal swing. For example, if the LMH5401 is
used to drive an ADC with a 1-V input common mode, then the designed supply voltages are 3.5 V and –1.5 V.
The GND pin can then be connected to the system ground and the PD pin is ground referenced.
10.1 Supply Voltage
Using a 5-V power supply gives the best balance of performance and power dissipation. If power dissipation is a
critical design criteria, a power supply as low as 3.3 V (±1.65) can be used. When using a lower power supply,
the input common-mode and output swing capabilities are drastically reduced. Take care to study the commonmode voltages required before deciding on a lower-voltage power supply. In most cases, the extra performance
achieved with 5-V supplies is worth the power.
10.2 Single-Supply
Single-supply voltages from 3.3 V to 5 V are supported. When using a single supply check both the input and
output common-mode voltages that are required by the system.
10.3 Split-Supply
In general, split-supplies allow the most flexibility in system design. To operate as split-supply, apply the positive
supply voltage to VS+, the negative supply voltage to VS–, and the ground reference to GND. Note that supply
voltages are not required to be symmetrical. Provided the total supply voltage is between 3.3 V and 5.25 V, any
combination of positive and negative supply voltages is acceptable. This feature is often used when the output
common-mode voltage must be set to a particular value. For best performance, the power-supply voltages are
symmetrical around the desired output common-mode voltage. The input common-mode voltage range is much
more flexible than the output.
10.4 Supply Decoupling
Power-supply decoupling is critical to high-frequency performance. Onboard bypass capacitors are used on the
LMH5401EVM; however, the most important component of the supply bypassing is provided by the PCB. As
shown in Figure 78, there are multiple vias connecting the LMH5401 power planes to the power-supply traces.
These vias connect the internal power planes to the LMH5401. VS+ and VS– must be connected to the internal
power planes with several square centimeters of continuous plane in the immediate vicinity of the amplifier. The
capacitance between these power planes provides the bulk of the high-frequency bypassing for the LMH5401.
44
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11 Layout
11.1 Layout Guidelines
With a GBP of 8 GHz, layout for the LMH5401 is critical and nothing can be neglected. To simplify board design,
the LMH5401 has on-chip resistors that reduce the effect of off-chip capacitance. For this reason, TI does not
recommend cutting the ground layer below the LMH5401. The recommendation to not cut the ground plane
under the amplifier input and output pins is different than many other high-speed amplifiers, but parasitic
inductance is more harmful to the LMH5401 performance than parasitic capacitance. By leaving the ground layer
under the device intact, parasitic inductance of the output and power traces is minimized. The DUT portion of the
evaluation board layout is shown in Figure 78 and Figure 79.
The EVM uses long-edge capacitors for the decoupling capacitors, which reduces series resistance and
increases the resonant frequency. Vias are also placed to the power planes before the bypass capacitors.
Although not evident in the top layer, two vias are used at the capacitor in addition to the two vias underneath the
device.
The output matching resistors are 0402 size and are placed very close to the amplifier output pins, which
reduces parasitic inductance and capacitance. The use of 0603 output matching resistors produces a
measurable decrease in bandwidth.
When the signal is on a 50-Ω controlled impedance transmission line, the layout then becomes much less critical.
The transition from the 50-Ω transmission line to the amplifier pins is the most critical area.
The CM pin requires a bypass capacitor. Place this capacitor near the device. See LMH5401EVM Evaluation
Module for more details on board layout and design.
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11.2 Layout Example
Figure 78. Layout Example
46
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Layout Example (continued)
Figure 79. EVM Layout Ground Layer Showing Solid Ground Plane
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12 Device and Documentation Support
12.1 Device Support
12.1.1 Device Nomenclature
L5401
= Pin 1 designator
THS770006IRGE = device name
TIYMF
TI = TI LETTERS
PLLL
YM = YEAR MONTH DATE CODE
F P = ASSEMBLY SITE CODES
LLL = ASSY LOT CODE
Figure 80. Device Marking Information
12.2 Documentation Support
12.2.1 Related Documentation
For related documentation see the following:
• Texas Instruments, LMH3401 7-GHz, Ultra-Wideband, Fixed-Gain, Fully-Differential Amplifier
• Texas Instruments, LMH6554 2.8-GHz Ultra Linear Fully Differential Amplifier
• Texas Instruments, LMH6552 1.5-GHz Fully Differential Amplifier
• Texas Instruments, ADC12D1800RF 12-Bit, Single 3.6 GSPS RF Sampling ADC
• Texas Instruments, ADS5424 14 Bit, 105 MSPS Analog-to-Digital Converter
• Texas Instruments, ADS548x 16-Bit, 170/200-MSPS Analog-to-Digital Converters
• Texas Instruments, ADS614x, ADS612x 14/12-Bit, 250/210 MSPS ADCs With DDR LVDS and Parallel
CMOS Outputs
• Texas Instruments, ADS412x, ADS414x 12-/14-Bit, 160/250MSPS, Ultralow-Power ADC
• Texas Instruments, LMH5401EVM Evaluation Module
• Texas Instruments, AN-2188 Between the Amplifier and the ADC: Managing Filter Loss in Communications
Systems
• Texas Instruments, AN-2235 Circuit Board Design for LMH6517/21/22 and Other High-Speed IF/RF
Feedback Amplifiers
• Texas Instruments, LMH5401 TINA Macromodel
12.3 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper
right corner, click on Alert me to register and receive a weekly digest of any product information that has
changed. For change details, review the revision history included in any revised document.
12.4 Community Resources
The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.
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12.5 Trademarks
E2E is a trademark of Texas Instruments.
Marki is a trademark of Marki Microwave, Inc.
Rohde & Schwarz is a registered trademark of Rohde & Schwarz.
All other trademarks are the property of their respective owners.
12.6 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
12.7 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
13 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
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PACKAGE OPTION ADDENDUM
www.ti.com
6-Feb-2020
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
Lead/Ball Finish
MSL Peak Temp
(2)
(6)
(3)
Op Temp (°C)
Device Marking
(4/5)
LMH5401IRMSR
ACTIVE
UQFN
RMS
14
3000
Green (RoHS
& no Sb/Br)
SN
Level-2-260C-1 YEAR
-40 to 85
L5401
LMH5401IRMST
ACTIVE
UQFN
RMS
14
250
Green (RoHS
& no Sb/Br)
SN
Level-2-260C-1 YEAR
-40 to 85
L5401
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of
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