LMH6502
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SNOSA65D – OCTOBER 2003 – REVISED MARCH 2013
LMH6502 Wideband, Low Power, Linear-in-dB Variable Gain Amplifier
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FEATURES
DESCRIPTION
•
The LMH™6502 is a wideband DC coupled
differential input voltage controlled gain stage
followed by a high-speed current feedback Op Amp
which can directly drive a low impedance load. Gain
adjustment range is more than 70dB for up to 10MHz.
1
23
•
•
•
•
•
•
•
•
•
•
•
•
VS = ±5V, TA = 25°C, RF = 1kΩ, RG = 174Ω, RL =
100Ω, AV = AV(MAX) = 10 Typical Values Unless
Specified.
-3dB BW: 130MHz
Gain Control BW: 100MHz
Adjustment Range (Typical Over Temp): 70dB
Gain Matching (Limit): ±0.6dB
Slew Rate: 1800V/µs
Supply Current (No Load): 27mA
Linear Output Current: ±75mA
Output Voltage (RL = 100Ω): ±3.2V
Input Voltage Noise: 7.7nV/√Hz
Input Current Noise: 2.4pA/√Hz
THD (20MHz, RL = 100Ω, VO = 2VPP): −53dBc
Replacement for CLC520
APPLICATIONS
•
•
•
•
Variable Attenuator
AGC
Voltage Controller Filter
Video Imaging Processing
Maximum gain is set by external components and the
gain can be reduced all the way to cut-off. Power
consumption is 300mW with a speed of 130MHz.
Output referred DC offset voltage is less than 350mV
over the entire gain control voltage range. Device-todevice Gain matching is within ±0.6dB at maximum
gain. Furthermore, gain at any VG is tested and the
tolerance is ensured. The output current feedback Op
Amp allows high frequency large signals (Slew Rate
= 1800V/μs) and can also drive heavy load current
(75mA). Differential inputs allow common mode
rejection in low level amplification or in applications
where signals are carried over relatively long wires.
For single ended operation, the unused input can
easily be tied to ground (or to a virtual half-supply in
single supply application). Inverting or non-inverting
gains could be obtained by choosing one input
polarity or the other.
To provide ease of use when working with a single
supply, VG range is set to be from 0V to +2V relative
to pin 11 potential (ground pin). In single supply
operation, this ground pin is tied to a "virtual" half
supply.
LMH6502 gain control is linear in dB for a large
portion of the total gain control range. This makes the
device suitable for AGC circuits among other
applications. For linear gain control applications, see
the LMH6503 datasheet. The LMH6502 is available in
the SOIC and TSSOP package.
1
2
3
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
LMH is a trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2003–2013, Texas Instruments Incorporated
LMH6502
SNOSA65D – OCTOBER 2003 – REVISED MARCH 2013
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Typical Application
30
+5V
10
+VIN
dB
85°C
0
R1
50:
25°C
-10
-40°C
-20
85°C
-30
6
V/V
4
-40
-60
14
12
4
13
VOUT
LMH6502
10
5
7
6 8
R2
50:
2
-40°C
-70
RG
170:
-VIN
25°C
-50
3
NC
1
8
GAIN (V/V)
GAIN (dB)
RF
1k:
10
20
2
9
RL
100:
11
-5V
VIN_DIFF = ±0.1V
0
-80
VG
0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 2
VG (V)
Figure 1. Gain vs. VG for Various Temperature
Figure 2. AVMAX = 10V/V
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
Absolute Maximum Ratings (1) (2)
ESD Tolerance (3):
Human Body
2KV
Machine Model
200V
Input Current
±10mA
±(V+ -V−)
VIN Differential
120mA (4)
Output Current
+
−
Supply Voltages (V - V )
12.6V
Voltage at Input/ Output pins
V+ +0.8V,V− - 0.8V
Storage Temperature Range
−65°C to +150°C
Junction Temperature
+150°C
Soldering Information:
(1)
(2)
(3)
(4)
Infrared or Convection (20 sec)
235°C
Wave Soldering (10 sec)
260°C
Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for
which the device is intended to be functional, but specific performance is not ensured. For specific specifications, see the Electrical
Characteristics tables.
If Military/Aerospace specified devices are required, please contact the Texas Instruments Sales Office/Distributors for availability and
specifications.
Human body model: 1.5kΩ in series with 100pF. Machine model: 0Ω in series with 200pF.
The maximum output current (IOUT) is determined by device power dissipation limitations or value specified, whichever is lower.
Operating Ratings (1)
Supply Voltages (V+ - V−)
5V to 12V
−40°C to +85°C
Temperature Range
Thermal Resistance:
14-Pin SOIC
14-Pin TSSOP
(1)
2
(θJC)
45°C/W
(θJA)
138°C/W
(θJC)
51°C/W
(θJA)
160°C/W
Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for
which the device is intended to be functional, but specific performance is not ensured. For specific specifications, see the Electrical
Characteristics tables.
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Electrical Characteristics (1)
Unless otherwise specified, all limits specified for TJ = 25°C, VS = ±5V, AV(MAX) = 10, VCM = 0V, RF = 1kΩ, RG = 174Ω, VIN_DIFF
= ±0.1V, RL = 100Ω, VG = +2V. Boldface limits apply at the temperature extremes.
Symbol
Parameter
Conditions
Min (2)
Typ (2)
Max (2)
Units
Frequency Domain Response
BW
-3dB Bandwidth
VOUT < 0.5PP
130
VOUT < 0.5PP, AV(MAX) = 100
50
30
MHz
GF
Gain Flatness
VOUT < 0.5VPP
0.6V ≤ VG ≤ 2V, ±0.3dB
MHz
Att Range
Flat Band (Relative to Max Gain)
Attenuation Range (3)
±0.2dB, f < 30MHz
16
±0.1dB, f < 30MHz
7.5
BW
Control
Gain control Bandwidth
VG = 1V (4)
100
MHz
PL
Linear Phase Deviation
DC to 60MHz
1.5
deg
G Delay
Group Delay
DC to 130MHz
2.5
ns
CT (dB)
Feed-through
VG = 0V, 30MHz (Output
Referred)
−47
dB
GR
Gain Adjustment Range
f < 10MHz
72
f < 30MHz
67
dB
dB
Time Domain Response
tr, tf
Rise and Fall Time
0.5V Step
2.2
ns
OS %
Overshoot
0.5V Step
10
%
SR
Slew Rate
4V Step
1800
V/μs
Δ G Rate
Gain Change Rate
VIN = 0.3V, 10%-90% of Final
Output
4.8
dB/ns
Distortion & Noise Performance
HD2
2nd Harmonic Distortion
2VPP, 20MHz
−55
dBc
HD3
3rd Harmonic Distortion
2VPP, 20MHz
−57
dBc
THD
Total Harmonic Distortion
2VPP, 20MHz
−53
dBc
En tot
Total Equivalent Input Noise
1MHz to 150MHz
7.7
nV/√Hz
IN
Input Noise Current
1MHz to 150MHz
2.4
pA/√Hz
DG
Differential Gain
f = 4.43MHz, RL = 150Ω, Neg.
Sync
0.34
%
(1)
(2)
(3)
(4)
Electrical Table values apply only for factory testing conditions at the temperature indicated. Factory testing conditions result in very
limited self-heating of the device such that TJ = TA. No ensurance of parametric performance is indicated in the electrical tables under
conditions of internal self-heating where TJ > TA.
Typical values represent the most likely parametric norm. Bold numbers refer to over temperature limits.
Flat Band Attenuation (Relative to Max Gain) Range Definition: Specified as the attenuation range from maximum which allows gain
flatness specified (either ±0.2dB or ±0.1dB) relative to AVMAX gain. For example, for f < 30MHz, here are the Flat Band Attenuation
ranges:
±0.2dB 20dB down to 4dB = 16dB range
±0.1dB 20dB down to 12.5 dB = 7.5dB range
Gain Control Frequency Response Schematic:
RF
910:
+0.2VDC
+VIN
ROUT
50:
+
R1
50:
RG
820:
-VIN
R2
50:
PORT 1
RT
50:
RL
50:
2
VG
+5V
C1
0.01PF
RF IN
PORT 2
LMH6502
RP1
10k:
0V
DC
-5V
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Electrical Characteristics(1) (continued)
Unless otherwise specified, all limits specified for TJ = 25°C, VS = ±5V, AV(MAX) = 10, VCM = 0V, RF = 1kΩ, RG = 174Ω, VIN_DIFF
= ±0.1V, RL = 100Ω, VG = +2V. Boldface limits apply at the temperature extremes.
Symbol
DP
Parameter
Conditions
Differential Phase
Min (2)
f = 4.43MHz, RL = 150Ω, Neg.
Sync
Typ (2)
Max (2)
0.10
Units
deg
DC & Miscellaneous Performance
GACCU
G Match
Gain Accuracy (See Application
Information)
VG = 2.0V
0.0
Gain Matching (See Application
Information)
VG = 2.0V
–
±0.6
1 < VG < 2V
–
+2.8/−3.9
1.61
1.58
1.72
1.84
1.91
1V < VG < 2V
+0.6/−0.3
+0.6
+3.1/−3.6
K
Gain Multiplier (See Application
Information)
VCM
Input Voltage Range
Pin 3 & 6 Common Mode,
|CMRR| > 55dB (5)
±2.0
±1.70
±2.2
VIN_DIFF
Differential Input Voltage
Between pins 3 & 6
±0.3
±0.12
±0.39
I RG_MAX
RG Current
Pins 4 & 5
±1.70
±1.56
±2.22
IBIAS
Bias Current
Pins 3 & 6 (6)
9
18
20
Pins 3 & 6 (6),
VS = ±2.5V
2.5
5
6
TC IBIAS
Bias Current Drift
Pin 3 & 6 (7)
100
I OFF
Offset Current
Pin 3 & 6
0.01
TC IOFF
Offset Current Drift
See (7)
RIN
Input Resistance
CIN
Input Capacitance
IVG
VG Bias Current
Pin 2, VG = 0V (6)
TC IVG
VG Bias Drift
R VG
dB
dB
V/V
V
V
mA
µA
nA/°C
2.0
3.6
µA
5
nA/°C
Pin 3 & 6
750
kΩ
Pin 3 & 6
5
pF
−300
µA
Pin 2 (7)
20
nA/°C
VG Input Resistance
Pin 2
10
kΩ
C VG
VG Input Capacitance
Pin 2
1.3
pF
VOUT
Output Voltage Range
RL = 100Ω
±3.00
±2.95
±3.20
RL = Open
±3.95
±3.82
±4.00
0.1
Ω
±80
±75
±90
mA
V
ROUT
Output Impedance
DC
IOUT
Output Current
VOUT = ±4V from Rails
VO
Output Offset Voltage
0V < VG < 2V
±80
±300
±380
mV
+PSRR
+Power Supply Rejection Ratio (8)
Input Referred, 1V change,
VG = 2.2V
−69
−47
−45
dB
−PSRR
−Power Supply Rejection Ratio (8)
Input Referred, 1V change,
VG = 2.2V
−58
−41
−40
OFFSET
(5)
CMRR
Common Mode Rejection Ratio
Input Referred,VG = 2V
−1.8V < VCM < 1.8V
−72
IS
Supply Current
No Load
27
38
41
VS = ±2.5V, RL= Open
9.3
16
19
(5)
(6)
(7)
(8)
4
dB
dB
mA
CMRR definition: [|ΔVOUT/ΔVCM| / AV] with 0.1V differential input voltage.
Positive current corresponds to current flowing in the device.
Drift determined by dividing the change in parameter distribution average at temperature extremes by the total temperature change.
+PSRR definition: [|ΔVOUT/ΔV+| / AV], −PSRR definition: [|ΔVOUT/ΔV−| / AV] with 0.1V differential input voltage.
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Connection Diagram
V
+
1
14
+
V
2
13
3
12
4
11
5
10
6
9
7
8
NC
VG
+VIN
+RG
I
V
-
GND
VOUT
-RG
-VIN
-
VREF
-
V
14-Pin SOIC/TSSOP (Top View)
See Package Numbers D (R-PDSO-G14) and PW (R-PDSO-G14)
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Typical Performance Characteristics
Unless otherwise specified: VS = ±5V, 25°C, VG = VGMAX, VCM = 0V, RF = 1kΩ, RG = 174Ω, both inputs terminated in 50Ω, RL
= 100Ω, Typical values, results referred to device output.
GAIN
150
1
1.0V
GAIN
100
0
-1
2.0V
100
0
50
-1
-2
0
-2
0
-3
-50
-3
-50
-4
-100
-4
-100
GAIN (dB)
-200
-6
-250
-7
100
10M 100M 1G
1k
Figure 4.
Frequency Response Over Temperature (AV = 10)
Frequency Response for Various VG (AVMAX = 10)
150
1
100
0
50
-1
-40°C
0
GAIN
25°C
85°C
-2
0
-3
-50
-40°C
25°C
-4
-5
85°C
VG = VGMAX
-7
VO = 0.5VPP
-150
-8
100k
1M
2.1V
10M 100M
-20
-40
-3
1.0V
-60
-4
0.80V
-80
-5
AVMAX = 10
-100
-6
-250
-7
-120
-300
-8 SEE NOTE 12
-9
1k
10k 100k
-140
1G
FREQUENCY (Hz)
1
3
0.1V
2
0.3V
1
0
PHASE
0
0.1V
-4
0.3V
-5
-80
-2
VS = ±2.5V
-6
-120
1M
2k:
1k:
2k:
10M
100M
225
180
135
90
45
0
10
2
-45
-90
-135
-7
-8
-160
100k
100
10
2
-4
-5
10k
RF (k:)
100
-3
AVMAX = 10
SEE NOTE 12
-9
1k
GAIN (dB)
-40
PHASE (°)
GAIN (dB)
1.1V
-7
GAIN
AVMAX
-1
-3
-8
270
0.5VPP
0
-2
-6
1G
Small Signal Frequency Response for Various AVMAX
40
-1
10M 100M
Figure 6.
Frequency Response for Various VG (AVMAX = 10)
(±2.5V)
1.1V
-160
1M
FREQUENCY (Hz)
Figure 5.
GAIN
0
-200
-350
10k
20
2.1V
SEE NOTE 11
-9
1k
40
1.0V
-2
-100
AVMAX = 10
-6
0.80V
PHASE
GAIN (dB)
GAIN (dB)
PHASE
PHASE (°)
-1
-250
10M 100M 1G
FREQUENCY (Hz)
Figure 3.
GAIN
-200
1.0V
10k 100k 1M
FREQUENCY (Hz)
1
2.0V
SEE NOTE 12
1.0V
10k 100k 1M
-150
PIN = 12dBm
PHASE (°)
SEE NOTE 12
1k
AVMAX = 2
-5
PHASE (°)
-6
-7
100
PHASE (°)
-150
2.0V
PIN = -8dBm
1.0V
PHASE
AVMAX = 2
-5
50
2.0V
PHASE
GAIN (dB)
Large Signal Frequency for Various VG
150
PHASE (°)
Small Signal Frequency for Various VG
1
PHASE
-180
-225
SEE NOTE 12
-270
-9
f (25 MHz/DIV)
1G
FREQUENCY (Hz)
Figure 7.
6
Figure 8.
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Typical Performance Characteristics (continued)
Unless otherwise specified: VS = ±5V, 25°C, VG = VGMAX, VCM = 0V, RF = 1kΩ, RG = 174Ω, both inputs terminated in 50Ω, RL
= 100Ω, Typical values, results referred to device output.
Large Signal Frequency Response for Various AVMAX
270
1
GAIN
0
AVMAX
RF (k:)
100
10
2
2k:
1k:
2k:
GAIN (dB)
-1
-2
-3
100
0
40
135
20
90
-2
0
2
-4
-45
-5
-90
-135
-6
-7
-8
GAIN
-1
45
10
2.0V
SEE NOTE 12
-9
0
0.60V
-3
-20
0.4V
-40
-4
PHASE
-60
-5
-6
AVMAX = 100
-80
-225
-7
PIN = -42dBm
SEE NOTE 12
-100
-270
-8
-180
PHASE
60
1
225
180
GAIN (dB)
5VPP
PHASE (°)
2
PHASE (°)
3
Frequency Response for Various VG (AVMAX= 105)
(Small Signal)
-120
f (25 MHz/DIV)
f (10 MHz/DIV)
Figure 9.
Figure 10.
Frequency Response for Various VG (AVMAX= 105)
(Large Signal)
IS vs. VS
60
45
0
40
40
-1
20
35
0
30
1
RL = OPEN
GAIN
VG = VG_MAX
85°C
-20
0.4V
-40
-4
PHASE
-5
IS (mA)
GAIN (dB)
0.60V
-3
PHASE (°)
2.0V
-2
20
-60
15
10
-6
AVMAX = 100
-80
-7
PIN = -22dBm
SEE NOTE 12
-100
5
-120
0
-8
25°C
25
-40°C
2.5
f (10 MHz/DIV)
3
3.5
4
4.5
5
5.5
6
±SUPPLY VOLTAGE (V)
Figure 11.
Figure 12.
IS vs. VS
Input Bias Current vs. VS
40
35
14
RL = OPEN
12
VG = VG_MIN
10
25°C
25
25°C
IB (PA)
IS (mA)
85°C
85°C
30
20
15
8
6
-40°C
-40°C
4
10
2
5
0
0
2.5
3
3.5
4
4.5
5
5.5
6
±SUPPLY VOLTAGE (V)
2.5
3
3.5
4
4.5
5
5.5
6
±SUPPLY VOLTAGES (V)
Figure 13.
Figure 14.
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Typical Performance Characteristics (continued)
Unless otherwise specified: VS = ±5V, 25°C, VG = VGMAX, VCM = 0V, RF = 1kΩ, RG = 174Ω, both inputs terminated in 50Ω, RL
= 100Ω, Typical values, results referred to device output.
AVMAX vs. VCM
AVMAX vs. VCM
12
12
10
8
85°C
6
25°C
4
-40°C
2
AVMAX (V/V)
AVMAX (V/V)
10
8
4
VS = ±5V
VIN_DIFF = 0.1V
VIN_DIFF = 0.1V
2
VG = VGMAX
VG = VGMAX
0
-2
-3
-1 -0.8 -0.6 -0.4 -0.2 0 0.2 0.4 0.6 0.8 1
-2
-1
VCM (V)
Figure 15.
Figure 16.
PSRR ±5V
-10
1
0
VCM (V)
2
3
PSRR ±2.5V
0
0
SEE NOTE 10
VS = ±5V
-5
VG = VGMAX
VS = ±2.5V
SEE NOTE 10
VG = VGMAX
-10
-20
-15
-30
-40
PSRR (dB)
PSRR (dB)
-40°C
6
VS = ±2.5V
0
25°C
85°C
+PSRR
-50
+PSRR
-20
-25
-30
-60
-35
-PSRR
-70
-40
-PSRR
-45
-80
1k
1M
100k
10k
10M
1k
100M
100k
10k
Figure 17.
Figure 18.
CMRR ±5V
100M
CMRR ±2.5V
0
VS = ±5V
VS = ±2.5V
SEE NOTE 9
AVMAX = 10
-20
PIN = 0dBm
SEE NOTE 9
AVMAX = 10
PIN = 0dBm
-40
CMRR (dB)
-40
CMRR (dB)
10M
FREQUENCY (Hz)
0
-20
1M
FREQUENCY (Hz)
-60
MAX GAIN
-80
-60
-80
-100
-100
MID GAIN
-120
-120
1k
10k
100k
1M
10M
100M
FREQUENCY (Hz)
10k
100k
1M
10M
100M
FREQUENCY (Hz)
Figure 19.
8
1k
Figure 20.
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Typical Performance Characteristics (continued)
Unless otherwise specified: VS = ±5V, 25°C, VG = VGMAX, VCM = 0V, RF = 1kΩ, RG = 174Ω, both inputs terminated in 50Ω, RL
= 100Ω, Typical values, results referred to device output.
AVMAX vs. Supply Voltage
Supply Current vs. VCM
14
35
-40°C
30
25
85°C
8
25°C
-40°C
25°C
IS (mA)
AVMAX (V/V)
10
6
4
20
15
10
VG = VG_MAX
2
VS = ±5V
5
VG = VGMAX
VIN_DIFF = 0.1V
0
0
2
3
4
5
6
-2
-3
2
Figure 21.
Figure 22.
Supply Current vs. VCM
Output Offset Voltage vs. VCM
(Typical Unit #1)
-30
VG = VGMAX
-40
VO_OFFSET (mV)
10
8
6
-40°C
4
3
VS = ±5V
25°C
12
-50
-60
-40°C
25°C
-70
-80
VS = ±2.5V
VG = VGMAX
85°C
-90
0
-1
-1.5
-0.5
0
0.5
1
1.5
-2
-3
-1
VCM (V)
0
1
2
3
VCM (V)
Figure 23.
Figure 24.
Output Offset Voltage vs. VCM
(Typical Unit #2)
Output Offset Voltage vs. VCM
(Typical Unit #3)
30
170
25°C
25°C
85°C
20
85°C
160
10
VO_OFFSET (mV)
VO_OFFSET (mV)
1
0
VCM (V)
85°C
2
-1
±SUPPLY VOLTAGE (V)
14
IS (mA)
25°C
85°C
12
25°C
0
-40°C
-10
-20
25°C
150
140
-40°C
130
120
VS = ±5V
-30
VS = ±5V
110
VG = VGMAX
VG = VGMAX
-40
100
-3
-2
-1
0
1
2
3
VCM (V)
-3
-2
-1
0
1
2
3
VCM (V)
Figure 25.
Figure 26.
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Typical Performance Characteristics (continued)
Unless otherwise specified: VS = ±5V, 25°C, VG = VGMAX, VCM = 0V, RF = 1kΩ, RG = 174Ω, both inputs terminated in 50Ω, RL
= 100Ω, Typical values, results referred to device output.
Gain Flatness and Linear Phase Deviation vs. VG
40
0.3
2
0.2
1.6
GAIN
20
1.0V
1.2
2.1V
GAIN (dB)
-20
AVMAX = 100
AVMAX = 2
AVMAX =10
-40
-60
0
0.8
-0.1
PHASE
0.80V
0.4
1.0V
-0.2
0
-0.4
-0.3
2.1V
-80
-0.4
-0.8
-100
-0.5
-1.2
-120
-0.6
100
1k
0
200M
10M
1M
100k
10k
SEE NOTE 12
6M
12M
18M
24M
-1.6
30M
FREQUENCY (Hz)
FREQUENCY (Hz)
Figure 27.
Figure 28.
Gain Flatness Frequency vs. Gain (1)
Group Delay vs. Frequency
2.60
100M
VG = VGMAX
AVMAX = 10
2.50
±0.2dB
10M
GROUP DELAY (ns)
GAIN FLATNESS
(RELATIVE TO MAX GAIN) (Hz)
0.80V
0.1
0
GAIN (dB)
2.4
0.4
LINEAR PHASE DEVIATION (°)
Feed through Isolation
60
1M
±0.1dB
100k
RF = 1k:
10k
RG = 170
PIN = -10dBm
1k
2.40
2.30
2.20
2.10
VG VARIED
100
-40
-30
-20
-10
10
0
20
2.00
30
0
GAIN (dB)
5M 10M 15M 20M 25M 30M 35M 40M
FREQUENCY (Hz)
Figure 29.
Figure 30.
K Factor vs. RG
Gain vs. VG Including Limits
2.1
30
RF = 477:
2
20
10
RF = 690:
1.9
MAX VALUE
0
GAIN (dB)
K (V/V)
1.8
1.7
RF = 6.18k:
1.6
RF = 1.3k:
1.5
-10
-20
-40
-50
1.4
-60
1.3
-70
1.2
-80
10
100
1k
2k
RG (:)
10
GAIN (TYPICAL)
VIN_DIFF = ±0.1V
0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 2
VG (V)
Figure 31.
(1)
MIN VALUE
-30
Figure 32.
Flat Band Attenuation (Relative to Max Gain) Range Definition: Specified as the attenuation range from maximum which allows gain
flatness specified (either ±0.2dB or ±0.1dB) relative to AVMAX gain. For example, for f < 30MHz, here are the Flat Band Attenuation
ranges:
±0.2dB 20dB down to 4dB = 16dB range
±0.1dB 20dB down to 12.5 dB = 7.5dB range
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Typical Performance Characteristics (continued)
Unless otherwise specified: VS = ±5V, 25°C, VG = VGMAX, VCM = 0V, RF = 1kΩ, RG = 174Ω, both inputs terminated in 50Ω, RL
= 100Ω, Typical values, results referred to device output.
BW vs. RF
Gain vs. VG (±5V)
30
RG = 100:
10
RG = 466:
100
dB
85°C
0
GAIN (dB)
RG = 1190:
BW (MHz)
10
20
RG = 180:
RG = 47:
10
RG = 27:
-40°C
-20
85°C
-30
4
25°C
-50
2
-40°C
-70
VIN_DIFF = ±0.1V
0
-80
1k
10k
100k
0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 2
RF (:)
VG (V)
Figure 33.
Figure 34.
Gain vs. VG (±2.5V)
Output Offset Voltage vs. VG
(Typical Unit #1)
30
0
10
GAIN (dB)
0
VS = ±2.5V
-10
RF = 1k:
-20
RG = 170:
25°C
VO_OFFSET (mV)
20
-10
-20
-30
-40
-50
-30
-40°C
-40
-50
-60
-70
-60
-70
-80
-80
-1.4
-90
-0.5
85°C
-0.9
-0.4
0.1
0.6
1.1
0.5
0
1
1.5
2
Figure 35.
Figure 36.
Output Offset Voltage vs. VG
(Typical Unit #2)
Output Offset Voltage vs. VG
(Typical Unit #3)
20
180
85°C
85°C
18
160
16
140
25°C
VO_OFFSET (mV)
14
12
-40°C
10
8
6
2.5
VG (V)
VG (V)
VO_OFFSET (mV)
6
V/V
-40
-60
1
100
8
25°C
-10
GAIN (V/V)
1000
-40°C
25°C
120
-40°C
100
25°C
80
60
4
40
2
20
-40°C
85°C
0
-0.5
0
0.5
1
1.5
2
2.5
0
-0.5
0
0.5
1
1.5
2
2.5
VG (V)
VG (V)
Figure 37.
Figure 38.
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Typical Performance Characteristics (continued)
Unless otherwise specified: VS = ±5V, 25°C, VG = VGMAX, VCM = 0V, RF = 1kΩ, RG = 174Ω, both inputs terminated in 50Ω, RL
= 100Ω, Typical values, results referred to device output.
Output Offset Voltage vs. ±VS for various VG
(Typical Unit# 1)
Output Offset Voltage vs. ±VS for various VG
(Typical Unit# 2)
0
25
MAX
MIN
VO_OFFSET (mV)
-20
20
VO_OFFSET (mV)
-40
MID
-60
-80
MAX
15
10
MID
5
MIN
0
-100
-5
-120
2.5
3
3.5
4
4.5
5
5.5
6
-10
2.5
6.5
3
3.5
4
±VS (V)
4.5
5
5.5
6
6.5
±VS (V)
Figure 39.
Figure 40.
Output Offset Voltage vs. ±VS for various VG
(Typical Unit# 3)
250
Noise vs. Frequency (AVMAX = 2)
100000
AVMAX = 2
RF = 974:
MAX
RG = 902:
10000
eno (nV/ Hz)
VO_OFFSET (mV)
200
150
100
VGMAX
1000
VGMID
MID
100
50
MIN
VGMIN
0
10
2.5
3
3.5
4
4.5
5
5.5
6
6.5
10
1k
100
±VS (V)
10k
100k
Figure 42.
Noise vs. Frequency (AVMAX = 10)
Noise vs. Frequency (AVMAX = 105)
10000
100k
AVMAX = 100
AVMAX = 10
RF = 1k:
RF = 2k:
MAX GAIN
RG = 180:
RG = 24:
10k
en(OUT) (nV/ Hz)
eno (nV/ Hz)
10M
FREQUENCY (Hz)
Figure 41.
1000
1M
MAX GAIN
MID GAIN
100
1k
NO GAIN
100
NO GAIN
MID GAIN
10
100
1k
10k
100k
1M
100
1k
10k
100k
1M
FREQUENCY (Hz)
FREQUENCY (Hz)
Figure 43.
12
10
10
Figure 44.
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Typical Performance Characteristics (continued)
Unless otherwise specified: VS = ±5V, 25°C, VG = VGMAX, VCM = 0V, RF = 1kΩ, RG = 174Ω, both inputs terminated in 50Ω, RL
= 100Ω, Typical values, results referred to device output.
−1dB Compression
Output Voltage vs. Output Current
4.5
24
20
18
RF = 620:
16
14
VG = VGMAX
12
VIN_DIFF = ±0.5V
4
VOUT FROM SUPPLY (V)
-1dB COMPRESSION (dBm)
RF = 1.46k:
22
SINK
3.5
3
2.5
2
SOURCE
1.5
1
0.5
RG = 160:
0
10
20
0
40
60
80
0
100 120 140 160
20
40
FREQUENCY (MHz)
60
80
100
IOUT (mA)
Figure 45.
Figure 46.
HD2 & HD3 vs. POUT
THD vs. POUT
100
100
HD2, 1MHz
1MHz
90
90
80
HD3, 1MHz
70
HD3, 20MHz
|THD (dBc)|
|HD (dBc)|
80
70
60
60
50
20MHz
40
30
HD2, 20MHz
20
50
10
40
VG = VGMAX = 2.0V
0
-10
-5
0
5
10
15
-10
20
-5
0
5
10
POUT (dBm)
POUT (dBm)
Figure 47.
Figure 48.
THD vs. POUT
HD2 & HD3 vs. VG
HD3, 0.25VPP
90
80
HD2, 0.25VPP
80
|HD2 OR HD3 (dBc)|
1MHz
70
|THD (dBc)|
20
90
100
60
50
40
20MHz
30
70
HD3, 1VPP
60
50
HD2, 2VPP
40
HD2,1VPP
20
10
15
30
VG = VGMID = 1.0V
f = 20MHz
HD3, 2VPP
20
0
-10
-5
0
5
10
15
20
0.6
0.8
1
1.2
1.4
1.6
1.8
2
VG (V)
POUT (dBm)
Figure 49.
Figure 50.
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Typical Performance Characteristics (continued)
Unless otherwise specified: VS = ±5V, 25°C, VG = VGMAX, VCM = 0V, RF = 1kΩ, RG = 174Ω, both inputs terminated in 50Ω, RL
= 100Ω, Typical values, results referred to device output.
THD vs. VG
THD vs. VG
100
80
0.25VPP
0.25VPP
90
70
1VPP
80
60
2VPP
60
50
|THD (dBc)|
|THD (dBc)|
70
1VPP
40
50
40
2VPP
30
30
20
20
10
10
f = 20MHz
f = 1MHz
0
0.60 0.80 1.00 1.20 1.40
0
1.60 1.80 2.00
0.60 0.80 1.00 1.20 1.40 1.60 1.80 2.00
VG (V)
VG (V)
Figure 51.
Figure 52.
VG Bias Current vs. VG
Step Response Plot
-350
0.5VPP SMALL SIGNAL
-250
IVG (PA)
SS REF
LS REF
-150
-50
5VPP LARGE SIGNAL
0
0.5
1
1.5
2
4 ns/DIV
2.5
VG (V)
Figure 53.
Figure 54.
Gain vs. VG Step
2
10
1.8
GAIN
1.6
1.4
VG (V)
SS REF
LS REF
0.4
0.2
2.5VPP LARGE SIGNAL
7
6
1
0.6
VG = VG_MID
8
VG
1.2
0.8
9
5
VIN= 0.3V
AVMAX= 10
RL= 100:
VG Stepped
From 0.6V
To 1.6V
0
4
GAIN (V/V)
Step Response Plot
0.5VPP SMALL SIGNAL
3
2
1
0
4 ns/DIV
t (10ns/DIV)
Figure 55.
14
Figure 56.
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Typical Performance Characteristics (continued)
Unless otherwise specified: VS = ±5V, 25°C, VG = VGMAX, VCM = 0V, RF = 1kΩ, RG = 174Ω, both inputs terminated in 50Ω, RL
= 100Ω, Typical values, results referred to device output.
Feedthrough from VG
AVMAX= 10
VG (0.5V/DIV)
VG Stepped From 0.6V
To 1.6V
0
VOUT
VG
VOUT (50mV/DIV)
RL= 100:
0
t (10ns/DIV)
Figure 57.
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APPLICATION INFORMATION
THEORY OF OPERATION
A simplified schematic is shown in Figure 58. +VIN and −VIN are buffered with closed loop voltage followers
inducing a signal current in Rg proportional to (+VIN) - (−VIN), the differential input voltage. This current controls a
current source which supplies two well-matched transistor, Q1 and Q2.
The current flowing through Q2 is converted to the final output voltage using RF and the output amplifier, U1. By
changing the fraction of the signal current "I" which flows through Q2, the gain is changed. This is done by
changing the voltage applied differentially to the bases of Q1 and Q2. For example, with VG = 0V, Q1 conducts
heavily and Q2 is off. With none of "I" flowing through RF, the LMH6502's input to output gain is strongly
attenuated. With VG = +2V, Q1 is off and the entire signal current flows through Q2 to RF producing maximum
gain. With VG set to 1V, the bases of Q1 and Q2 are set to approximately the same voltage, Q1 and Q2 have the
same collector currents - equal to one half of the signal current "I", thus the gain is approximately one half the
maximum gain.
Figure 58. LMH6502 Block Diagram
CHOOSING RF & RG
Maximum input amplitude and maximum gain are the two key specifications that determine component values in
a LMH6502 application.
The output stage op amp is a current-feedback type amplifier optimized for RF = 1kΩ. RG can then be computed
as:
RF x 1.72
RG =
AVMAX
- 3: WITH RF = 1K:
(1)
To determine whether the maximum input amplitude will overdrive the LMH6502, compute:
VDMAX = (RG + 3.0Ω) × 1.70mA
(2)
the maximum differential input voltage for linear operation. If the maximum input amplitude exceeds the above
VDMAX limit, then LMH6502 should either be moved to a location in the signal chain where input amplitudes are
reduced, or the LMH6502 gain AVMAX should be reduced or the values for RG and RF should be increased. The
overall system performance impact is different based on the choice made. If the input amplitude is reduced, recompute the impact on signal-to-noise ratio. If AVMAX is reduced, post LMH6502 amplifier gain, should be
increased, or another gain stage added to make up for reduced system gain. To increase RG and RF, compute
the lowest acceptable value for RG:
RG > 590 × VDMAX - 3Ω
(3)
Operating with RG larger than this value insures linear operation of the input buffers.
RF may be computed from selected RG and AVMAX: RF should be > = 1kΩ for overall best performance, however
RF < 1kΩ can be implemented if necessary using a loop gain reducing resistor to ground on the inverting
summing node of the output amplifier (see application note OA-13 (SNOA366) for details).
16
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ADJUSTING OFFSET
Offset can be broken into two parts; an input-referred term and an output-referred term. The input-referred offset
shows up as a variation in output voltage as VG is changed. This can be trimmed using the circuit in Figure 59 by
placing a low frequency square wave (VLOW = 0V, VHIGH = 2V into VG with VIN = 0V, the input referred VOS term
shows up as a small square wave riding a DC value. Adjust R10 to null the VOS square wave term to zero. After
adjusting the input-referred offset, adjust R14 (with VIN = 0, VG = 0) until VOUT is zero. Finally, for inverting
applications VIN may be applied to pin 6 and the offset adjustment to pin 3. These steps will minimize the output
offset voltage. However, since the offset term itself varies with the gain setting, the correction is not perfect and
some residual output offset will remain at in-between VG's. Also, this offset trim does not improve output offset
temperature coefficient.
Figure 59. Nulling the output offset voltage
GAIN ACCURACY
Defined as the actual gain compared against the theoretical gain at a certain VG (results expressed in dB).
Theoretical gain is given by:
A(V/V) = K x
RF
RG
1
1 - VG
x
1+e
VC
(4)
Where K = 1.72 (nominal) & VC = 90mV @ room temperature.
For a VG range, the value specified in the tables represents the worst case accuracy over the entire range. The
"Typical" value would be the worst case difference between the "Typical Gain" and the "Theoretical gain". The
"Max" value would be the worst case difference between the max/min gain limit and the "Theoretical gain".
GAIN MATCHING
Defined as the limit on gain variation at a certain VG (expressed in dB). Specified as "Max" only (no "Typical").
For a VG range, the value specified represents the worst case matching over the entire range. The "Max" value
would be the worst case difference between the max/min gain limit and the typical gain.
NOISE
Figure 60 describes the LMH6502's output-referred spot noise density as a function of frequency with AVMAX =
10V/V. The plot includes all the noise contributing terms. However, with both inputs terminated in 50Ω, the input
noise contribution is minimal. At AVMAX = 10V/V, the LMH6502 has a typical input-referred spot noise density (ein)
of 7.7nV/
flat-band. For applications extending well into the flat-band region, the input RMS voltage noise can
be determined from the following single-pole model:
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VRMS = ein * 1.57 * (-3dB BANDWIDTH)
(5)
10000
AVMAX = 10
RF = 1k:
eno (nV/ Hz)
RG = 180:
MAX GAIN
1000
MID GAIN
100
NO GAIN
10
100
1k
10k
100k
1M
FREQUENCY (Hz)
Figure 60. Output Referred Voltage Noise vs. Frequency
CIRCUIT LAYOUT CONSIDERATIONS & EVALUATION BOARD
A good high frequency PCB layout including ground plane construction and power supply bypassing close to the
package are critical to achieving full performance. The amplifier is sensitive to stray capacitance to ground at the
I− input (pin 12); keep node trace area small. Shunt capacitance across the feedback resistor should not be used
to compensate for this effect. For best performance at low maximum gains (AVMAX < 10) +RG and -RG
connections should be treated in a similar fashion. Capacitance to ground should be minimized by removing the
ground plane from under the body of RG.. Parasitic or load capacitance directly on the output (pin 10) degrades
phase margin leading to frequency response peaking.
The LMH6502 is fully stable when driving a 100Ω load. With reduced load (e.g. 1kΩ) there is a possibility of
instability at very high frequencies beyond 400MHz especially with a capacitive load. When the LMH6502 is
connected to a light load as such, it is recommended to add a snubber network to the output (e.g. 100Ω and
39pF in series tied between the LMH6502 output and ground). CL can also be isolated from the output by placing
a small resistor in series with the output (pin 10).
Component parasitics also influence high frequency results. Therefore it is recommended to use metal film
resistors such as RN55D or leadless components such as surface mount devices. High profile sockets are not
recommended.
Texas Instruments suggests the following evaluation boards as a guide for high frequency layout and as an aid in
device testing and characterization:
Device
Package
Evaluation Board Part Number
LMH6502MA
SOIC
LMH730033
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SINGLE SUPPLY OPERATION
It is possible to operate the LMH6502 with a single supply. To do so, tie pin 11 (GND) to a potential about mid
point between V+ and V−. Two examples are shown in Figure 61 & Figure 62.
R2
510:
R1
510:
VS
14
+VIN
13
3
+
RG
180:
-VIN
VS/2
RF
1k:
1
COUT
0.1µF
12
LMH6502
6
8
R4 7
2k:
R3
2k:
C1
0.1µF
11
2
9
10
ROUT
50:
VOUT
VG
Figure 61. AC Coupled Single Supply VGA
C1
0.1µF
R2
510:
R1
510:
VS
14
3
13
+
RG
160:
VS/2
RF
1k:
1
COUT
0.1µF
12
LMH6502
6
7
8
11
9
2
10
ROUT
50:
VOUT
VG
Figure 62. Transformer Coupled Single Supply VGA
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OPERATING AT LOWER SUPPLY VOLTAGES
The LMH6502 is rated for operation down to 5V supplies (V+ -V−). There are some specifications shown for
operation at ±2.5V within the data sheet (i.e. Frequency Response, CMRR, PSRR, Gain vs. VG, etc.). Compared
to ±5V operation, at lower supplies:
a)
VG range shifts lower.
Here are the approximate expressions for various VG voltages as a function of V+:
Table 1. VG Definition Based on V+
VG
Definition
Expression (V)
VG_MIN
Gain Cut-off
0.2 × V+ −1
VG_MID
AVMAX/2
0.2 × V+
VG_MAX
AVMAX
0.2 × V+ +1
b)
VG_LIMIT (maximum permissible voltage on VG) is reduced. This is due to limitations within the device
arising from transistor headroom. Beyond this limit, device performance will be affected (non-destructive).
This could reveal itself as premature high frequency response roll-off. With ±2.5V supplies, VG_LIMIT is
below 1.1V whereas VG = 1.5V is needed to get maximum gain. This means that operating under these
conditions has reduced the maximum permissible voltage on VG to a level below what is needed to get
Max gain. If supply voltages are asymmetrical with V+ being lower, further "pinching" of VG range could
result; for example, with V+ = 2V, and V− = −3V, VG_LIMIT = 0.40V which results in maximum gain being
2.5dB less than what would be expected when VS is higher.
c)
"Max_gain" reduces. There is an intrinsic reduction in max gain when the total supply voltage is reduced
(see Typical Performance Characteristics plots for Gain vs. VG (VS = ±2.5V). In addition, there is the more
drastic mechanism described in "b" above. Beyond VG_LIMIT, high frequency response is also effected.
Application Circuits
AGC LOOP
Figure 63 shows a typical AGC circuit. The LMH6502 is followed up with a LMH6714 for higher overall gain. The
output of the LMH6714 is rectified and fed to an inverting integrator using a LMH6657 (wideband voltage
feedback op amp). When the output voltage, VOUT, is too large the integrator output voltage ramps down
reducing the net gain of the LMH6502 and VOUT. If the output voltage is too small, the integrator ramps up
increasing the net gain and the output voltage. Actual output level is set with R1. To prevent shifts in DC output
voltage with DC changes in input signal level, trim pot R2 is provided. AGC circuits are always limited in the
range of input signals over which constant output level can be maintained. In this circuit, we would expect that
reasonable AGC action could be maintained for at least 40dB. In practice, rectifier dynamic range limits reduce
this slightly.
20
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Product Folder Links: LMH6502
LMH6502
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SNOSA65D – OCTOBER 2003 – REVISED MARCH 2013
Figure 63. Automatic Gain Control (AGC) Loop
FREQUENCY SHAPING
Frequency Shaping Frequency shaping and bandwidth extension of the LMH6502 can be accomplished using
parallel networks connected across the RG ports. The network shown in the Figure 64 schematic will effectively
extend the LMH6502's bandwidth.
Figure 64. Frequency Shaping
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Product Folder Links: LMH6502
21
LMH6502
SNOSA65D – OCTOBER 2003 – REVISED MARCH 2013
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REVISION HISTORY
Changes from Revision C (March 2013) to Revision D
•
22
Page
Changed layout of National Data Sheet to TI format .......................................................................................................... 21
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PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
(4/5)
(6)
LMH6502MA/NOPB
ACTIVE
SOIC
D
14
55
RoHS & Green
SN
Level-1-260C-UNLIM
-40 to 85
LMH6502MA
LMH6502MAX/NOPB
ACTIVE
SOIC
D
14
2500
RoHS & Green
SN
Level-1-260C-UNLIM
-40 to 85
LMH6502MA
LMH6502MT/NOPB
ACTIVE
TSSOP
PW
14
94
RoHS & Green
SN
Level-1-260C-UNLIM
-40 to 85
LMH65
02MT
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of
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