LMK00334RTVRQ1

Product Folder Order Now Support & Community Tools & Software Technical Documents LMK00334-Q1 SNAS760 – APRIL 2018 LMK00334-Q1 Four-Output PCIe/Gen1/Gen2/Gen3/Gen4 Clock Buffer and Level Translator 1 Features 2 • • • • 1 • • • • • • • • • AEC-Q100 Qualified for Automotive Applications: – Device Temperature Grade 2: –40°C to 105°C Ambient Operating Temperature Range – Device HBM ESD Classification Level 2 – Device CDM ESD Classification Level C5 – Device MM ESD Classification Level M2 3:1 Input Multiplexer – Two Universal Inputs Operate up to 400 MHz and Accept LVPECL, LVDS, CML, SSTL, HSTL, HCSL, or Single-Ended Clocks – One Crystal Input Accepts a 10- to 40-MHz Crystal or Single-Ended Clock Two Banks With Two Differential Outputs Each – HCSL, or Hi-Z (Selectable) – Additive RMS Phase Jitter for PCIe Gen3/Gen4 at 100 MHz: – 30 fs RMS (typical) High PSRR: –72 dBc at 156.25 MHz LVCMOS Output With Synchronous Enable Input Pin-Controlled Configuration VCC Core Supply: 3.3 V ± 5% Three Independent VCCO Output Supplies: 3.3 V, 2.5 V ± 5% Industrial Temperature Range: –40°C to +105°C 32-Lead WQFN (5 mm × 5 mm) Applications Infotainment: Telematics Control Unit Infotainment: Head Unit ADAS: Autonomous Driving Controller 3 Description The LMK00334-Q1 device is a 4-output HCSL fanout buffer intended for high-frequency, low-jitter clock, data distribution, and level translation. The input clock can be selected from two universal inputs or one crystal input. The selected input clock is distributed to two banks of two HCSL outputs and one LVCMOS output. The LVCMOS output has a synchronous enable input for runt-pulse-free operation when enabled or disabled. The LMK00334-Q1 operates from a 3.3-V core supply and three independent 3.3-V or 2.5-V output supplies. The LMK00334-Q1 provides high performance, versatility, and power efficiency, making it ideal for replacing fixed-output buffer devices while increasing timing margin in the system. Device Information(1) PART NUMBER LMK00334-Q1 PACKAGE WQFN (32) BODY SIZE (NOM) 5.00 mm × 5.00 mm (1) For all available packages, see the orderable addendum at the end of the data sheet. LMK00334-Q1 Functional Block Diagram CLKout_EN CLKout_EN 1 An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. PRODUCTION DATA. LMK00334-Q1 SNAS760 – APRIL 2018 www.ti.com Table of Contents 1 2 3 4 5 6 Features .................................................................. Applications ........................................................... Description ............................................................. Revision History..................................................... Pin Configuration and Functions ......................... Specifications......................................................... 1 1 1 2 3 4 6.1 6.2 6.3 6.4 6.5 6.6 6.7 4 4 5 5 5 8 9 Absolute Maximum Ratings ...................................... ESD Ratings.............................................................. Recommended Operating Conditions....................... Thermal Information .................................................. Electrical Characteristics........................................... Propagation Delay and Output Skew........................ Typical Characteristics .............................................. 7 Parameter Measurement Information ................ 11 8 Detailed Description ............................................ 12 9 9.1 Application Information............................................ 15 9.2 Typical Application .................................................. 15 10 Power Supply Recommendations ..................... 20 10.1 Current Consumption and Power Dissipation Calculations.............................................................. 20 10.2 Power Supply Bypassing ...................................... 22 11 Layout................................................................... 23 11.1 Layout Guidelines ................................................. 23 11.2 Layout Example .................................................... 23 11.3 Thermal Management ........................................... 24 12 Device and Documentation Support ................. 25 12.1 12.2 12.3 12.4 12.5 12.6 7.1 Differential Voltage Measurement Terminology...... 11 8.1 8.2 8.3 8.4 Overview ................................................................. Functional Block Diagram ....................................... Feature Description................................................. Device Functional Modes........................................ Application and Implementation ........................ 15 12 12 12 14 Documentation Support ....................................... Receiving Notification of Documentation Updates Community Resources.......................................... Trademarks ........................................................... Electrostatic Discharge Caution ............................ Glossary ................................................................ 25 25 25 25 25 25 13 Mechanical, Packaging, and Orderable Information ........................................................... 25 4 Revision History NOTE: Page numbers for previous revisions may differ from page numbers in the current version. 2 DATE REVISION NOTES April 2018 * Initial release. Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated Product Folder Links: LMK00334-Q1 LMK00334-Q1 www.ti.com SNAS760 – APRIL 2018 5 Pin Configuration and Functions VCC REFout_EN VCCOC REFout VCC CLKin1 CLKin1* NC RTV Package 32-Pin WQFN Top View 32 31 30 29 28 27 26 25 GND 1 24 GND VCCOA 2 23 VCCOB CLKoutA0 3 22 CLKoutB0 CLKoutA0* 4 21 CLKoutB0* 20 VCCOB 19 CLKoutB1 Top Down View VCCOA 5 CLKoutA1 6 DAP 9 10 11 12 13 14 15 16 CLKin_SEL1 GND CLKin0* 17 CLKin0 8 CLKin_SEL0 GND OSCout CLKoutB1* OSCin 18 VCC 7 CLKout_EN CLKoutA1* Pin Functions (1) PIN I/O NAME NO. DAP DAP GND 13 I CLKin_SEL0 DESCRIPTION Die Attach Pad. Connect to the PCB ground plane for heat dissipation. Clock input selection pins (2) (2) CLKin_SEL1 16 I Clock input selection pins CLKin0 14 I Universal clock input 0 (differential/single-ended) CLKin0* 15 I Universal clock input 0 (differential/single-ended) CLKin1 27 I Universal clock input 1 (differential/single-ended) CLKin1* 26 I Universal clock input 1 (differential/single-ended) CLKout_EN 9 I Bank A and Bank B low active output buffer enable. CLKoutA0 3 O Differential clock output A0. CLKoutA0* 4 O Differential clock output A0. CLKoutA1 6 O Differential clock output A1. CLKoutA1* 7 O Differential clock output A1. CLKoutB1 19 O Differential clock output B1. CLKoutB1* 18 O Differential clock output B1. CLKoutB0 22 O Differential clock output B0. Differential clock output B0. CLKoutB0* GND NC (1) (2) 21 O 1, 8 17, 24 GND 25 — (2) Ground Not connected internally. Pin may be floated, grounded, or otherwise tied to any potential within the Supply Voltage range stated in the Absolute Maximum Ratings. Any unused output pins should be left floating with minimum copper length (see note in Clock Outputs), or properly terminated if connected to a transmission line, or disabled/Hi-Z if possible. See Clock Outputs for output configuration and Termination and Use of Clock Drivers for output interface and termination techniques. CMOS control input with internal pulldown resistor. Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated Product Folder Links: LMK00334-Q1 3 LMK00334-Q1 SNAS760 – APRIL 2018 www.ti.com Pin Functions(1) (continued) PIN I/O DESCRIPTION NAME NO. OSCin 11 I Input for crystal. Can also be driven by a XO, TCXO, or other external single-ended clock. OSCout 12 O Output for crystal. Leave OSCout floating if OSCin is driven by a single-ended clock. REFout 29 O LVCMOS reference output. Enable output by pulling REFout_EN pin high. REFout_EN 31 I REFout enable input. Enable signal is internally synchronized to selected clock input. 10, 28, 32 PWR Power supply for Core and Input Buffer blocks. The VCC supply operates from 3.3 V. Bypass with a 0.1-µF, low-ESR capacitor placed very close to each VCC pin. VCCOA 2, 5 PWR Power supply for Bank A Output buffers. VCCOA operates from 3.3 V or 2.5 V. The VCCOA pins are internally tied together. Bypass with a 0.1-µF, low-ESR capacitor placed very close to each VCCO pin. (3) VCCOB 20, 23 PWR Power supply for Bank B Output buffers. VCCOB operates from 3.3 V or 2.5 V. The VCCOB pins are internally tied together. Bypass with a 0.1-µF, low-ESR capacitor placed very close to each VCCO pin. (3) VCCOC 30 PWR Power supply for REFout buffer. VCCOC operates from 3.3 V or 2.5 V. Bypass with a 0.1-µF, low-ESR capacitor placed very close to each VCCO pin. (3) VCC (3) (2) The output supply voltages or pins (VCCOA, VCCOB, and VCCOC) will be called VCCO in general when no distinction is needed, or when the output supply can be inferred from the output bank/type. 6 Specifications 6.1 Absolute Maximum Ratings over operating free-air temperature range (unless otherwise noted) (1) (2) MIN MAX UNIT V VCC, VCCO Supply voltages –0.3 3.6 VIN Input voltage –0.3 (VCC + 0.3) V TL Lead temperature (solder 4 s) 260 °C TJ Junction temperature 150 °C Tstg Storage temperature 150 °C (1) (2) –65 Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. If Military/Aerospace specified devices are required, please contact the Texas Instruments Sales Office/Distributors for availability and specifications. 6.2 ESD Ratings VALUE V(ESD) (1) (2) 4 Electrostatic discharge Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001 (1) ±2000 Charged-device model (CDM), per JEDEC specification JESD22-C101 (2) ±750 Machine model (MM) ±150 UNIT V JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process. Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated Product Folder Links: LMK00334-Q1 LMK00334-Q1 www.ti.com SNAS760 – APRIL 2018 6.3 Recommended Operating Conditions over operating free-air temperature range (unless otherwise noted) TA Ambient temperature TJ Junction temperature VCC Core supply voltage VCCO (1) (2) Output supply voltage (1) (2) MIN TYP MAX UNIT –40 25 105 °C 125 °C V 3.15 3.3 3.45 3.3-V range 3.3 – 5% 3.3 3.3 + 5% 2.5-V range 2.5 – 5% 2.5 2.5 + 5% V The output supply voltages or pins (VCCOA, VCCOB, and VCCOC) will be called VCCO in general when no distinction is needed, or when the output supply can be inferred from the output bank/type. VCCO for any output bank should be less than or equal to VCC (VCCO ≤ VCC). 6.4 Thermal Information LMK00334-Q1 (2) THERMAL METRIC (1) RTV (WQFN) UNIT 32 PINS RθJA Junction-to-ambient thermal resistance 38.1 °C/W RθJC(top) Junction-to-case (top) thermal resistance 7.2 °C/W RθJB Junction-to-board thermal resistance 12 °C/W ψJT Junction-to-top characterization parameter 0.4 °C/W ψJB Junction-to-board characterization parameter 11.9 °C/W RθJC(bot) Junction-to-case (bottom) thermal resistance 4.5 °C/W (1) (2) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report. Specification assumes 5 thermal vias connect the die attach pad (DAP) to the embedded copper plane on the 4-layer JEDEC board. These vias play a key role in improving the thermal performance of the package. TI recommends using the maximum number of vias in the board layout. 6.5 Electrical Characteristics Unless otherwise specified: VCC = 3.3 V ± 5%, VCCO = 3.3 V ± 5%, 2.5 V ± 5%, –40°C ≤ TA ≤ 105°C, CLKin driven differentially, input slew rate ≥ 3 V/ns. Typical values represent the most likely parametric norms at VCC = 3.3 V, VCCO = 3.3 V, TA = 25°C, and at the Recommended Operation Conditions at the time of product characterization; because of this, typical values are not ensured. (1) PARAMETER CURRENT CONSUMPTION ICC_CORE TEST CONDITIONS MIN TYP MAX UNIT CLKinX selected 8.5 10.5 mA OSCin selected (2) Core supply current, all outputs disabled 10 13.5 mA ICC_HCSL 50 58.5 mA ICC_CMOS 3.5 5.5 mA 65 81.5 mA VCCO = 3.3 V ±5% 9 10 mA VCCO = 2.5V ± 5% 7 8 mA ICCO_HCSL Additive output supply current, HCSL banks enabled Includes output bank bias and load currents for both banks, RT = 50 Ω on all outputs ICCO_CMOS Additive output supply current, LVCMOS output enabled 200 MHz, CL = 5 pF (1) (2) The output supply voltages or pins (VCCOA, VCCOB, and VCCOC) will be called VCCO in general when no distinction is needed, or when the output supply can be inferred from the output bank/type. See Power Supply Recommendations and Thermal Management for more information on current consumption and power dissipation calculations. Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated Product Folder Links: LMK00334-Q1 5 LMK00334-Q1 SNAS760 – APRIL 2018 www.ti.com Electrical Characteristics (continued) Unless otherwise specified: VCC = 3.3 V ± 5%, VCCO = 3.3 V ± 5%, 2.5 V ± 5%, –40°C ≤ TA ≤ 105°C, CLKin driven differentially, input slew rate ≥ 3 V/ns. Typical values represent the most likely parametric norms at VCC = 3.3 V, VCCO = 3.3 V, TA = 25°C, and at the Recommended Operation Conditions at the time of product characterization; because of this, typical values are not ensured. (1) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT POWER SUPPLY RIPPLE REJECTION (PSRR) PSRRHCSL Ripple-induced phase spur level (3) Differential HCSL Output 156.25 MHz –72 312.5 MHz –63 dBc CMOS CONTROL INPUTS (CLKin_SELn, CLKout_TYPEn, REFout_EN) VIH High-level input voltage 1.6 VCC V VIL Low-level input voltage GND 0.4 V IIH High-level input current VIH = VCC, internal pulldown resistor 50 μA IIL Low-level input current VIL = 0 V, internal pulldown resistor –5 0.1 μA CLOCK INPUTS (CLKin0/CLKin0*, CLKin1/CLKin1*) fCLKin Input frequency range (4) VIHD Differential input high voltage VILD Differential input low voltage VID Differential input voltage swing (5) VCMD Differential input CMD commonmode voltage VIH Single-ended input high voltage VIL Single-ended input low voltage VI_SE Single-ended input voltage swing (4) VCM Single-ended input CM commonmode voltage ISOMUX Mux isolation, CLKin0 to CLKin1 Functional up to 400 MHz Output frequency range and timing specified per output type (refer to LVCMOS output specifications) CLKin driven differentially DC 400 MHz Vcc V GND V 0.15 1.3 VID = 150 mV 0.25 VCC – 1.2 VID = 350 mV 0.25 VCC – 1.1 VID = 800 mV 0.25 VCC – 0.9 VCC GND CLKinX driven single-ended (AC- or DCcoupled), CLKinX* AC-coupled to GND or externally biased within VCM range fOFFSET > 50 kHz, PCLKinX = 0 dBm V V V V 0.3 2 0.25 VCC – 1.2 fCLKin0 = 100 MHz –84 fCLKin0 = 200 MHz –82 fCLKin0 = 500 MHz –71 fCLKin0 = 1000 MHz –65 Vpp V dBc CRYSTAL INTERFACE (OSCin, OSCout) FCLK External clock frequency range (4) OSCin driven single-ended, OSCout floating FXTAL Crystal frequency range Fundamental mode crystal ESR ≤ 200 Ω (10 to 30 MHz) ESR ≤ 125 Ω (30 to 40 MHz) (6) CIN OSCin input capacitance (3) (4) (5) (6) 6 10 1 250 MHz 40 MHz pF Power supply ripple rejection, or PSRR, is defined as the single-sideband phase spur level (in dBc) modulated onto the clock output when a single-tone sinusoidal signal (ripple) is injected onto the VCCO supply. Assuming no amplitude modulation effects and small index modulation, the peak-to-peak deterministic jitter (DJ) can be calculated using the measured single-sideband phase spur level (PSRR) as follows: DJ (ps pk-pk) = [ (2 × 10(PSRR / 20)) / (π × fCLK) ] × 1E12 Specification is ensured by characterization and is not tested in production. See Differential Voltage Measurement Terminology for definition of VID and VOD voltages. The ESR requirements stated must be met to ensure that the oscillator circuitry has no startup issues. However, lower ESR values for the crystal may be necessary to stay below the maximum power dissipation (drive level) specification of the crystal. Refer to Crystal Interface for crystal drive level considerations. Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated Product Folder Links: LMK00334-Q1 LMK00334-Q1 www.ti.com SNAS760 – APRIL 2018 Electrical Characteristics (continued) Unless otherwise specified: VCC = 3.3 V ± 5%, VCCO = 3.3 V ± 5%, 2.5 V ± 5%, –40°C ≤ TA ≤ 105°C, CLKin driven differentially, input slew rate ≥ 3 V/ns. Typical values represent the most likely parametric norms at VCC = 3.3 V, VCCO = 3.3 V, TA = 25°C, and at the Recommended Operation Conditions at the time of product characterization; because of this, typical values are not ensured. (1) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT 400 MHz HCSL OUTPUTS (CLKoutAn/CLKoutAn*, CLKoutBn/CLKoutBn*) Output frequency range (4) RL = 50 Ω to GND, CL ≤ 5 pF JitterADD_PCle Additive RMS phase jitter for PCIe 4.0 PCIe Gen 4, PLL BW = 2–5 MHz, CDR = 10 MHz CLKin: 100 MHz, slew rate ≥ 1.8 V/ns 0.03 ps JitterADD_PCle Additive RMS phase jitter for PCIe 3.0 PCIe Gen 3, PLL BW = 2–5 MHz, CDR = 10 MHz CLKin: 100 MHz, slew rate ≥ 0.6 V/ns 0.03 ps JitterADD Additive RMS jitter integration bandwidth 12 MHz to 20 MHz (7) VCCO = 3.3 V, RT = 50 Ω to GND CLKin: 100 MHz, slew rate ≥ 3 V/ns 77 fs Noise Floor Noise floor fOFFSET ≥ 10 MHz (8) (9) VCCO = 3.3 V, RT = 50 Ω to GND CLKin: 100 MHz, slew rate ≥ 3 V/ns –161.3 fCLKout DUTY Duty cycle (4) VOH Output high voltage VOL Output low voltage DC 50% input clock duty cycle 45% TA = 25°C, DC measurement, RT = 50 Ω to GND (10) VCROSS Absolute crossing voltage tR Output rise time 20% to 80% (10) (11) tF Output fall time 80% to 20% (10) (11) dBc/Hz 55% 520 810 920 mV –150 0.5 150 mV RL = 50 Ω to GND, CL ≤ 5 pF 350 250 MHz, uniform transmission line up to 10 in. with 50-Ω characteristic impedance, RL = 50 Ω to GND, CL ≤ 5 pF 225 400 ps 225 400 ps 250 MHz mV LVCMOS OUTPUT (REFout) fCLKout Output frequency range (4) CL ≤ 5 pF JitterADD Additive RMS jitter integration bandwidth 1 MHz to 20 MHz (7) VCCO = 3.3 V, CL ≤ 5 pF 100 MHz, input slew rate ≥ 3 V/ns 95 Noise Floor Noise floor fOFFSET ≥ 10 MHz (8) VCCO = 3.3 V, CL ≤ 5 pF 100 MHz, input slew rate ≥ 3 V/ns –159.3 DUTY Duty cycle (4) VOH Output high voltage VOL Output low voltage IOH (9) 50% input clock duty cycle dBc/Hz 55% V 0.1 Output high current (source) VO = VCCO / 2 Output low current (sink) tR Output rise time 20% to 80% (10) Output fall time 80% to 20% 45% fs VCCO – 0.1 1-mA load IOL tF DC (12) VCCO = 3.3 V 28 VCCO = 2.5 V 20 VCCO = 3.3 V 28 VCCO = 2.5 V 20 250 MHz, uniform transmission line up to 10 in. with 50-Ω characteristic impedance, RL = 50 Ω to GND, CL ≤ 5 pF V mA mA 225 ps 225 ps For the 100-MHz and 156.25-MHz clock input conditions, Additive RMS Jitter (JADD) is calculated using Method #1: JADD = SQRT(JOUT2 - JSOURCE2), where JOUT is the total RMS jitter measured at the output driver and JSOURCE is the RMS jitter of the clock source applied to CLKin. For the 625-MHz clock input condition, Additive RMS Jitter is approximated using Method #2: JADD = SQRT(2 × 10dBc/10) / (2 × π × fCLK), where dBc is the phase noise power of the Output Noise Floor integrated from 12-kHz to 20-MHz bandwidth. The phase noise power can be calculated as: dBc = Noise Floor + 10 × log10(20 MHz – 12 kHz). (8) The noise floor of the output buffer is measured as the far-out phase noise of the buffer. Typically this offset is ≥ 10 MHz, but for lower frequencies this measurement offset can be as low as 5 MHz due to measurement equipment limitations. (9) Phase noise floor will degrade as the clock input slew rate is reduced. Compared to a single-ended clock, a differential clock input (LVPECL, LVDS) will be less susceptible to degradation in noise floor at lower slew rates due to its common-mode noise rejection. However, TI recommends using the highest possible input slew rate for differential clocks to achieve optimal noise floor performance at the device outputs. (10) AC timing parameters for HCSL or LVCMOS are dependent on output capacitive loading. (11) Parameter is specified by design, not tested in production. (12) Output Enable Time is the number of input clock cycles it takes for the output to be enabled after REFout_EN is pulled high. Similarly, Output Disable Time is the number of input clock cycles it takes for the output to be disabled after REFout_EN is pulled low. The REFout_EN signal should have an edge transition much faster than that of the input clock period for accurate measurement. (7) Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated Product Folder Links: LMK00334-Q1 7 LMK00334-Q1 SNAS760 – APRIL 2018 www.ti.com Electrical Characteristics (continued) Unless otherwise specified: VCC = 3.3 V ± 5%, VCCO = 3.3 V ± 5%, 2.5 V ± 5%, –40°C ≤ TA ≤ 105°C, CLKin driven differentially, input slew rate ≥ 3 V/ns. Typical values represent the most likely parametric norms at VCC = 3.3 V, VCCO = 3.3 V, TA = 25°C, and at the Recommended Operation Conditions at the time of product characterization; because of this, typical values are not ensured. (1) PARAMETER TEST CONDITIONS tEN Output enable time (12) tDIS Output disable time (12) MIN CL ≤ 5 pF TYP MAX UNIT 3 cycles 3 cycles 6.6 Propagation Delay and Output Skew MIN tPD_HCSL tPD_CMOS tSK(O) tSK(PP) (1) (2) (3) (4) 8 Propagation delay CLKin-to-HCSL (1) Propagation delay CLKin-to-LVCMOS Output skew (2) (3) Part-to-part output skew (1) (4) RT = 50 Ω to GND, CL ≤ 5 pF (1) CL ≤ 5 pF TYP MAX UNIT 590 VCCO = 3.3 V 1475 VCCO = 2.5 V 1550 Skew specified between any two CLKouts. Load conditions are the same as propagation delay specifications. ps ps 30 ps 80 ps AC timing parameters for HCSL or LVCMOS are dependent on output capacitive loading. Output skew is the propagation delay difference between any two outputs with identical output buffer type and equal loading while operating at the same supply voltage and temperature conditions. AC timing parameters for HCSL or LVCMOS are dependent on output capacitive loading. Output skew is the propagation delay difference between any two outputs with identical output buffer type and equal loading while operating at the same supply voltage and temperature conditions. Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated Product Folder Links: LMK00334-Q1 LMK00334-Q1 www.ti.com SNAS760 – APRIL 2018 6.7 Typical Characteristics Unless otherwise specified: VCC = 3.3 V, VCCO = 3.3 V, TA = 25°C, CLKin driven differentially, input slew rate ≥ 3 V/ns. 1.0 1.00 OUTPUT SWING (V) OUTPUT SWING (V) 0.8 0.6 0.4 0.2 0.0 0.50 0.25 0.00 -0.25 -0.50 -1.00 0 1 2 3 TIME (ns) 4 0 5 -140 -135 HCSL LVCMOS CLKin Source -150 -155 -160 5 6 HCSL CLKin Source -150 -155 -160 -170 -165 0.5 1.0 1.5 2.0 2.5 3.0 3.5 Differential Input Slew Rate (V/ns) Fclk = 100 MHz Foffset = 20 MHz Figure 3. Noise Floor vs. CLKin Slew Rate at 100 MHz 350 3 4 TIME (ns) -145 -165 400 2 -140 Noise Floor (dBc/Hz) -145 1 Figure 2. LVCMOS Output Swing at 250 MHz Figure 1. HCSL Output Swing at 250 MHz Noise Floor (dBc/Hz) load load -0.75 -0.2 0.5 1.0 1.5 2.0 2.5 3.0 3.5 Differential Input Slew Rate (V/ns) Fclk = 156.25 MHz Foffset = 20 MHz Figure 4. Noise Floor vs. CLKin Slew Rate at 156.25 MHz 500 HCSL LVCMOS CLKin Source 450 HCSL CLKin Source 400 RMS Jitter (fs) 300 RMS Jitter (fs) Vcco=3.3 V, AC coupled, 50 Vcco=2.5 V, AC coupled, 50 0.75 250 200 150 100 350 300 250 200 150 100 50 50 0 0 0.5 Fclk 1.0 1.5 2.0 2.5 3.0 3.5 Differential Input Slew Rate (V/ns) = 100 MHz Int. BW = 1 to 20 MHz Figure 5. RMS Jitter vs. CLKin Slew Rate at 100 MHz 0.5 1.0 1.5 2.0 2.5 3.0 3.5 Differential Input Slew Rate (V/ns) Fclk = 156.25 MHz Int. BW = 1 to 20 MHz Figure 6. RMS Jitter vs. CLKin Slew Rate at 156.25 MHz Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated Product Folder Links: LMK00334-Q1 9 LMK00334-Q1 SNAS760 – APRIL 2018 www.ti.com Typical Characteristics (continued) -50 HCSL Ripple Induced Spur Level (dBc) Ripple Induced Spur Level (dBc) -50 -55 -60 -65 -70 -75 -80 -85 -60 -65 -70 -75 -80 -85 -90 -90 Fclk = 156.25 MHz 1 10 Ripple Frequency (MHz) Vccco Ripple = 100 mVpp Figure 7. PSRR vs. Ripple Frequency at 156.25 MHz HCSL (0.35 ps/°C) LVCMOS (2.2 ps/°C) 1850 750 650 1950 Right Y-axis plot 1750 550 1650 450 1550 350 1450 1350 250 -50 REFout Propagation Delay (ps) 850 -25 0 25 50 75 Temperature (°C) .1 Figure 8. PSRR vs. Ripple Frequency at 312.5 MHz 200 20 MHz Crystal 40 MHz Crystal 175 150 125 100 75 50 25 0 0 100 Figure 9. Propagation Delay vs. Temperature 1 10 Ripple Frequency (MHz) Vccco Ripple = 100 mVpp Fclk = 312.5 MHz CRYSTAL POWER DISSIPATION ( W) .1 CLKout Propagation Delay (ps) HCSL -55 500 1k 1.5k 2k 2.5k 3k 3.5k 4k RLIM( ) Figure 10. Crystal Power Dissipation vs. RLIM Figure 11. HCSL Phase Noise at 100 MHz 10 Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated Product Folder Links: LMK00334-Q1 LMK00334-Q1 www.ti.com SNAS760 – APRIL 2018 7 Parameter Measurement Information 7.1 Differential Voltage Measurement Terminology The differential voltage of a differential signal can be described by two different definitions, causing confusion when reading data sheets or communicating with other engineers. This section will address the measurement and description of a differential signal so that the reader will be able to understand and discern between the two different definitions when used. The first definition used to describe a differential signal is the absolute value of the voltage potential between the inverting and noninverting signal. The symbol for this first measurement is typically VID or VOD depending on if an input or output voltage is being described. The second definition used to describe a differential signal is to measure the potential of the noninverting signal with respect to the inverting signal. The symbol for this second measurement is VSS and is a calculated parameter. Nowhere in the IC does this signal exist with respect to ground; it only exists in reference to its differential pair. VSS can be measured directly by oscilloscopes with floating references, otherwise this value can be calculated as twice the value of VOD as described in the first description. Figure 12 illustrates the two different definitions side-by-side for inputs and Figure 13 illustrates the two different definitions side-by-side for outputs. The VID (or VOD) definition show the DC levels, VIH and VOL (or VOH and VOL), that the noninverting and inverting signals toggle between with respect to ground. VSS input and output definitions show that if the inverting signal is considered the voltage potential reference, the noninverting signal voltage potential is now increasing and decreasing above and below the noninverting reference. Thus the peak-to-peak voltage of the differential signal can be measured. VID and VOD are often defined as volts (V) and VSS is often defined as volts peak-to-peak (VPP). VID Definition VSS Definition for Input Non-Inverting Clock VIH VCM VSS VID VIL Inverting Clock VSS = 2· VID VID = | VIH ± VIL | GND Figure 12. Two Different Definitions for Differential Input Signals VOD Definition VSS Definition for Output Non-Inverting Clock VOH VOS VOL VSS VOD Inverting Clock VOD = | VOH - VOL | VSS = 2· VOD GND Figure 13. Two Different Definitions for Differential Output Signals Refer to Common Data Transmission Parameters and their Definitions (SNLA036) for more information. Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated Product Folder Links: LMK00334-Q1 11 LMK00334-Q1 SNAS760 – APRIL 2018 www.ti.com 8 Detailed Description 8.1 Overview The LMK00334-Q1 is a 4-output HCSL clock fanout buffer with low additive jitter that can operate up to 400 MHz. It features a 3:1 input multiplexer with an optional crystal oscillator input, two banks of two HCSL outputs, one LVCMOS output, and three independent output buffer supplies. The input selection and output buffer modes are controlled through pin strapping. The device is offered in a 32-pin WQFN package and leverages much of the high-speed, low-noise circuit design employed in the LMK04800 family of clock conditioners. 8.2 Functional Block Diagram CLKout_EN CLKout_EN 8.3 Feature Description 8.3.1 Crystal Power Dissipation vs. RLIM For Figure 10, the following applies: • The typical RMS jitter values in the plots show the total output RMS jitter (JOUT) for each output buffer type and the source clock RMS jitter (JSOURCE). From these values, the Additive RMS Jitter can be calculated as: JADD = SQRT(JOUT2 – JSOURCE2). • 20-MHz crystal characteristics: Abracon ABL series, AT cut, CL = 18 pF, C0 = 4.4 pF measured (7 pF maximum), ESR = 8.5 Ω measured (40 Ω maximum), and Drive Level = 1 mW maximum (100 µW typical). • 40-MHz crystal characteristics: Abracon ABLS2 series, AT cut, CL = 18 pF, C0 = 5 pF measured (7 pF maximum), ESR = 5 Ω measured (40 Ω maximum), and Drive Level = 1 mW maximum (100 µW typical). 12 Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated Product Folder Links: LMK00334-Q1 LMK00334-Q1 www.ti.com SNAS760 – APRIL 2018 Feature Description (continued) 8.3.2 Clock Inputs The input clock can be selected from CLKin0/CLKin0*, CLKin1/CLKin1*, or OSCin. Clock input selection is controlled using the CLKin_SEL[1:0] inputs as shown in Table 1. Refer to Driving the Clock Inputs for clock input requirements. When CLKin0 or CLKin1 is selected, the crystal circuit is powered down. When OSCin is selected, the crystal oscillator circuit will start up and its clock will be distributed to all outputs. Refer to Crystal Interface for more information. Alternatively, OSCin may be driven by a single-ended clock (up to 250 MHz) instead of a crystal. Table 1. Input Selection CLKin_SEL1 CLKin_SEL0 SELECTED INPUT 0 0 CLKin0, CLKin0* 0 1 CLKin1, CLKin1* 1 X OSCin Table 2 shows the output logic state vs. input state when either CLKin0/CLKin0* or CLKin1/CLKin1* is selected. When OSCin is selected, the output state will be an inverted copy of the OSCin input state. Table 2. CLKin Input vs. Output States STATE OF SELECTED CLKin STATE OF ENABLED OUTPUTS CLKinX and CLKinX* inputs floating Logic low CLKinX and CLKinX* inputs shorted together Logic low CLKin logic low Logic low CLKin logic high Logic high 8.3.3 Clock Outputs The HCSL output buffer for both Bank A and B outputs are can be disabled to Hi-Z using the CLKout_EN [1:0] as shown in Table 3. For applications where all differential outputs are not needed, any unused output pin should be left floating with a minimum copper length (see note below) to minimize capacitance and potential coupling and reduce power consumption. If all differential outputs are not used, TI recommends disabling (Hi-Z) the banks to reduce power. Refer to Termination and Use of Clock Drivers for more information on output interface and termination techniques. NOTE For best soldering practices, the minimum trace length for any unused pin should extend to include the pin solder mask. This way during reflow, the solder has the same copper area as connected pins. This allows for good, uniform fillet solder joints helping to keep the IC level during reflow. Table 3. Differential Output Buffer Type Selection CLKout_EN CLKoutX BUFFER TYPE (BANK A AND B) 0 HCSL 1 Disabled (Hi-Z) Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated Product Folder Links: LMK00334-Q1 13 LMK00334-Q1 SNAS760 – APRIL 2018 www.ti.com 8.3.3.1 Reference Output The reference output (REFout) provides a LVCMOS copy of the selected input clock. The LVCMOS output high level is referenced to the VCCO voltage. REFout can be enabled or disabled using the enable input pin, REFout_EN, as shown in Table 4. Table 4. Reference Output Enable REFout_EN REFout STATE 0 Disabled (Hi-Z) 1 Enabled The REFout_EN input is internally synchronized with the selected input clock by the SYNC block. This synchronizing function prevents glitches and runt pulses from occurring on the REFout clock when enabled or disabled. REFout will be enabled within three cycles (tEN) of the input clock after REFout_EN is toggled high. REFout will be disabled within three cycles (tDIS) of the input clock after REFout_EN is toggled low. When REFout is disabled, the use of a resistive loading can be used to set the output to a predetermined level. For example, if REFout is configured with a 1-kΩ load to ground, then the output will be pulled to low when disabled. 8.4 Device Functional Modes 8.4.1 VCC and VCCO Power Supplies The LMK00334-Q1 has separate 3.3-V core supplies (VCC) and three independent 3.3-V or 2.5-V output power supplies (VCCOA, VCCOB, VCCOC). Output supply operation at 2.5 V enables lower power consumption and outputlevel compatibility with 2.5-V receiver devices. The output levels for HCSL are relatively constant over the specified VCCO range. Refer to Power Supply Recommendations for additional supply related considerations, such as power dissipation, power supply bypassing, and power supply ripple rejection (PSRR). NOTE Take care to ensure the VCCO voltages do not exceed the VCC voltage to prevent turningon the internal ESD protection circuitry. 14 Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated Product Folder Links: LMK00334-Q1 LMK00334-Q1 www.ti.com SNAS760 – APRIL 2018 9 Application and Implementation NOTE Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining suitability of components for their purposes. Customers should validate and test their design implementation to confirm system functionality. 9.1 Application Information A common automotive PCIe application, such as ADAS (Advanced Driver Assistance Systems), requires several clocks and timing sources to drive the building blocks of the system. In a common ADAS system, the clock is distributed to an SoC, PCIe Switch, WiFi Controller, and Gigabit Ethernet to transmit high-speed video data from the IP-Based Cameras on the vehicle. The LMK00334-Q1 provides an automotive qualified solution that saves cost and space. When transmitting high-speed video data, the additive jitter of the buffer clock may noticeably impact performance. In order to optimize signal speed and cable length, system designs must account for this additive jitter. The LMK00334-Q1 is an ultra-low-jitter PCIe clock buffer suitable for current and future automotive PCIe applications. 9.2 Typical Application Figure 14. Example Automotive Application Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated Product Folder Links: LMK00334-Q1 15 LMK00334-Q1 SNAS760 – APRIL 2018 www.ti.com Typical Application (continued) 9.2.1 Design Requirements 9.2.1.1 Driving the Clock Inputs The LMK00334-Q1 has two universal inputs (CLKin0/CLKin0* and CLKin1/CLKin1*) that can accept DC-coupled, 3.3-V or 2.5-V LVPECL, LVDS, CML, SSTL, and other differential and single-ended signals that meet the input requirements specified in Electrical Characteristics. The device can accept a wide range of signals due to its wide input common-mode voltage range (VCM ) and input voltage swing (VID) / dynamic range. For 50% duty cycle and DC-balanced signals, AC coupling may also be employed to shift the input signal to within the VCM range. Refer to Termination and Use of Clock Drivers for signal interfacing and termination techniques. To achieve the best possible phase noise and jitter performance, it is mandatory for the input to have high slew rate of 3 V/ns (differential) or higher. Driving the input with a lower slew rate will degrade the noise floor and jitter. For this reason, a differential signal input is recommended over single-ended because it typically provides higher slew rate and common-mode rejection. Refer to the Noise Floor vs. CLKin Slew Rate and RMS Jitter vs. CLKin Slew Rate plots in Typical Characteristics. While TI recommends driving the CLKin/CLKin* pair with a differential signal input, it is possible to drive it with a single-ended clock provided it conforms to the single-ended input specifications for CLKin pins listed in the Electrical Characteristics. For large single-ended input signals, such as 3.3-V or 2.5-V LVCMOS, a 50-Ω load resistor should be placed near the input for signal attenuation to prevent input overdrive as well as for line termination to minimize reflections. Again, the single-ended input slew rate should be as high as possible to minimize performance degradation. The CLKin input has an internal bias voltage of about 1.4 V, so the input can be AC coupled as shown in Figure 15. The output impedance of the LVCMOS driver plus Rs should be close to 50 Ω to match the characteristic impedance of the transmission line and load termination. RS 0.1 PF 0.1 PF 50: Trace 50: CMOS Driver LMK Input 0.1 PF Figure 15. Single-Ended LVCMOS Input, AC Coupling A single-ended clock may also be DC-coupled to CLKinX as shown in Figure 16. A 50-Ω load resistor should be placed near the CLKin input for signal attenuation and line termination. Because half of the single-ended swing of the driver (VO,PP / 2) drives CLKinX, CLKinX* should be externally biased to the midpoint voltage of the attenuated input swing ((VO,PP / 2) × 0.5). The external bias voltage should be within the specified input common voltage (VCM) range. This can be achieved using external biasing resistors in the kΩ range (RB1 and RB2) or another low-noise voltage reference. This will ensure the input swing crosses the threshold voltage at a point where the input slew rate is the highest. CMOS Driver VO,PP Rs VO,PP/2 VCC 50: Trace VBB ~ (VO,PP/2) x 0.5 50: LMK Input RB1 VCC RB2 0.1 PF Figure 16. Single-Ended LVCMOS Input, DC Coupling With Common-Mode Biasing 16 Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated Product Folder Links: LMK00334-Q1 LMK00334-Q1 www.ti.com SNAS760 – APRIL 2018 Typical Application (continued) If the crystal oscillator circuit is not used, it is possible to drive the OSCin input with an single-ended external clock as shown in Figure 17. The input clock should be AC coupled to the OSCin pin, which has an internallygenerated input bias voltage, and the OSCout pin should be left floating. While OSCin provides an alternative input to multiplex an external clock, TI recommends using either universal input (CLKinX) because it offers higher operating frequency, better common-mode and power supply noise rejection, and greater performance over supply voltage and temperature variations. 0.1 PF OSCin 50: 50: Trace OSCout LMK00334 RS 0.1 PF CMOS Driver Figure 17. Driving OSCin With a Single-Ended Input 9.2.1.2 Crystal Interface The LMK00334-Q1 has an integrated crystal oscillator circuit that supports a fundamental mode, AT-cut crystal. The crystal interface is shown in Figure 18. C1 XTAL RLIM OSCout LMK00334 OSCin C2 Figure 18. Crystal Interface The load capacitance (CL) is specific to the crystal, but usually on the order of 18 to 20 pF. While CL is specified for the crystal, the OSCin input capacitance (CIN = 1 pF typical) of the device and PCB stray capacitance (CSTRAY is approximately around 1 to 3 pF) can affect the discrete load capacitor values, C1 and C2. For the parallel resonant circuit, the discrete capacitor values can be calculated as follows: CL = (C1 × C2) / (C1 + C2) + CIN + CSTRAY (1) Typically, C1 = C2 for optimum symmetry, so Equation 1 can be rewritten in terms of C1 only: CL = C12 / (2 × C1) + CIN + CSTRAY (2) Finally, solve for C1: C1 = (CL – CIN – CSTRAY) × 2 (3) Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated Product Folder Links: LMK00334-Q1 17 LMK00334-Q1 SNAS760 – APRIL 2018 www.ti.com Typical Application (continued) Electrical Characteristics provides crystal interface specifications with conditions that ensure start-up of the crystal, but it does not specify crystal power dissipation. The designer must ensure the crystal power dissipation does not exceed the maximum drive level specified by the crystal manufacturer. Overdriving the crystal can cause premature aging, frequency shift, and eventual failure. Drive level should be held at a sufficient level necessary to start up and maintain steady-state operation. The power dissipated in the crystal, PXTAL, can be computed by: PXTAL = IRMS2 × RESR × (1 + C0/CL)2 where • • • • IRMS is the RMS current through the crystal. RESR is the maximum equivalent series resistance specified for the crystal CL is the load capacitance specified for the crystal C0 is the minimum shunt capacitance specified for the crystal (4) IRMS can be measured using a current probe (Tektronix CT-6 or equivalent, for example) placed on the leg of the crystal connected to OSCout with the oscillation circuit active. As shown in Figure 18, an external resistor, RLIM, can be used to limit the crystal drive level, if necessary. If the power dissipated in the selected crystal is higher than the drive level specified for the crystal with RLIM shorted, then a larger resistor value is mandatory to avoid overdriving the crystal. However, if the power dissipated in the crystal is less than the drive level with RLIM shorted, then a zero value for RLIM can be used. As a starting point, a suggested value for RLIM is 1.5 kΩ. 9.2.2 Detailed Design Procedure 9.2.2.1 Termination and Use of Clock Drivers When terminating clock drivers, keep these guidelines in mind for optimum phase noise and jitter performance: • Transmission line theory should be followed for good impedance matching to prevent reflections. • Clock drivers should be presented with the proper loads. – HCSL drivers are switched current outputs and require a DC path to ground through 50-Ω termination. • Receivers should be presented with a signal biased to their specified DC bias level (common-mode voltage) for proper operation. Some receivers have self-biasing inputs that automatically bias to the proper voltage level; in this case, the signal should normally be AC coupled. 9.2.2.2 Termination for DC-Coupled Differential Operation 50: For DC-coupled operation of an HCSL driver, terminate with 50 Ω to ground near the driver output as shown in Figure 19. Series resistors, Rs, may be used to limit overshoot due to the fast transient current. Because HCSL drivers require a DC path to ground, AC coupling is not allowed between the output drivers and the 50-Ω termination resistors. CLKoutX Rs HCSL Driver 50: Traces Rs HCSL Receiver 50: CLKoutX* Figure 19. HCSL Operation, DC Coupling 18 Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated Product Folder Links: LMK00334-Q1 LMK00334-Q1 www.ti.com SNAS760 – APRIL 2018 Typical Application (continued) 9.2.2.3 Termination for AC-Coupled Differential Operation AC coupling allows for shifting the DC bias level (common-mode voltage) when driving different receiver standards. Because AC-coupling prevents the driver from providing a DC bias voltage at the receiver, it is important to ensure the receiver is biased to its ideal DC level. 9.2.3 Application Curve Figure 20. HCSL Phase Noise at 100 MHz Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated Product Folder Links: LMK00334-Q1 19 LMK00334-Q1 SNAS760 – APRIL 2018 www.ti.com 10 Power Supply Recommendations 10.1 Current Consumption and Power Dissipation Calculations The current consumption values specified in Electrical Characteristics can be used to calculate the total power dissipation and IC power dissipation for any device configuration. The total VCC core supply current (ICC_TOTAL) can be calculated using Equation 5: ICC_TOTAL = ICC_CORE + ICC_BANKS + ICC_CMOS where • • • ICC_CORE is the VCC current for core logic and input blocks and depends on selected input (CLKinX or OSCin). ICC_HCSL is the VCC current for Banks A and B ICC_CMOS is the VCC current for the LVCMOS output (or 0 mA if REFout is disabled). (5) Because the output supplies (VCCOA, VCCOB, VCCOC) can be powered from three independent voltages, the respective output supply currents (ICCO_BANK_A, ICCO_BANK_B, and ICCO_CMOS) should be calculated separately. ICCO_BANK for either Bank A or B may be taken as 50% of the corresponding output supply current specified for two banks (ICCO_HCSL) provided the output loading matches the specified conditions. Otherwise, ICCO_BANK should be calculated per bank as shown in Equation 6: ICCO_BANK = IBANK_BIAS + (N × IOUT_LOAD) where • • • IBANK_BIAS is the output bank bias current (fixed value). IOUT_LOAD is the DC load current per loaded output pair. N is the number of loaded output pairs (N = 0 to 2). (6) Table 5 shows the typical IBANK_BIAS values and IOUT_LOAD expressions for HCSL. Table 5. Typical Output Bank Bias and Load Currents CURRENT PARAMETER HCSL IBANK_BIAS 2.4 mA IOUT_LOAD VOH/RT Once the current consumption is known for each supply, the total power dissipation (PTOTAL) can be calculated by Equation 7: PTOTAL = (VCC × ICC_TOTAL) + (VCCOA × ICCO_BANK) + (VCCOB × ICCO_BANK) + (VCCOC × ICCO_CMOS) (7) If the device is configured with HCSL outputs, then it is also necessary to calculate the power dissipated in any termination resistors (PRT_HCSL). The external power dissipation values can be calculated by Equation 8: PRT_HCSL (per HCSL pair) = VOH2 / RT (8) Finally, the IC power dissipation (PDEVICE) can be computed by subtracting the external power dissipation values from PTOTAL as shown in Equation 9: PDEVICE = PTOTAL – N × PRT_HCSL where • 20 N is the number of HCSL output pairs with termination resistors to GND. Submit Documentation Feedback (9) Copyright © 2018, Texas Instruments Incorporated Product Folder Links: LMK00334-Q1 LMK00334-Q1 www.ti.com SNAS760 – APRIL 2018 10.1.1 Power Dissipation Example: Worst-Case Dissipation This example shows how to calculate IC power dissipation for a configuration to estimate worst-case power dissipation. In this case, the maximum supply voltage and supply current values specified in Electrical Characteristics are used: • Max VCC = VCCO = 3.465 V. Max ICC and ICCO values. • CLKin0/CLKin0* input is selected. • Banks A and B are enabled, and all outputs are terminated with 50 Ω to GND. • REFout is enabled with 5-pF load. • TA = 105°C Using the power calculations from the previous section and maximum supply current specifications, the user can compute PTOTAL and PDEVICE. • From Equation 5: ICC_TOTAL = 10.5 mA + 58.5 mA + 5.5 mA = 74.5 mA • From ICCO_HCSL max spec: ICCO_BANK = 50% of ICCO_HCSL = 40.75 mA • From Equation 7: PTOTAL = (3.465 V × 74.5 mA) + (3.465 V × 40.75 mA) + (3.465 V × 40.75 mA) + (3.465 V × 10 mA) = 575.2 mW • From Equation 8: PRT_HCSL = (0.92 V)2 / 50 Ω = 16.9 mW (per output pair) • From Equation 9: PDEVICE = 575.2 mW – (4 × 16.9 mW) = 510.4 mW In this worst-case example, the IC device will dissipate about 510.4 mW or 88.7% of the total power (575.2 mW), while the remaining 11.3% will be dissipated in the termination resistors (64.8 mW for 4 pairs). Based on RθJA of 38.1°C/W, the estimate die junction temperature would be about 19.4°C above ambient, or 104.4°C when TA = 85°C. Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated Product Folder Links: LMK00334-Q1 21 LMK00334-Q1 SNAS760 – APRIL 2018 www.ti.com 10.2 Power Supply Bypassing The VCC and VCCO power supplies should have a high-frequency bypass capacitor, such as 0.1 µF or 0.01 µF, placed very close to each supply pin. 1-µF to 10-µF decoupling capacitors should also be placed nearby the device between the supply and ground planes. All bypass and decoupling capacitors should have short connections to the supply and ground plane through a short trace or via to minimize series inductance. 10.2.1 Power Supply Ripple Rejection In practical system applications, power supply noise (ripple) can be generated from switching power supplies, digital ASICs or FPGAs, and so forth. While power supply bypassing will help filter out some of this noise, it is important to understand the effect of power supply ripple on the device performance. When a single-tone sinusoidal signal is applied to the power supply of a clock distribution device, such as LMK00334-Q1, it can produce narrow-band phase modulation as well as amplitude modulation on the clock output (carrier). In the single-side band phase noise spectrum, the ripple-induced phase modulation appears as a phase spur level relative to the carrier (measured in dBc). For the LMK00334-Q1, power supply ripple rejection, or PSRR, was measured as the single-sideband phase spur level (in dBc) modulated onto the clock output when a ripple signal was injected onto the VCCO supply. The PSRR test setup is shown in Figure 21. Ripple Source Vcco Clock Source Power Supplies Bias-Tee Vcc OUT+ IN+ Limiting Amp IC IN- OUTDUT Board OUT Phase Noise Analyzer Scope Measure 100 mVPP ripple on Vcco at IC Measure single sideband phase spur power in dBc Figure 21. PSRR Test Setup A signal generator was used to inject a sinusoidal signal onto the VCCO supply of the DUT board, and the peakto-peak ripple amplitude was measured at the VCCO pins of the device. A limiting amplifier was used to remove amplitude modulation on the differential output clock and convert it to a single-ended signal for the phase noise analyzer. The phase spur level measurements were taken for clock frequencies of 156.25 MHz and 312.5 MHz under the following power supply ripple conditions: • Ripple amplitude: 100 mVpp on VCCO = 2.5 V • Ripple frequencies: 100 kHz, 1 MHz, and 10 MHz Assuming no amplitude modulation effects and small index modulation, the peak-to-peak deterministic jitter (DJ) can be calculated using the measured single-sideband phase spur level (PSRR) as follows: DJ (ps pk-pk) = [(2 × 10(PSRR / 20)) / (π × fCLK)] × 1012 (10) The PSRR vs. Ripple Frequency plots in Typical Characteristics show the ripple-induced phase spur levels at 156.25 MHz and 312.5 MHz. The LMK00334-Q1 exhibits very good and well-behaved PSRR characteristics across the ripple frequency range. The phase spur levels for HCSL are below –72 dBc at 156.25 MHz and below –63 dBc at 312.5 MHz. Using Equation 10, these phase spur levels translate to Deterministic Jitter values of 1.02 ps pk-pk at 156.25 MHz and 1.44 ps pk-pk at 312.5 MHz. Testing has shown that the PSRR performance of the device improves for VCCO = 3.3 V under the same ripple amplitude and frequency conditions. 22 Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated Product Folder Links: LMK00334-Q1 LMK00334-Q1 www.ti.com SNAS760 – APRIL 2018 11 Layout 11.1 Layout Guidelines For this device, consider the following guidelines: • For DC-coupled operation of an HCSL driver, terminate with 50 Ω to ground near the driver output as shown in Figure 22. • Keep the connections between the bypass capacitors and the power supply on the device as short as possible. • Ground the other side of the capacitor using a low impedance connection to the ground plane. • If the capacitors are mounted on the back side, 0402 components can be employed. However, soldering to the Thermal Dissipation Pad can be difficult. • For component side mounting, use 0201 body size capacitors to facilitate signal routing. 11.2 Layout Example Figure 22. LMK00334-Q1 Layout Example Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated Product Folder Links: LMK00334-Q1 23 LMK00334-Q1 SNAS760 – APRIL 2018 www.ti.com 11.3 Thermal Management Power dissipation in the LMK00334-Q1 device can be high enough to require attention to thermal management. For reliability and performance reasons the die temperature should be limited to a maximum of 125°C. That is, as an estimate, TA (ambient temperature) plus device power dissipation times RθJA should not exceed 125°C. The package of the device has an exposed pad that provides the primary heat removal path as well as excellent electrical grounding to the printed-circuit board. To maximize the removal of heat from the package, a thermal land pattern including multiple vias to a ground plane must be incorporated on the PCB within the footprint of the package. The exposed pad must be soldered down to ensure adequate heat conduction out of the package. A recommended land and via pattern is shown in Figure 23. More information on soldering WQFN packages can be obtained at: http://www.ti.com/packaging. 3.1 mm, min 0.2 mm, typ 1.27 mm, typ Figure 23. Recommended Land and Via Pattern To minimize junction temperature, TI recommends building a simple heat sink into the PCB (if the ground plane layer is not exposed). This is done by including a copper area of about 2 square inches on the opposite side of the PCB from the device. This copper area may be plated or solder coated to prevent corrosion but should not have conformal coating (if possible), which could provide thermal insulation. The vias shown in Figure 23 should connect these top and bottom copper layers and to the ground layer. These vias act as heat pipes to carry the thermal energy away from the device side of the board to where it can be more effectively dissipated. 24 Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated Product Folder Links: LMK00334-Q1 LMK00334-Q1 www.ti.com SNAS760 – APRIL 2018 12 Device and Documentation Support 12.1 Documentation Support 12.1.1 Related Documentation For related documents, see the following: • Absolute Maximum Ratings for Soldering (SNOA549) • Common Data Transmission Parameters and their Definitions (SNLA036) • "How to Optimize Clock Distribution in PCIe Applications" on the Texas Instruments E2E community forum • LMK00338EVM User's Guide (SNAU155) • Semiconductor and IC Package Thermal Metrics (SPRA953). 12.2 Receiving Notification of Documentation Updates To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper right corner, click on Alert me to register and receive a weekly digest of any product information that has changed. For change details, review the revision history included in any revised document. 12.3 Community Resources The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of Use. TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help solve problems with fellow engineers. Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and contact information for technical support. 12.4 Trademarks E2E is a trademark of Texas Instruments. All other trademarks are the property of their respective owners. 12.5 Electrostatic Discharge Caution This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications. 12.6 Glossary SLYZ022 — TI Glossary. This glossary lists and explains terms, acronyms, and definitions. 13 Mechanical, Packaging, and Orderable Information The following pages include mechanical, packaging, and orderable information. This information is the most current data available for the designated devices. This data is subject to change without notice and revision of this document. For browser-based versions of this data sheet, refer to the left-hand navigation. Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated Product Folder Links: LMK00334-Q1 25 PACKAGE OPTION ADDENDUM www.ti.com 10-Dec-2020 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan (2) Lead finish/ Ball material MSL Peak Temp Op Temp (°C) Device Marking (3) (4/5) (6) LMK00334RTVRQ1 ACTIVE WQFN RTV 32 1000 RoHS & Green SN Level-3-260C-168 HR -40 to 105 K00334Q LMK00334RTVTQ1 ACTIVE WQFN RTV 32 250 RoHS & Green SN Level-3-260C-168 HR -40 to 105 K00334Q (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of