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LMK00804B-Q1
SNAS784B – MARCH 2019 – REVISED AUGUST 2019
LMK00804B-Q1 1.5-V to 3.3-V, 1-to-4 High-Performance LVCMOS Fan-Out Buffer and
Level Translator
1 Features
2 Applications
•
•
1
•
•
•
•
•
AEC-Q100 qualified with the following results:
– Device temperature grade 1: –40°C to +125°C,
TA
Four LVCMOS/LVTTL outputs supporting 1.5-V to
3.3-V levels
– Additive jitter: 0.1-ps RMS (typical) at 40 MHz
– Noise floor: –168 dBc/Hz (typical) at 40 MHz
– Output frequency: 350 MHz (maximum)
– Output skew: 35 ps (maximum)
– Part-to-part skew: 550 ps (maximum)
Two selectable inputs
– CLK_P, CLK_N pair accepts LVPECL, LVDS,
HCSL, SSTL, LVHSTL, or LVCMOS/LVTTL
– LVCMOS_CLK accepts LVCMOS/LVTTL
Synchronous clock enable
Core/output power supplies:
– 3.3 V/3.3 V
– 3.3 V/2.5 V
– 3.3 V/1.8 V
– 3.3 V/1.5 V
Package: 16-pin VQFN
Advanced Driver Assistance Systems (ADAS)
– Forward-facing long range radar
– Medium/short range radar
– Ultra short range radar
3 Description
The LMK00804B-Q1 is a high-performance clock fanout buffer and level translator that can distribute up to
four LVCMOS/LVTTL outputs (3.3-V, 2.5-V, 1.8-V, or
1.5-V levels) from one of two selectable inputs that
can accept differential or single-ended inputs. The
clock enable input is synchronized internally to
eliminate runt or glitch pulses on the outputs when
the clock enable terminal is asserted or deasserted.
The outputs are held in logic low state when the clock
is disabled. The LMK00804B-Q1 can also distribute a
low-jitter clock across four transceivers and can
improve the overall target detection and resolution in
a cascaded mmWave radar system.
Device Information(1)
PART NUMBER
LMK00804B-Q1
PACKAGE
VQFN (16)
BODY SIZE (NOM)
3.00 mm × 3.00 mm
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
Simplified Schematic
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
LMK00804B-Q1
SNAS784B – MARCH 2019 – REVISED AUGUST 2019
www.ti.com
Table of Contents
1
2
3
4
5
6
7
8
Features ..................................................................
Applications ...........................................................
Description .............................................................
Revision History.....................................................
Pin Configuration and Functions .........................
Specifications.........................................................
1
1
1
2
3
4
6.1
6.2
6.3
6.4
6.5
6.6
6.7
6.8
6.9
6.10
4
4
4
5
5
6
6
7
7
8
Absolute Maximum Ratings ......................................
ESD Ratings..............................................................
Recommended Operating Conditions.......................
Thermal Information ..................................................
Power Supply Characteristics ...................................
LVCMOS / LVTTL DC Electrical Characteristics ......
Differential Input DC Electrical Characteristics .........
Switching Characteristics ..........................................
Pin Characteristics ....................................................
Typical Characteristics ............................................
Parameter Measurement Information .................. 9
Detailed Description ............................................ 10
8.1 Overview ................................................................. 10
8.2 Functional Block Diagram ....................................... 10
8.3 Feature Description................................................. 11
8.4 Device Functional Modes........................................ 11
9
Applications and Implementation ...................... 12
9.1 Application Information............................................ 12
9.2 Typical Applications ................................................ 12
9.3 Do's and Don'ts ....................................................... 16
10 Power Supply Recommendations ..................... 18
10.1 Power Supply Considerations............................... 18
11 Layout................................................................... 18
11.1 Layout Guidelines ................................................. 18
11.2 Layout Example .................................................... 19
12 Device and Documentation Support ................. 20
12.1
12.2
12.3
12.4
12.5
12.6
Documentation Support ........................................
Receiving Notification of Documentation Updates
Community Resources..........................................
Trademarks ...........................................................
Electrostatic Discharge Caution ............................
Glossary ................................................................
20
20
20
20
20
20
13 Mechanical, Packaging, and Orderable
Information ........................................................... 20
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision A (June 2019) to Revision B
Page
•
Changed part-to-part skew maximum from: 700 ps to: 550 ps ............................................................................................. 1
•
Changed front long range radar application to: forward-facing long range radar ................................................................. 1
•
Changed Simplified Schematic graphic.................................................................................................................................. 1
•
Changed pin 2 in the RGT package from: OE to: NC ........................................................................................................... 3
•
Changed the pin descriptions ................................................................................................................................................. 3
•
Changed Changed CDM ESD ratings from: +/-250 V to: +/-750 V........................................................................................ 4
•
Added the Typical Characteristics section back to the data sheet......................................................................................... 8
•
Changed Differential Input Level timing diagram .................................................................................................................. 9
•
Changed the Overview section ............................................................................................................................................ 10
•
Changed Functional Block Diagram ..................................................................................................................................... 10
•
Added the Typical Connection Diagram ............................................................................................................................... 12
•
Changed the Power Considerations section to Power Dissipation Calculations.................................................................. 16
•
Moved the Thermal Management section to Do's and Don'ts.............................................................................................. 16
•
Changed the recommendations for unused output pins ..................................................................................................... 17
•
Changed the Input Slew Rate Considerations section ......................................................................................................... 17
•
Added content to the Ground Planes section....................................................................................................................... 18
•
Changed the Layout Example section.................................................................................................................................. 19
Changes from Original (March 2019) to Revision A
•
2
Page
Changed data sheet status from Advanced Information to Production Data ........................................................................ 1
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SNAS784B – MARCH 2019 – REVISED AUGUST 2019
5 Pin Configuration and Functions
12
Q2
11
VDDO
10
Q3
Q0
VDDO
Q1
GND
15
14
13
9
8
4
LVCMOS_CLK
CLK_EN
Pad
7
3
CLK_SEL
VDD
Thermal
6
2
CLK_N
NC
5
1
CLK_P
GND
16
RGT Package
16-Pin VQFN
Top View
GND
Not to scale
Pin Functions (1)
PIN
NAME
NO.
TYPE (2)
DESCRIPTION
CLK_EN
4
I, PU
Synchronous clock enable input. CLK_EN must be held low until a valid
reference clock is provided. Typically connected to VDD with an external
1-kΩ pullup. When unused, leave floating.
0 = Outputs are forced to logic low state
1 = Outputs are enabled with LVCMOS/LVTTL levels
CLK_N
6
I, PD, PU
Inverting differential clock input with internal 51-kΩ (typ) pullup resistor to
VDD and internal 51-kΩ (typ) pulldown resistor to GND. Typically
connected to the inverting clock input. When unused, leave floating.
Internally biased to VDD/2 when left floating.
CLK_P
5
I, PD
Noninverting differential clock input with internal 51-kΩ (typ) pulldown
resistor to GND. Typically connected to the noninverting clock input. A
single-ended clock input can also be connected to CLK_P. When unused,
leave floating.
CLK_SEL
7
I, PU
Clock select input. Typically connected to VDD with an external 1-kΩ
pullup. When unused, leave floating.
0 = Select LVCMOS_CLK (pin 8)
1 = Select CLK_P, CLK_N (pins 5, 6)
1, 9, 13
G
LVCMOS_CLK
8
I, PD
NC
2
NC
Q0
16
Q1
14
Q2
12
Q3
10
GND
(1)
(2)
O
Power supply ground.
Single-ended clock input with internal 51-kΩ (typ) pulldown resistor to
GND. Typically connected to a single-ended clock input. When unused,
leave floating. Accepts LVCMOS/LVTTL levels.
No connect pin. Typically left floating. Do not connect to GND.
Single-ended clock outputs with LVCMOS/LVTTL levels at 7-Ω output
impedance. Typically connected to a receiver with a 43-Ω series
termination. When unused, leave floating.
See Recommendations for Unused Input and Output Pins, if applicable.
G = Ground, I = Input, O = Output, P = Power, PU = 51-kΩ pullup, PD = 51-kΩ pulldown. NC = No connect
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Pin Functions(1) (continued)
PIN
NAME
NO.
DESCRIPTION
3
P
Power supply terminal. Typically connected to a 3.3-V supply. The VDD
pin is typically connected GND with an external 0.1-uF capacitor.
11, 15
P
Output supply terminals. Typically connected to a 3.3-V, 2.5-V, 1.8-V, or
1.5-V supply. The VDDO pins are typically connected GND with external
0.1-uF capacitors.
VDD
VDDO
TYPE (2)
6 Specifications
6.1 Absolute Maximum Ratings (1) (2)
Over operating free-air temperature range (unless otherwise noted) (1)
MIN
MAX
UNIT
VDD
Supply input voltage
–0.3
3.6
V
VDDO
Supply output voltage
–0.3
3.6
V
V
Input voltage
CLK_EN, CLK_SEL, CLK_P, CLK_N, LVCMOS_CLK
–0.3
VDD
+ 0.3
Input voltage
Q0, Q1, Q2, Q3
–0.3
VDDO
+ 0.3
V
150
°C
150
°C
VI
TJ
Junction temperature
Tstg
Storage temperature
(1)
(2)
–65
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating
Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
If Military/Aerospace specified devices are required, contact the Texas Instruments Sales Office/Distributors for availability and
specifications.
6.2 ESD Ratings
VALUE
V(ESD)
(1)
Electrostatic discharge
Human-body model (HBM), per AEC Q100-002 (1)
HBM ESD Classification Level 2
±2000
Charged-device model (CDM), per AEC Q100-011
CDM ESD Classification Level C5
±750
UNIT
V
AEC Q100-002 indicates that HBM stressing shall be in accordance with the ANSI/ESDA/JEDEC JS-001 specification.
6.3 Recommended Operating Conditions
Over operating free-air temperature range (unless otherwise noted)
VDD
Supply input voltage
MIN
NOM
MAX
UNIT
3.135
3.3
3.465
V
3.135
3.3
3.465
2.375
2.5
2.625
1.71
1.8
1.89
1.425
1.5
1.575
VDDO
Supply output voltage
TA
Ambient temperature
–40
125
TJ
Junction temperature
–40
135
°C
fOUT
Maximum output frequency (1)
350
MHz
(1)
4
V
°C
There is no minimum input / output frequency provided the input slew rate is sufficiently fast. Refer to Input Slew Rate Considerations.
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6.4 Thermal Information
LMK00804B-Q1
THERMAL METRIC (1) (2)
RGT (VQFN)
UNIT
16 PINS
RθJA
Junction-to-ambient thermal resistance
48.0
°C/W
RθJC(top)
Junction-to-case (top) thermal resistance
58.6
°C/W
RθJB
Junction-to-board thermal resistance
22.6
°C/W
ψJT
Junction-to-top characterization parameter
2.1
°C/W
ψJB
Junction-to-board characterization parameter
22.6
°C/W
RθJC(bot)
Junction-to-case (bottom) thermal resistance
6.5
°C/W
(1)
(2)
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report (SPRA953).
The package thermal impedance is calculated in accordance with JESD 51 and JEDEC2S2P (high-K board).
6.5 Power Supply Characteristics
Over recommended operating supply and temperature ranges unless otherwise specified.
PARAMETER
IDD
Power supply current through VDD
IDDO
Power supply current through VDDO
MIN
TYP
MAX
UNIT
21
mA
5
mA
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6.6 LVCMOS / LVTTL DC Electrical Characteristics
VDD = 3.3 V ± 5%, VDDO = 1.5 V ± 5%, 1.8 V ± 5%, 2.5 V ± 5%, 3.3 V ± 5% and TA = –40°C to 125°C
PARAMETER
VIH
VIL
IIH
IIL
TEST CONDITIONS
Input high voltage
Input low voltage
Input high current
Input low current
MAX
UNIT
2
VDD +
0.3
V
2
VDD +
0.3
V
CLK_EN,
CLK_SEL
–0.3
0.8
LVCMOS_CLK
–0.3
1.3
CLK_EN,
CLK_SEL
LVCMOS_CLK
CLK_EN,
CLK_SEL
VIH = VDD
LVCMOS_CLK
VDD = 3.465 V,
VIN = 3.465 V
CLK_EN,
CLK_SEL
VIL = GND
–150
LVCMOS_CLK
VDD = 3.465 V,
VIN = 0 V
–150
VDDO = 3.3 V ± 5%
VOH
Output high voltage (1)
MIN
TYP
15
µA
150
µA
2.64
VDDO = 2.5 V ± 5%
2
VDDO = 1.8 V ± 5%
1.44
VDDO = 1.5 V ± 5%
1.2
V
VDDO = 3.3 V ± 5%
VOL
Output low voltage (1)
IOZL
Output Hi-Z current low
IOZH
Output Hi-Z current high
0.66
VDDO = 2.5 V ± 5%
0.5
VDDO = 1.8 V ± 5%
0.36
VDDO = 1.5 V ± 5%
(1)
V
V
0.3
–5
5
µA
Outputs terminated with 50 Ω to VDDO/2.
6.7 Differential Input DC Electrical Characteristics
VDD = 3.3 V ± 5%, VDDO = 1.5 V ± 5%, 1.8 V ± 5%, 2.5 V ± 5%, 3.3 V ± 5% and TA = –40°C to 125°C
PARAMETER
VID
TEST CONDITIONS
Differential input voltage swing, (VIH – VIL) (1)
(1) (2)
VIC
Input common-mode voltage
IIH
Input high current (3)
CLK_N, CLK_P
VDD = 3.465 V,
VIN = 3.465 V
IIL
Input low current (3)
CLK_N, CLK_P
VDD = 3.465 V ,
VIN = 0 V
(1)
(2)
(3)
6
MIN
TYP
MAX
UNIT
0.15
1.4
V
0.5
VDD –
0.85
V
150
µA
–150
µA
VIL should not be less than –0.3 V.
Input common-mode voltage is defined as VIH.
For IIH and IIL measurements on CLK_Por CLK_N, one must comply with VID and VIC specifications by using the appropriate bias on
CLK_N or CLK.
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6.8 Switching Characteristics
VDD = 3.3 V ± 5%, VDDO = 1.5 V ± 5%, 1.8 V ± 5%, 2.5 V ± 5%, 3.3 V ± 5% and TA = –40°C to 125°C
PARAMETER
TEST CONDITIONS
tPDLH
Propagation delay,
Low-to-high
LVCMOS_CLK (1),
CLK_P/CLK_N (2)
tSK(O)
Output skew (3) (4)
Measured on rising edge
tSK(PP)
Part-to-part skew (4) (5)
tR/tF
Output rise/fall time
20% to 80%, CL= 5 pF
Additive jitter (6)
f = 40 MHz,
Input slew rate = 1.25 V/ns,
12-kHz to 20-MHz integration band
tJIT
PNFLOOR
DO
(1)
(2)
(3)
(4)
(5)
(6)
(7)
f = 40 MHz,
Input slew rate = 1.25
V/ns
Phase noise floor (7)
Output duty cycle
MIN
–40°C to 125°C
TYP
MAX
1
100
UNIT
2.5
ns
35
ps
550
ps
310
600
ps
115
200
fs RMS
10-kHz offset
–151
100-kHz offset
–160
1-MHz offset
–162
10-MHz offset
–162
20-MHz offset
–162
dBc/Hz
REF = CLK_P/CLK_N, 50% input duty cycle, f <
166 MHz
45%
55%
REF = LVCMOS_CLK, 50% input duty cycle, f >
166 MHz
42%
58%
Measured from the VDD/2 of the input to the VDDO/2 of the output.
Measured from the differential input crossing point to VDDO/2 of the output.
Defined as skew between outputs at the same supply voltage and with equal loading conditions. Measured at VDDO/2 of the output.
Parameter is defined in accordance with JEDEC Standard 65.
Calculation for part-to-part skew is the difference between the fastest and slowest tPD across multiple devices, various supply voltages,
operating at the same frequency, same temperature, with equal load conditions, and using the same type of inputs on each device.
Buffer additive jitter: tJIT = SQRT(tJIT_SYS2 – tJIT_SOURCE2), where t JIT_SYS is the RMS jitter of the system output (source+buffer) and
tJIT_SOURCE is the RMS jitter of the input source, and system output noise is not correlated to the input source noise. Additive jitter
should be considered only when the input source noise floor is 3 dB or better than the buffer noise floor (PNFLOOR). This is usually the
case for high-quality, ultra-low-noise oscillators. Refer to System-Level Phase Noise and Additive Jitter Measurement for input source
and measurement details.
Buffer phase noise floor: PNFLOOR (dBc/Hz) = 10 × log10[10^(PNSYSTEM/10) – 10^(PNSOURCE/10)], where PNSYSTEM is the phase noise
floor of the system output (source+buffer) and PNSOURCE is the phase noise floor of the input source. Buffer Phase Noise Floor should
be considered only when the input source noise floor is 3 dB or better than the buffer noise floor (PNFLOOR). This is usually the case for
high-quality, ultra-low-noise oscillators. Refer to System-Level Phase Noise and Additive Jitter Measurement for input source and
measurement details.
6.9 Pin Characteristics
MIN
CI
Input capacitance
RPU
TYP
MAX
UNIT
1
pF
Input pullup resistance
51
kΩ
RPD
Input pulldown resistance
51
kΩ
CPD
Power dissipation capacitance (per output)
2
pF
ROUT
Output impedance
7
Ω
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6.10 Typical Characteristics
ICCO vs. Temperature
Propagation Delay vs. Temeprature
80
2.1
75
2.05
70
2
65
60
55
1.9
50
ICCO (mA)
Propagation Delay (ns)
1.95
1.85
1.8
45
40
35
30
1.75
25
1.7
20
1.65
15
VCCO = 3.3V
VCCO = 2.5V
VCCO = 1.8V
VCCO = 1.5V
1.6
1.55
-40
-20
0
20
40
60
Temperature (°C)
80
100
VCCO = 3.3V
VCCO = 2.5V
VCCO = 1.8V
VCCO = 1.5V
10
5
0
-40
120
-20
0
D001
Figure 1. Propagation Delay vs. Temperature and Supply
Voltage
20
40
60
Temperature (°C)
80
100
120
D002
Figure 2. ICCO vs. Temperature and Supply Voltage
ICC vs. Temperature
Additive Jitter vs. Temperature
18.6
140
VCCO = 3.3V
VCCO = 2.5V
VCCO = 1.8V
VCCO = 1.5V
18.55
130
18.5
120
RJadd (fsRMS)
ICC (mA)
18.45
18.4
18.35
110
100
18.3
90
18.25
18.15
-40
-20
0
20
40
60
Temperature (°C)
80
100
120
70
-40
-20
D003
Figure 3. ICC vs. Temperature and Supply Voltage
8
VCCO = 3.3V
VCCO = 2.5V
VCCO = 1.8V
VCCO = 1.5V
80
18.2
0
20
40
60
Temperature (°C)
80
100
120
D004
Figure 4. Additive Jitter vs. Temperature and Supply Voltage
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7 Parameter Measurement Information
NOTE: VCM = VIC – VID/2 = (V IH + VIL)/2
Figure 5. Differential Input Level
space
VOH
80%
VOUT
20%
VOL
Q
tR
tF
Figure 6. Output Voltage, and Rise and Fall Times
space
LVCMOS
Input
LVCMOS_CLK
CLK_N
CLK_P
Differential
Input
tPD
LVCMOS
Outputx
Qx
tSK
LVCMOS
Outputy
Qy
Figure 7. Output Skew and Propagation Delay
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8 Detailed Description
8.1 Overview
The LMK00804B-Q1 is a clock fan-out buffer with two selectable clock inputs and four LVCMOS outputs. The
LVCMOS_CLK input accepts a single-ended clock input, and the CLK_P/CLK_N input accepts a differential or
single-ended clock input. The LMK00804B-Q1 has a synchronous clock enable feature that allows the device to
synchronously enable or disable the outputs using the CLK_EN pin.
8.2 Functional Block Diagram
10
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8.3 Feature Description
8.3.1 Clock Enable Timing
After CLK_EN switches, the clock outputs are disabled or enabled following a rising and falling input clock edge as shown in
Figure 8.
LVCMOS_CLK
CLK_N
CLK_P
Disabled
CLK_EN
Enabled
Qx
Figure 8. Clock Enable Timing Diagram
8.4 Device Functional Modes
The device can provide fan-out and level translation from a differential or single-ended input to a
LVCMOS/LVTTL output where the output VOH and VOL levels are applied to the VDDO pin and output load
condition.
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9 Applications and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
9.1 Application Information
The LMK00804B-Q1 enables the distribution of up to four LVCMOS copies of a low-noise source designed for
general-purpose and high-performance applications. For best jitter performance, TI recommends to use the
appropriate matching networks for the clock driver and receiver format, as detailed in the Typical Applications
section. Practice good high-speed layout design outlined in the High-speed Layout Guidelines application report
(SCAA082).
The LMK00804B-Q1 is designed to drive 50-Ω controlled-impedance traces. TI recommends to design these
clock traces as 50-Ω, single-ended controlled impedance traces. Use a series 43-Ω resistor at the clock outputs
Q[3:0] to match the driver impedance and series resistance to the trace impedance.
9.2 Typical Applications
Refer to the following sections for output clock and input clock interface circuits.
10µF
10µF
1µF
1µF
VDDO [11]
[16] Q0
VDDO [15]
[14] Q1
0.1µF
0.1µF
VDD [3]
10µF
1µF
43O
[12] Q2
0.1µF
[10] Q3
43O
43O
LVCMOS
Clock Outputs
43O
CLK_P [5]
Differential
Clock Input
100O
CLK_N [6]
Single-Ended
Clock Input
LVCMOS_CLK [8]
NC [2]
CLK_EN [4]
CLK_SEL [7]
[1] GND
[9] GND
[13] GND
[17] GND
Figure 9. Typical Connection Diagram
12
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Typical Applications (continued)
9.2.1 Output Clock Interface Circuit
VDDO
RS= 43Ÿ
LVCMOS
Input
Zo = 50Ÿ
LMK00804
Parasitic Input Capacitance
Figure 10. LVCMOS Output Configuration
9.2.1.1 Design Requirements
For high-performance devices, limitations of the equipment can affect phase-noise measurements. The noise
floor of the equipment is often higher than the noise floor of the device. The real noise floor of the device is
probably lower. It is important to understand that system-level phase noise measured at the DUT output is
influenced by the input source and the measurement equipment.
For Figure 11 and system-level phase noise plots, a Rohde & Schwarz SMA100A low-noise signal generator was
cascaded with an Agilent 70429A K95 single-ended-to-differential converter block with ultra-low phase noise and
fast-edge slew rate (>3 V/ns) to provide a low-noise clock input source to the LMK00804B-Q1. An Agilent E5052
source signal analyzer with an ultra-low measurement noise floor was used to measure the phase noise of the
input source (SMA100A + 70429A K95) and system output (input source + LMK00804B-Q1). The light blue trace
shows the input source phase noise, and the dark blue trace in Figure 11 shows the system output phase noise.
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Typical Applications (continued)
9.2.1.2 Detailed Design Procedure
Use Equation 1 to calculate the additive phase noise or noise floor of the buffer (PNFLOOR):
PNFLOOR (dBc/Hz) = 10 × log10[10^(PNSYSTEM/10) – 10^(PNSOURCE/10)]
where
•
•
PNSYSTEM is the phase noise of the system output (source+buffer)
PNSOURCE is the phase noise of the input source
(1)
Use Equation 2 to calculate the additive jitter of the buffer (tJIT):
tJIT = SQRT(tJIT_SYS2 – tJIT_SOURCE2)
where:
•
•
tJIT_SYS is the RMS jitter of the system output (source+buffer), integrated from 10 kHz to 20 MHz
tJIT_SOURCE is the RMS jitter of the input source, integrated from 10 kHz to 20 MHz
(2)
9.2.1.3 Application Curve
9.2.1.3.1 System-Level Phase Noise and Additive Jitter Measurement
Figure 11. 40-MHz Input Phase Noise (181 fs rms, Light Blue),
and Output Phase Noise (196 fs rms, Dark Blue),
Additive Jitter = 77 fs rms
14
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Typical Applications (continued)
9.2.2 Input Detail
LMK00804
LVCMOS_CLK
51k
CLK_P
51k
VDD
51k
CLK_N
51k
Figure 12. Clock Input Components
9.2.3 Input Clock Interface Circuits
3.3 V
3.3V
LMK00804B
Rs
LVMOS
_CLK
Zo = 50Ω
Zo
Clock generator:
Zo + Rs = 50Ω
Figure 13. LVCMOS_CLK Input Configuration
3.3V
3.3V
3.3V
3.3V
LMK00804B
R = 100Ω
R = 1kΩ
Rs
CLK_P
DUT
CLK_N
Z o = 50Ω
Zo
R = 100Ω
C = 0.1µF
R = 1kΩ
Clock generator:
Z o + R s = 50Ω
(1)
The Thevenin/split termination values (R = 100 Ω) at the CLK_P input may be adjusted to provide a small differential
offset voltage (50 mV, for example) between the CLK_P and CLK_N inputs to prevent input chatter if the LVCMOS
driver in a tri-state condition. For example, the engineer can use 105 Ω 1% to the 3.3-V rail and 97.6 Ω 1% to GND to
receive a –60-mV offset voltage (VCLK_N – VCLK_P) . Ensure a logic low state if the LVCMOS driver enters a tri-state
condition.
Figure 14. Single-Ended/LVCMOS Input DC Configuration
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9.3 Do's and Don'ts
9.3.1 Power Dissipation Calculations
The following power considerations refer to the device-consumed power consumption only. The device power
consumption is the sum of static and dynamic power. The dynamic power usage consists of two components:
• Power used by the device as it switches states
• Power required to charge any output load
The output load can be capacitive-only or capacitive and resistive. Use Equation 3 through Equation 5 to
calculate the power consumption of the device:
PDev = Pstat + Pdyn + PCload
Pstat = (IDD × VDD) + (IDDO × VDDO)
Pdyn + PCload = (IDDO,dyn + IDDO,Cload) × VDDO
(3)
(4)
where:
•
•
IDDO,dyn = CPD × VDDO × f × n [mA]
IDDO,Cload = Cload × VDDO × f × n [mA]
(5)
Example for power consumption of the LMK00804B-Q1: 4 outputs are switching, f = 100 MHz,
VDD = VDDO = 3.465 V and assuming Cload = 5 pF per output:
PDev = 90 mW + 34 mW = 124 mW
Pstat = (21 mA × 3.465 V) + (5 mA × 3.465 V) = 90 mW
Pdyn + PCload = (2.8 mA + 6.9 mA) × 3.465 V = 34 mW
IDD,dyn = 2 pF × 3.465 V × 100 MHz × 4 = 2.8 mA
IDD,Cload = 5 pF × 3.465 V × 100 MHz × 4 = 6.9 mA
(6)
(7)
(8)
(9)
(10)
NOTE
For dimensioning the power supply, consider the total power consumption. The total
power consumption is the sum of device power consumption and the power consumption
of the load.
9.3.2 Thermal Management
For reliability and performance reasons, limit the die temperature to a maximum of 125°C. That is, as an
estimate, TA (ambient temperature) plus device power consumption times RθJA should not exceed 125°C.
Assuming the conditions in the Power Dissipation Calculations section and operating at an ambient temperature
of 70°C with all outputs loaded, Equation 11 shows the estimate of the LMK00804B-Q1 junction temperature:
TJ = TA + PTotal × RθJA = 70°C + (124 mW × 48°C/W) = 70°C + 6.0°C = 76.0°C
(11)
Here are some recommendations to improve heat flow away from the die:
• Use multi-layer boards
• Specify a higher copper thickness for the board
• Increase the number of vias from the top level ground plane under and around the device to internal layers
and to the bottom layer with as much copper area flow on each level as possible
• Apply air flow
• Leave unused outputs floating
16
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Do's and Don'ts (continued)
9.3.3 Recommendations for Unused Input and Output Pins
• CLK_SEL and CLK_EN: CLK_EN must be held low until a valid reference clock is provided before the
engineer can use the pin to enable the outputs. These inputs both have an internal pullup (PU) according to
Table 1. Table 1 shows the default floating state of these inputs:
Table 1. Input Floating Default States
INPUT
•
•
•
FLOATING STATE SELECTION
CLK_SEL
CLK_P/CLK_N selected
CLK_EN
Synchronous outputs enable
CLK_P/CLK_N Inputs: See Figure 12 for the internal connections. When using a single-ended input, take
note of the internal pullup and pulldown to make sure the unused input is properly biased. To interface a
single-ended input to the CLK_P/CLK_N input, the configuration shown in Figure 14 is recommended.
LVCMOS_CLK Input: See Figure 12 for the internal connection. The internal pulldown (PD) resistor ensures
a low state when this input is left floating.
Outputs: Any unused output may be left floating.
9.3.4 Input Slew Rate Considerations
LMK00804B-Q1 employs high-speed and low-latency circuit topology to allow ultra-low additive jitter/phase noise
and high-frequency operation. To take advantage of these benefits in the system application, it is optimal for the
input signal to have a high slew rate of 3 V/ns or greater. Driving the input with a slower slew rate can degrade
the additive jitter and noise floor performance. For this reason, a differential signal input is recommended over a
single-ended signal, because a differential signal typically provides a higher slew rate and common-moderejection.
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10 Power Supply Recommendations
10.1 Power Supply Considerations
While there is no strict power supply sequencing requirement, it is generally best practice to sequence the supply
input voltage (VDD) before the supply output voltage (VDDO).
10.1.1 Power-Supply Filtering
High-performance clock buffers are sensitive to noise on the power supply, which can dramatically increase the
additive jitter of the buffer. Thus, it is essential to reduce noise from the system power supply, especially when
jitter or phase noise is critical to applications.
The use of bypass capacitors eliminates the low-frequency noise from power supply, because they can provide a
very low-impedance path for high-frequency noise and guard the power-supply system against induced
fluctuations. The bypass capacitors also provide instantaneous current surges as required by the device, and
should have low ESR. To use the bypass capacitors properly, place them close to the power supply terminals
and lay out traces with short loops to minimize inductance. TI recommends that the engineer add as many highfrequency (for example, 0.1-µF) bypass capacitors as there are supply terminals in the package. TI recommends
that the engineer insert a ferrite bead between the board power supply and the chip power supply to isolate the
high-frequency switching noises generated by the clock driver. This would prevent leakage into the board supply.
It is important to choose an appropriate ferrite bead with low DC resistance, because the bead must provide
adequate isolation between the board supply and the chip supply. It is also important to maintain a voltage at the
supply terminals that is greater than the minimum voltage required for proper operation.
Figure 15. Power-Supply Decoupling
11 Layout
11.1 Layout Guidelines
11.1.1 Ground Planes
Solid ground planes are recommended because these planes provide a low-impedance return paths between the
device and bypass capacitors, along with the clock source and destination devices.
LMK00804B-Q1 has a die attach pad (DAP) for enhanced thermal and electrical performance. Use five VIAs to
connect the DAP to a solid GND plane. Full-through VIAs are preferred.
Avoid return paths of other system circuitry (for example, high-speed/digital logic, switching power supplies, and
so forth) from passing through the local ground of the device to minimize noise coupling. Remember that noise
coupling can lead to added jitter and spurious noise.
11.1.2 Power Supply Pins
Follow the power supply schematic and layout example described in Power-Supply Filtering.
18
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Layout Guidelines (continued)
11.1.3 Differential Input Termination
• Place input termination or biasing resistors as close to the CLK_P/CLK_N pins as possible.
• Avoid or minimize vias in the 50-Ω input traces to minimize impedance discontinuities. Intra-pair skew should
also be minimized on the differential input traces.
• If not used, CLK_P/CLK_N inputs may be left as no connect.
11.1.4 LVCMOS Input Termination
• Input termination is not necessary when the LVCMOS_CLK input is driven from a LVCMOS driver that is
series-terminated to match the characteristic impedance of the trace. Otherwise, place the input termination
resistor as close to the LVCMOS_CLK input as possible.
• Avoid or minimize vias in the 50-Ω input trace to minimize impedance discontinuities.
• If not used, LVCMOS_CLK input may be left as no connect.
11.1.5 Output Termination
• Place 43-Ω series termination resistors close to the Qx outputs at the launch of the 50-Ω traces.
• Avoid or minimize vias in the 50-Ω input traces to minimize impedance discontinuities.
• If not used, any Qx output should be left as no connect.
11.2 Layout Example
Figure 16 shows the recommended PCB design for good electrical and thermal performance. To maximize the
heat dissipation from the package, a thermal landing pattern including multiple vias to a ground plane must be
incorporated into the PCB within the footprint of the package. The thermal pad must be soldered down to ensure
adequate heat conduction to of the package. Refer to the Example Board Layout in the Package Option
Addendum.
Figure 16. General PCB Ground Layout for Thermal Reliability
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12 Device and Documentation Support
12.1 Documentation Support
12.1.1 Related Documentation
For related documentation, see the following:
High-Speed Layout Guidelines (SCAA082)
12.2 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper
right corner, click on Alert me to register and receive a weekly digest of any product information that has
changed. For change details, review the revision history included in any revised document.
12.3 Community Resources
The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.
12.4 Trademarks
E2E is a trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
12.5 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
12.6 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
13 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
20
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PACKAGE OPTION ADDENDUM
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10-Dec-2020
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
(4/5)
(6)
LMK00804BQWRGTRQ1
ACTIVE
VQFN
RGT
16
3000
RoHS & Green
SN
Level-2-260C-1 YEAR
-40 to 125
804BQ
LMK00804BQWRGTTQ1
ACTIVE
VQFN
RGT
16
250
RoHS & Green
SN
Level-2-260C-1 YEAR
-40 to 125
804BQ
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of
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