LMK04832NKDR

Product Folder Order Now Support & Community Tools & Software Technical Documents LMK04832 SNAS688C – FEBRURAY 2017 – REVISED MAY 2018 LMK04832 Ultra Low-Noise JESD204B Compliant Clock Jitter Cleaner With Dual Loop PLLs 1 Features 3 Description • • The LMK04832 is an ultra-high performance clock conditioner with JEDEC JESD204B support and is also pin compatible with the LMK0482x family of devices. 1 • • • • • • • • • • • • Maximum Clock Output Frequency: 3255 MHz Multi-Mode: Dual PLL, Single PLL, and Clock Distribution Ultra-Low Noise, at 2500 MHz: – 54 fs RMS Jitter (12 kHz to 20 MHz) – 64 fs RMS Jitter (100 Hz to 20 MHz) – –157.6 dBc/Hz Noise Floor Ultra-Low Noise, at 3200 MHz: – 61 fs RMS Jitter (12 kHz to 20 MHz) – 67 fs RMS Jitter (100 Hz to 100 MHz) – –156.5 dBc/Hz Noise Floor PLL2 – PLL FOM of –230 dBc/Hz – PLL 1/f of –128 dBc/Hz – Phase Detector Rate up to 320 MHz – Two Integrated VCOs: 2440 to 2580 MHz and 2945 to 3255 MHz Up to 14 Differential Device Clocks – CML, LVPECL, LCPECL, HSDS, LVDS, and 2xLVCMOS Programmable Outputs Up to 1 Buffered VCXO/XO Output – LVPECL, LVDS, 2xLVCMOS Programmable 1-1023 CLKout Divider 1-8191 SYSREF Divider 25-ps Step Analog Delay for SYSREF Clocks Digital Delay and Dynamic Digital Delay for Device Clock and SYSREF Holdover Mode With PLL1 0-Delay with PLL1 or PLL2 Supports 105°C PCB Temperature (Measured at Thermal Pad) The 14 clock outputs from PLL2 can be configured to drive seven JESD204B converters or other logic devices using device and SYSREF clocks. SYSREF can be provided using both DC and AC coupling. Not limited to JESD204B applications, each of the 14 outputs can be individually configured as high performance outputs for traditional clocking systems. The LMK04832 can be configured for operation in dual PLL, single PLL, or clock distribution modes with or without SYSREF generation or reclocking. PLL2 may operate with either internal or external VCO. The high performance combined with features like the ability to trade off between power and performance, dual VCOs, dynamic digital delay, and holdover make the LMK04832 ideal for providing flexible high performance clocking trees. Device Information(1) PART NUMBER LMK04832NKDT LMK04832NKDR WQFN (64) • • • • Test and Measurement RADAR Microwave Backhaul Data Converter Clocking BODY SIZE (NOM) 9.00 mm × 9.00 mm (1) For all available packages, see the orderable addendum at the end of the data sheet. (2) T = Tape; R = Reel Simplified Schematic CLKout10 VCXO Recovered ³GLUW\´ FORFN RU clean clock LMX2594 CLKout11 PLL+VCO CLKin0 Backup Reference Clock CLKin1 CLKout0 & CLKout2 2 Applications DESCRIPTION ADC CLKout1 & CLKout3 0XOWLSOH ³FOHDQ´ clocks at different frequencies OSCout CLKout8 CLKout9 LMK04832 FPGA CLKout4 & CLKout6 CLKout5 & CLKout7 CLKout12, CLKout13 DAC DAC Serializer/ Deserializer Copyright © 2017, Texas Instruments Incorporated 1 An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. PRODUCTION DATA. LMK04832 SNAS688C – FEBRURAY 2017 – REVISED MAY 2018 www.ti.com Table of Contents 1 2 3 4 5 6 Features .................................................................. Applications ........................................................... Description ............................................................. Revision History..................................................... Pin Configuration and Functions ......................... Specifications......................................................... 6.1 6.2 6.3 6.4 6.5 6.6 6.7 6.8 7 1 1 1 2 3 5 Absolute Maximum Ratings ...................................... 5 ESD Ratings.............................................................. 5 Recommended Operating Conditions....................... 6 Thermal Information .................................................. 6 Electrical Characteristics........................................... 6 Timing Requirements .............................................. 17 Timing Diagram....................................................... 17 Typical Characteristics – Clock Output AC Characteristics ......................................................... 18 Parameter Measurement Information ................ 20 7.1 Charge Pump Current Specification Definitions...... 20 7.2 Differential Voltage Measurement Terminology ..... 21 8 Detailed Description ............................................ 22 8.1 Overview ................................................................. 22 8.2 Functional Block Diagram ....................................... 26 8.3 8.4 8.5 8.6 9 Feature Description................................................. Device Functional Modes........................................ Programming........................................................... Register Maps ........................................................ 29 41 44 45 Application and Implementation ........................ 90 9.1 Application Information............................................ 90 9.2 Typical Application .................................................. 93 9.3 Do's and Don'ts ....................................................... 97 10 Power Supply Recommendations ..................... 97 10.1 Current Consumption ............................................ 97 11 Layout................................................................... 98 11.1 Layout Guidelines ................................................. 98 11.2 Layout Example .................................................... 98 12 Device and Documentation Support ............... 100 12.1 12.2 12.3 12.4 12.5 Device Support .................................................. Community Resources........................................ Trademarks ......................................................... Electrostatic Discharge Caution .......................... Glossary .............................................................. 100 100 100 100 100 13 Mechanical, Packaging, and Orderable Information ......................................................... 100 4 Revision History NOTE: Page numbers for previous revisions may differ from page numbers in the current version. Changes from Revision B (January 2018) to Revision C • Page Changed device status from ADVANCED INFORMATION to PRODUCTION DATA ........................................................... 1 Changes from Revision A (August 2017) to Revision B Page • Updated features: Jitter, Noise Floor, PLL Performance, and VCO Range ........................................................................... 1 • Updated the Electrical Characteristics table .......................................................................................................................... 5 • Updated the Detailed Description section ........................................................................................................................... 22 Changes from Original (February 2017) to Revision A • 2 Page Changed device status from PRODUCT PREVIEW to ADVANCED INFORMATION ........................................................... 1 Submit Documentation Feedback Copyright © 2017–2018, Texas Instruments Incorporated Product Folder Links: LMK04832 LMK04832 www.ti.com SNAS688C – FEBRURAY 2017 – REVISED MAY 2018 5 Pin Configuration and Functions NKD Package 64-Pin WQFN Top View CLKin_SEL1 CLKout11* CLKout11 CLKout10* CLKout10 Vcc11_CG3 CLKout8* CLKout8 CLKout9* CLKout9 57 56 55 54 53 52 51 50 49 CLKout13 60 CLKin_SEL0 CLKout13* 61 58 CLKout12 62 59 Vcc12_CG0 CLKout12* 63 Clock Group 3 64 Clock Group 0 CLKout0 1 48 Status_LD2 CLKout0* 2 47 Vcc10_PLL2 CLKout1 3 46 CPout2 CLKout1* 4 45 Vcc9_CP2 RESET/GPO 5 44 OSCin* SYNC/SYSREF_REQ 6 43 OSCin NC 7 42 Vcc8_OSCin NC 8 41 OSCout*/CLKin2* LLP-64 Top down view NC 9 40 OSCout/CLKin2 Vcc1_VCO 10 39 Vcc7_OSCout LDObyp1 11 38 CLKin0* LDObyp2 12 37 CLKin0 CLKout3 13 36 Vcc6_PLL1 CLKout3* 14 35 CLKin1*/Fin*/FBCLKin* CLKout2 15 34 CLKin1/Fin/FBCLKin CLKout2* 16 33 Vcc5_DIG 26 27 28 29 30 31 32 Vcc4_CG2 CLKout6 CLKout6* CLKout7 CLKout7* Status_LD1 CPout1 23 CLKout5* 25 22 CLKout5 24 21 Vcc3_SYSREF CLKout4 20 Clock Group 1 CLKout4* 19 SCK 18 CS* SDIO 17 Vcc2_CG1 DAP Clock Group 2 Pin Functions PIN NO. NAME 1 CLKout0 2 CLKout0* DESCRIPTION (1) I/O TYPE O Programmable Clock output 0. For JESD204B systems suggest Device Clock. Programmable formats: CML, LVPECL, LCPECL, or LVDS. O Programmable Clock output 1. For JESD204B systems suggest SYSREF Clock. Programmable formats: CML, LVPECL, LCPECL, LVDS, or 2xLVCMOS. 3 CLKout1 4 CLKout1* 5 RESET/GPO I CMOS Device reset input or GPO 6 SYNC/SYSREF_ REQ I CMOS Synchronization input or SYSREF_REQ for requesting continuous SYSREF. NC — — 7 8 Do not connect. 9 10 Vcc1_VCO PWR Power supply for VCO and clock distribution. 11 LDObyp1 ANLG LDO Bypass, bypassed to ground with 10-µF capacitor. 12 LDObyp2 ANLG LDO Bypass, bypassed to ground with a 0.1-µF capacitor. 13 CLKout3 14 CLKout3* (1) O Programmable Clock output 3. For JESD204B systems suggest SYSREF Clock. Programmable formats: CML, LVPECL, LCPECL, LVDS, or 2xLVCMOS. See Pin Connection Recommendations for recommended connections. Submit Documentation Feedback Copyright © 2017–2018, Texas Instruments Incorporated Product Folder Links: LMK04832 3 LMK04832 SNAS688C – FEBRURAY 2017 – REVISED MAY 2018 www.ti.com Pin Functions (continued) PIN NO. NAME 15 CLKout2 16 CLKout2* 17 Vcc2_CG1 I/O TYPE O Programmable PWR DESCRIPTION (1) Clock output 2. For JESD204B systems suggest Device Clock. Programmable formats: CML, LVPECL, LCPECL, or LVDS. Power supply for clock outputs 2 and 3. 18 CS* I CMOS Chip Select 19 SCK I CMOS SPI Clock 20 SDIO I/O CMOS SPI Data 21 Vcc3_SYSREF 22 CLKout5 23 CLKout5* 24 CLKout4 25 CLKout4* 26 Vcc4_CG2 27 CLKout6 28 CLKout6* PWR Power supply for SYSREF divider and SYNC. O Programmable Clock output 5. For JESD204B systems suggest SYSREF Clock. Programmable formats: CML, LVPECL, LCPECL, LVDS, or 2xLVCMOS. O Programmable Clock output 4. For JESD204B systems suggest Device Clock. Programmable formats: CML, LVPECL, LCPECL, or LVDS. PWR Power supply for clock outputs 4, 5, 6 and 7. O Programmable Clock output 6. For JESD204B systems suggest Device Clock. Programmable formats: CML, LVPECL, LCPECL, or LVDS. O Programmable Clock output 7. For JESD204B systems suggest SYSREF Clock. Programmable formats: CML, LVPECL, LCPECL, LVDS, or 2xLVCMOS. Programmable status pin. 29 CLKout7 30 CLKout7* 31 Status_LD1 I/O Programmable 32 CPout1 O ANLG Charge pump 1 output. 33 Vcc5_DIG PWR Power supply for the digital circuitry. CLKin1 34 FBCLKin Reference Clock Input Port 1 for PLL1. I ANLG Fin1 External VCO Input or clock distribution input. CLKin1* 35 FBCLKin* Reference Clock Input Port 1 for PLL1. I ANLG Fin1* 36 CLKin0 38 CLKin0* 39 Vcc7_OSCout 40 41 OSCout CLKin2 OSCout* CLKin2* 42 Vcc8_OSCin 43 OSCin 44 OSCin* 45 Vcc9_CP2 46 CPout2 47 Vcc10_PLL2 48 Status_LD2 49 CLKout9 50 CLKout9* 51 CLKout8 52 CLKout8* 53 Vcc11_CG3 4 Feedback input for external clock feedback input (0–delay mode). External VCO Input or clock distribution input. Vcc6_PLL1 37 Feedback input for external clock feedback input (0–delay mode). I PWR Power supply for PLL1, charge pump 1, holdover DAC ANLG Reference Clock Input Port 0 for PLL1. PWR Power supply for OSCout port. I/O Programmable I/O Programmable Buffered output of OSCin port. Reference Clock Input Port 2 for PLL1. Buffered output of OSCin port. Reference Clock Input Port 2 for PLL1. PWR Power supply for OSCin I ANLG Feedback to PLL1 and reference input to PLL2. AC-coupled. PWR Power supply for PLL2 Charge Pump. O ANLG Charge pump 2 output. PWR Power supply for PLL2. I/O Programmable Programmable status pin. O Programmable Clock output 9. For JESD204B systems suggest SYSREF Clock. Programmable formats: CML, LVPECL, LCPECL, LVDS, or 2xLVCMOS. O Programmable Clock output 8. For JESD204B systems suggest Device Clock. Programmable formats: CML, LVPECL, LCPECL, LVDS, or 2xLVCMOS. PWR Power supply for clock outputs 8, 9, 10, and 11. Submit Documentation Feedback Copyright © 2017–2018, Texas Instruments Incorporated Product Folder Links: LMK04832 LMK04832 www.ti.com SNAS688C – FEBRURAY 2017 – REVISED MAY 2018 Pin Functions (continued) PIN NO. NAME DESCRIPTION (1) I/O TYPE O Programmable Clock output 10. For JESD204B systems suggest Device Clock. Programmable formats: CML, LVPECL, LCPECL, LVDS, or 2xLVCMOS. O Programmable Clock output 11. For JESD204B systems suggest SYSREF Clock. Programmable formats: CML, LVPECL, LCPECL, LVDS, or 2xLVCMOS. 54 CLKout10 55 CLKout10* 56 CLKout11 57 CLKout11* 58 CLKin_SEL0 I/O Programmable Programmable status pin. 59 CLKin_SEL1 I/O Programmable Programmable status pin. O Programmable Clock output 13. For JESD204B systems suggest SYSREF Clock. Programmable formats: CML, LVPECL, LCPECL, LVDS, or 2xLVCMOS. O Programmable Clock output 12. For JESD204B systems suggest Device Clock. Programmable formats: CML, LVPECL, LCPECL, or LVDS. 60 CLKout13 61 CLKout13* 62 CLKout12 63 CLKout12* 64 Vcc12_CG0 PWR Power supply for clock outputs 0, 1, 12, and 13. DAP GND DIE ATTACH PAD, connect to GND. DAP 6 Specifications 6.1 Absolute Maximum Ratings over operating free-air temperature range (unless otherwise noted) (1) MIN MAX UNIT -0.3 3.6 V -0.3 (VCC+0.3) V Lead temperature (solder 4 seconds) 260 °C Junction temperature 150 °C IIN Differential input current (CLKinX/X*, OSCin/OSCin*) ±5 mA MSL Moisture sensitivity level Tstg Storage Temperature VCC Supply voltage VIN Input voltage TL TJ (1) (2) (2) 3 -65 150 °C Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. Never to exceed 3.6 V 6.2 ESD Ratings VALUE V(ESD) (1) (2) Electrostatic discharge Human body model (HBM), per ANSI/ESDA/JEDEC JS-001, all pins (1) ±2000 Machine Model (MM) ±150 Charged device model (CDM), per JEDEC specification JESD22-C101, all pins (2) ±250 UNIT V JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. Manufacturing with less than 500-V HBM is possible with the necessary precautions. Pins listed as ±2000 V may actually have higher performance. JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process. Manufacturing with less than 250-V CDM is possible with the necessary precautions. Pins listed as ±250 V may actually have higher performance. Submit Documentation Feedback Copyright © 2017–2018, Texas Instruments Incorporated Product Folder Links: LMK04832 5 LMK04832 SNAS688C – FEBRURAY 2017 – REVISED MAY 2018 www.ti.com 6.3 Recommended Operating Conditions over operating free-air temperature range (unless otherwise noted) TJ Junction Temperature TA Ambient Temperature TPCB PCB Temperature (measured at thermal pad) VCC Supply Voltage MIN NOM -40 25 3.15 3.3 MAX UNIT 125 °C 85 °C 105 °C 3.45 V 6.4 Thermal Information LMK04832 THERMAL METRIC (1) NKD (WQFN) UNIT 64 PINS Junction-to-ambient thermal resistance (2) RθJA (3) 24.3 °C/W RθJC(top) Junction-to-case (top) thermal resistance 6.1 °C/W RθJB Junction-to-board thermal resistance (4) 3.5 °C/W ΨJT Junction-to-top characterization parameter (5) 0.1 °C/W ΨJB Junction-to-board characterization parameter (6) 3.5 °C/W (7) 0.7 °C/W RθJC(bot) (1) (2) (3) (4) (5) (6) (7) Junction-to-case (bottom) thermal resistance For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report, SPRA953. The junction-to-ambient thermal resistance under natural convection is obtained in a simulation on a JEDEC-standard, High-K board, as specified in JESD51-7, in an environment described in JESD51-2a. The junction-to-case(top) thermal resistance is obtained by simulating a cold plate test on the package top. No specific JEDEC-standard test exists, but a close description can be found in the ANSI SEMI standard G30-88. The junction-to-board thermal resistance is obtained by simulating in an environment with a ring cold plate fixture to control the PCB temperature, as described in JESD51-8. The junction-to-top characterization parameter, ΨJT, estimates the junction temperature of a device in a real system and is extracted from the simulation data for obtaining RΘJA, using a procedure described in JESD51-2a (sections 6 and 7). The junction-to-board characterization parameter, ΨJB estimates the junction temperature of a device in a real system and is extracted from the simulation data for obtaining RΘJA , using a procedure described in JESD51-2a (sections 6 and 7). The junction-to-case(bottom) thermal resistance is obtained by simulating a cold plate test on the exposed (power) pad. No specific JEDEC standard test exists, but a close description can be found in the ANSI SEMI standard G30-88. 6.5 Electrical Characteristics (3.15 V < VCC < 3.45 V, -40 °C < TA < 85 °C. Typical values at VCC = 3.3 V, TA = 25 °C, at the Recommended Operating Conditions are not assured.) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT CURRENT CONSUMPTION (1) ICC_PD Power Down Supply Current ICC_JESD204B_ALL 4 Supply Current for JESD204B use case during JESD204B 3 synchronization VCO = 2949.12 MHz 4 Dual Loop (2) 3 ICC_JESD204B_LOW Supply Current for JESD204B use case during JESD204B steady state while holding SYSREF as low in DC coupled configuration. (2) 4 3 4 3 ICC_JESD204B_VCM Supply Current for JESD204B use case during JESD204B steady state while setting SYSREF outputs as Vcm. (2) (1) (2) 6 1.5 3 mA CML 32 mA clocks in bypass LVDS clock /12 SYSREF as LCPECL SYSREF as LVDS 930 1120 mA CML 32 mA clocks in bypass LVDS clock /12 SYSREF as LCPECL (low state) SYSREF as LVDS (low state) 780 940 mA 4 CML 32 mA clocks in bypass 3 LVDS clock /12 7 SYSREF outputs powered down 675 810 mA Use the TICS Pro tool to calculate Icc for a specific configuration. LCPECL clocks have 120 Ω emitter resistors. OSCout LVPECL clock uses 240 Ω ohm emitter resistors. Other settings include CLKoutX_Y_IDL = 0, CLKoutX_Y_ODL = 0, DCLKX_Y_DCC = 0. SCLK_X_Y_ADLY_EN = 0. Submit Documentation Feedback Copyright © 2017–2018, Texas Instruments Incorporated Product Folder Links: LMK04832 LMK04832 www.ti.com SNAS688C – FEBRURAY 2017 – REVISED MAY 2018 Electrical Characteristics (continued) (3.15 V < VCC < 3.45 V, -40 °C < TA < 85 °C. Typical values at VCC = 3.3 V, TA = 25 °C, at the Recommended Operating Conditions are not assured.) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT CLKin0/0*, CLKin1/1*, and CLKin2/2* INPUT CLOCK SPECIFICATIONS fCLKinX_LOS fCLKin0_PLL1_MOS fCLKin1_PLL1_MOS fCLKin2_PLL1_MOS fCLKin0_PLL1 fCLKin1_PLL1 fCLKin2_PLL1 Clock Input LOS (CLKin0/1/2) LOS_EN = 1 Clock Input Frequency for PLL1 Reference (CLKin0/1/2) CLKinX_TYPE = 1 (MOS) CLKin0_OUT_MUX = 2 (PLL1) Clock Input Frequency for PLL1 Reference (CLKin0/1/2) CLKinX_TYPE = 0 (Bipolar) CLKin0_OUT_MUX = 2 (PLL1) CLKin1_OUT_MUX = 2 (PLL1) 250 MHz MHz 0.001 250 MHz OSCout_FMT = 0 (Power down) CLKin1_OUT_MUX = 2 (PLL1) MHz 0.001 750 MHz OSCout_FMT = 0 (Power down) CLKin0_OUT_MUX = 2 (PLL1) PLL2R_CLK_MUX = 1 (PLL1 CLKinX) fCLKin0_PLL2 fCLKin1_PLL2 0.001 Clock Input Frequency for PLL2 Reference (CLKin0/1/2) CLKinX_TYPE = 0 (Bipolar) CLKin1_OUT_MUX = 2 (PLL1) PLL2R_CLK_MUX = 1 (PLL1 CLKinX) 500 MHz OSCout_FMT = 0 (Power down) PLL2R_CLK_MUX = 1 (PLL1 CLKinX) fCLKin2_PLL2 fCLKin1_FB Clock Input Frequency for 0-delay with external feedback (CLKin1) CLKin1_OUT_MUX = 1 (FB Mux) CLKin1_TYPE = 0 (Bipolar) 0.001 750 MHz fCLKin1_Fin Clock Input Frequency for external VCO or distribution mode (CLKin1) CLKin1_OUT_MUX = 0 (Fin) CLKin1_TYPE = 0 (Bipolar) 0.001 3250 MHz SLEWCLKin Clock Input Slew Rate (3) 20% to 80% Differential Clock Input Voltage (4) AC-coupled VCLKin Clock Input Single-ended Input Voltage AC-coupled to CLKinX; CLKinX* AC-coupled to Ground CLKinX_TYPE = 0 (Bipolar) |VCLKinX-offset| Each pin AC-coupled, CLKin0/1/2 CLKinX_TYPE = 0 (Bipolar) DC offset voltage between CLKinX/CLKinX* (CLKinX* - CLKinX) Each pin AC-coupled, CLKin0/1 CLKinX_TYPE = 1 (MOS) VIDCLKin_AC VSSCLKin_AC DC offset voltage between CLKin2/CLKin2* (CLKin2* - CLKin2) Each pin AC-coupled CLKinX_TYPE = 1 (MOS) VCLKinVIH High Input Voltage VCLKinVIL Low Input Voltage DC-coupled to CLKinX; CLKinX* AC-coupled to Ground CLKinX_TYPE = 1 (MOS) (3) (4) 0.15 0.5 V/ns 0.125 1.55 |V| 0.25 3.1 Vpp 0.5 2.4 Vpp 0 |mV| 55 |mV| 20 |mV| 2 Vcc V 0 0.4 V In order to meet the jitter performance listed in the subsequent sections of this data sheet, the minimum recommended slew rate for all input clocks is 0.5 V/ns. This is especially true for single-ended clocks. Phase noise performance will begin to degrade as the clock input slew rate is reduced. However, the device will function at slew rates down to the minimum listed. When compared to single-ended clocks, differential clocks (LVDS, LVPECL) will be less susceptible to degradation in phase noise performance at lower slew rates due to their common mode noise rejection. However, it is also recommended to use the highest possible slew rate for differential clocks to achieve optimal phase noise performance at the device outputs. See Differential Voltage Measurement Terminology for definition of VID and VOD voltages. Submit Documentation Feedback Copyright © 2017–2018, Texas Instruments Incorporated Product Folder Links: LMK04832 7 LMK04832 SNAS688C – FEBRURAY 2017 – REVISED MAY 2018 www.ti.com Electrical Characteristics (continued) (3.15 V < VCC < 3.45 V, -40 °C < TA < 85 °C. Typical values at VCC = 3.3 V, TA = 25 °C, at the Recommended Operating Conditions are not assured.) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT PLL1 SPECIFICATIONS fPD1 PLL1 Phase Detector Frequency ICPout1SOURCE ICPout1SINK PLL1 Charge Pump Source Current (5) PLL1 Charge Pump Sink Current (5) 40 MHz VCPout1 = Vcc/2, PLL1_CP_GAIN = 0 50 VCPout1 = Vcc/2, PLL1_CP_GAIN = 1 150 VCPout1 = Vcc/2, PLL1_CP_GAIN = 2 250 ... ... VCPout1 = Vcc/2, PLL1_CP_GAIN = 14 1450 VCPout1 = Vcc/2, PLL1_CP_GAIN = 15 1550 VCPout1 = Vcc/2, PLL1_CP_GAIN = 0 -50 VCPout1 = Vcc/2, PLL1_CP_GAIN = 1 -150 VCPout1 = Vcc/2, PLL1_CP_GAIN = 2 -250 ... VCPout1 = Vcc/2, PLL1_CP_GAIN = 14 -1450 VCPout1 = Vcc/2, PLL1_CP_GAIN = 15 -1550 Charge Pump Sink / Source Mismatch VCPout1 = Vcc/2, TA = 25 °C 1% ICPout1%VTUNE Magnitude of Charge Pump Current Variation vs. Charge Pump Voltage 0.5 V < VCPout1 < VCC - 0.5 V TA = 25 °C 4% ICPout1%TEMP Charge Pump Current vs. Temperature Variation ICPout1TRI Charge Pump TRI-STATE Leakage Current PN10 kHz (6) PLL 1/f Noise at 10 kHz offset. Normalized to 1 GHz Output Frequency (5) (6) (7) 8 Normalized Phase Noise Contribution µA ... ICPout1%MIS PN1 Hz (7) µA 10% 4% 0.5 V < VCPout1 < VCC - 0.5 V 5 PLL1_CP_GAIN = 50 µA -113 PLL1_CP_GAIN = 450 µA -117 PLL1_CP_GAIN = 1550 µA -119 PLL1_CP_GAIN = 50 µA -217 PLL1_CP_GAIN = 450 µA -224 PLL1_CP_GAIN = 1550 µA -225 nA dBc/ Hz dBc/ Hz This parameter is programmable A specification in modeling PLL in-band phase noise is the 1/f flicker noise, LPLL_flicker(f), which is dominant close to the carrier. Flicker noise has a 10 dB/decade slope. PN10 kHz is normalized to a 10 kHz offset and a 1 GHz carrier frequency. PN10 kHz = LPLL_flicker(10 kHz) - 20 log(Fout / 1 GHz), where LPLL_flicker(f) is the single side band phase noise of only the flicker noise's contribution to total noise, L(f). To measure LPLL_flicker(f) it is important to be on the 10 dB/decade slope close to the carrier. A high compare frequency and a clean crystal are important to isolating this noise source from the total phase noise, L(f). LPLL_flicker(f) can be masked by the reference oscillator performance if a low-power or noisy source is used. The total PLL in-band phase noise performance is the sum of LPLL_flicker(f) and LPLL_flat(f). A specification modeling PLL in-band phase noise. The normalized phase noise contribution of the PLL, LPLL_flat(f), is defined as: PN1 HZ = LPLL_flat(f) - 20 log(N) - 10 log(fPDX). LPLL_flat(f) is the single side band phase noise measured at an offset frequency, f, in a 1 Hz bandwidth and fPDX is the phase detector frequency of the synthesizer. LPLL_flat(f) contributes to the total noise, L(f). Submit Documentation Feedback Copyright © 2017–2018, Texas Instruments Incorporated Product Folder Links: LMK04832 LMK04832 www.ti.com SNAS688C – FEBRURAY 2017 – REVISED MAY 2018 Electrical Characteristics (continued) (3.15 V < VCC < 3.45 V, -40 °C < TA < 85 °C. Typical values at VCC = 3.3 V, TA = 25 °C, at the Recommended Operating Conditions are not assured.) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT OSCin INPUT CLOCK SPECIFICATIONS fOSCin PLL2 Reference Input SLEWOSCin PLL2 Reference Clock minimum slew 20% to 80% rate on OSCin (3) VOSCin Input Voltage for OSCin or OSCin* AC coupled; Single-ended (Unused pin AC-coupled to GND) Differential voltage swing (4) AC-coupled |VOSCin-offset| DC offset voltage between OSCin/OSCin* (OSCinX* - OSCinX) Each pin AC-coupled fdoubler_max Doubler input frequency EN_PLL2_REF_2X = 1 (8); OSCin Duty Cycle 40% to 60% VIDOSCin VSSOSCin 500 MHz 0.15 0.5 V/ns 0.2 2.4 Vpp 0.2 1.55 |V| 0.4 3.1 Vpp 20 |mV| 320 MHz PLL2 SPECIFICATIONS fPD2 Phase Detector Frequency ICPout2 SOURCE PLL2 Charge Pump Source Current (5) 320 MHz ICPout2 SINK PLL2 Charge Pump Sink Current (5) VCPout2 = VCC/2, PLL2_CP_GAIN = 2 1600 VCPout2 = VCC/2, PLL2_CP_GAIN = 3 3200 VCPout2 = VCC/2, PLL2_CP_GAIN = 2 -1600 VCPout2 = VCC/2, PLL2_CP_GAIN = 3 -3200 µA µA ICPout2%MIS Charge Pump Sink / Source Mismatch VCPout2 = Vcc/2, TA = 25 °C 1% ICPout2%VTUNE Magnitude of Charge Pump Current Variation vs. Charge Pump Voltage 0.5 V < VCPout2 < VCC - 0.5 V TA = 25 °C 4% ICPout2%TEMP Charge Pump Current vs. Temperature Variation ICPout2 Charge Pump TRI-STATE Leakage Current 0.5 V < VCPout2 < VCC - 0.5 V PN10 kHz (6) PLL 1/f Noise at 10 kHz offset. Normalized to 1 GHz Output Frequency PLL2_CP_GAIN = 3200 µA -128 dBc/ Hz PN1 Hz (7) Normalized Phase Noise Contribution PLL2_CP_GAIN = 3200 µA -230 dBc/ Hz (8) TRI 10% 4% 10 nA The EN_PLL2_REF_2X bit enables/disables a frequency doubler mode for the PLL2 OSCin path. Submit Documentation Feedback Copyright © 2017–2018, Texas Instruments Incorporated Product Folder Links: LMK04832 9 LMK04832 SNAS688C – FEBRURAY 2017 – REVISED MAY 2018 www.ti.com Electrical Characteristics (continued) (3.15 V < VCC < 3.45 V, -40 °C < TA < 85 °C. Typical values at VCC = 3.3 V, TA = 25 °C, at the Recommended Operating Conditions are not assured.) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT INTERNAL VCO SPECIFICATIONS fVCO LMK04832 VCO Tuning Range VCO0 2440 2580 VCO1 2945 3255 VCO0 KVCO LMK04832 Vtune Tuning Sensitivity VCO1 |ΔTCL| Allowable Temperature Drift for Continuous Lock (9) 2440 MHz -11.8 2580 MHz -14.5 2945 MHz -22.9 3255 MHz -31.4 After programming for lock, no changes to output configuration are permitted to assure continuous lock 1 kHz VCO0 at 2440 MHz L(f)VCO Open-loop phase noise VCO1 at 2945 MHz VCO1 at 3250 MHz (9) 10 MHz/ V 125 °C -55 10 kHz -86.3 100 kHz -115.2 800 kHz -136.3 1 MHz -137.6 1 kHz -53.3 10 kHz VCO0 at 2580 MHz MHz dBc/ Hz -85 100 kHz -114.3 800 kHz -135.3 1 MHz -136.9 1 kHz -49.2 10 kHz -81.1 100 kHz -111.1 800 kHz -133.8 1 MHz -135.9 1 kHz -46.6 10 kHz -78.9 100 kHz -108.9 800 kHz -131.7 1 MHz -133.3 dBc/ Hz dBc/ Hz dBc/ Hz Maximum Allowable Temperature Drift for Continuous Lock is how far the temperature can drift in either direction from the value it was at the time that the 0x168 register was last programmed with PLL2_FCAL_DIS = 0, and still have the part stay in lock. The action of programming the 0x168 register, even to the same value, activates a frequency calibration routine. This implies the part will work over the entire frequency range, but if the temperature drifts more than the maximum allowable drift for continuous lock, then it will be necessary to reload the appropriate register to ensure it stays in lock. Regardless of what temperature the part was initially programmed at, the temperature can never drift outside the frequency range of – 40 °C to 85 °C without violating specifications. Submit Documentation Feedback Copyright © 2017–2018, Texas Instruments Incorporated Product Folder Links: LMK04832 LMK04832 www.ti.com SNAS688C – FEBRURAY 2017 – REVISED MAY 2018 Electrical Characteristics (continued) (3.15 V < VCC < 3.45 V, -40 °C < TA < 85 °C. Typical values at VCC = 3.3 V, TA = 25 °C, at the Recommended Operating Conditions are not assured.) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT CLOCK OUTPUT NOISE FLOOR L(f)CLKout LVDS CLKoutX_Y_ODL=1 -159.5 L(f)CLKout HSDS 6 mA CLKoutX_Y_ODL=1 -161.5 L(f)CLKout HSDS 8 mA CLKoutX_Y_ODL=1 -162.5 L(f)CLKout LCPECL CLKoutX_Y_ODL=1 -162.5 L(f)CLKout LVPECL 1.6 Vpp CLKoutX_Y_ODL=1 -162 L(f)CLKout LVPECL 2 Vpp CLKoutX_Y_ODL=1 -163 L(f)CLKout CML 16 mA, odd CLKoutY DC bias: 50 Ω to Vcc CLKoutX_Y_ODL=1 -162.5 L(f)CLKout CML 24 mA, odd CLKoutY DC bias: 50 Ω to Vcc CLKoutX_Y_ODL=1 -162.5 L(f)CLKout CML 32 mA, odd CLKoutY DC bias: 50 Ω to Vcc CLKoutX_Y_ODL=1 -163 L(f)CLKout LVCMOS CLKoutX_Y_ODL=1 -160 L(f)CLKout CML 16 mA, even CLKoutX DC bias: 68 nH to 20 Ω to Vcc CLKoutX_Y_IDL=1 -155.5 CML 24 mA, even CLKoutX DC bias: 68 nH to 20 Ω to Vcc CLKoutX_Y_IDL=1 -156 CML 32 mA, even CLKoutX DC bias: 68 nH to 20 Ω to Vcc CLKoutX_Y_IDL=1 -156.5 L(f)CLKout 245.76 MHz Noise Floor 20 MHz Offset 3.2 GHz Noise Floor 20 MHz Offset L(f)CLKout dBc/ Hz dBc/ Hz CLKout CLOSED LOOP PHASE NOISE SPECIFICATIONS L(f)CLKout L(f)CLKout VCO0 SSB Phase Noise 245.76 MHz (10) Doubler disabled VCO1 SSB Phase Noise 245.76 MHz (10) Doubler disabled Offset = 1 kHz -125 Offset = 10 kHz -134 Offset = 100 kHz -137 Offset = 1 MHz -154 Offset = 1 kHz -125 Offset = 10 kHz -135 Offset = 100 kHz -137 Offset = 1 MHz -151 dBc/ Hz dBc/ Hz (10) Dual Loop, OSCin reference is a 122.88 MHz Crystek 603281 VCXO. Data collected using a MACOM H-183-4 Hybrid Junction for differential to single ended converstion. PLL2_CP = 3.2 mA. PLL2 Loop filter is C1i = 60 pF, C1 (external) = 4.7 pF, R2 = 820 Ω (external), C2 = 3.9 nF (external), R3 = 2.4 kΩ, C3 = 50 pF, R4 = 200 Ω, C4 = 10 pF. PLL1_CP = 450 µA with a narrow loop bandwidth. CLKoutX_Y_IDL = 0, CLKoutX_Y_ODL = 1. Even CLKout with LVPECL20 format using 120-Ω to GND. Submit Documentation Feedback Copyright © 2017–2018, Texas Instruments Incorporated Product Folder Links: LMK04832 11 LMK04832 SNAS688C – FEBRURAY 2017 – REVISED MAY 2018 www.ti.com Electrical Characteristics (continued) (3.15 V < VCC < 3.45 V, -40 °C < TA < 85 °C. Typical values at VCC = 3.3 V, TA = 25 °C, at the Recommended Operating Conditions are not assured.) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT CLKout CLOSED LOOP JITTER SPECIFICATIONS PDF = 312.5 MHz BW = 12 kHz to 20 MHz 54 fs rms PDF = 312.5 MHz BW = 100 Hz to 100 MHz 64 fs rms PDF = 320 MHz BW = 12 kHz to 20 MHz 61 fs rms PDF = 320 MHz BW = 100 Hz to 100 MHz 67 fs rms VCO0, fCLKout = 2457.6 MHz Integrated RMS Jitter (10) PDF = 245.76 MHz (Doubler enabled) BW = 12 kHz to 20 MHz 55 fs rms VCO0, fCLKout = 2457.6 MHz Integrated RMS Jitter (10) PDF = 122.88 MHz BW = 12 kHz to 20 MHz 70 fs rms VCO1, fCLKout = 2949.12 MHz Integrated RMS Jitter (10) PDF = 245.76 (Doubler enabled) BW = 12 kHz to 20 MHz 60 fs rms VCO1, fCLKout = 2949.12 MHz Integrated RMS Jitter (10) PDF = 122.88 MHz BW = 12 kHz to 20 MHz 75 fs rms VCO0, fCLKout = 2500 MHz (11) Integrated RMS Jitter JCLKout VCO1, fCLKout = 3200 MHz (11) Integrated RMS Jitter JCLKout DEFAULT POWER on RESET CLOCK OUTPUT FREQUENCY OSCout default frequency (12) fOSCout CLOCK SKEW 500 MHz (13) |TSKEW| Maximum skew CLKoutX to CLKoutX Any even CLKoutX, same format (14) Device Clock FCLK = 1.6 GHz, RL = 100 Ω ACcoupled DCLKX_Y_BYP = 1 |TSKEW| Maximum skew for CLKoutX to CLKoutX or CLKoutY to CLKoutY FCLK = 250 MHz, RL = 100 Ω ACcoupled Even to even or odd to odd clock, same format (15) Device clock DCLKX_Y_BYP = 0 DCLKX_Y_DIV = 12 |TSKEW| Maximum skew for any CLKoutX or Y to any CLKoutX or Y FCLK = 250 MHz, RL = 100 Ω ACcoupled Any output, same format (15) Device clock DCLKX_Y_BYP = 0 DCLKX_Y_DIV = 12 |TSKEW| Delay from CLKoutX to CLKoutY in same pair FCLK = 250 MHz, RL = 100 Ω ACcoupled Same pair of device clocks, same format (15) 60 |ps| 60 |ps| 100 |ps| 35 ps (11) Single Loop, OSCin reference is R&S SMA100B Signal Generator with option SMAB-B711 through Prodyn BIB-100G Balun to OSCin. Data collected using a MACOM H-183-4 Hybrid Junction for differential to single ended converstion. PLL2 Loop filter is C1 = 60 pF, R2 = 470 Ω (external), C2 = 150 nF (external), R3 = 2.4 kΩ, C3 = 50 pF, R4 = 200 Ω, C4 = 10 pF, PLL2_CP = 3.2 mA. CLKoutX_Y_IDL = 1, CLKoutX_Y_ODL = 0; Even CLKout with CML 32 mA format using DC bias 68-nH to 20-Ω to Vcc. (12) OSCout will oscillate at start-up at the frequency of the VCXO attached to OSCin port. (13) Equal loading and identical clock configuration on each clock input and/or output is required for skew, setup, and hold specifications to be valid. (14) Valid for CML 32 mA, CML 24 mA, CML 16 mA. CML DC bias is 50 ohms to Vcc or 68 nH to 20 Ω to Vcc. (15) Valid for HSDS 8 mA, HSDS 6 mA, LVDS. LVPECL20, LVPECL16, LCPECL with 120 Ω emitter resistor to ground. 12 Submit Documentation Feedback Copyright © 2017–2018, Texas Instruments Incorporated Product Folder Links: LMK04832 LMK04832 www.ti.com SNAS688C – FEBRURAY 2017 – REVISED MAY 2018 Electrical Characteristics (continued) (3.15 V < VCC < 3.45 V, -40 °C < TA < 85 °C. Typical values at VCC = 3.3 V, TA = 25 °C, at the Recommended Operating Conditions are not assured.) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT CML 32 mA CLOCK OUTPUTS (CLKoutX/Y) TR / TF 20% to 80% Output Rise/Fall VOH Output High Voltage VOL Output Low Voltage VOD Differential Output Voltage RL = AC-coupled 100 Ω, 250 MHz Odd CLKoutY, CLKoutX_Y_ODL = 1 DC Bias, 50 ohm to Vcc Differential Output Voltage ps Vcc T = 25 °C, DC measurement Termination 50-Ω pull up to Vcc DC bias is 50-Ω pull up to Vcc RL = AC-coupled 100 Ω VOD 135 DC bias is 68-nH to 20-Ω to Vcc RL = AC-coupled 100 Ω Vcc 1.66 V 1660 |mV| 250 MHz (16) 1070 2.5 GHz (17) 765 (18) 550 3.2 GHz (17) 610 3.2 GHz (18) 385 2.5 GHz |mV| CML 24 mA CLOCK OUTPUTS (CLKoutX/Y) TR / TF 20% to 80% Output Rise/Fall VOH Output High Voltage VOL Output Low Voltage VOD Differential Output Voltage RL = AC-coupled 100 Ω, 250 MHz Odd CLKoutY, CLKoutX_Y_ODL = 1 DC Bias, 50 ohm to Vcc Differential Output Voltage ps Vcc T = 25 °C, DC measurement Termination 50-Ω pull up to Vcc DC bias is 50-Ω pull up to Vcc RL = AC-coupled 100 Ω VOD 125 DC bias is 68-nH to 20-Ω to Vcc RL = AC-coupled 100 Ω Vcc 1.26 V 1260 |mV| 250 MHz (16) 815 2.5 GHz (17) 595 2.5 GHz (18) 445 3.2 GHz (17) 480 (18) 330 3.2 GHz |mV| (16) For even and odd outputs CLKoutX_Y_IDL=0. For even outputs CLKoutX_Y_ODL=X and for odd CLKoutX_Y_ODL=1. (17) Even clock outputs (CLKoutX). CLKoutX_Y_IDL=1, CLKoutX_Y_ODL=X. (18) Odd clock outputs (CLKoutY). CLKoutX_Y_IDL=X, CLKoutX_Y_ODL=1 Submit Documentation Feedback Copyright © 2017–2018, Texas Instruments Incorporated Product Folder Links: LMK04832 13 LMK04832 SNAS688C – FEBRURAY 2017 – REVISED MAY 2018 www.ti.com Electrical Characteristics (continued) (3.15 V < VCC < 3.45 V, -40 °C < TA < 85 °C. Typical values at VCC = 3.3 V, TA = 25 °C, at the Recommended Operating Conditions are not assured.) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT CML 16 mA CLOCK OUTPUTS (CLKoutX/Y) TR / TF 20% to 80% Output Rise/Fall VOH Output High Voltage VOL Output Low Voltage VOD Differential Output Voltage Differential Output Voltage VOD VOD VOD 120 ps Vcc T = 25 °C, DC measurement Termination is 50-Ω pull up to Vcc Vcc 0.84 840 DC bias is 50-Ω pull up to Vcc RL = AC-coupled 100 Ω VOD VOD RL = AC-coupled 100 Ω, 250 MHz Odd CLKoutY, CLKoutX_Y_ODL = 1 DC Bias, 50 ohm to Vcc V |mV| 250 MHz (16) 550 2.5 GHz (17) 400 (18) 325 3.2 GHz (17) 325 3.2 GHz (18) 250 RL = AC-coupled 100 Ω, 250 MHz 140 ps VCC - 1 V DC bias is 68-nH to 20-Ω to Vcc RL = AC-coupled 100 Ω 2.5 GHz |mV| LVPECL CLOCK OUTPUT (CLKoutX/Y, OSCout) TR / TF 20% to 80% Output Rise/Fall LVPECL 2000 mVpp CLOCK OUTPUTS (CLKoutX/Y, OSCout) VOH Output High Voltage VOL Output Low Voltage VOD Output Voltage (4) DC Measurement Termination = 50-Ω to VCC - 2.0 V 250 MHz (19) VOD Differential Output Voltage Em = 120 Ω to ground Termination = ACcoupled 100 Ω VCC - 2 1000 925 (20) 585 2.5 GHz (21) 545 3.2 GHz (20) 415 3.2 GHz (21) 370 2.5 GHz V |mV| |mV| LVPECL 1600 mVpp CLOCK OUTPUTS (CLKoutX/Y, OSCout) VOH VOL VOD VOD Output High Voltage Output Low Voltage Output Voltage DC Measurement Termination = 50-Ω to VCC - 2.0 V (4) Differential Output Voltage VCC - 1 V VCC 1.8 V 800 Em = 120 Ω to ground Termination = ACcoupled 100 Ω 250 MHz (19) 760 2.5 GHz (20) 510 2.5 GHz (21) 480 3.2 GHz (20) 370 3.2 GHz (21) 340 |mV| |mV| LCPECL CLOCK OUTPUT (CLKoutX/Y, OSCout) TR / TF 20% to 80% Output Rise/Fall VOH Output High Voltage VOL Output Low Voltage VOD Output Voltage (4) RL = AC-coupled 100 Ω DC bias = 120 Ω to GND DC Measurement Termination = 50-Ω to 0.5 V 135 ps 1.6 V 0.6 V 1000 |mV| 170 ps HSDS 8 mA CLOCK OUTPUTS (CLKoutX/Y) TR / TF 20% to 80% Output Rise/Fall RL = 100 Ω, 250 MHz (19) CLKoutX_Y_IDL=X and CLKoutX_Y_ODL=X. (20) Even clock outputs (CLKoutX). CLKoutX_Y_IDL=X, CLKoutX_Y_ODL=1. (21) Odd clock outputs (CLKoutY). CLKoutX_Y_IDL=X, CLKoutX_Y_ODL=1 14 Submit Documentation Feedback Copyright © 2017–2018, Texas Instruments Incorporated Product Folder Links: LMK04832 LMK04832 www.ti.com SNAS688C – FEBRURAY 2017 – REVISED MAY 2018 Electrical Characteristics (continued) (3.15 V < VCC < 3.45 V, -40 °C < TA < 85 °C. Typical values at VCC = 3.3 V, TA = 25 °C, at the Recommended Operating Conditions are not assured.) PARAMETER VOH Output High Voltage VOL Output Low Voltage VOD Output Voltage (4) ΔVOD Change in Magnitude of VOD for complementary output states TEST CONDITIONS MIN DC Measurement Termination = 50-Ω to VCC - 1.64 V TYP MAX UNIT VCC 0.95 V VCC 1.7 V 750 -115 |mV| 115 mV HSDS 6 mA CLOCK OUTPUTS (CLKoutX/Y) TR / TF 20% to 80% Output Rise VOH Output High Voltage VOL Output Low Voltage RL = 100 Ω, 250 MHz DC Measurement Termination = 50-Ω to VCC - 1.42 V (4) VOD Output Voltage ΔVOD Change in Magnitude of VOD for complementary output states 170 ps VCC 0.9 V VCC 1.5 V 600 -80 |mV| 80 mV LVDS CLOCK OUTPUTS (CLKoutX/Y, OSCout) TR / TF 20% to 80% Output Rise VOD Differential Output Voltage RL = 100 Ω, 250 MHz ΔVOD Change in Magnitude of VOD for complementary output states VOS Output Offset Voltage ΔVOS Change in VOS for complementary output states ISA ISB Output short circuit current - singleended T = 25 °C, DC measurement AC-coupled to receiver input RL = 100-Ω differential termination 175 ps 400 |mV| -60 1.125 60 1.25 1.375 mV V 35 |mV| Single-ended output shorted to GND T = 25 °C -24 24 Submit Documentation Feedback Copyright © 2017–2018, Texas Instruments Incorporated Product Folder Links: LMK04832 mA 15 LMK04832 SNAS688C – FEBRURAY 2017 – REVISED MAY 2018 www.ti.com Electrical Characteristics (continued) (3.15 V < VCC < 3.45 V, -40 °C < TA < 85 °C. Typical values at VCC = 3.3 V, TA = 25 °C, at the Recommended Operating Conditions are not assured.) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT LVCMOS CLOCK OUTPUTS (CLKout8/10/Y, OSCout) fCLKout Maximum Frequency 5 pF Load 250 MHz Vcc 0.1 VOH Output High Voltage 1 mA Load VOL Output Low Voltage 1 mA Load IOH Output High Current (Source) VCC = 3.3 V, VO = 1.65 V -28 mA IOL Output Low Current (Sink) VCC = 3.3 V, VO = 1.65 V 28 mA DUTYCLK Output Duty Cycle (22) VCC/2 to VCC/2, FCLK = 100 MHz, T = 25°C 50 % (23) V 0.1 V DIGITAL OUTPUTS (CLKin_SELX, Status_LDX, and RESET/GPO) VOH VOL High-Level Output Voltage IOH = -500 µA CLKin_SELX_TYPE = 3 or 4 Status_LDX_TYPE = 3 or 4 RESET_TYPE = 3 or 4 Low-Level Output Voltage IOL = 500 µA CLKin_SELX_TYPE = 3, 4, or 6 Status_LDX_TYPE = 3, 4, or 6 RESET_TYPE = 3, 4, or 6 VCC 0.4 V 0.4 V DIGITAL OUTPUTS (SDIO) VOH High-Level Output Voltage IOH = -500 µA; During SPI read. SDIO_RDBK_TYPE = 0 VOL Low-Level Output Voltage IOL = 500 µA; During SPI read. SDIO_RDBK_TYPE = 0 or 1 VCC 0.4 V 0.4 V DIGITAL INPUTS (CLKinX_SEL, RESET/GPO, SYNC, SCK, SDIO, and CS*) VIH High-Level Input Voltage VIL Low-Level Input Voltage 1.2 V 0.5 V DIGITAL INPUT (CLKinX_SEL) IIH IIL High-Level Input Current VIH = VCC Low-Level Input Current VIL = 0 V CLKin_SELX_TYPE = 0 (High Impedance) -5 5 CLKin_SELX_TYPE = 1 (Pull up) -5 5 CLKin_SELX_TYPE = 2 (Pull-down) 10 80 CLKin_SELX_TYPE = 0 (High Impedance) -5 5 -40 -5 CLKin_SELX_TYPE = 2 (Pull-down) -5 5 RESET_TYPE = 2 (Pull-down) 10 80 RESET_TYPE = 0 (High Impedance) -5 5 -40 -5 -5 5 CLKin_SELX_TYPE = 1 (Pull up) µA µA DIGITAL INPUT (RESET/GPO) IIH IIL High-Level Input Current VIH = VCC Low-Level Input Current VIL = 0 V RESET_TYPE = 1 (Pull up) RESET_TYPE = 2 (Pull-down) µA µA DIGITAL INPUT (SYNC) IIH High-Level Input Current VIH = VCC 25 µA IIL Low-Level Input Current VIL = 0 V -5 5 µA DIGITAL INPUTS (SCK, SDIO, CS*) IIH High-Level Input Current VIH = VCC -5 5 µA IIL Low-Level Input Current VIL = 0 V -5 5 µA (22) For OSCout when driven by OSCin, assumes OSCin has 50% input duty cycle. (23) For any device clock with an odd divide value, assumes selected clock output has DCLKX_Y_DCC = 1 to enable duty cycle correction. 16 Submit Documentation Feedback Copyright © 2017–2018, Texas Instruments Incorporated Product Folder Links: LMK04832 LMK04832 www.ti.com SNAS688C – FEBRURAY 2017 – REVISED MAY 2018 6.6 Timing Requirements (1) DIGITAL INPUT TIMING MIN tdS Setup time for SDI edge to SCLK rising edge 20 NOM MAX UNIT ns tdH Hold time for SDI edge to SCLK rising edge 10 ns tSCLK Period of SCLK 200 (1) ns tHIGH High width of SCLK 60 ns tLOW Low width of SCLK 60 ns tcS Setup time for CS* falling edge to SCLK rising edge 20 ns tcH Hold time for CS* rising edge from SCLK rising edge 20 tdV SCLK falling edge to valid read back data ns 60 ns 5 MHz 6.7 Timing Diagram Register programming information on the SDIO pin is clocked into a shift register on each rising edge of the SCK signal. On the rising edge of the CS* signal, the register is sent from the shift register to the register addressed. A slew rate of at least 30 V/µs is recommended for these signals. After programming is complete the CS* signal should be returned to a high state. If the SCK or SDIO lines are toggled while the VCO is in lock, as is sometimes the case when these lines are shared with other parts, the phase noise may be degraded during this programming. 4-cwire mode read back has same timing as SDIO pin. R/W bit = 0 is for SPI write. R/W bit = 1 is for SPI read. SDIO (WRITE) R/W A14 tdS tdH tcS tHIGH A13 A12 to A0, D7 to D2 D1 D0 SCLK SDIO (Read) tcH tLOW tSCLK D7 to D2 D1 D0 tdV CS* Figure 1. SPI Timing Diagram Submit Documentation Feedback Copyright © 2017–2018, Texas Instruments Incorporated Product Folder Links: LMK04832 17 LMK04832 SNAS688C – FEBRURAY 2017 – REVISED MAY 2018 www.ti.com 6.8 Typical Characteristics – Clock Output AC Characteristics Jitter from 100 Hz to 100 MHz = 63.6 fs rms. Output is CLKout4 as CML 32 mA with 68-nH to 20-Ω DC bias. Other settings are CLKout4_5_IDL = 1 and CLKout4_5_BYP = 1. PLL2 Loop Filter R2 = 470 Ω, C2 = 150 nF, Charge Pump = 3200 µA. Reference is R&S SMA100B Signal Generator with option SMAB - B711 through Prodyn BIB-100G Balun to OSCin. Figure 2. PLL2 with VCO1 Performance at 2500 MHz With 312.5-MHz OSCin/Phase Detector Frequency 18 Submit Documentation Feedback Copyright © 2017–2018, Texas Instruments Incorporated Product Folder Links: LMK04832 LMK04832 www.ti.com SNAS688C – FEBRURAY 2017 – REVISED MAY 2018 Typical Characteristics – Clock Output AC Characteristics (continued) Jitter from 100 Hz to 100 MHz = 67 fs rms. Output is CLKout4 as CML 32 mA with 68-nH to 20-Ω DC bias. Other settings are CLKout4_5_IDL = 1 and CLKout4_5_BYP = 1. PLL2 Loop Filter R2 = 470 Ω, C2 = 150 nF, Charge Pump = 3200 µA. Reference is R&S SMA100B Signal Generator with option SMAB - B711 through Prodyn BIB-100G Balun to OSCin. Figure 3. PLL2 with VCO1 Performance at 3200 MHz With 320-MHz OSCin/Phase Detector Frequency Submit Documentation Feedback Copyright © 2017–2018, Texas Instruments Incorporated Product Folder Links: LMK04832 19 LMK04832 SNAS688C – FEBRURAY 2017 – REVISED MAY 2018 www.ti.com 7 Parameter Measurement Information 7.1 Charge Pump Current Specification Definitions I1 = Charge Pump Sink Current at VCPout = VCC - ΔV I2 = Charge Pump Sink Current at VCPout = VCC/2 I3 = Charge Pump Sink Current at VCPout = ΔV I4 = Charge Pump Source Current at VCPout = VCC - ΔV I5 = Charge Pump Source Current at VCPout = VCC/2 I6 = Charge Pump Source Current at VCPout = ΔV ΔV = Voltage offset from the positive and negative supply rails. Defined to be 0.5 V for this device. 7.1.1 Charge Pump Output Current Magnitude Variation vs Charge Pump Output Voltage 7.1.2 Charge Pump Sink Current vs Charge Pump Output Source Current Mismatch 7.1.3 Charge Pump Output Current Magnitude Variation vs Ambient Temperature 20 Submit Documentation Feedback Copyright © 2017–2018, Texas Instruments Incorporated Product Folder Links: LMK04832 LMK04832 www.ti.com SNAS688C – FEBRURAY 2017 – REVISED MAY 2018 7.2 Differential Voltage Measurement Terminology The differential voltage of a differential signal can be described by two different definitions causing confusion when reading data sheets or communicating with other engineers. This section will address the measurement and description of a differential signal so that the reader will be able to understand and distinguish between the two different definitions when used. The first definition used to describe a differential signal is the absolute value of the voltage potential between the inverting and noninverting signal. The symbol for this first measurement is typically VID or VOD depending on if an input or output voltage is being described. The second definition used to describe a differential signal is to measure the potential of the noninverting signal with respect to the inverting signal. The symbol for this second measurement is VSS and is a calculated parameter. Nowhere in the IC does this signal exist with respect to ground, it only exists in reference to its differential pair. VSS can be measured directly by oscilloscopes with floating references, otherwise this value can be calculated as twice the value of VOD as described in the first description. Figure 4 illustrates the two different definitions side-by-side for inputs and Figure 5 illustrates the two different definitions side-by-side for outputs. The VID and VOD definitions show VA and VB DC levels that the noninverting and inverting signals toggle between with respect to ground. VSS input and output definitions show that if the inverting signal is considered the voltage potential reference, the noninverting signal voltage potential is now increasing and decreasing above and below the noninverting reference. Thus the peak-to-peak voltage of the differential signal can be measured. VID and VOD are often defined as volts (V) and VSS is often defined as volts peak-to-peak (VPP). VID Definition VSS Definition for Input Noninverting Clock VA 2 × VID VID VB Inverting Clock VID = | VA s 9B | VSS = 2 × VID GND Figure 4. Two Different Definitions for Differential Input Signals VOD Definition VSS Definition for Output Non-Inverting Clock VA 2·VOD VOD VB Inverting Clock VOD = | VA - VB | VSS = 2·VOD GND Figure 5. Two Different Definitions for Differential Output Signals Refer to application note AN-912 Common Data Transmission Parameters and their Definitions (SNLA036) for more information. Submit Documentation Feedback Copyright © 2017–2018, Texas Instruments Incorporated Product Folder Links: LMK04832 21 LMK04832 SNAS688C – FEBRURAY 2017 – REVISED MAY 2018 www.ti.com 8 Detailed Description 8.1 Overview The LMK04832 device is very flexible to meet many application requirements. Use cases include dual loop, dual loop 0-delay nested, dual loop 0-delay cascaded, single loop, single loop 0-delay, and clock distribution. The device may be used in JESD204B systems by providing a device clock and SYSREF to target devices, however traditional (non-JESD204B) systems are possible by programming pairs of outputs to share the clock divider or any mix of JESD204B and traditional. 8.1.1 Differences to LMK0482x The LMK04832 is pin-to-pin compatible with LMK0482x. The LMK04832 can be substituted directly into an existing LMK0482x hardware design. However, if a CML output is to be used on LMK04832, then 50-Ω pullups to VCC are required. For higher amplitude on high frequency CML outputs, use 68 nH on each output pin to a common to 20 ohms to Vcc. The LMK04832 does support LVPECL20 and LVPECL16 modes, but best performance is achieved with CML outputs in bypass mode. Division of up to 1023 is supported by DCLKx_DIV and each output clock can be a DEVCLK or a SYSREF. In addition, some programming updates are required from LMK04828 to LMK04832, particularly for controlling the clock output groups. 8.1.2 Jitter Cleaning The dual loop PLL architecture of the LMK04832 provides the lowest jitter performance over a wide range of output frequencies and phase noise integration bandwidths. The first stage PLL (PLL1) is driven by an external reference clock and uses an external VCXO to provide a frequency accurate, low phase noise reference clock for the second stage frequency multiplication PLL (PLL2). PLL1 typically uses a narrow loop bandwidth (typically 10 Hz to 200 Hz) to retain the frequency accuracy of the reference clock input signal while at the same time suppressing the higher offset frequency phase noise that the reference clock may have accumulated along its path or from other circuits. This cleaned reference clock provides the reference input to PLL2. The low phase noise reference provided to PLL2 allows PLL2 to operate with a wide loop bandwidth (typically 50 kHz to 200 kHz). The loop bandwidth for PLL2 is chosen to take advantage of the superior high offset frequency phase noise profile of the internal VCO and the good low offset frequency phase noise of the reference VCXO. Ultra-low jitter is achieved by allowing the phase noise of the external VCXO to dominate the final output phase noise at low offset frequencies and the phase noise of the internal VCO to dominate the final output phase noise at high offset frequencies. This results in best overall phase noise and jitter performance. 8.1.3 JEDEC JESD204B Support The LMK04832 provides support for JEDEC JESD204B. The LMK04832 clocks up to 7 JESD204B targets using 7 device clocks and 7 SYSREF clocks. The LMK04832 allows every clock output to be configured as a device clock or SYSREF clock. 8.1.4 Clock Inputs NOTE CLKin1 can be used as a reference for dual loop, single loop, or clock distribution mode, providing flexibility configuring the device for different operation modes from one clock input.. 8.1.4.1 Three Redundant PLL1 Reference Inputs The LMK04832 has up to three reference clock inputs for PLL1. They are CLKin0, CLKin1, and CLKin2. Automatic or manual switching can occur between the inputs. CLKin0, CLKin1, and CLKin2 each have their own PLL1 R dividers allowing clock switching references of different frequencies. 22 Submit Documentation Feedback Copyright © 2017–2018, Texas Instruments Incorporated Product Folder Links: LMK04832 LMK04832 www.ti.com SNAS688C – FEBRURAY 2017 – REVISED MAY 2018 Overview (continued) CLKin1 is shared for use as an external 0-delay feedback (FBCLKin), or for use with an external VCO (Fin). CLKin2 is shared for use as OSCout. To use CLKin2 as an input power down OSCout, see VCO_MUX, OSCout_MUX, OSCout_FMT. Fast manual switching between reference clocks and holdover is possible with external pins CLKin_SEL0 and CLKin_SEL1. 8.1.4.2 PLL2 Reference Inputs In dual loop configurations, the PLL2 reference is from OSCin. However, in single PLL2 loop operation, it is also possible to use any of the three CLKins of PLL1 as a reference to PLL2. 8.1.4.3 Clock Distribution Reference Input For clock distribution mode, a reference signal is applied to the Fin1 pins for clock distribution. CLKin0 can be used to distribute a SYSREF signal through the device. In this use case, CLKin0 is re-clocked by CLKin1. 8.1.5 VCXO Buffered Output The LMK04832 provides OSCout, which by power-on default is a buffered copy of the PLL1 feedback and PLL2 reference input at OSCin. This reference input is typically a low noise VCXO or XO. This output can be used to clock external devices such as microcontrollers, FPGAs, CPLDs, and so forth, before the LMK04832 is programmed. The OSCout buffer output type is programmable to LVDS, LVPECL, or LVCMOS. The VCXO buffered output can be synchronized to the VCO clock distribution outputs by using Cascaded 0Delay Mode. 8.1.6 Frequency Holdover The LMK04832 supports holdover operation to keep the clock outputs on frequency with minimum drift when the reference is lost until a valid reference clock signal is re-established. 8.1.7 Internal VCOs The LMK04832 has two internal VCOs. The output of the selected VCO is routed to the Clock Distribution Path. This same selection is also fed back to the PLL2 phase detector through a prescaler and N-divider. 8.1.8 External VCO Mode The Fin1 input allows an external VCO to be used with PLL2 of the LMK04832. Using Fin1 input for external VCO prevents use of CLKin1 for other purposes. 8.1.9 Clock Distribution The LMK04832 features a total of 14 PLL2 clock outputs driven from the internal or external VCO. All clock outputs have programmable output types. They can be programmed to CML, LVPECL, LVDS, HSDS, or LCPECL. All odd clock outputs plus CLKout8 and CLKout10 may be programmed to LVCMOS. If OSCout is included in the total number of clock outputs the LMK04832 is able to distribute up to 15 differential clocks. OSCout may be a buffered version of OSCin, DCLKout6, DCLKout8, or SYSREF. Its output format is programmable to LVDS, LVPECL, or LVCMOS. The following sections discuss specific features of the clock distribution channels that allow the user to control various aspects of the output clocks. 8.1.9.1 Clock Divider The LMK04832 has 7 clock dividers. In a traditional clocking system each divider can drive two outputs. The divider range is 1 to 1023. Duty cycle correction may be enabled for the output. When the divider is used even clocks may not output CML. Submit Documentation Feedback Copyright © 2017–2018, Texas Instruments Incorporated Product Folder Links: LMK04832 23 LMK04832 SNAS688C – FEBRURAY 2017 – REVISED MAY 2018 www.ti.com Overview (continued) In a JESD204B system, one clock output is a device clock driven from the clock divider and the other paired clock is from the SYSREF divider. For connectivity flexibility, either the even or odd clock output may be driven by the clock divider or be the SYSREF output. 8.1.9.2 High Performance Divider Bypass Mode Even clock outputs (CLKoutX) of the LMK04832 may bypass the clock divider to achieve the best possible noise floor and output swing. In this mode, the only usable output format is CML. 8.1.9.3 SYSREF Clock Divider The SYSREF divider supports a divide range of 8 to 8191 (even and odd). There is no duty cycle correction for the SYSREF divider. The SYSREF output may be routed to all clock outputs. 8.1.9.4 Device Clock Delay The device clocks support digital delay for phase adjustment of the clock outputs. The digital delay allows outputs to be delayed from 8 to 1023 VCO cycles. The delay step can be as small as half the period of the clock distribution path. For example, a 3.2-GHz VCO frequency results in 156.25-ps steps. The digital delay value takes effect on the clock output phase after a SYNC event. 8.1.9.5 Dynamic Digital Delay The device clock dividers support a dynamic digital delay feature which allows the clock to be delayed by one full device clock cycle. With a single programming, an adjustment of up to 255 one cycle delays may occur. When making a multi-step adjustment, the adjustments are periodically applied to reduce impact to the clock. Dynamic phase adjustments of half a clock distribution cycle are possible by half step. The SYSREF digital delay value is reused for dynamic digital delay. To achieve a one cycle delay program the SYSREF digital delay value to one greater than half the SYSREF divide value. 8.1.9.6 SYSREF Delay: Global and Local The SYSREF divider includes a digital delay block which allows a global phase shift with respect to the device clocks. Each clock output pair includes a local SYSREF analog and digital delay for unique phase adjustment of each SYSREF clock. The local analog delay allows for approximately 21-ps steps. Turning-on analog delay adds an additional 124ps of delay in the clock path. The digital delay step can be as small as half the period of the clock distribution path. For example, a 3.2-GHz VCO frequency results in 156.25-ps steps. The local digital delay and half step allows a SYSREF output to be delayed from 1.5 to 11 clock distribution path cycles. 8.1.9.7 Programmable Output Formats All LMK04832 clock outputs can be programmed to an LVDS, HSDS, LVPECL, or LCPECL output type. Odd clock outputs in addition to CLKout8 and CLKout10 may also be programmed to LVCMOS. All odd clock outputs can also be programmed to CML. When in bypass mode the even clock output may only be CML. The OSCout can be programmed to an LVDS, LVPECL, or LVCMOS output type. Any HSDS output type can be programmed to 6-mA or 8-mA amplitude levels. Any LVPECL output type can be programmed to 1600-mVpp or 2000-mVpp amplitude levels. The 2000-mVpp LVPECL output type is a Texas Instruments proprietary configuration that produces a 2000-mVpp differential swing for compatibility with many data converters and is also known as 2VPECL. LCPECL allows for DC-coupling SYSREF to low voltage JESD204B targets. 24 Submit Documentation Feedback Copyright © 2017–2018, Texas Instruments Incorporated Product Folder Links: LMK04832 LMK04832 www.ti.com SNAS688C – FEBRURAY 2017 – REVISED MAY 2018 Overview (continued) 8.1.9.8 Clock Output Synchronization Using the SYNC input causes all active clock outputs to share a rising edge as programmed by fixed digital delay. The SYNC event must occur for digital delay values to take effect. 8.1.10 0-Delay The LMK04832 supports two types of 0-delay. 1. Cascaded 0-delay 2. Nested 0-delay Cascaded 0-delay mode establishes a fixed deterministic phase relationship of the phase of the PLL2 input clock (OSCin) to the phase of a clock selected by the feedback mux. The 0-delay feedback uses internal feedback from the CLKout6, CLKout8, or SYSREF. The 0-delay feedback can also be from an external feedback through the FBCLKin port. The FB_MUX selects the feedback source. Because OSCin has a fixed deterministic phase relationship to the feedback clock, OSCout will also have a fixed deterministic phase relationship to the feedback clock. In this mode, PLL1 input clock (CLKinX) also has a fixed deterministic phase relationship to PLL2 input clock (OSCin); this results in a fixed deterministic phase relationship between all clocks from CLKinX to the clock outputs. Nested 0-delay mode establishes a fixed deterministic phase relationship of the phase of the PLL1 input clock (CLKinX) to the phase of a clock selected by the feedback mux. The 0-delay feedback uses internal feedback from the CLKout6, CLKout8, or SYSREF. The 0-delay feedback can also be from an external feedback through the FBCLKin port. The FB_MUX selects the feedback source. Without using 0-delay mode, there will be n possible fixed phase relationships from clock input to clock output depending on the clock output divide value. Using an external 0-delay feedback reduces the number of available clock inputs by one. 8.1.11 Status Pins The LMK04832 provides status pins which can be monitored for feedback or in some cases used for input depending upon device programming. For example: • The CLKin_SEL0 pin may indicate the LOS (loss-of-signal) for CLKin0. • The CLKin_SEL1 pin may be an input for selecting the active clock input. • The Status_LD1 pin may indicate if the device is locked. • The Status_LD2 pin may indicate if PLL2 is locked. The status pins can be programmed to a variety of other outputs including PLL divider outputs, combined PLL lock detect signals, PLL1 Vtune railing, readback, and so forth. Refer to the Register Maps section of this data sheet for more information. Submit Documentation Feedback Copyright © 2017–2018, Texas Instruments Incorporated Product Folder Links: LMK04832 25 LMK04832 SNAS688C – FEBRURAY 2017 – REVISED MAY 2018 www.ti.com 8.2 Functional Block Diagram Figure 6 illustrates the high level LMK04832 block diagram. CLKin1/Fin/ FBCLKin CLKin1*/Fin*/ FBCLKin* CLKin1 _DEMUX CLKin0 R Divider (1 to 16,383) CLKin0 N1 Divider (1 to 16,383) CLKin2 R Divider (1 to 16,383) CLKin1 FB Mux CLKout6 CLKout8 SYSREF Div OSCout/ CLKin2 OSCout*/ CLKin2* CLKin MUX CLKin1 R Divider (1 to 16,383) PLL1 _NCLK _MUX 2X PLL2 _REF _2X_EN OSCin OSCin* RESET/GPO SYNC CLKin_SEL0 CLKin_SEL1 SCLK SDIO CS* Device Control Status_LD1 Status_LD2 N2 Prescaler (2 to 8) PLL2 _RCLK _MUX R2 Divider (1 to 4,095) PLL2 _NCLK _MUX N2 Divider (1 to 262,143) Phase Detector PLL2 Clock Distribution Path SPI CPout1 Holdover FB_ MUX SPI Selectable Phase Detector PLL1 CPout2 CLKin0 CLKin0* CLKin0 _DEMUX Internal Dual Core VCO VCO_ MUX CLKin1 Control Registers D SYNC CLKin0 Pulser CLKout0 CLKout0* Div (1 to 1023) SYSREF_MUX SYSREF/SYNC Control Divider (8 to 8191) SYSREF/SYNC Distribution Path Dig. Delay A. Delay CLKout2 CLKout2* Div (1 to 1023) Dig. Delay Dig. Delay A. Delay CLKout4 CLKout4* Div (1 to 1023) Dig. Delay Dig. Delay CLKout13 CLKout13* Div (1 to 1023) CLKout10 CLKout10* A. Delay CLKout11 CLKout11* Div (1 to 1023) CLKout8 CLKout8* A. Delay CLKout9 CLKout9* Div (1 to 1023) CLKout6 CLKout6* A. Delay CLKout7 CLKout7* Dig. Delay Dig. Delay Dig. Delay Dig. Delay CLKout5 CLKout5* A. Delay Dig. Delay Dig. Delay CLKout3 CLKout3* CLKout12 CLKout12* Dig. Delay Dig. Delay CLKout1 CLKout1* Div (1 to 1023) Dig. Delay A. Delay Copyright © 2017, Texas Instruments Incorporated Figure 6. High Level LMK04832 Block Diagram 26 Submit Documentation Feedback Copyright © 2017–2018, Texas Instruments Incorporated Product Folder Links: LMK04832 LMK04832 www.ti.com SNAS688C – FEBRURAY 2017 – REVISED MAY 2018 Functional Block Diagram (continued) CLKou t0, 2, 4, 6, 8, 10, 12 CLKou tX_Y_PD DCL KX_Y_PD Device Clock (DCLK) DCL KX _BYP CLKou tX_ FMT DCL KX_Y_DDL Y_PD CML DCL KX_Y _POL VCO DCL KX_Y_ DDL Y (8 to 102 3) DCL KX_Y_ DIV (1 to 102 3) DCL KX_Y_ HS DCC CLKou tX_ SRC_MUX DCL KX_Y_ DCC DDL YdX_Y_EN DCL Kout6/8 to FB_MUX CLKou tX_Y_ODL SYNC_ DIS_DCL KX_Y CLKou tX_Y_IDL SYS RE F_GBL_PD SDCLKou tY_DIS_MODE SYS RE F/SYNC SCLKX_Y_ DDL Y SCLKX_Y _HS Ana log DLY SCLKX_Y _ADLY_EN SCLKX_Y _POL SYS RE F Clock (SCLK) SCLKX_Y_PD CLKou tY_ SRC_MUX CLKou tY_ FMT SYS RE F_CLR CLKou t1, 3, 5, 7, 9, 11, 13 Legend SPI Re gister SYS RE F/SYNC Clo ck VCO/Distribu tion Clock X = Odd Numbers Y = Even Numbers Copyright © 201 7, Texas Instrumen ts Incorpor ate d Figure 7. Device and SYSREF Clock Output Block Submit Documentation Feedback Copyright © 2017–2018, Texas Instruments Incorporated Product Folder Links: LMK04832 27 LMK04832 SNAS688C – FEBRURAY 2017 – REVISED MAY 2018 www.ti.com Functional Block Diagram (continued) CLKin0 CLKin0_ DEMUX SPI Register: SYNC_EN Must Be Set To Enable Any SYNC/SYSREF Functionality PLL1 D SYNC_PLL1_DLD PLL1_DLD SYNC_PLL2_DLD SYSREF_REQ_EN PLL2_DLD SYNC SYNC _MODE SYNC _POL SYSREF_ MUX D PULSER MODE SYSREF_PULSE_CNT VCO0 VCO1 VCO _MUX SYSREF DDLY SYSREF Divider Pulser SYSREF_PLSR_PD SYNC/SYSREF External VCO SYSREF_PD SYSREF_DDLY_PD DCLKout6 OSCin DCLKout8 SYNC_ DISSYSREF CLKin1 CLKin1_ DEMUX FB_MUX OSCout _MUX OSCout CLKin1 FB_MUX PLL1 DCLKout0, 2, 4, 6, 8, 10, 12 Clock Distribution Path VCO Frequency DDLY (4 to 32) Divider (1 to 32) Analog DLY DCC Output Buffer Digital DLY Analog DLY Output Buffer SYNC_ DISX SYSREF/SYNC Legend SYSREF_CLR SYSREF/SYNC Clock VCO/Distribution Clock SPI Register SDCLKout1, 3, 5, 7, 9, 11, 13 Copyright © 2017, Texas Instruments Incorporated Figure 8. SYNC/SYSREF Clocking Paths 28 Submit Documentation Feedback Copyright © 2017–2018, Texas Instruments Incorporated Product Folder Links: LMK04832 LMK04832 www.ti.com SNAS688C – FEBRURAY 2017 – REVISED MAY 2018 8.3 Feature Description 8.3.1 Synchronizing PLL R Dividers In some cases, it is necessary to synchronize PLL R dividers to enable determinism of clocks outputs to inputs. This typically is required when the fraction Total PLL N divide / Total PLL R divide does not reduce to N / 1 8.3.1.1 PLL1 R Divider Synchronization It is possible to use the CLKin0 or SYNC pin to synchronize the PLL1 R divider. In either case, the PLL1 R divider is armed for reset, then the rising sync edge arrives from either SYNC pin or CLKin0. After the PLL1 R divider is armed, PLL1 is unlocked until the synchronization edge arrives and allows the divider to operate and the PLL to lock. The procedure to synchronize PLL1 R is as follows: 1. Setup device for synchronizing PLL1 R: – PLL1R_SYNC_EN = 0x1 – PLL1R_SYNC_SRC = 0x1 (SYNC pin) or 0x2 (CLKin0) – CLKin0_DEMUX = 0x2 (PLL1) – CLKin1_DEMUX = 0x2 (PLL1) – CLKin0_TYPE = 0x1 (MOS) for DC-coupled or CLKin0_TYPE = 0x0 (Bipolar) for AC-coupled 2. Arm PLL1 R divider for synchronization – PLL1R_RST = 1, then 0. – PLL1 is unlocked. 3. Send rising edge on SYNC pin or CLKin0. – PLL1 R divider is released from reset and PLL1 relocks. It is necessary to meet a setup and hold time when CLKin0 or SYNC pin goes high to ensure deterministic reset of the PLL1 R divider. The SYNC_POL bit has no effect on SYNC polarity for PLL1 R synchronization. 8.3.1.2 PLL2 R Divider Synchronization The SYNC pin must be used to synchronized the PLL2 R divider. When PLL2R_SYNC_EN = 1, as long as the SYNC pin is held high, the PLL2 R divider is held in reset. When the SYNC pin is returned low, the divider is allowed to continue dividing. While PLL2R_SYNC_EN = 1 and SYNC pin is high PLL2 is unlocked. It is necessary to meet a setup and hold time when SYNC pin goes low to ensure deterministic reset of the PLL2 R divider. The SYNC_POL bit has no effect on SYNC polarity for PLL2 R synchronization. Submit Documentation Feedback Copyright © 2017–2018, Texas Instruments Incorporated Product Folder Links: LMK04832 29 LMK04832 SNAS688C – FEBRURAY 2017 – REVISED MAY 2018 www.ti.com Feature Description (continued) 8.3.2 SYNC/SYSREF The SYNC and SYSREF signals share the same SYNC/SYSREF Clock Distribution path. To properly use SYNC and/or SYSREF for JESD204B it is important to understand the SYNC/SYSREF system. Figure 7 illustrates the detailed diagram of a clock output block with SYNC circuitry included. Figure 8 illustrates the interconnects and highlights some important registers used in controlling the device for SYNC/SYSREF purposes. To reset or synchronize a divider, the following conditions must be met: 1. SYNC_EN must be set. This ensures proper operation of the SYNC circuitry. 2. SYSREF_MUX and SYNC_MODE must be set to a proper combination to provide a valid SYNC/SYSREF signal. – If SYSREF block is being used, the SYSREF_PD bit must be clear. – If the SYSREF Pulser is being used, the SYSREF_PLSR_PD bit must be clear. – For each CLKoutX or CLKoutY being used for SYSREF, the respective SCLKX_Y_PD bit must be cleared. 3. DCLKX_Y_DDLY_PD and SYSREF_DDLY_PD bits must be clear to power up the digital delay circuitry used during SYNC to cause deterministic phase between the device clock dividers and the global SYSREF divider. 4. The SYNC_DISX bit must be clear to allow SYNC/SYSREF signal to divider circuit. The SYSREF_MUX register selects the SYNC source which resets the SYSREF/CLKoutX dividers provided the corresponding SYNC_DISX bit is clear. 5. Other bits which impact the operation of SYNC such as SYNC_1SHOT_EN may be set as desired. 6. After these dividers are synchronized, the DCLKX_Y_DDLY_PD and SYSREF_DDLY_PD bits may be set to save current. Clearing them to power up may disrupt the output clock phase. Table 1 illustrates the some possible combinations of SYSREF_MUX and SYNC_MODE. Table 1. Some Possible SYNC Configurations SYNC_MODE SYSREF_MUX SYNC Disabled NAME 0 0 CLKin0_DEMUX ≠ 0 No SYNC will occur. Pin or SPI SYNC 1 0 CLKin0_DEMUX ≠ 0 Basic SYNC functionality, SYNC pin polarity is selected by SYNC_POL. To achieve SYNC through SPI, toggle the SYNC_POL bit. Differential input SYNC X 0 or 1 CLKin0_DEMUX = 0 Differential CLKin0 now operates as SYNC input. JESD204B Pulser on pin transition. 2 2 SYSREF_PULSE_CNT sets pulse count Produce SYSREF_PULSE_CNT programmed number of pulses on pin transition. SYNC_POL can be used to cause SYNC through SPI. JESD204B Pulser on SPI programming. 3 2 SYSREF_PULSE_CNT sets pulse count Programming SYSREF_PULSE_CNT register starts sending the number of pulses. 1 SYSREF operational, SYSREF Divider as required for training frame size. Allows precise SYNC for n-bit frame training patterns for non-JESD converters such as LM97600. 2 SYSREF_REQ_EN = 1 Pulser powered up When SYNC pin is asserted, continuous SYSERF pulses occur. Turning on and off of the pulses is synchronized to prevent runt pulses from occurring on SYSREF. Re-clocked SYNC External SYSREF request Continuous SYSREF (1) 30 1 0 X 3 OTHER SYSREF_PD = 0 SYSREF_DDLY_PD = 0 SYSREF_PLSR_PD = 1 DESCRIPTION Continuous SYSREF signal. (1) SCLKX_Y_PD = 0 as required per SYSREF output. This applies to any SYNC or SYSREF output on SCLKX_Y when SCLKX_Y_MUX = 1 (SYSREF output) Submit Documentation Feedback Copyright © 2017–2018, Texas Instruments Incorporated Product Folder Links: LMK04832 LMK04832 www.ti.com SNAS688C – FEBRURAY 2017 – REVISED MAY 2018 Feature Description (continued) Table 1. Some Possible SYNC Configurations (continued) NAME SYNC_MODE Re-clocked SYSREF distribution SYSREF_MUX 0 0 OTHER DESCRIPTION SYSREF_DDLY_PD = 1 SYSREF_PLSR_PD = 1 SYSREF_PD = 1. Fan-out of CLKin0 reclocked to the clock distribution path. NOTE Because the SYNC/SYSREF signal is reclocked by the Clock Distribution Path, an active clock must be present on the Clock Distribution Path (either from VCO or CLKin1/Fin pins in distribution mode) for SYNC to take effect. NOTE Any device clock divider or the SYSREF divider which does not have the SYNC_DISX bit or SYNC_DISSYSREF bit set will reset while SYNC/SYSREF Distribution Path is high. This is especially important for the SYSREF divider which has the ability to reset itself if the SYNC_DISSYSREF = 0! Be sure to set SYNC_DISX/SYNC_DISSYSREF bits as required. NOTE While using Divide-by-2 or Divide-by-3 for DCLK_X_Y_DIV, SYNC procedure requires to first program Divide-by-4 and then back to Divide-by-2 or Divide-by-3 before doing SYNC. 8.3.3 JEDEC JESD204B 8.3.3.1 How to Enable SYSREF Table 2 summarizes the bits needed to make SYSREF functionality operational. Table 2. SYSREF Bits REGIS TER FIELD VALUE DESCRIPTION 0x140 SYSREF_PD 0 Must be clear, power-up SYSREF circuitry including the SYSREF divider. 0x140 SYSREF_DDLY_ PD 0 Must be clear to power-up digital delay circuitry. Must be powered up during initial SYNC to ensure deterministic timing to other clock dividers. 0x143 SYNC_EN 1 Must be set, enable SYNC. 0x143 SYSREF_CLR 1→0 Do not hold local SYSREF DDLY block in reset except at start. Anytime SYSREF_PD = 1 because of user programming or device RESET, it is necessary to set SYSREF_CLR for 15 VCO clock cycles to clear the local SYSREF digital delay. Once cleared, SYSREF_CLR must be cleared to allow SYSREF to operate. Enabling JESD204B operation involves synchronizing all the clock dividers with the SYSREF divider, then configuring the actual SYSREF functionality. 8.3.3.1.1 Setup of SYSREF Example The following procedure is a programming example for a system which is to operate with a 3000-MHz VCO frequency. Use CLKout0 and CLKout2 to drive converters at 1500 MHz. Use CLKout4 to drive an FPGA at 150 MHz. Synchronize the converters and FPGA using a two SYSREF pulses at 10 MHz. 1. Program registers 0x000 to 0x555 (refer to Recommended Programming Sequence). Key to prepare for SYSREF operations: a. Prepare for manual SYNC: SYNC_POL = 0, SYNC_MODE = 1, SYSREF_MUX = 0 b. Setup output dividers as per example: DCLK0_1_DIV and DCLK2_3_DIV = 2 for frequency of 1500 MHz. DCLK4_5_DIV = 20 for frequency of 150 MHz. Submit Documentation Feedback Copyright © 2017–2018, Texas Instruments Incorporated Product Folder Links: LMK04832 31 LMK04832 SNAS688C – FEBRURAY 2017 – REVISED MAY 2018 2. 3. 4. 5. 6. www.ti.com c. Setup output dividers as per example: SYSREF_DIV = 300 for 10 MHz SYSREF d. Setup SYSREF: SYSREF_PD = 0, SYSREF_DDLY_PD = 0, DCLK0_1_DDLY_PD = 0, DCLK2_3_DDLY_PD = 0, DCLK4_5_DDLY_PD = 0, SYNC_EN = 1, SYSREF_PLSR_PD = 0, SYSREF_PULSE_CNT = 1 (2 pulses). SCLK0_1_PD = 0, SCLK2_3_PD = 0, SCLK4_5_PD = 0 e. Clear Local SYSREF DDLY: SYSREF_CLR = 1. Establish deterministic phase relationships between SYSREF and Device Clock for JESD204B: a. Set device clock and SYSREF divider digital delays: DCLK0_1_DDLY, DCLK2_3_DDLY, DCLK4_5_DDLY, and SYSREF_DDLY. b. Set device clock digital delay half steps: DCLK0_1_HS, DCLK2_3_HS, DCLK4_5_HS. c. Set SYSREF clock digital delay as required to achieve known phase relationships: SCLK0_1_DDLY, SCLK2_3_DDLY, and SCLK4_5_DDLY. If half step adjustments are required SCLK0_1_HS, SCLK2_3_HS, and SCLK4_5_HS. d. To allow SYNC to affect dividers: SYNC_DIS0 = 0, SYNC_DIS2 = 0, SYNC_DIS4 = 0, SYNC_DISSYSREF = 0 e. Perform SYNC by toggling SYNC_POL = 1 then SYNC_POL = 0. Now that dividers are synchronized, disable SYNC from resetting these dividers. It is not desired for SYSREF to reset it's own divider or the dividers of the output clocks. a. Prevent SYNC (SYSREF) from affecting dividers: SYNC_DIS0 = 1, SYNC_DIS2 = 1, SYNC_DIS4 = 1, SYNC_DISSYSREF = 1. Release reset of local SYSREF digital delay. a. SYSREF_CLR = 0. Note this bit needs to be set for only 15 clock distribution path clocks after SYSREF_PD = 0. Set SYSREF operation. a. Allow pin SYNC event to start pulser: SYNC_MODE = 2. b. Select pulser as SYSREF signal: SYSREF_MUX = 2. Complete! Now asserting the SYNC pin, or toggling SYNC_POL will result in a series of 2 SYSREF pulses. 8.3.3.1.2 SYSREF_CLR The local digital delay of the SCLKX_Y_DDLY is implemented as a shift buffer. To ensure no unwanted pulses occur at this SYSREF output at start-up, when using SYSREF, requires clearing the buffers by setting SYSREF_CLR = 1 for 15 VCO clock cycles. After a reset, this bit is set, so it must be cleared before SYSREF output is used. If the SYSREF pulser is used. It is also required to set SYSREF_CLR = 1 for 15 VCO clock cycles after the SYSREF pulser is powered up. 8.3.3.2 SYSREF Modes 8.3.3.2.1 SYSREF Pulser This mode allows for the output of 1, 2, 4, or 8 SYSREF pulses for every SYNC pin event or SPI programming. This implements the gapped periodic functionality of the JEDEC JESD204B specification. When in SYSREF Pulser mode, programming the field SYSREF_PULSE_CNT in register 0x13E will result in the pulser sending the programmed number of pulses. 8.3.3.2.2 Continuous SYSREF This mode allows for continuous output of the SYSREF clock. NOTE Continuous operation of SYSREF is not recommended due to crosstalk from the SYSREF clock to device clock. JESD204B is designed to operate with a single burst of pulses to initialize the system at start-up, after which it is theoretically not required to send another SYSREF because the system will continue to operate with deterministic phases. 32 Submit Documentation Feedback Copyright © 2017–2018, Texas Instruments Incorporated Product Folder Links: LMK04832 LMK04832 www.ti.com SNAS688C – FEBRURAY 2017 – REVISED MAY 2018 8.3.3.2.3 SYSREF Request This mode allows an external source to synchronously turn on or off a continuous stream of SYSREF pulses using the SYNC/SYSREF_REQ pin. Setup the mode by programming SYSREF_REQ_EN = 1 and SYSREF_MUX = 2 (Pulser). The pulser does not need to be powered for this mode of operation. When the SYSREF_REQ pin is asserted, the SYSREF_MUX will synchronously be set to continuous mode providing continuous pulses at the SYSREF frequency until the SYSREF_REQ pin is unasserted and the final SYSREF pulse will complete sending synchronously. 8.3.4 Digital Delay Digital (coarse) delay allows a group of outputs to be delayed by 8 to 1023 clock distribution path cycles. The delay step can be as small as half the period of the clock distribution path cycle by using the DCLKX_Y_HS bit. There are two different ways to use the digital delay: 1. Fixed digital delay 2. Dynamic digital delay In both delay modes, the regular clock divider is substituted with an alternative divide value. 8.3.4.1 Fixed Digital Delay Fixed digital delay value takes effect on the clock outputs after a SYNC event. As such, the outputs will be LOW for a while during the SYNC event. Applications that cannot accept clock breakup when adjusting digital delay during application run time should use dynamic digital delay to adjust phase. 8.3.4.1.1 Fixed Digital Delay Example Assuming the device already has the following initial configurations, and the application should delay CLKout2 by one VCO cycle compared to CLKout0. • VCO frequency = 2949.12 MHz • CLKout0 = 368.64 MHz (DCLK0_1_DIV = 8, CLKout0_SRC_MUX = 0 (Device Clock)) • CLKout2 = 368.64 MHz (DCLK2_3_DIV = 8, CLKout2_SRC_MUX = 0 (Device Clock)) The following steps should be followed 1. Set DCLK0_1_DDLY = 8 and DCLK2_3_DDLY = 9. Static delay for each clock. 2. Set DCLK0_1_DDLY_PD = 0 and DCLK2_3_DDLY_PD = 0. Power up the digital delay circuit. 3. Set SYNC_DIS0 = 0 and SYNC_DIS2 = 0. Allow the outputs to be synchronized. 4. Perform SYNC by asserting, then unasserting SYNC. Either by using SYNC_POL bit or the SYNC pin. 5. Now that the SYNC is complete, to save power it is allowable to power down DCLK0_1_DDLY_PD = 1 and/or DCLK2_3_DDLY_PD = 1. 6. Set SYNC_DIS0 = 1 and SYNC_DIS2 = 1. Prevent the output from being synchronized, very important for steady-state operation when using JESD204B. No CLKout during SYNC CLKout0 368.64 MHz CLKout2 368.64 MHz SYNC event 1 VCO cycle delay Figure 9. Fixed Digital Delay Example Submit Documentation Feedback Copyright © 2017–2018, Texas Instruments Incorporated Product Folder Links: LMK04832 33 LMK04832 SNAS688C – FEBRURAY 2017 – REVISED MAY 2018 www.ti.com 8.3.4.2 Dynamic Digital Delay Dynamic digital delay allows the phase of clocks to be changed with respect to each other with little impact to the clock signal. For the device clock dividers this is accomplished by substituting the regular clock divider with an alternate divide value of one larger than the regular divider for one cycle. This substitution will occur a number of times equal to the value programmed into the DDLYd_STEP_CNT field for all outputs with DDLYdX_EN = 1. For the SYSREF divider an alternate divide value will be substituted for the regular divide value. This substitution will occur a number of times equal to the value programmed into the DDLYd_STEP_CNT if DDLYd_SYSREF_EN = 1. To achieve one cycle delay as is done for the device clock dividers, set the SYSREF_DDLY value to one greater than SYSREF_DIV+SYSREF_DIV/2. For example, for a SYSREF divider of 100, to achieve 1 cycle delay, SYSREF_DIV = 100 + 50 + 1 = 151. While using the Dynamic Digital Delay feature, CLKin_OVERRIDE must be set to 0. • By programming a larger alternate divider (delay) value, the phase of the adjusted outputs are delayed with respect to the other clocks. • By programming a smaller alternate divider (delay) value, the phase of the adjusted outputs are advanced with respect to the other clocks. 8.3.4.3 Single and Multiple Dynamic Digital Delay Example In this example, two separate adjustments are made to the device clocks. In the first adjustment, a single delay of 1 VCO cycle occurs between CLKout2 and CLKout0. In the second adjustment, two delays of 1 VCO cycle occur between CLKout2 and CLKout0. At this point in the example, CLKout2 is delayed 3 VCO cycles behind CLKout0. Assuming the device already has the following initial configurations: • VCO frequency: 2949.12 MHz • CLKout0 = 368.64 MHz, DCLK0_1_DIV = 8 • CLKout2 = 368.64 MHz, DCLK2_3_DIV = 8 The following steps illustrate the example above: 1. Set DCLK2_3_DDLY = 4. First part of delay for CLKout2. 2. Set DCLK2_3_DDLY_PD = 0. Enable the digital delay for CLKout2. 3. Set DDLYd0_EN = 0 and DDLYd2_EN = 1. Enable dynamic digital delay for CLKout2 but not CLKout0. 4. Set DDLYd_STEP_CNT = 1. This begins the first adjustment. Before step 4, CLKout2 clock edge is aligned with CLKout0. After step 4, CLKout2 counts nine clock distribution path cycles to the next rising edge, one greater than the divider value, effectively delaying CLKout2 by one VCO cycle with respect to CLKout0. This is the first adjustment. 5. Set DDLYd_STEP_CNT = 2. This begins the second adjustment. Before step 5, CLKout2 clock edge was delayed 1 clock distribution path cycle from DCLKout0. After step 5, CLKout2 counts nine clock distribution path cycles twice, each time one greater than the divide value, effectively delaying CLKout2 by two clock distribution path cycles with respect to CLKout0. This is the second adjustment. 34 Submit Documentation Feedback Copyright © 2017–2018, Texas Instruments Incorporated Product Folder Links: LMK04832 LMK04832 www.ti.com SNAS688C – FEBRURAY 2017 – REVISED MAY 2018 VCO 2949.12 MHz CLKout0 368.64 MHz CLKout2 368.64 MHz First Adjustment DCLK2_3_DIV + 1 CLKout2 368.64 MHz Second Adjustment DCLK2_3_DIV + 1 DCLK2_3_DIV + 1 Figure 10. Single and Multiple Adjustment Dynamic Digital Delay Example 8.3.5 SYSREF to Device Clock Alignment To ensure proper JESD204B operation, the timing relationship between the SYSREF and the Device clock must be adjusted for optimum setup and hold time as shown in Figure 11. The global SYSREF digital delay (SYSREF_DDLY), local SYSREF digital delay (SCLKX_Y_DDLY), local SYSREF half step (SCLKX_Y_HS), and local SYSREF analog delay (SCLKX_Y_ADLY, SCLK2_3_ADLY_EN) can be adjusted to provide the required setup and hold time between SYSREF and Device Clock. It is also possible to adjust the device clock digital delay (DCLKX_Y_DDLY) and half step (DCLK0_1_HS, DCLK0_1_DCC) to adjust phase with respect to SYSREF. Figure 11. SYSREF to Device Clock Timing alignment Depending on the DCLKout_X path settings, local SCLK_X_Y_DDLY might need adjustment factor. Following equation can be used to calculate the required Digital Delay Values to align SYSREF to the corresponding DCLKout: SYSREF_DDLY = DCLKX_Y_DDLY - 1 + DCLK_DIV_ADJUST + DCLK_HS_ADJUST - SCLK_X_Y_DDLY (1) SYSREF_DDLY > 7; SCLK_X_Y_DDLY > 1. Table 3. DCLK_DIV_ADJUST DCLKX_Y_DIV DCLK_DIV_ADJUST >6 0 6 -1 Submit Documentation Feedback Copyright © 2017–2018, Texas Instruments Incorporated Product Folder Links: LMK04832 35 LMK04832 SNAS688C – FEBRURAY 2017 – REVISED MAY 2018 www.ti.com Table 3. DCLK_DIV_ADJUST (continued) DCLKX_Y_DIV DCLK_DIV_ADJUST 5 3 4 (1) 0 3 (1) -2 2 (1) -2 Refer to the SYNC requirement SYNC/SYSREF Table 4. DCLK_HS_ADJUST DCLK & HS DCLK_HS_ADJUST 0 0 1 1 For example, DCLKX_Y_DIV = 32, DCLKX_Y_DDLY = 10,DCC&HS = 1; SYSREF_DDLY=10 - 1 + 0 + 1 - 2 = 8 36 Submit Documentation Feedback Copyright © 2017–2018, Texas Instruments Incorporated Product Folder Links: LMK04832 LMK04832 www.ti.com SNAS688C – FEBRURAY 2017 – REVISED MAY 2018 8.3.6 Input Clock Switching Manual, pin select, and automatic are three different kinds clock input switching modes can be selected according to the combination of bits as illustrated in Figure 12. Input Clock Select Yes CLKin_SEL_ AUTO_EN Active CLKin is set Auto Mode State Machine Yes No CLKin_SEL_ PIN_EN It is required for CLKin1 to be selected for distribution mode. Recommend using CLKin_SEL_MANUAL No Active CLKin is set by CLKin_SEL_MANUAL Yes CLKin_SEL_ PIN_POL Active CLKin is set by CLKin_SEL# and Status_LD1 pins, inverted. No Active CLKin is set by CLKin_SEL# and Status_LD1 pins. Figure 12. CLKinX Input Reference The following sections provide information about how the active input clock is selected and what causes a switching event in the various clock input selection modes. 8.3.6.1 Input Clock Switching - Manual Mode When CLKin_SEL_AUTO_EN = 0 and CLKin_SEL_PIN_EN = 0, the active CLKin is selected by CLKin_SEL_MANUAL. Programming a value of 0, 1, or 2 to CLKin_SEL_MANUAL causes CLKin0, CLKin1, or CLKin2, respectively, to be the selected active input clock. In this mode, the EN_CLKinX bits are overriden such that the CLKinX buffer operates even if CLKinX is disabled with EN_CLKinX = 0. If holdover is entered in this mode by setting CLKin_SEL_MANUAL = 3, then the device will re-lock to the selected CLKin upon holdover exit. 8.3.6.2 Input Clock Switching - Pin Select Mode When CLKin_SEL_AUTO_EN = 0 and CLKin_SEL_PIN_EN = 1, the active CLKin is selected by the CLKin_SEL# and Status_LD1 pins. Configuring Pin Select Mode The CLKin_SEL0_TYPE must be programmed to an input value for the CLKin_SEL0 pin to function as an input for pin select mode. The CLKin_SEL1_TYPE must be programmed to an input value for the CLKin_SEL1 pin to function as an input for pin select mode. The polarity of the clock input select pins can be inverted with the CLKin_SEL_PIN_POL bit. The pin select mode overrides the EN_CLKinX bits such that the CLKinX buffer operates even if CLKinX is disabled with EN_CLKinX = 0. To switch as fast as possible, keep the clock input buffers enabled (EN_CLKinX = 1) that could be switched to. Submit Documentation Feedback Copyright © 2017–2018, Texas Instruments Incorporated Product Folder Links: LMK04832 37 LMK04832 SNAS688C – FEBRURAY 2017 – REVISED MAY 2018 www.ti.com 8.3.6.3 Input Clock Switching - Automatic Mode When CLKin_SEL_AUTO_EN = 1, LOS_EN = 1, and HOLDOVER_EXIT_MODE = 0 (Exit based on LOS), the active clock is selected in priority order with CLKin0 being the highest priority, CLKin1 second, and CLKin2 third. For a clock input to be eligible to be switched to, it must be enabled using EN_CLKinX. The LOS_TIMEOUT should also be set to a frequency below the input frequency. To ensure LOS is valid for AC-coupled inputs, the MOS mode must be set for the CLKin and no termination is allowed to be between the pins unless DC blocked, for example, no 100-Ω termination across CLKin0 and CLKin0* pins on IC side of AC-coupling capacitors. 8.3.7 Digital Lock Detect Both PLL1 and PLL2 support digital lock detect. Digital lock detect compares the phase between the reference path (R) and the feedback path (N) of the PLL. When the time error, which is phase error, between the two signals is less than a specified window size (ε) a lock detect count increments. When the lock detect count reaches a user specified value, PLL1_DLD_CNT or PLL2_DLD_CNT, lock detect is asserted true. Once digital lock detect is true, a single phase comparison outside the specified window will cause digital lock detect to be asserted false. This is illustrated in Figure 13. NO START PLLX Lock Detected = False Lock Count = 0 NO YES Phase Error < g Increment PLLX Lock Count PLLX Lock Count = PLLX_DLD_CNT NO YES PLLX Lock Detected = True Phase Error < g YES Figure 13. Digital Lock Detect Flowchart This incremental lock detect count feature functions as a digital filter to ensure that lock detect is not asserted for only a brief time when the phases of R and N are within the specified tolerance for only a brief time during initial phase lock. See Digital Lock Detect Frequency Accuracy for more detailed information on programming the registers to achieve a specified frequency accuracy in ppm with lock detect. The digital lock detect signal can be monitored on the Status_LD1 or Status_LD2 pin. The pin may be programmed to output the status of lock detect for PLL1, PLL2, or both PLL1 and PLL2. 8.3.7.1 Calculating Digital Lock Detect Frequency Accuracy See Digital Lock Detect Frequency Accuracy for more detailed information on programming the registers to achieve a specified frequency accuracy in ppm with lock detect. The digital lock detect feature can also be used with holdover to automatically exit holdover mode. See Exiting Holdover for more info. 38 Submit Documentation Feedback Copyright © 2017–2018, Texas Instruments Incorporated Product Folder Links: LMK04832 LMK04832 www.ti.com SNAS688C – FEBRURAY 2017 – REVISED MAY 2018 8.3.8 Holdover Holdover mode causes PLL2 to stay locked on frequency with minimal frequency drift when an input clock reference to PLL1 becomes invalid. While in holdover mode, the PLL1 charge pump is TRI-STATED and a fixed tuning voltage is set on CPout1 to operate PLL1 in open loop. 8.3.8.1 Enable Holdover Program HOLDOVER_EN = 1 to enable holdover mode. Holdover mode can be configured to set the CPout1 voltage upon holdover entry to a fixed user defined voltage (EN_MAN_DAC = 1) or a tracked voltage (EN_MAN_DAC = 0). 8.3.8.1.1 Fixed (Manual) CPout1 Holdover Mode By programming MAN_DAC_EN = 1, then the MAN_DAC value will be set on the CPout1 pin during holdover. The user can optionally enable CPout1 voltage tracking (TRACK_EN = 1), read back the tracked DAC value, then re-program MAN_DAC value to a user desired value based on information from previous DAC read backs. This allows the most user control over the holdover CPout1 voltage, but also requires more user intervention. 8.3.8.1.2 Tracked CPout1 Holdover Mode By programming MAN_DAC_EN = 0 and TRACK_EN = 1, the tracked voltage of CPout1 is set on the CPout1 pin during holdover. When the DAC has acquired the current CPout1 voltage, the DAC_Locked signal is set which may be observed on Status_LD1 or Status_LD2 pins by programming PLL1_LD_MUX or PLL2_LD_MUX, respectively. Updates to the DAC value for the Tracked CPout1 sub-mode occurs at the rate of the PLL1 phase detector frequency divided by (DAC_CLK_MULT × DAC_CLK_CNTR). The DAC update rate should be programmed for ≤ 100 kHz to ensure DAC holdover accuracy. The ability to program slow DAC update rates, for example one DAC update per 4.08 seconds when using 1024kHz PLL1 phase detector frequency with DAC_CLK_MULT = 16,384 and DAC_CLK_CNTR = 255, allows the device to look-back and set CPout1 at a previous good CPout1 tuning voltage values before the event which caused holdover to occur. The current voltage of DAC value can be read back using RB_DAC_VALUE, see RB_DAC_VALUE. 8.3.8.2 During Holdover PLL1 is run in open-loop mode. • PLL1 charge pump is set to TRI-STATE. • PLL1 DLD is unasserted. • The HOLDOVER status is asserted • During holdover, if PLL2 was locked prior to entry of holdover mode, PLL2 DLD continues to be asserted. • CPout1 voltage is set to: – a voltage set in the MAN_DAC register (MAN_DAC_EN = 1). – a voltage determined to be the last valid CPout1 voltage (MAN_DAC_EN = 0). • PLL1 attempts to lock with the active clock input. The HOLDOVER status signal can be monitored on the Status_LD1 or Status_LD2 pin by programming the PLL1_DLD_MUX or PLL2_DLD_MUX register to Holdover Status. Submit Documentation Feedback Copyright © 2017–2018, Texas Instruments Incorporated Product Folder Links: LMK04832 39 LMK04832 SNAS688C – FEBRURAY 2017 – REVISED MAY 2018 www.ti.com 8.3.8.3 Exiting Holdover Holdover mode can be exited in one of two ways. • Manually, by programming the device from the host. • Automatically, when the LOS signal unasserts for a clock that provides a valid input to PLL1. 8.3.8.4 Holdover Frequency Accuracy and DAC Performance When in holdover mode, PLL1 runs in open loop and the DAC sets the CPout1 voltage. If fixed CPout1 mode is used, then the output of the DAC is dependant upon the MAN_DAC register. If tracked CPout1 mode is used, then the output of the DAC is approximately the same voltage at the CPout1 pin before holdover mode was entered. When using Tracked mode and MAN_DAC_EN = 1, the DAC value during holdover is loaded with the programmed value in MAN_DAC and not the tracked value. When in Tracked CPout1 mode, the DAC has a worst-case tracking error of ±2 LSBs once PLL1 tuning voltage is acquired. The step size is approximately 3.2 mV, therefore the VCXO frequency error during holdover mode caused by the DAC tracking accuracy is ±6.4 mV × Kv, where Kv is the tuning sensitivity of the VCXO in use. Therefore, the accuracy of the system when in holdover mode in ppm is: Holdover accuracy (ppm) = ± 6.4 mV × Kv × 1e6 VCXO Frequency (2) As an example, consider a system with a 19.2-MHz clock input, a 153.6-MHz VCXO with a Kv of 17 kHz/V. The accuracy of the system in holdover in ppm is: ±0.71 ppm = ±6.4 mV × 17 kHz/V × 1e6 / 153.6 MHz (3) It is important to account for this frequency error when determining the allowable frequency error window to cause holdover mode to exit. 8.3.9 PLL2 Loop Filter PLL2 has an integrated loop filter of C1i = 60 pF, R3 = 2400 Ω, C3 = 50 pF, R4 = 200 Ω and C4 = 10 pF as shown in Figure 14. Loop filter components C1, C2, and R2 can be solved using TI software. See Device Support for more information. Figure 14. PLL2 On-Chip Loop Filter 40 Submit Documentation Feedback Copyright © 2017–2018, Texas Instruments Incorporated Product Folder Links: LMK04832 LMK04832 www.ti.com SNAS688C – FEBRURAY 2017 – REVISED MAY 2018 8.4 Device Functional Modes The following section describes the settings to enable various modes of operation for the LMK04832. The LMK04832 is a flexible device that can be configured for many different use cases. The following simplified block diagrams help show the user the different use cases of the device. 8.4.1 DUAL PLL 8.4.1.1 Dual Loop Figure 15 illustrates the typical use case of the LMK04832 in dual loop mode. In dual loop mode, the reference to PLL1 is from CLKin0, CLKin1, or CLKin2. An external VCXO is used to provide feedback for the first PLL and a reference to the second PLL. This first PLL cleans the jitter with the VCXO by using a narrow loop bandwidth. The VCXO may be buffered through the OSCout port. The VCXO is used as the reference to PLL2 and may be doubled using the frequency doubler. The internal VCO drives up to seven divide/delay blocks which drive up to 14 clock outputs. Hitless switching and holdover functionality are optionally available when the input reference clock is lost. Holdover works by forcing a DAC voltage to the tuning voltage of the VCXO. It is also possible to use an external VCO in place of PLL2's internal VCO. In this case one less CLKin is available as a reference as CLKin1 is used for external Fin input. PLL1 PLL2 R N Phase Detector PLL1 External VCXO External Loop Filter OSCout OSCout* OSCin CLKinX CLKinX* Up to 3 inputs CPout1 Up to 1 OSCout External Loop Filter CPout2 Dual Internal VCOs R Input Buffer N Phase Detector PLL2 7 blocks Device Clock Divider Digital Delay Up to 14 Device or SYSREF Clocks CLKoutX CLKoutX* 7 blocks Global SYSREF Divider and DDLY SYSREF Digital Delay Analog Delay CLKoutY CLKoutY* LMK04832 Copyright © 2017, Texas Instruments Incorporated Figure 15. Simplified Functional Block Diagram for Dual Loop Mode 8.4.1.2 Dual Loop With Cascaded 0-Delay Figure 16 illustrates the use case of cascaded 0-delay dual loop mode. This configuration differs from dual loop mode Figure 15 in that the feedback for PLL2 is driven by a clock output instead of the VCO output directly. It is also possible to use an external VCO in place of the internal VCO of the PLL2, but one less CLKin is available as a reference and the external 0-delay feedback is not available. Submit Documentation Feedback Copyright © 2017–2018, Texas Instruments Incorporated Product Folder Links: LMK04832 41 LMK04832 SNAS688C – FEBRURAY 2017 – REVISED MAY 2018 www.ti.com Device Functional Modes (continued) PLL1 PLL2 R N Phase Detector PLL1 External VCXO External Loop Filter OSCout OSCout* OSCin CLKinX CLKinX* Up to 3 inputs CPout1 Up to 1 OSCout External Loop Filter CPout2 Dual Internal VCOs R Input Buffer N Phase Detector PLL2 7 blocks Device Clock Divider Digital Delay Up to 14 Device or SYSREF Clocks CLKoutX CLKoutX* 7 blocks Global SYSREF Divider and DDLY SYSREF Digital Delay Analog Delay CLKoutY CLKoutY* Internal or external loopback, user programmable LMK04832 Copyright © 2017, Texas Instruments Incorporated Figure 16. Simplified Functional Block Diagram for Cascaded 0-Delay Dual Loop Mode 8.4.1.3 Dual Loop With Nested 0-Delay Figure 17 illustrates the use case of nested 0-delay dual loop mode. This configuration is similar to the dual PLL in Figure 15 except that the feedback to the first PLL is driven by a clock output. The PLL2 reference OSCin is not deterministic to the CLKin or feedback clock. PLL1 PLL2 R N Phase Detector PLL1 External VCXO External Loop Filter OSCout OSCout* OSCin CLKinX CLKinX* Up to 3 inputs CPout1 Up to 1 OSCout External Loop Filter CPout2 Dual Internal VCOs R Input Buffer N Phase Detector PLL2 7 blocks Device Clock Divider Digital Delay Up to 14 Device or SYSREF Clocks CLKoutX CLKoutX* 7 blocks Internal or external loopback, user programmable Global SYSREF Divider and DDLY SYSREF Digital Delay Analog Delay CLKoutY CLKoutY* LMK04832 Copyright © 2017, Texas Instruments Incorporated Figure 17. Simplified Functional Block Diagram for Nested 0-Delay Dual Loop Mode 42 Submit Documentation Feedback Copyright © 2017–2018, Texas Instruments Incorporated Product Folder Links: LMK04832 LMK04832 www.ti.com SNAS688C – FEBRURAY 2017 – REVISED MAY 2018 Device Functional Modes (continued) 8.4.2 Single PLL 8.4.2.1 PLL2 Single Loop Figure 18 illustrates the use case of PLL2 single loop mode. When used with a high-frequency clean reference performance as good as dual loop mode may be achieved. Traditionally the OSCin is used as a reference to PLL2, but it is also possible to use CLKinX as a reference to PLL2. PLL2 Up to 1 OSCout OSCout OSCout* Up to 4 inputs External Loop Filter Up to 14 Device or SYSREF Clocks CPout2 OSCin OSCin* 7 blocks Dual Internal VCOs R Device Clock Divider Digital Delay Phase Detector PLL2 Input Buffer N CLKoutX CLKoutX* 7 blocks CLKinX CLKinX* SYSREF Digital Delay Analog Delay Global SYSREF Divider and DDLY CLKoutY CLKoutY* LMK04832 Copyright © 2017, Texas Instruments Incorporated Figure 18. Simplified Functional Block Diagram for Single Loop Mode 8.4.2.2 PLL2 With External VCO Adding an external VCO is possible using the CLKin1/Fin input port. The input may be single-ended or differential. At high frequency the input impedance to Fin is low, a resistive pad is recommended for matching. External VCO PLL2 Up to 1 OSCout External Loop Filter OSCout OSCout* Up to 3 inputs CPout2 CLKin1/Fin CLKin1*/Fin* 7 blocks OSCin OSCin* R Input Buffer N Device Clock Divider Digital Delay Phase Detector PLL2 Up to 14 Device or SYSREF Clocks CLKoutX CLKoutX* 7 blocks CLKinX CLKinX* SYSREF Digital Delay Analog Delay Global SYSREF Divider and DDLY CLKoutY CLKoutY* LMK04832 Copyright © 2017, Texas Instruments Incorporated Figure 19. Simplified Functional Block Diagram for Single Loop Mode With External VCO Submit Documentation Feedback Copyright © 2017–2018, Texas Instruments Incorporated Product Folder Links: LMK04832 43 LMK04832 SNAS688C – FEBRURAY 2017 – REVISED MAY 2018 www.ti.com Device Functional Modes (continued) 8.4.3 Distribution Mode Figure 20 illustrates the use case of distribution mode. As in all the other use cases, OSCin to OSCout can be used as a buffer to OSCin or from clock distribution path via CLKout6, CLKout8, or the SYSREF divider. At high frequency, the input impedance to Fin is low and a resistive pad is recommended for matching. OSCin OSCin* 7 blocks CLKout6/8 Device Clock Divider Digital Delay CLKin1/Fin CLKin1*/Fin* OSCout OSCout* CLKoutX CLKoutX* 7 blocks Global SYSREF Divider and DDLY CLKin0 CLKin0* SYSREF Digital Delay Analog Delay Up to 14 Device or SYSREF Clocks CLKoutY CLKoutY* LMK04832 Copyright © 2017, Texas Instruments Incorporated Figure 20. Simplified Functional Block Diagram for Distribution Mode 8.5 Programming The LMK04832 device is programmed using 24-bit registers. Each register consists of a 1-bit command field (R/W), a 15-bit address field (A14 to A0) and a 8-bit data field (D7 to D0). The contents of each register is clocked in MSB first (R/W), and the LSB (D0) last. During programming, the CS* signal is held low. The serial data is clocked in on the rising edge of the SCK signal. After the LSB is clocked in, the CS* signal goes high to latch the contents into the shift register. It is recommended to program registers in numeric order (for example, 0x000 to 0x555 with exceptions noted in the Recommended Programming Sequence). Each register consists of one or more fields which control the device functionality. See the Electrical Characteristics section and Figure 1 for timing details. 8.5.1 Recommended Programming Sequence Registers are generally programmed in numeric order with 0x000 being the first and 0x555 being the last register programmed. The recommended programming sequence from POR involves: 1. Program register 0x000 with RESET = 1. 2. Program defined registers from 0x000 to 0x165. 3. If PLL2 is used, program 0x173 with PLL2_PD and PLL2_PRE_PD clear to allow PLL2 to lock after PLL2_N is programmed. 4. Continue programming defined registers from 0x166 to 0x555. NOTE When using the internal VCO, PLL2_N registers 0x166, 0x167, and 0x168 must be programmed after other PLL2 dividers are programed to ensure proper VCO frequency calibration. This is also true for PLL2_N_CAL registers 0x163, 0x164, 0x165 when PLL2_NCLK_MUX = 1. So if any divider such as PLL2_R is altered to change the VCO frequency, the VCO calibration must be run again by programming PLL2_N. Power up PLL2 by setting PLL2_PRE_PD = 0 and PLL2_PD = 0 in register 0x173 before programming PLL2_N. 44 Submit Documentation Feedback Copyright © 2017–2018, Texas Instruments Incorporated Product Folder Links: LMK04832 LMK04832 www.ti.com SNAS688C – FEBRURAY 2017 – REVISED MAY 2018 8.6 Register Maps 8.6.1 Register Map for Device Programming Table 5 provides the register map for device programming. Any register can be read from the same data address it is written to. Table 5. LMK04832 Register Map ADDRESS [14:0] 23:8 DATA[7:0] 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 POWER DOWN 0x000 RESET 0 0 SPI_3WIRE _DIS 0x002 0 0 0 0 0x003 ID_DEVICE_TYPE 0x004 ID_PROD[15:8] 0x005 ID_PROD[7:0] 0x006 ID_MASKREV 0x00C ID_VNDR[15:8] 0x00D ID_VNDR[7:0] 0x100 DCLK0_1_DIV[7:0] 0x101 DCLK0_1_DDLY[7:0] 0x102 CLKout0_1_PD CLKout0_1_OD L 0x103 0 1 CLKout0_SRC_ MUX DCLK0_1_PD 0x104 0 0 CLKout1_SRC_ MUX SCLK0_1_PD 0x105 0 0 SCLK0_1_ADL Y_EN 0x106 0 0 0 0x107 CLKout0_1_IDL DCLK0_1_DDL Y_PD DCLK0_1_BYP DCLK0_1_DIV[9:8] DCLK0_1_DCC SCLK0_1_DIS_MODE DCLK0_1_POL DCLK0_1_HS SCLK0_1_POL SCLK0_1_HS SCLK0_1_ADLY 0 SCLK0_1_DDLY CLKout1_FMT CLKout0_FMT 0x108 DCLK2_3_DIV[7:0] 0x109 DCLK2_3_DDLY[7:0] 0x10A CLKout2_3_PD CLKout2_3_OD L 0x10B 0 1 CLKout2_SRC_ MUX DCLK2_3_PD 0x10C 0 0 CLKout3_SRC_ MUX SCLK2_3_PD 0x10D 0 0 SCLK2_3_ADL Y_EN 0x10E 0 0 0x10F CLKout2_3_IDL DCLK2_3_DDL Y_PD 0 DCLK2_3_DDLY[9:8] DCLK2_3_BYP DCLK2_3_DIV[9:8] DCLK2_3_DCC SCLK2_3_DIS_MODE DCLK2_3_POL DCLK2_3_HS SCLK2_3_POL SCLK2_3_HS SCLK2_3_ADLY 0 SCLK2_3_DDLY CLKout3_FMT CLKout2_FMT 0x110 DCLK4_5_DIV[7:0] 0x111 DCLK4_5_DDLY[7:0] 0x112 CLKout4_5_PD CLKout4_5_OD L 0x113 0 1 CLKout4_SRC_ MUX DCLK4_5_PD 0x114 0 0 CLKout5_SRC_ MUX SCLK4_5_PD 0x115 0 0 SCLK4_5_ADL Y_EN 0x116 0 0 0x117 DCLK0_1_DDLY[9:8] CLKout4_5_IDL DCLK4_5_DDL Y_PD 0 DCLK4_5_DDLY[9:8] DCLK4_5_BYP DCLK4_5_DIV[9:8] DCLK4_5_DCC SCLK4_5_DIS_MODE DCLK4_5_POL DCLK4_5_HS SCLK4_5_POL SCLK4_5_HS SCLK4_5_ADLY 0 CLKout5_FMT SCLK4_5_DDLY CLKout4_FMT 0x118 DCLK6_7_DIV[7:0] 0x119 DCLK6_7_DDLY[7:0] Submit Documentation Feedback Copyright © 2017–2018, Texas Instruments Incorporated Product Folder Links: LMK04832 45 LMK04832 SNAS688C – FEBRURAY 2017 – REVISED MAY 2018 www.ti.com Register Maps (continued) Table 5. LMK04832 Register Map (continued) ADDRESS [14:0] 23:8 DATA[7:0] 7 6 5 4 0x11A CLKout6_7_PD CLKout6_7_OD L CLKout6_7_IDL DCLK6_7_DDL Y_PD 0x11B 0 1 CLKout6_SRC_ MUX DCLK6_7_PD 0x11C 0 0 CLKout7_SRC_ MUX SCLK6_7_PD 0x11D 0 0 SCLK6_7_ADL Y_EN 0x11E 0 0 0x11F 0 DCLK6_7_DIV[9:8] DCLK6_7_DCC SCLK6_7_DIS_MODE DCLK6_7_POL DCLK6_7_HS SCLK6_7_POL SCLK6_7_HS SCLK6_7_DDLY CLKout6_FMT DCLK8_9_DIV[7:0] DCLK8_9_DDLY[7:0] 0x122 CLKout8_9_PD 0x123 0 1 CLKout8_SRC_ MUX DCLK8_9_PD 0x124 0 0 CLKout9_SRC_ MUX SCLK8_9_PD 0x125 0 0 SCLK8_9_ADL Y_EN 0x126 0 0 0x127 CLKout8_9_IDL DCLK8_9_DDL Y_PD 0 DCLK8_9_DDLY[9:8] DCLK8_9_BYP DCLK8_9_DIV[9:8] DCLK8_9_DCC SCLK8_9_DIS_MODE DCLK8_9_POL DCLK8_9_HS SCLK8_9_POL SCLK8_9_HS SCLK8_9_ADLY 0 SCLK8_9_DDLY CLKout9_FMT CLKout8_FMT 0x128 DCLK10_11_DIV[7:0] 0x129 DCLK10_11_DDLY[7:0] 0x12A CLKout10_11_P D CLKout10_11_ ODL CLKout10_11_I DL DCLK10_11_D DLY_PD 0x12B 0 1 CLKout10_SRC _MUX DCLK10_11_PD 0x12C 0 0 CLKout11_SRC _MUX SCLK10_11_PD 0x12D 0 0 SCLK10_11_AD LY_EN 0x12E 0 0 0x12F 0 DCLK10_11_DDLY[9:8] DCLK10_11_BY P DCLK10_11_DIV[9:8] DCLK10_11_D CC SCLK10_11_DIS_MODE DCLK10_11_P OL DCLK10_11_HS SCLK10_11_P OL SCLK10_11_HS SCLK10_11_ADLY 0 SCLK10_11_DDLY CLKout11_FMT CLKout10_FMT 0x130 DCLK12_13_DIV[7:0] 0x131 DCLK12_13_DDLY[7:0] 0x132 CLKout12_13_P D CLKout12_13_ ODL CLKout12_13_I DL DCLK12_13_D DLY_PD 0x133 0 1 CLKout12_SRC _MUX DCLK12_13_PD 0x134 0 0 CLKout13_SRC _MUX SCLK12_13_PD 0x135 0 0 SCLK12_13_AD LY_EN 0x136 0 0 0x137 0 DCLK12_13_DDLY[9:8] DCLK12_13_BY P 0 DCLK12_13_DIV[9:8] DCLK12_13_D CC SCLK12_13_DIS_MODE DCLK12_13_P OL DCLK12_13_HS SCLK12_13_P OL SCLK12_13_HS SCLK12_13_ADLY 0 SCLK12_13_DDLY CLKout13_FMT CLKout12_FMT VCO_MUX OSCout_MUX 0x139 0 0 0 0x13A 0 0 0 0x13B OSCout_FMT SYSREF_REQ_ SYNC_BYPASS EN 0 SYSREF_MUX SYSREF_DIV[12:8] SYSREF_DIV[7:0] 0 0 0 0 0 0 0x13D 46 DCLK6_7_BYP 0 SCLK6_7_ADLY CLKout8_9_OD L 0x13E 1 DCLK6_7_DDLY[9:8] 0 0x121 0x13C 2 CLKout7_FMT 0x120 0x138 3 SYSREF_DDLY[12:8] SYSREF_DDLY[7:0] 0 0 Submit Documentation Feedback SYSREF_PULSE_CNT Copyright © 2017–2018, Texas Instruments Incorporated Product Folder Links: LMK04832 LMK04832 www.ti.com SNAS688C – FEBRURAY 2017 – REVISED MAY 2018 Register Maps (continued) Table 5. LMK04832 Register Map (continued) ADDRESS [14:0] DATA[7:0] 23:8 7 6 5 0x13F PLL2_RCLK_ MUX 0 PLL2_NCLK_ MUX 4 0x140 PLL1_PD VCO_LDO_PD VCO_PD OSCin_PD SYSREF_GBL_ PD SYSREF_PD SYSREF_DDLY _PD SYSREF_PLSR _PD 0x141 DDLYd_ SYSREF_EN DDLYd12_EN DDLYd10_EN DDLYd8_EN DDLYd6_EN DDLYd4_EN DDLYd2_EN DDLYd0_EN 0x143 SYSREF_CLR SYNC_1SHOT_ EN SYNC_POL SYNC_EN SYNC_PLL2_ DLD SYNC_PLL1_ DLD 0x144 SYNC_DISSYS REF SYNC_DIS12 SYNC_DIS10 SYNC_DIS8 SYNC_DIS6 SYNC_DIS4 SYNC_DIS2 SYNC_DIS0 0x145 0 PLL1R_SYNC_ EN PLL2R_SYNC_ EN 0 0 0 CLKin0_EN CLKin2_TYPE CLKin1_TYPE CLKin0_TYPE 0x142 0x146 3 2 1 PLL1_NCLK_MUX 0 FB_MUX FB_MUX_EN DDLYd_STEP_CNT CLKin_SEL_PIN CLKin_SEL_PIN _EN _POL PLL1R_SYNC_SRC CLKin2_EN CLKin1_EN SYNC_MODE 0x147 CLKin_SEL_ AUTO_ REVERT_EN 0x148 0 0 CLKin_SEL0_MUX CLKin_SEL0_TYPE 0x149 0 SDIO_RDBK_ TYPE CLKin_SEL1_MUX CLKin_SEL1_TYPE 0x14A 0 0 RESET_MUX 0x14B CLKin_SEL_ AUTO_EN LOS_TIMEOUT CLKin_SEL_MANUAL LOS_EN TRACK_EN 0x14C 0x14D 0x14E 0x151 DAC_TRIP_HIGH 0 0 HOLDOVER_ EXIT_MODE HOLDOVER_ PLL1_DET 0 0 0 0 CLKin1_R[13:8] CLKin1_R[7:0] 0 0 CLKin2_R[13:8] CLKin2_R[7:0] 0 0 PLL1_N[13:8] 0x15A PLL1_N[7:0] PLL1_WND_SIZE 0 0 0 0 PLL1_CP_TRI PLL1_CP_POL PLL1_CP_GAIN PLL1_DLD_CNT[13:8] 0x15D PLL1_DLD_CNT[7:0] 0x15F 0 HOLDOVER_EXIT_NADJ PLL1_LD_MUX 0 0 0 PLL1_LD_TYPE 0 0x161 PLL2_R PLL2_R 0x162 0x163 HOLDOVER_ EN CLKin0_R[13:8] 0x158 0x160 CLKin_SWITCH _CP_TRI CLKin0_R[7:0] 0x156 0x15E HOLDOVER_ VTUNE_DET HOLDOVER_DLD_CNT[7:0] 0x154 0x15B LOS_EXTERNA L_INPUT HOLDOVER_DLD_CNT[13:8] 0x152 0x15C MAN_DAC[9:8] DAC_CLK_CNTR CLKin_OVERRI DE 0x159 MAN_DAC_EN DAC_TRIP_LOW DAC_CLK_MULT 0 0x157 RESET_TYPE HOLDOVER_ FORCE 0 0x150 0x155 CLKin0_DEMUX MAN_DAC[7:0] 0 0x14F 0x153 CLKin1_DEMUX PLL2_P 0 0 0 0 0 OSCin_FREQ 0 0x164 PLL2_N_CAL[15:8] 0x165 PLL2_N_CAL[7:0] PLL2_XTAL_EN 0 PLL2_REF_2X_ EN PLL2_N_CAL[17:16] Submit Documentation Feedback Copyright © 2017–2018, Texas Instruments Incorporated Product Folder Links: LMK04832 47 LMK04832 SNAS688C – FEBRURAY 2017 – REVISED MAY 2018 www.ti.com Register Maps (continued) Table 5. LMK04832 Register Map (continued) ADDRESS [14:0] DATA[7:0] 23:8 7 6 5 4 3 2 0x166 0 0 0 0 0 0 0x167 0 PLL2_N[17:16] PLL2_N[15:8] 0x168 PLL2_N[7:0] 0x169 0 PLL2_WND_SIZE PLL2_CP_GAIN 0x16A 0 0 PLL2_CP_POL 0x16C 0 0 0 0 0 0x173 0 PLL2_PRE_PD PLL2_PD 0 0 PLL2_CP_TRI PLL2_DLD_EN 0 0 0 0 0 0 PLL2_DLD_CNT[13:8] 0x16B PLL2_DLD_CNT[7:0] 0x177 PLL1R_RST CLR_PLL1_LD_ CLR_PLL2_LD_ LOST LOST 0x182 0 0 0 0 0 0 0x183 0 0 0 0 RB_PLL1_DLD_ LOST RB_PLL1_DLD RB_PLL2_DLD_ LOST RB_PLL2_DLD RB_CLKin2_ SEL RB_CLKin1_ SEL RB_CLKin0_ SEL RB_CLKin2_ LOS RB_CLKin1_ LOS RB_CLKin0_ LOS RB_DAC_HIGH RB_DAC_LOW RB_DAC_ LOCKED 0x184 RB_DAC_VALUE[9:8] 0x185 0x188 RB_DAC_VALUE[7:0] 0 X 0x555 48 1 RB_ HOLDOVER X RB_DAC_RAIL SPI_LOCK Submit Documentation Feedback Copyright © 2017–2018, Texas Instruments Incorporated Product Folder Links: LMK04832 LMK04832 www.ti.com SNAS688C – FEBRURAY 2017 – REVISED MAY 2018 8.6.2 Device Register Descriptions The following section details the fields of each register, the Power-On-Reset Defaults, and specific descriptions of each bit. In some cases similar fields are located in multiple registers. In this case specific outputs may be designated as X or Y. In these cases, the X represents even numbers from 0 to 12 and the Y represents odd numbers from 1 to 13. In the case where X and Y are both used in a bit name, then Y = X + 1. 8.6.2.1 System Functions 8.6.2.1.1 RESET, SPI_3WIRE_DIS This register contains the RESET function and the ability to turn off 3-wire SPI mode. To use a 4-wire SPI mode, selecting SPI Read back in one of the output MUX settings. For example CLKin0_SEL_MUX or RESET_MUX. It is possible to have 3-wire and 4-wire readback at the same time. Table 6. Register 0x000 BIT NAME POR DEFAULT DESCRIPTION 7 RESET 0 0: Normal operation 1: Reset (automatically cleared) 6:5 NA 0 Reserved 4 SPI_3WIRE_DIS 0 Disable 3-wire SPI mode. 0: 3 Wire Mode enabled 1: 3 Wire Mode disabled 3:0 NA NA Reserved 8.6.2.1.2 POWERDOWN This register contains the POWERDOWN function. Table 7. Register 0x002 BIT NAME POR DEFAULT 7:1 NA 0 Reserved DESCRIPTION 0 POWERDOWN 0 0: Normal operation 1: Power down device. 8.6.2.1.3 ID_DEVICE_TYPE This register contains the product device type. This is read only register. Table 8. Register 0x003 BIT NAME POR DEFAULT 7:0 ID_DEVICE_TYPE 6 DESCRIPTION PLL product device type. Submit Documentation Feedback Copyright © 2017–2018, Texas Instruments Incorporated Product Folder Links: LMK04832 49 LMK04832 SNAS688C – FEBRURAY 2017 – REVISED MAY 2018 www.ti.com 8.6.2.1.4 ID_PROD These registers contain the product identifier. This is a read only register. Table 9. ID_PROD Field Registers MSB LSB 0x004[7:0] / ID_PROD[15:8] 0x005[7:0] / ID_PROD[7:0] Table 10. Registers 0x004 and 0x005 REGISTER BIT FIELD NAME POR DEFAULT 0x004 7:0 ID_PROD[15:8] 209 (0xD1) MSB of the product identifier. DESCRIPTION 0x005 7:0 ID_PROD[7:0] 99 (0x63) LSB of the product identifier. 8.6.2.1.5 ID_MASKREV This register contains the IC version identifier. This is a read only register. Table 11. Register 0x006 BIT NAME POR DEFAULT 7:0 ID_MASKREV 112 (0x70) DESCRIPTION IC version identifier for LMK04832. 8.6.2.1.6 ID_VNDR These registers contain the vendor identifier. This is a read only register. Table 12. ID_VNDR Field Registers MSB LSB 0x00C[7:0] / ID_VNDR[15:8] 0x00D[7:0] / ID_VNDR[7:0] Table 13. Registers 0x00C, 0x00D REGISTER BIT NAME POR DEFAULT 0x00C 7:0 ID_VNDR[15:8] 81 (0x51) MSB of the vendor identifier. 0x00D 7:0 ID_VNDR[7:0] 4 (0x04) LSB of the vendor identifier. 50 DESCRIPTION Submit Documentation Feedback Copyright © 2017–2018, Texas Instruments Incorporated Product Folder Links: LMK04832 LMK04832 www.ti.com SNAS688C – FEBRURAY 2017 – REVISED MAY 2018 8.6.2.2 (0x100 - 0x138) Device Clock and SYSREF Clock Output Controls 8.6.2.2.1 DCLKX_Y_DIV The device clock divider can drive up to two outputs, an even (X) and an odd (Y) clock output. Divide is a 10 bit number and split across two registers. Table 14. DCLKX_Y_DIV Field Registers MSB LSB 0x0102[1:0] = DCLK0_1_DIV[9:8] 0x100[7:0] = DCLK0_1_DIV[7:0] 0x010A[1:0] = DCLK2_3_DIV[9:8] 0x108[7:0] = DCLK2_3_DIV[7:0] 0x0112[1:0] = DCLK4_5_DIV[9:8] 0x110[7:0] = DCLK4_5_DIV[7:0] 0x011A[1:0] = DCLK6_7_DIV[9:8] 0x118[7:0] = DCLK6_7_DIV[7:0] 0x0122[1:0] = DCLK8_9_DIV[9:8] 0x120[7:0] = DCLK8_9_DIV[7:0] 0x012A[1:0] = DCLK10_11_DIV[9:8] 0x128[7:0] = DCLK10_11_DIV[7:0] 0x0132[1:0] = DCLK12_13_DIV[9:8] 0x130[7:0] = DCLK12_13_DIV[7:0] Table 15. Registers 0x100, 0x108, 0x110, 0x118, 0x120, 0x128, and 0x130 0x102, 0x10A, 0x112, 0x11A, 0x122, 0x12A, 0x132 REGISTER 0x102, 0x10A, 0x112, 0x11A, 0x122, 0x12A, 0x132 0x100, 0x108, 0x110, 0x118, 0x120, 0x128, and 0x130 (1) BIT 1:0 7:0 NAME DCLKX_Y_DIV[9:8] DCLKX_Y_DIV[7:0] POR DEFAULT DESCRIPTION DCLKX_Y_DIV sets the divide value for the clock output, the divide may be even or odd. Both even or odd divides output a 50% duty cycle clock if duty cycle correction (DCC) is enabled. X_Y = 0_1 → 2 X_Y = 2_3 → 4 X_Y = 4_5 → 8 X_Y = 6_7 → 8 X_Y = 8_9 → 8 X_Y = 10_11 → 8 X_Y = 12_13 → 2 Field Value Divider Value 0 (0x00) Reserved 1 (0x01) 2 (0x02) 1 (1) 2 ... ... 1022 (0x3FE) 1022 1023 (0x3FF) 1023 Duty cycle correction must also be enabled, DCLKX_Y_DCC = 1. Submit Documentation Feedback Copyright © 2017–2018, Texas Instruments Incorporated Product Folder Links: LMK04832 51 LMK04832 SNAS688C – FEBRURAY 2017 – REVISED MAY 2018 www.ti.com 8.6.2.2.2 DCLKX_Y_DDLY This register controls the digital delay for the device clock outputs. Table 16. DCLKX_Y_DDLY Field Registers MSB LSB 0x0102[2:3] = DCLK0_1_DDLY[9:8] 0x101[7:0] = DCLK0_1_DDLY[7:0] 0x010A[2:3] = DCLK2_3_DDLY[9:8] 0x109[7:0] = DCLK2_3_DDLY[7:0] 0x0112[2:3] = DCLK4_5_DDLY[9:8] 0x111[7:0] = DCLK4_5_DDLY[7:0] 0x011A[2:3] = DCLK6_7_DDLY[9:8] 0x119[7:0] = DCLK6_7_DDLY[7:0] 0x0122[2:3] = DCLK8_9_DDLY[9:8] 0x121[7:0] = DCLK8_9_DDLY[7:0] 0x012A[2:3] = DCLK10_11_DDLY[9:8] 0x129[7:0] = DCLK10_11_DDLY[7:0] 0x0132[2:3] = DCLK12_13_DDLY[9:8] 0x131[7:0] = DCLK12_13_DDLY[7:0] Table 17. Registers 0x101, 0x109, 0x111, 0x119, 0x121, 0x129, 0x131 0x102, 0x10A, 0x112, 0x11A, 0x122, 0x12A, 0x132 REGISTER 0x102, 0x10A, 0x112, 0x11A, 0x122, 0x12A, 0x132 0x101, 0x109, 0x111, 0x119, 0x121, 0x129, 0x131 BIT NAME POR DEFAULT DESCRIPTION Static digital delay which takes effect after a SYNC. 2:3 DCLKX_Y_DDLY[9:8] 10 (0x0A) 7:0 DCLKX_Y_DDLY[7:0] Field Value Delay Values 0 (0x00) Reserved 1 (0x01) Reserved ... ... 7 (0x07) Reserved 8 (0x08) 8 9 (0x09) 9 ... ... 1022 (0x3FE) 1022 1023 (0x3FF) 1023 Depending on the DCLK divide value, there may be an adjustment in phase delay required. Table 18 illustrate the impact of different divide values on the final digital delay. Table 18. Digital Delay Adjustment based on Divide Values (1) Divide Value Digital delay Adjustment 2, 3 -2 (1) 4, 7 to 1023 0 5 +3 6 +1 Before SYNC, program divider to Divide-by-4, then back to Divide-by-2 or Divide-by-3 to ensure '-2' delay relationship. For example, Table 19 illustrates a system with clock outputs having divide values /2,/4,/5 and /6 to share a common edge. Table 19. Digital Delay Adjustment Illustration 52 Divide Value Programmed DDLY Actual DDLY 2 13 11 4 11 11 5 8 11 6 10 11 Submit Documentation Feedback Copyright © 2017–2018, Texas Instruments Incorporated Product Folder Links: LMK04832 LMK04832 www.ti.com SNAS688C – FEBRURAY 2017 – REVISED MAY 2018 8.6.2.2.3 CLKoutX_Y_PD, CLKoutX_Y_ODL, CLKoutX_Y_IDL, DCLKX_Y_DDLY_PD, DCLKX_Y_DDLY[9:8], DCLKX_Y_DIV[9:8] Table 20. Registers 0x102, 0x10A, 0x112, 0x11A, 0x122, 0x12A, 0x132 BIT NAME POR DEFAULT DESCRIPTION 7 CLKoutX_Y_PD 1 Power down the clock group defined by X and Y. 0: Enabled 1: Power down entire clock group including both CLKoutX and CLKoutY. 6 CLKoutX_Y_ODL 0 Sets output drive level for clocks. This has no impact for the even clock output in bypass mode. 0: Normal operation 1: Higher current consumption and lower noise floor. 5 CLKoutX_Y_IDL 0 Sets input drive level for clocks. 0: Normal operation 1: Higher current consumption and lower noise floor. 4 DCLKX_Y_DDLY_PD 0 Powerdown the device clock digital delay circuitry. 0: Enabled 1: Power down static digital delay for device clock divider. 3:2 DCLKX_Y_DDLY[9:8] 0 MSB of static digital delay, see DCLKX_Y_DDLY. 1:0 DCLKX_Y_DIV[9:8] 0 MSB of device clock divide value, see Table 15. Submit Documentation Feedback Copyright © 2017–2018, Texas Instruments Incorporated Product Folder Links: LMK04832 53 LMK04832 SNAS688C – FEBRURAY 2017 – REVISED MAY 2018 www.ti.com 8.6.2.2.4 CLKoutX_SRC_MUX, CLKoutX_Y_PD, DCLKX_Y_BYP, DCLKX_Y_DCC, DCLKX_Y_POL, DCLKX_Y_HS These registers control the analog delay properties for the device clocks. Table 21. Registers 0x103, 0x10B, 0x113, 0x11B, 0x123, 0x12B, 0x133 BIT NAME POR DEFAULT 7 NA 0 Reserved 6 NA 1 Reserved 5 CLKoutX_SRC_MUX 0 Select CLKoutX clock source. Source must also be powered up. 0: Device Clock 1: SYSREF 4 CLKoutX_Y_PD 0 Power down the clock group defined by X and Y. 0: Enabled 1: Power down enter clock group X_Y. 3 DCLKX_BYP 0 Enable high performance bypass path for even clock outputs. 0: CLKoutX not in high performance bypass mode. CML is not valid for CLKoutX_FMT. 1: CLKoutX in high performance bypass mode. Only CML clock format is valid. 2 DCLKX_Y_DCC 0 Duty cycle correction for device clock divider. Required for half step. 0: No duty cycle correction. 1: Duty cycle correction enabled. 54 DESCRIPTION 1 DCLKX_Y_POL 0 Invert polarity of device clock output. This also applies to CLKoutX in high performance bypass mode. Polarity invert is a method to get a half-step phase adjustment in high performance bypass mode or /1 divide value. 0: Normal polarity 1: Invert polarity 0 DCLKX_Y_HS 0 Sets the device clock half step value. Must be set to zero (0) for a divide of 1. No effect if DCLKX_Y_DCC = 0. 0: No phase adjustment 1: Adjust device clock phase -0.5 clock distribution path cycles. Submit Documentation Feedback Copyright © 2017–2018, Texas Instruments Incorporated Product Folder Links: LMK04832 LMK04832 www.ti.com SNAS688C – FEBRURAY 2017 – REVISED MAY 2018 8.6.2.2.5 CLKoutY_SRC_MUX, SCLKX_Y_PD, SCLKX_Y_DIS_MODE, SCLKX_Y_POL, SCLKX_Y_HS These registers set the half step for the device clock, the SYSREF output MUX, the SYSREF clock digital delay, and half step. Table 22. Registers 0x104, 0x10C, 0x114, 0x11C, 0x124, 0x12C, 0x134 BIT NAME POR DEFAULT 7:6 NA 0 Reserved DESCRIPTION 5 CLKoutY_SRC_MUX 0 Select CLKoutX clock source. Source must also be powered up. 0: Device Clock 1: SYSREF 4 SCLKX_Y_PD 1 Power down the SYSREF clock output circuitry. 0: SYSREF enabled 1: Power down SYSREF path for clock pair. Set disable mode for clock outputs controlled by SYSREF. Some cases will assert when SYSREF_GBL_PD = 1. 3:2 (1) SCLKX_Y_DIS_MODE 0 Field Value Disable Mode 0 (0x00) Active in normal operation 1 (0x01) If SYSREF_GBL_PD = 1, the output is a logic low, otherwise it is active. 2 (0x02) If SYSREF_GBL_PD = 1, the output is a nominal Vcm voltage for odd clock channels (1) and low for even clocks. Otherwise outputs are active. 3 (0x03) Output is a nominal Vcm voltage (1) 1 SCLKX_Y_POL 0 Sets the polarity of clock on SCLKX_Y when SYSREF clock output is selected with CLKoutX_MUX or CLKoutY_MUX. 0: Normal 1: Inverted 0 SCLKX_Y_HS 0 Sets the local SYSREF clock half step value. 0: No phase adjustment 1: Adjust device SYSREF phase -0.5 clock distribution path cycles. If LVPECL mode is used with emitter resistors to ground, the output Vcm will be approximately 0 V, each pin will be approximately 0 V. If CML mode is used with pullups to VCC, the output VCM will be approximately VCC V, each pin will be approximately VCC V. Submit Documentation Feedback Copyright © 2017–2018, Texas Instruments Incorporated Product Folder Links: LMK04832 55 LMK04832 SNAS688C – FEBRURAY 2017 – REVISED MAY 2018 www.ti.com 8.6.2.2.6 SCLKX_Y_ADLY_EN, SCLKX_Y_ADLY These registers set the analog delay parameters for the SYSREF outputs. Table 23. Registers 0x105, 0x10D, 0x115, 0x11D, 0x125, 0x12D, 0x135 BIT NAME POR DEFAULT DESCRIPTION 7:6 NA 0 Reserved 5 SCLKX_Y _ADLY_EN 0 Enables analog delay for the SYSREF output. 0: Disabled 1: Enabled SYSREF analog delay in approximately 21 ps steps. Selecting analog delay adds an additional 125 ps in propagation delay. Range is 125 ps to 608 ps. Field Value 4:0 SCLKX_Y _ADLY 0 Delay Value 0 (0x0) 125 ps 1 (0x1) 146 ps (+21 ps from 0x00) 2 (0x2) 167 ps (+42 ps from 0x00) 3 (0x3) 188 ps (+63 ps from 0x00) ... ... 14 (0xE) 587 ps (+462 ps from 0x00) 15 (0xF) 608 ps (+483 ps from 0x00) 8.6.2.2.7 SCLKX_Y_DDLY Table 24. Registers 0x106, 0x10E, 0x116, 0x11E, 0x126, 0x12E, 0x136 56 BIT NAME POR DEFAULT 7:4 NA 0 Reserved DESCRIPTION 3:0 SCLKX_Y_DDLY 0 Set digital delay value for SYSREF clock ( minimum 8 ) Submit Documentation Feedback Copyright © 2017–2018, Texas Instruments Incorporated Product Folder Links: LMK04832 LMK04832 www.ti.com SNAS688C – FEBRURAY 2017 – REVISED MAY 2018 8.6.2.2.8 CLKoutY_FMT, CLKoutX_FMT The difference in the tables is that some of the clock outputs have inverted CMOS polarity settings. Table 25. Registers 0x107 (CLKout0_1), 0x11F (CLKout6_7), 0x12F (CLKout10_11) BIT NAME POR DEFAULT DESCRIPTION Set CLKoutY clock format 7:4 CLKoutY_FMT 0 Field Value Output Format 0 (0x00) Powerdown 1 (0x01) LVDS 2 (0x02) HSDS 6 mA 3 (0x03) HSDS 8 mA 4 (0x04) LVPECL 1600 mV 5 (0x05) LVPECL 2000 mV 6 (0x06) LCPECL 7 (0x07) CML 16 mA 8 (0x08) CML 24 mA 9 (0x09) CML 32 mA 10 (0x0A) CMOS (Off/Inv) 11 (0x0B) CMOS (Norm/Off) 12 (0x0C) CMOS (Inv/Inv) 13 (0x0D) CMOS (Inv/Norm) 14 (0x0E) CMOS (Norm/Inv) 15 (0x0F) CMOS (Norm/Norm) Set CLKoutX clock format 3:0 CLKoutX_FMT 0 Field Value Output Format DCLKX_BYP = 0 Output Format DCLKX_BYP = 1 0 (0x00) Powerdown Reserved 1 (0x01) LVDS Reserved 2 (0x02) HSDS 6 mA Reserved 3 (0x03) HSDS 8 mA Reserved 4 (0x04) LVPECL 1600 mV Reserved 5 (0x05) LVPECL 2000 mV Reserved 6 (0x06) LCPECL Reserved 7 (0x07) Reserved CML 16 mA 8 (0x08) Reserved CML 24 mA 9 (0x09) Reserved CML 32 mA 10 (0x0A) CMOS (Off/Inv) (1) Reserved 11 (0x0B) CMOS (Norm/Off) (1) Reserved 12 (0x0C) (1) CMOS (Inv/Inv) (1) Reserved 13 (0x0D) CMOS (Inv/Norm) (1) Reserved 14 (0x0E) CMOS (Norm/Inv) (1) Reserved 15 (0x0F) CMOS (Norm/Norm) (1) Reserved Only valid for CLKout10. Submit Documentation Feedback Copyright © 2017–2018, Texas Instruments Incorporated Product Folder Links: LMK04832 57 LMK04832 SNAS688C – FEBRURAY 2017 – REVISED MAY 2018 www.ti.com Table 26. Registers 0x10F (CLKout2_3), 0x117 (CLKout4_5), 0x127 (CLKout8_9), 0x137 (CLKout12_13) BIT NAME POR DEFAULT DESCRIPTION Set CLKoutY clock format 7:4 CLKoutY_FMT 0 Field Value Output Format 0 (0x00) Powerdown 1 (0x01) LVDS 2 (0x02) HSDS 6 mA 3 (0x03) HSDS 8 mA 4 (0x04) LVPECL 1600 mV 5 (0x05) LVPECL 2000 mV 6 (0x06) LCPECL 7 (0x07) CML 16 mA 8 (0x08) CML 24 mA 9 (0x09) CML 32 mA 10 (0x0A) CMOS (Off/Norm) 11 (0x0B) CMOS (Inv/Off) 12 (0x0C) CMOS (Norm/Norm) 13 (0x0D) CMOS (Norm/Inv) 14 (0x0E) CMOS (Inv/Norm) 15 (0x0F) CMOS (Inv/Inv) Set CLKoutX clock format 3:0 CLKoutX_FMT 0 Field Value Output Format DCLKX_BYP = 0 Output Format DCLKX_BYP = 1 0 (0x00) Powerdown Reserved 1 (0x01) LVDS Reserved 2 (0x02) HSDS 6 mA Reserved 3 (0x03) HSDS 8 mA Reserved 4 (0x04) LVPECL 1600 mV Reserved 5 (0x05) LVPECL 2000 mV Reserved 6 (0x06) LCPECL Reserved 7 (0x07) Reserved CML 16 mA 8 (0x08) Reserved CML 24 mA 9 (0x09) Reserved CML 32 mA 10 (0x0A) CMOS (Off/Norm) (1) 11 (0x0B) 58 Reserved Reserved 12 (0x0C) CMOS (Norm/Norm) (1) Reserved 13 (0x0D) CMOS (Norm/Inv) (1) Reserved 14 (0x0E) (1) Reserved 15 (0x0F) (1) CMOS (Inv/Off) (1) CMOS (Inv/Norm) CMOS (Inv/Inv) (1) Reserved Only valid for CLKout8. Submit Documentation Feedback Copyright © 2017–2018, Texas Instruments Incorporated Product Folder Links: LMK04832 LMK04832 www.ti.com SNAS688C – FEBRURAY 2017 – REVISED MAY 2018 8.6.2.3 SYSREF, SYNC, and Device Config 8.6.2.3.1 VCO_MUX, OSCout_MUX, OSCout_FMT Table 27. Register 0x138 BIT NAME POR DEFAULT 7 NA 0 DESCRIPTION Reserved Selects clock distribution path source from VCO0, VCO1, or CLKin (external VCO) 6:5 4 VCO_MUX OSCout_MUX 2 0 Field Value VCO Selected 0 (0x00) VCO 0 1 (0x01) VCO 1 2 (0x02) Fin1 / CLKin1 (external VCO) 3 (0x03) Reserved Select the source for OSCout: 0: Buffered OSCin 1: Feedback Mux Selects the output format of OSCout. When powered down, these pins may be used as CLKin2. 3:0 OSCout_FMT 4 Field Value OSCout Format 0 (0x00) Power down (CLKin2) 1 (0x01) LVDS 2 (0x02) Reserved 3 (0x03) Reserved 4 (0x04) LVPECL 1600 mVpp 5 (0x05) LVPECL 2000 mVpp 6 (0x06) LVCMOS (Norm / Inv) 7 (0x07) LVCMOS (Inv / Norm) 8 (0x08) LVCMOS (Norm / Norm) 9 (0x09) LVCMOS (Inv / Inv) 10 (0x0A) LVCMOS (Off / Norm) 11 (0x0B) LVCMOS (Off / Inv) 12 (0x0C) LVCMOS (Norm / Off) 13 (0x0D) LVCMOS (Inv / Off) 14 (0x0E) LVCMOS (Off / Off) Submit Documentation Feedback Copyright © 2017–2018, Texas Instruments Incorporated Product Folder Links: LMK04832 59 LMK04832 SNAS688C – FEBRURAY 2017 – REVISED MAY 2018 www.ti.com 8.6.2.3.2 SYSREF_REQ_EN, SYNC_BYPASS, SYSREF_MUX This register sets the source for the SYSREF outputs. Refer to Figure 8 and SYNC/SYSREF. Table 28. Register 0x139 BIT NAME POR DEFAULT DESCRIPTION 7:6 NA 0 Reserved 5 NA 0 Reserved 4 SYSREF_REQ_EN 0 Enables the SYNC/SYSREF_REQ pin to force the SYSREF_MUX = 3 for continuous pulses. When using this feature enable pulser and set SYSREF_MUX = 2 (Pulser). 3 SYNC_BYPASS 0 Bypass SYNC polarity invert and other circuitry. 0: Normal 1: SYNC signal is bypassed 2 NA 0 Reserved Selects the SYSREF source. 1:0 60 SYSREF_MUX 0 Field Value SYSREF Source 0 (0x00) Normal SYNC 1 (0x01) Re-clocked 2 (0x02) SYSREF Pulser 3 (0x03) SYSREF Continuous Submit Documentation Feedback Copyright © 2017–2018, Texas Instruments Incorporated Product Folder Links: LMK04832 LMK04832 www.ti.com SNAS688C – FEBRURAY 2017 – REVISED MAY 2018 8.6.2.3.3 SYSREF_DIV These registers set the value of the SYSREF output divider. Table 29. SYSREF_DIV[12:0] MSB LSB 0x13A[4:0] = SYSREF_DIV[12:8] 0x13B[7:0] = SYSREF_DIV[7:0] Table 30. Registers 0x13A and 0x13B REGISTER BIT NAME POR DEFAULT 0x13A 7:5 NA 0 DESCRIPTION Reserved Divide value for the SYSREF outputs. 0x13A 0x13B 4:0 7:0 SYSREF_DIV[12:8] SYSREF_DIV[7:0] 12 0 Field Value Divide Value 0 to 7 (0x00 to 0x07) Reserved 8 (0x08) 8 9 (0x09) 9 ... ... 8190 (0x1FFE) 8190 8191 (0X1FFF) 8191 8.6.2.3.4 SYSREF_DDLY These registers set the delay of the SYSREF digital delay value. Table 31. SYSREF Digital Delay Register Configuration, SYSREF_DDLY[12:0] MSB LSB 0x13C[4:0] / SYSREF_DDLY[12:8] 0x13D[7:0] / SYSREF_DDLY[7:0] Table 32. Registers 0X13C and 0X13D REGISTER BIT NAME POR DEFAULT 0x13C 7:5 NA 0 DESCRIPTION Reserved Sets the value of the SYSREF digital delay. 0x13C 0x13D 4:0 7:0 SYSREF_DDLY[12:8] SYSREF_DDLY[7:0] 0 8 Field Value Delay Value 0x00 to 0x07 Reserved 8 (0x08) 8 9 (0x09) 9 ... ... 8190 (0x1FFE) 8190 8191 (0X1FFF) 8191 Submit Documentation Feedback Copyright © 2017–2018, Texas Instruments Incorporated Product Folder Links: LMK04832 61 LMK04832 SNAS688C – FEBRURAY 2017 – REVISED MAY 2018 www.ti.com 8.6.2.3.5 SYSREF_PULSE_CNT This register sets the number of SYSREF pulses if SYSREF is not in continuous mode. See SYSREF_REQ_EN, SYNC_BYPASS, SYSREF_MUX for further description of SYSREF's outputs. Programming the register causes the specified number of pulses to be output if "SYSREF Pulses" is selected by SYSREF_MUX and SYSREF functionality is powered up. Table 33. Register 0x13E BIT NAME POR DEFAULT 7:2 NA 0 DESCRIPTION Reserved Sets the number of SYSREF pulses generated when not in continuous mode. See SYSREF_REQ_EN, SYNC_BYPASS, SYSREF_MUX for more information on SYSREF modes. Field Value 1:0 SYSREF_PULSE_CNT 3 Number of Pulses 0 (0x00) 1 pulse 1 (0x01) 2 pulses 2 (0x02) 4 pulses 3 (0x03) 8 pulses 8.6.2.3.6 PLL2_RCLK_MUX, PLL2_NCLK_MUX, PLL1_NCLK_MUX, FB_MUX, FB_MUX_EN This register controls the feedback feature. Table 34. Register 0x13F BIT NAME POR DEFAULT DESCRIPTION 7 PLL2_RCLK_MUX 0 Selects the source for PLL2 reference. 0: OSCin 1: Currently selected CLKin. 6 NA 0 Reserved 5 PLL2_NCLK_MUX 0 Selects the input to the PLL2 N Divider 0: PLL2 Prescaler 1: Feedback Mux 4:3 PLL1_NCLK_MUX 0 Selects the input to the PLL1 N Divider. 0: OSCin 1: Feedback Mux 2: PLL2 Prescaler When in 0-delay mode, the feedback mux selects the clock output to be fed back into the PLL1 N Divider. 2:1 0 62 FB_MUX FB_MUX_EN 0 0 Field Value Source 0 (0x00) CLKout6 1 (0x01) CLKout8 2 (0x02) SYSREF Divider 3 (0x03) External When using 0-delay, FB_MUX_EN must be set to 1 power up the feedback mux. 0: Feedback mux powered down 1: Feedback mux enabled Submit Documentation Feedback Copyright © 2017–2018, Texas Instruments Incorporated Product Folder Links: LMK04832 LMK04832 www.ti.com SNAS688C – FEBRURAY 2017 – REVISED MAY 2018 8.6.2.3.7 PLL1_PD, VCO_LDO_PD, VCO_PD, OSCin_PD, SYSREF_GBL_PD, SYSREF_PD, SYSREF_DDLY_PD, SYSREF_PLSR_PD This register contains power down controls for OSCin and SYSREF functions. Table 35. Register 0x140 BIT NAME POR DEFAULT DESCRIPTION 7 PLL1_PD 1 Power down PLL1 0: Normal operation 1: Power down 6 VCO_LDO_PD 1 Power down VCO_LDO 0: Normal operation 1: Power down 5 VCO_PD 1 Power down VCO 0: Normal operation 1: Power down 4 OSCin_PD 0 Power down the OSCin port. 0: Normal operation 1: Power down 0 Power down individual SYSREF outputs depending on the setting of SCLKX_Y_DIS_MODE for each SYSREF output. SYSREF_GBL_PD allows many SYSREF outputs to be controlled through a single bit. 0: Normal operation 1: Activate Power down Mode 3 SYSREF_GBL_PD 2 SYSREF_PD 0 Power down the SYSREF circuitry and divider. If powered down, SYSREF output mode cannot be used. SYNC cannot be provided either. 0: SYSREF can be used as programmed by individual SYSREF output registers. 1: Power down 1 SYSREF_DDLY_PD 0 Power down the SYSREF digital delay circuitry. 0: Normal operation, SYSREF digital delay may be used. Must be powered up during SYNC for deterministic phase relationship with other clocks. 1: Power down 0 SYSREF_PLSR_PD 0 Powerdown the SYSREF pulse generator. 0: Normal operation 1: Powerdown 8.6.2.3.8 DDLYdSYSREF_EN, DDLYdX_EN This register enables dynamic digital delay for enabled device clocks and SYSREF when DDLYd_STEP_CNT is programmed. Table 36. Register 0x141 BIT NAME POR DEFAULT DESCRIPTION 7 DDLYd _SYSREF_EN 0 Enables dynamic digital delay on SYSREF outputs 6 DDLYd12_EN 0 Enables dynamic digital delay on DCLKout12 5 DDLYd10_EN 0 Enables dynamic digital delay on DCLKout10 4 DDLYd8_EN 0 Enables dynamic digital delay on DCLKout8 3 DDLYd6_EN 0 Enables dynamic digital delay on DCLKout6 2 DDLYd4_EN 0 Enables dynamic digital delay on DCLKout4 1 DDLYd2_EN 0 Enables dynamic digital delay on DCLKout2 0 DDLYd0_EN 0 Enables dynamic digital delay on DCLKout0 0: Disabled 1: Enabled Submit Documentation Feedback Copyright © 2017–2018, Texas Instruments Incorporated Product Folder Links: LMK04832 63 LMK04832 SNAS688C – FEBRURAY 2017 – REVISED MAY 2018 www.ti.com 8.6.2.3.9 DDLYd_STEP_CNT This register sets the number of dynamic digital delay adjustments occur. Upon programming, the dynamic digital delay adjustment begins for each clock output with dynamic digital delay enabled. Dynamic digital delay can only be started by SPI. Other registers must be set: SYNC_MODE = 3 Table 37. Register 0x142 BIT NAME POR DEFAULT DESCRIPTION Sets the number of dynamic digital delay adjustments that will occur. 7:0 64 DDLYd_STEP_CNT 0 Field Value Dynamic Digital Delay Adjustments 0 (0x00) No Adjust 1 (0x01) 1 step 2 (0x02) 2 steps 3 (0x03) 3 steps ... ... 254 (0xFE) 254 steps 255 (0xFF) 255 steps Submit Documentation Feedback Copyright © 2017–2018, Texas Instruments Incorporated Product Folder Links: LMK04832 LMK04832 www.ti.com SNAS688C – FEBRURAY 2017 – REVISED MAY 2018 8.6.2.3.10 SYSREF_CLR, SYNC_1SHOT_EN, SYNC_POL, SYNC_EN, SYNC_PLL2_DLD, SYNC_PLL1_DLD, SYNC_MODE This register sets general SYNC parameters such as polarization, and mode. Refer to Figure 8 for block diagram. Refer to Table 1 for using SYNC_MODE for specific SYNC use cases. Table 38. Register 0x143 BIT NAME POR DEFAULT DESCRIPTION 7 SYSREF_CLR 0 Except during SYSREF Setup Procedure (see SYNC/SYSREF), this bit should always be programmed to 0. While this bit is set, extra current is used. Refer to . 6 SYNC_1SHOT_EN 0 SYNC one shot enables edge sensitive SYNC. 0: SYNC is level sensitive and outputs will be held in SYNC as long as SYNC is asserted. 1: SYNC is edge sensitive, outputs will be SYNCed on rising edge of SYNC. This results in the clock being held in SYNC for a minimum amount of time. 5 SYNC_POL 0 Sets the polarity of the SYNC pin. 0: Normal 1: Inverted 4 SYNC_EN 0 Enables the SYNC functionality. 0: Disabled 1: Enabled 3 SYNC_PLL2_DLD 0 0: Off 1: Assert SYNC until PLL2 DLD = 1 2 SYNC_PLL1_DLD 0 0: Off 1: Assert SYNC until PLL1 DLD = 1 Sets the method of generating a SYNC event. 1:0 SYNC_MODE Field Value SYNC Generation 0 (0x00) Prevent SYNC Pin, SYNC_PLL1_DLD flag, or SYNC_PLL2_DLD flag from generating a SYNC event. 1 (0x01) SYNC event generated from SYNC pin or if enabled the SYNC_PLL1_DLD flag or SYNC_PLL2_DLD flag. 2 (0x02) For use with pulser - SYNC/SYSREF pulses are generated by pulser block via SYNC Pin or if enabled SYNC_PLL1_DLD flag or SYNC_PLL2_DLD flag. 3 (0x03) For use with pulser - SYNC/SYSREF pulses are generated by pulser block when programming register 0x13E (SYSREF_PULSE_CNT) is written to (see ). 1 Submit Documentation Feedback Copyright © 2017–2018, Texas Instruments Incorporated Product Folder Links: LMK04832 65 LMK04832 SNAS688C – FEBRURAY 2017 – REVISED MAY 2018 www.ti.com 8.6.2.3.11 SYNC_DISSYSREF, SYNC_DISX SYNC_DISX will prevent a clock output from being synchronized or interrupted by a SYNC event or when outputting SYSREF. Table 39. Register 0x144 BIT NAME POR DEFAULT 7 SYNC_DISSYSREF 0 6 SYNC_DIS12 0 5 SYNC_DIS10 0 4 SYNC_DIS8 0 3 SYNC_DIS6 0 2 SYNC_DIS4 0 1 SYNC_DIS2 0 0 SYNC_DIS0 0 DESCRIPTION Prevent the SYSREF clocks from becoming synchronized during a SYNC event. If SYNC_DISSYSREF is enabled it will continue to operate normally during a SYNC event. Prevent the device clock output from becoming synchronized during a SYNC event or SYSREF clock. If SYNC_DIS bit for a particular output is enabled then it will continue to operate normally during a SYNC event or SYSREF clock. 8.6.2.3.12 PLL1R_SYNC_EN, PLL1R_SYNC_SRC, PLL2R_SYNC_EN These bits are used when synchronizing PLL1 and PLL2 R dividers. Refer to Synchronizing PLL R Dividers for more information. Table 40. Register 0x145 BIT NAME POR DEFAULT DESCRIPTION 7 NA 0 Reserved 6 PLL1R_SYNC_EN 0 Enable synchronization for PLL1 R divider 0: Not enabled 1: Enabled Select the source for PLL1 R divider synchronization Field Value 5:4 PLL1R_SYNC_SRC 0 Definition 0 (0x00) Reserved 1 (0x01) SYNC Pin 2 (0x02) CLKin0 3 (0x03) Reserved 3 PLL2R_SYNC_EN 0 Enable synchronization for PLL2 R divider. Synchronization for PLL2 R always comes from the SYNC pin. 0: Not enabled 1: Enabled 2:0 NA 0 Reserved 66 Submit Documentation Feedback Copyright © 2017–2018, Texas Instruments Incorporated Product Folder Links: LMK04832 LMK04832 www.ti.com SNAS688C – FEBRURAY 2017 – REVISED MAY 2018 8.6.2.4 (0x146 - 0x149) CLKin Control 8.6.2.4.1 CLKin_SEL_PIN_EN, CLKin_SEL_PIN_POL, CLKin2_EN, CLKin1_EN, CLKin0_EN, CLKin2_TYPE, CLKin1_TYPE, CLKin0_TYPE This register has CLKin enable and type controls. See Input Clock Switching for more info on how clock input selection works. Table 41. Register 0x146 BIT NAME POR DEFAULT 7 CLKin_SEL_PIN_EN 0 Enables pin control according to Figure 12. DESCRIPTION 6 CLKin_SEL_PIN_POL 0 Inverts the CLKin polarity for use in pin select mode. 0: Active High 1: Active Low 5 CLKin2_EN 0 Enable CLKin2 to be used during auto-switching. 0: Not enabled for auto mode 1: Enabled for auto clock switching mode 4 CLKin1_EN 1 Enable CLKin1 to be used during auto-switching. 0: Not enabled for auto mode 1: Enabled for auto clock switching mode 3 CLKin0_EN 1 Enable CLKin0 to be used during auto-switching. 0: Not enabled for auto mode 1: Enabled for auto clock switching mode 2 CLKin2_TYPE 0 1 CLKin1_TYPE 0 There are two buffer types for CLKin0, 1, and 2: bipolar and CMOS. Bipolar is recommended for differential inputs like LVDS or LVPECL. CMOS is recommended for DC-coupled single ended inputs. When using bipolar, CLKinX and CLKinX* must be AC-coupled. When using CMOS, CLKinX and CLKinX* may be AC or DC-coupled if the input signal is differential. If the input signal is single-ended the used input may be either AC or DC-coupled and the unused input must AC grounded. 0: Bipolar 1: MOS 0 CLKin0_TYPE 0 8.6.2.4.2 CLKin_SEL_AUTO_REVERT_EN, CLKin_SEL_AUTO_EN, CLKin_SEL_MANUAL, CLKin1_DEMUX, CLKin0_DEMUX Table 42. Register 0x147 BIT NAME POR DEFAULT DESCRIPTION 7 CLKin_SEL_ AUTO_REVERT_EN 0 When in auto clock switching mode. If active clock is detected on higher priority clock, the clock input is immediately switched. Highest priority input is lowest numbered active clock input. 6 CLKin_SEL_AUTO_EN 0 Enables pin control according to Figure 12. Selects the clock input when in manual mode according to Figure 12. 5:4 CLKin_SEL_MANUAL 1 Field Value Definition 0 (0x00) CLKin0 1 (0x01) CLKin1 2 (0x02) CLKin2 3 (0x03) Holdover Selects where the output of the CLKin1 buffer is directed. Field Value 3:2 CLKin1_DEMUX 0 CLKin1 Destination 0 (0x00) Fin 1 (0x01) Feedback Mux (0-delay mode) 2 (0x02) PLL1 3 (0x03) Off Submit Documentation Feedback Copyright © 2017–2018, Texas Instruments Incorporated Product Folder Links: LMK04832 67 LMK04832 SNAS688C – FEBRURAY 2017 – REVISED MAY 2018 www.ti.com Table 42. Register 0x147 (continued) BIT NAME POR DEFAULT DESCRIPTION Selects where the output of the CLKin0 buffer is directed. 1:0 CLKin0_DEMUX 3 Field Value CLKin0 Destination 0 (0x00) SYSREF Mux 1 (0x01) Reserved 2 (0x02) PLL1 3 (0x03) Off 8.6.2.4.3 CLKin_SEL0_MUX, CLKin_SEL0_TYPE This register has CLKin_SEL0 controls. Table 43. Register 0x148 BIT NAME POR DEFAULT 7:6 NA 0 DESCRIPTION Reserved This set the output value of the CLKin_SEL0 pin. This register only applies if CLKin_SEL0_TYPE is set to an output mode Field Value 5:3 CLKin_SEL0_MUX 0 Output Format 0 (0x00) Logic Low 1 (0x01) CLKin0 LOS 2 (0x02) CLKin0 Selected 3 (0x03) DAC Locked 4 (0x04) DAC Low 5 (0x05) DAC High 6 (0x06) SPI Readback 7 (0x07) Reserved This sets the IO type of the CLKin_SEL0 pin. 2:0 68 CLKin_SEL0_TYPE 2 Field Value Configuration Function 0 (0x00) Input 1 (0x01) Input with pullup resistor 2 (0x02) Input with pulldown resistor Input mode, see Input Clock Switching - Pin Select Mode for description of input mode. 3 (0x03) Output (push-pull) 4 (0x04) Output inverted (pushpull) 5 (0x05) Reserved 6 (0x06) Output (open-drain) Submit Documentation Feedback Output modes; the CLKin_SEL0_MUX register for description of outputs. Copyright © 2017–2018, Texas Instruments Incorporated Product Folder Links: LMK04832 LMK04832 www.ti.com SNAS688C – FEBRURAY 2017 – REVISED MAY 2018 8.6.2.4.4 SDIO_RDBK_TYPE, CLKin_SEL1_MUX, CLKin_SEL1_TYPE This register has CLKin_SEL1 controls and register readback SDIO pin type. Table 44. Register 0x149 BIT NAME POR DEFAULT DESCRIPTION 7 NA 0 Reserved 6 SDIO_RDBK_TYPE 1 Sets the SDIO pin to open drain when during SPI readback in 3 wire mode. 0: Output, push-pull 1: Output, open drain. This set the output value of the CLKin_SEL1 pin. This register only applies if CLKin_SEL1_TYPE is set to an output mode. Field Value 5:3 CLKin_SEL1_MUX 0 Output Format 0 (0x00) Logic Low 1 (0x01) CLKin1 LOS 2 (0x02) CLKin1 Selected 3 (0x03) DAC Locked 4 (0x04) DAC Low 5 (0x05) DAC High 6 (0x06) SPI Readback 7 (0x07) Reserved This sets the IO type of the CLKin_SEL1 pin. Field Value 2:0 CLKin_SEL1_TYPE 2 Configuration Function 0 (0x00) Input 1 (0x01) Input with pullup resistor 2 (0x02) Input with pulldown resistor Input mode, see Input Clock Switching - Pin Select Mode for description of input mode. 3 (0x03) Output (push-pull) 4 (0x04) Output inverted (pushpull) 5 (0x05) Reserved 6 (0x06) Output (open-drain) Output modes; see the CLKin_SEL1_MUX register for description of outputs. Submit Documentation Feedback Copyright © 2017–2018, Texas Instruments Incorporated Product Folder Links: LMK04832 69 LMK04832 SNAS688C – FEBRURAY 2017 – REVISED MAY 2018 www.ti.com 8.6.2.5 RESET_MUX, RESET_TYPE This register contains control of the RESET pin. Table 45. Register 0x14A BIT NAME POR DEFAULT 7:6 NA 0 DESCRIPTION Reserved This sets the output value of the RESET pin. This register only applies if RESET_TYPE is set to an output mode. 5:3 RESET_MUX 0 Field Value Output Format 0 (0x00) Logic Low 1 (0x01) Reserved 2 (0x02) CLKin2 Selected 3 (0x03) DAC Locked 4 (0x04) DAC Low 5 (0x05) DAC High 6 (0x06) SPI Readback This sets the IO type of the RESET pin. Field Value 2:0 70 RESET_TYPE 2 Configuration 0 (0x00) Input 1 (0x01) Input with pullup resistor 2 (0x02) Input with pulldown resistor 3 (0x03) Output (push-pull) 4 (0x04) Output inverted (pushpull) 5 (0x05) Reserved 6 (0x06) Output (open-drain) Submit Documentation Feedback Function Reset Mode Reset pin high = Reset Output modes; see the RESET_MUX register for description of outputs. Copyright © 2017–2018, Texas Instruments Incorporated Product Folder Links: LMK04832 LMK04832 www.ti.com SNAS688C – FEBRURAY 2017 – REVISED MAY 2018 8.6.2.6 (0x14B - 0x152) Holdover 8.6.2.6.1 LOS_TIMEOUT, LOS_EN, TRACK_EN, HOLDOVER_FORCE, MAN_DAC_EN, MAN_DAC[9:8] This register contains the holdover functions. Table 46. Register 0x14B BIT NAME POR DEFAULT DESCRIPTION This controls the amount of time in which no activity on a CLKin forces a clock switch event. 7:6 5 4 LOS_TIMEOUT LOS_EN TRACK_EN 0 Field Value Timeout 0 (0x00) 5 MHz typical 1 (0x01) 25 MHz typical 2 (0x02) 100 MHz typical 3 (0x03) 200 MHz typical 0 Enables the LOS (Loss-of-Signal) timeout control. Valid for MOS clock inputs. 0: Disabled 1: Enabled 0 Enable the DAC to track the PLL1 tuning voltage, optionally for use in holdover mode. After device reset, tracking starts at DAC code = 512. Tracking can be used to monitor PLL1 voltage in any mode. 0: Disabled 1: Enabled, will only track when PLL1 is locked. 3 HOLDOVER _FORCE 0 This bit forces holdover mode. When holdover mode is forced, if MAN_DAC_EN = 1, then the DAC will set the programmed MAN_DAC value. Otherwise the tracked DAC value will set the DAC voltage. 0: Disabled 1: Enabled. 2 MAN_DAC_EN 1 This bit enables the manual DAC mode. 0: Automatic 1: Manual 1:0 MAN_DAC[9:8] 2 See MAN_DAC for more information on the MAN_DAC settings. Submit Documentation Feedback Copyright © 2017–2018, Texas Instruments Incorporated Product Folder Links: LMK04832 71 LMK04832 SNAS688C – FEBRURAY 2017 – REVISED MAY 2018 www.ti.com 8.6.2.6.2 MAN_DAC These registers set the value of the DAC in holdover mode when used manually. Table 47. MAN_DAC[9:0] REGISTER 0x14B MSB LSB 0x14B[1:0] 0x14C[7:0] BIT NAME POR DEFAULT DESCRIPTION See LOS_TIMEOUT, LOS_EN, TRACK_EN, HOLDOVER_FORCE, MAN_DAC_EN, MAN_DAC[9:8] for information on these bits. 7:2 Sets the value of the manual DAC when in manual DAC mode. 0x14B 0x14C 1:0 7:0 MAN_DAC[9:8] 2 MAN_DAC[7:0] 0 Field Value DAC Value 0 (0x00) 0 1 (0x01) 1 2 (0x02) 2 ... ... 1022 (0x3FE) 1022 1023 (0x3FF) 1023 8.6.2.6.3 DAC_TRIP_LOW This register contains the high value at which holdover mode is entered. Table 48. Register 0x14D BIT NAME POR DEFAULT 7:6 NA 0 DESCRIPTION Reserved Voltage from GND at which holdover is entered if HOLDOVER_VTUNE_DET is enabled. 5:0 72 DAC_TRIP_LOW 0 Field Value DAC Trip Value 0 (0x00) 1 x Vcc / 64 1 (0x01) 2 x Vcc / 64 2 (0x02) 3 x Vcc / 64 3 (0x03) 4 x Vcc / 64 ... ... 61 (0x17) 62 x Vcc / 64 62 (0x18) 63 x Vcc / 64 63 (0x19) 64 x Vcc / 64 Submit Documentation Feedback Copyright © 2017–2018, Texas Instruments Incorporated Product Folder Links: LMK04832 LMK04832 www.ti.com SNAS688C – FEBRURAY 2017 – REVISED MAY 2018 8.6.2.6.4 DAC_CLK_MULT, DAC_TRIP_HIGH This register contains the multiplier for the DAC clock counter and the low value at which holdover mode is entered. Table 49. Register 0x14E BIT NAME POR DEFAULT DESCRIPTION This is the multiplier for the DAC_CLK_CNTR which sets the rate at which the DAC value is tracked. 7:6 DAC_CLK_MULT 0 Field Value DAC Multiplier Value 0 (0x00) 4 1 (0x01) 64 2 (0x02) 1024 3 (0x03) 16384 Voltage from Vcc at which holdover is entered if HOLDOVER_VTUNE_DET is enabled. 5:0 8.6.2.6.5 DAC_TRIP_HIGH 0 Field Value DAC Trip Value 0 (0x00) 1 x Vcc / 64 1 (0x01) 2 x Vcc / 64 2 (0x02) 3 x Vcc / 64 3 (0x03) 4 x Vcc / 64 ... ... 61 (0x17) 62 x Vcc / 64 62 (0x18) 63 x Vcc / 64 63 (0x19) 64 x Vcc / 64 DAC_CLK_CNTR This register contains the value of the DAC when in tracked mode. Table 50. Register 0x14F BIT NAME POR DEFAULT DESCRIPTION This with DAC_CLK_MULT set the rate at which the DAC is updated. The update rate is = DAC_CLK_MULT * DAC_CLK_CNTR / PLL1 PDF 7:0 DAC_CLK_CNTR 127 Field Value DAC Value 0 (0x00) 0 1 (0x01) 1 2 (0x02) 2 3 (0x03) 3 ... ... 253 (0xFD) 253 254 (0xFE) 254 255 (0xFF) 255 Submit Documentation Feedback Copyright © 2017–2018, Texas Instruments Incorporated Product Folder Links: LMK04832 73 LMK04832 SNAS688C – FEBRURAY 2017 – REVISED MAY 2018 www.ti.com 8.6.2.6.6 CLKin_OVERRIDE, HOLDOVER_EXIT_MODE, HOLDOVER_PLL1_DET, LOS_EXTERNAL_INPUT, HOLDOVER_VTUNE_DET, CLKin_SWITCH_CP_TRI, HOLDOVER_EN This register has controls for enabling clock in switch events. Table 51. Register 0x150 BIT NAME POR DEFAULT 7 NA 0 Reserved 6 CLKin _OVERRIDE 0 When manual clock select is enabled, then CLKin_SEL_MANUAL = 0/1/2 selects a manual clock input. CLKin_OVERRIDE = 1 will force that clock input. CLKin_OVERRIDE = 1 is used with clock distribution mode for best performance. 0: Normal, no override. 1: Force select of only CLKin0/1/2 as specified by CLKin_SEL_MANUAL in manual mode. Dynamic digital delay will not operate. 5 HOLDOVER_ EXIT_MODE 0 0: Exit based on LOS status. If clock is active by LOS, then begin exit. 1: Exit based on PLL1 DLD. When the PLL1 phase detector confirming valid clock. 4 HOLDOVER _PLL1_DET 0 This enables the HOLDOVER when PLL1 lock detect signal transitions from high to low. 0: PLL1 DLD does not cause a clock switch event 1: PLL1 DLD causes a clock switch event 0 Use external signals for LOS status instead of internal LOS circuitry. CLKin_SEL0 pin is used for CLKin0 LOS, CLKin_SEL1 pin is used for CLKin1 LOS, and Status_LD1 is used for CLKin2 LOS. For any of these pins to be valid, the corresponding _TYPE register must be programmed as an input. 0: Disabled 1: Enabled 3 74 DESCRIPTION LOS_EXTERNAL_INPUT 2 HOLDOVER_ VTUNE_DET 0 Enables the DAC Vtune rail detector. When the DAC achieves a specified Vtune, if this bit is enabled, the current clock input is considered invalid and an input clock switch event is generated. 0: Disabled 1: Enabled 1 CLKin_SWITCH_CP_TRI 0 Enable clock switching with tri-stated charge pump. 0: Not enabled. 1: PLL1 charge pump tri-states during clock switching. 0 HOLDOVER_EN 0 Sets whether holdover mode is active or not. 0: Disabled 1: Enabled Submit Documentation Feedback Copyright © 2017–2018, Texas Instruments Incorporated Product Folder Links: LMK04832 LMK04832 www.ti.com SNAS688C – FEBRURAY 2017 – REVISED MAY 2018 8.6.2.6.7 HOLDOVER_DLD_CNT Table 52. HOLDOVER_DLD_CNT[13:0] MSB LSB 0x151[5:0] / HOLDOVER_DLD_CNT[13:8] 0x152[7:0] / HOLDOVER_DLD_CNT[7:0] This register has the number of valid clocks of PLL1 PDF before holdover is exited. Table 53. Registers 0x151 and 0x152 REGISTER BIT NAME POR DEFAULT 0x151 7:6 NA 0 DESCRIPTION Reserved The number of valid clocks of PLL1 PDF before holdover mode is exited. 0x151 0x152 5:0 7:0 HOLDOVER _DLD_CNT[13:8] HOLDOVER _DLD_CNT[7:0] 2 0 Field Value Count Value 0 (0x00) 0 1 (0x01) 1 2 (0x02) 2 ... ... 16382 (0x3FFE) 16382 16383 (0x3FFF) 16383 Submit Documentation Feedback Copyright © 2017–2018, Texas Instruments Incorporated Product Folder Links: LMK04832 75 LMK04832 SNAS688C – FEBRURAY 2017 – REVISED MAY 2018 www.ti.com 8.6.2.7 (0x153 - 0x15F) PLL1 Configuration 8.6.2.7.1 CLKin0_R Table 54. CLKin0_R[13:0] MSB LSB 0x153[5:0] / CLKin0_R[13:8] 0x154[7:0] / CLKin0_R[7:0] These registers contain the value of the CLKin0 divider. Table 55. Registers 0x153 and 0x154 REGISTER BIT NAME POR DEFAULT 0x153 7:6 NA 0 DESCRIPTION Reserved The value of PLL1 N counter when CLKin0 is selected. 0x153 0x154 5:0 7:0 CLKin0_R[13:8] 0 CLKin0_R[7:0] 120 Field Value Divide Value 0 (0x00) Reserved 1 (0x01) 1 2 (0x02) 2 ... ... 16382 (0x3FFE) 16382 16383 (0x3FFF) 16383 8.6.2.7.2 CLKin1_R Table 56. CLKin1_R[13:0] MSB LSB 0x155[5:0] / CLKin1_R[13:8] 0x156[7:0] / CLKin1_R[7:0] These registers contain the value of the CLKin1 R divider. Table 57. Registers 0x155 and 0x156 REGISTER BIT NAME POR DEFAULT 0x155 7:6 NA 0 DESCRIPTION Reserved The value of PLL1 N counter when CLKin1 is selected. 0x155 0x156 76 5:0 7:0 CLKin1_R[13:8] CLKin1_R[7:0] 0 150 Field Value Divide Value 0 (0x00) Reserved 1 (0x01) 1 2 (0x02) 2 ... ... 16382 (0x3FFE) 16382 16383 (0x3FFF) 16383 Submit Documentation Feedback Copyright © 2017–2018, Texas Instruments Incorporated Product Folder Links: LMK04832 LMK04832 www.ti.com SNAS688C – FEBRURAY 2017 – REVISED MAY 2018 8.6.2.7.3 CLKin2_R Table 58. CLKin2_R[13:0] MSB LSB 0x157[5:0] / CLKin2_R[13:8] 0x158[7:0] / CLKin2_R[7:0] Table 59. Registers 0x157 and 0x158 REGISTER BIT NAME POR DEFAULT 0x157 7:6 NA 0 DESCRIPTION Reserved The value of PLL1 N counter when CLKin2 is selected. 0x157 0x158 5:0 7:0 CLKin2_R[13:8] 0 CLKin2_R[7:0] 150 Field Value Divide Value 0 (0x00) Reserved 1 (0x01) 1 2 (0x02) 2 ... ... 16382 (0x3FFE) 16382 16383 (0x3FFF) 16383 8.6.2.7.4 PLL1_N Table 60. PLL1_N[13:0] MSB LSB 0x159[5:0] / PLL1_N[13:8] 0x15A[7:0] / PLL1_N[7:0] These registers contain the N divider value for PLL1. Table 61. Registers 0x159 and 0x15A REGISTER BIT NAME POR DEFAULT 0x159 7:6 NA 0 DESCRIPTION Reserved The value of PLL1 N counter. 0x159 0x15A 5:0 7:0 PLL1_N[13:8] PLL1_N[7:0] 0 Field Value Divide Value 0 (0x00) Not Valid 1 (0x01) 1 2 (0x02) 2 ... ... 4,095 (0xFFF) 4,095 120 Submit Documentation Feedback Copyright © 2017–2018, Texas Instruments Incorporated Product Folder Links: LMK04832 77 LMK04832 SNAS688C – FEBRURAY 2017 – REVISED MAY 2018 www.ti.com 8.6.2.7.5 PLL1_WND_SIZE, PLL1_CP_TRI, PLL1_CP_POL, PLL1_CP_GAIN This register controls the PLL1 phase detector. Table 62. Register 0x15B BIT NAME POR DEFAULT DESCRIPTION PLL1_WND_SIZE sets the window size used for digital lock detect for PLL1. If the phase error between the reference and feedback of PLL1 is less than specified time, then the PLL1 lock counter increments. 7:6 5 4 PLL1_WND_SIZE PLL1_CP_TRI PLL1_CP_POL 3 Field Value Definition 0 (0x00) 4 ns 1 (0x01) 9 ns 2 (0x02) 19 ns 3 (0x03) 43 ns 0 This bit allows for the PLL1 charge pump output pin, CPout1, to be placed into TRI-STATE. 0: PLL1 CPout1 is active 1: PLL1 CPout1 is at TRI-STATE 1 PLL1_CP_POL sets the charge pump polarity for PLL1. Many VCXOs use positive slope. A positive slope VCXO increases output frequency with increasing voltage. A negative slope VCXO decreases output frequency with increasing voltage. 0: Negative Slope VCO/VCXO 1: Positive Slope VCO/VCXO This bit programs the PLL1 charge pump output current level. 3:0 78 PLL1_CP_GAIN 4 Field Value Gain 0 (0x00) 50 µA 1 (0x01) 150 µA 2 (0x02) 250 µA 3 (0x03) 350 µA 4 (0x04) 450 µA ... ... 14 (0x0E) 1450 µA 15 (0x0F) 1550 µA Submit Documentation Feedback Copyright © 2017–2018, Texas Instruments Incorporated Product Folder Links: LMK04832 LMK04832 www.ti.com SNAS688C – FEBRURAY 2017 – REVISED MAY 2018 8.6.2.7.6 PLL1_DLD_CNT Table 63. PLL1_DLD_CNT[13:0] MSB LSB 0x15C[5:0] / PLL1_DLD_CNT[13:8] 0x15D[7:0] / PLL1_DLD_CNT[7:0] This register contains the value of the PLL1 DLD counter. Table 64. Registers 0x15C and 0x15D REGISTER BIT NAME POR DEFAULT 0x15C 7:6 NA 0 0x15C 0x15D PLL1_DLD _CNT[13:8] 5:0 PLL1_DLD _CNT[7:0] 7:0 DESCRIPTION Reserved The reference and feedback of PLL1 must be within the window of phase error as specified by PLL1_WND_SIZE for this many phase detector cycles before PLL1 digital lock detect is asserted. 32 Field Value Delay Value 0 (0x00) Reserved 1 (0x01) 1 2 (0x02) 2 3 (0x03) 3 ... ... 16,382 (0x3FFE) 16,382 16,383 (0x3FFF) 16,383 0 8.6.2.7.7 HOLDOVER_EXIT_NADJ Table 65. Register 0x15E BIT NAME POR DEFAULT 7:5 NA 0 Reserved DESCRIPTION 4:0 HOLDOVER_EXIT_NADJ 30 When holdover exists, PLL1 R counter and PLL1 N counter are reset. HOLDOVER_EXIT_NADJ is a 2s complement number which provides a relative timing offset between PLL1 R and PLL1 N divider. Submit Documentation Feedback Copyright © 2017–2018, Texas Instruments Incorporated Product Folder Links: LMK04832 79 LMK04832 SNAS688C – FEBRURAY 2017 – REVISED MAY 2018 www.ti.com 8.6.2.7.8 PLL1_LD_MUX, PLL1_LD_TYPE This register configures the PLL1 LD pin. Table 66. Register 0x15F BIT NAME POR DEFAULT DESCRIPTION This sets the output value of the Status_LD1 pin. 7:3 PLL1_LD_MUX 1 Field Value MUX Value 0 (0x00) Logic Low 1 (0x01) PLL1 DLD 2 (0x02) PLL2 DLD 3 (0x03) PLL1 & PLL2 DLD 4 (0x04) Holdover Status 5 (0x05) DAC Locked 6 (0x06) Reserved 7 (0x07) SPI Readback 8 (0x08) DAC Rail 9 (0x09) DAC Low 10 (0x0A) DAC High 11 (0x0B) PLL1_N 12 (0x0C) PLL1_N/2 13 (0x0D) PLL2_N 14 (0x0E) PLL2_N/2 15 (0x0F) PLL1_R 16 (0x10) PLL1_R/2 17 (0x11) PLL2_R (1) 18 (0x12) PLL2_R/2 (1) Sets the IO type of the Status_LD1 pin. Field Value 2:0 (1) 80 PLL1_LD_TYPE 6 TYPE 0 (0x00) Input for External CLKin2 LOS 1 (0x01) Input for External CLKin2 LOS (pullup) 2 (0x02) Input for External CLKin2 LOS (pulldwn) 3 (0x03) Output (push-pull) 4 (0x04) Output inverted (push-pull) 5 (0x05) Reserved 6 (0x06) Output (open-drain) Only valid when PLL2_LD_MUX is not set to 2 (PLL2_DLD) or 3 (PLL1 & PLL2 DLD). Submit Documentation Feedback Copyright © 2017–2018, Texas Instruments Incorporated Product Folder Links: LMK04832 LMK04832 www.ti.com SNAS688C – FEBRURAY 2017 – REVISED MAY 2018 8.6.2.8 (0x160 - 0x16E) PLL2 Configuration 8.6.2.8.1 PLL2_R Table 67. PLL2_R[11:0] MSB LSB 0x160[3:0] / PLL2_R[11:8] 0x161[7:0] / PLL2_R[7:0] This register contains the value of the PLL2 R divider. Table 68. Registers 0x160 and 0x161 REGISTER BIT NAME POR DEFAULT 0x160 7:4 NA 0 DESCRIPTION Reserved Valid values for the PLL2 R divider. 0x160 0x161 3:0 7:0 PLL2_R[11:8] PLL2_R[7:0] 0 Field Value Divide Value 0 (0x00) Not Valid 1 (0x01) 1 2 (0x02) 2 3 (0x03) 3 ... ... 4,094 (0xFFE) 4,094 4,095 (0xFFF) 4,095 2 Submit Documentation Feedback Copyright © 2017–2018, Texas Instruments Incorporated Product Folder Links: LMK04832 81 LMK04832 SNAS688C – FEBRURAY 2017 – REVISED MAY 2018 www.ti.com 8.6.2.8.2 PLL2_P, OSCin_FREQ, PLL2_REF_2X_EN This register sets other PLL2 functions. Table 69. Register 0x162 BIT NAME POR DEFAULT DESCRIPTION The PLL2 N Prescaler divides the output of the VCO as selected by Mode_MUX1 and is connected to the PLL2 N divider. 7:5 PLL2_P 2 Field Value Value 0 (0x00) 8 1 (0x01) 2 2 (0x02) 2 3 (0x03) 3 4 (0x04) 4 5 (0x05) 5 6 (0x06) 6 7 (0x07) 7 The frequency of the PLL2 reference input to the PLL2 Phase Detector (OSCin/OSCin* port) must be programmed in order to support proper operation of the frequency calibration routine which locks the internal VCO to the target frequency. 4:2 1 0 82 OSCin_FREQ NA PLL2_REF_2X_EN 3 Field Value OSCin Frequency 0 (0x00) 0 to 63 MHz 1 (0x01) >63 MHz to 127 MHz 2 (0x02) >127 MHz to 255 MHz 3 (0x03) Reserved 4 (0x04) >255 MHz to 500 MHz 5 (0x05) to 7(0x07) Reserved 0 Reserved 1 Enabling the PLL2 reference frequency doubler allows for higher phase detector frequencies on PLL2 than would normally be allowed with the given VCXO frequency. Higher phase detector frequencies reduces the PLL2 N values which makes the design of wider loop bandwidth filters possible. 0: Doubler Disabled 1: Doubler Enabled Submit Documentation Feedback Copyright © 2017–2018, Texas Instruments Incorporated Product Folder Links: LMK04832 LMK04832 www.ti.com 8.6.2.8.3 SNAS688C – FEBRURAY 2017 – REVISED MAY 2018 PLL2_N_CAL PLL2_N_CAL[17:0] PLL2 never uses 0-delay during frequency calibration. These registers contain the value of the PLL2 N divider used with PLL2 pre-scaler during calibration for cascaded 0-delay mode. Once calibration is complete, PLL2 will use PLL2_N value. Cascaded 0-delay mode occurs when PLL2_NCLK_MUX = 1. Table 70. PLL2_N_CAL[17:0] MSB — LSB 0x163[1:0] / PLL2_N_CAL[17:16] 0x164[7:0] / PLL2_N_CAL[15:8] 0x165[7:0] / PLL2_N_CAL[7:0] Table 71. Registers 0x163, 0x164, and 0x165 REGISTER BIT NAME POR DEFAULT 0x163 7:2 NA 0 0x163 1:0 PLL2_N _CAL[17:16] 0 0x164 0x165 7:0 7:0 PLL2_N_CAL[15:8] PLL2_N_CAL[7:0] DESCRIPTION Reserved Field Value Divide Value 0 (0x00) Not Valid 1 (0x01) 1 0 12 2 (0x02) 2 ... ... 262,143 (0x3FFFF) 262,143 8.6.2.8.4 PLL2_N This register disables frequency calibration and sets the PLL2 N divider value. Programming register 0x168 starts a VCO calibration routine if PLL2_FCAL_DIS = 0. Table 72. PLL2_N[17:0] MSB — LSB 0x166[1:0] / PLL2_N[17:16] 0x167[7:0] / PLL2_N[15:8] 0x168[7:0] / PLL2_N[7:0] Table 73. Registers 0x166, 0x167, and 0x168 REGISTER BIT NAME POR DEFAULT 0x166 7:3 NA 0 0x166 1:0 PLL2_N[17:16] 0 0x167 7:0 PLL2_N[15:8] 0 0x168 7:0 PLL2_N[7:0] 12 DESCRIPTION Reserved Field Value Divide Value 0 (0x00) Not Valid 1 (0x01) 1 2 (0x02) 2 ... ... 262,143 (0x3FFFF) 262,143 Submit Documentation Feedback Copyright © 2017–2018, Texas Instruments Incorporated Product Folder Links: LMK04832 83 LMK04832 SNAS688C – FEBRURAY 2017 – REVISED MAY 2018 www.ti.com 8.6.2.8.5 PLL2_WND_SIZE, PLL2_CP_GAIN, PLL2_CP_POL, PLL2_CP_TRI This register controls the PLL2 phase detector. Table 74. Register 0x169 BIT NAME POR DEFAULT 7 NA 0 DESCRIPTION Reserved PLL2_WND_SIZE sets the window size used for digital lock detect for PLL2. If the phase error between the reference and feedback of PLL2 is less than specified time, then the PLL2 lock counter increments. 6:5 PLL2_WND_SIZE 2 Field Value Maximum Phase Detector Frequency / Window Size 0 (0x00) Reserved 1 (0x01) 320 MHz / 1 ns 2 (0x02) 240 MHz / 1.8 ns 3 (0x03) 160 MHz / 2.6 ns This bit programs the PLL2 charge pump output current level. The table below also illustrates the impact of the PLL2 TRISTATE bit in conjunction with PLL2_CP_GAIN. 4:3 2 1 0 84 PLL2_CP_GAIN PLL2_CP_POL PLL2_CP_TRI PLL2_DLD_EN 3 0 Field Value Definition 0 (0x00) Reserved 1 (0x01) Reserved 2 (0x02) 1600 µA 3 (0x03) 3200 µA PLL2_CP_POL sets the charge pump polarity for PLL2. The internal VCO requires the negative charge pump polarity to be selected. Many VCOs use positive slope. A positive slope VCO increases output frequency with increasing voltage. A negative slope VCO decreases output frequency with increasing voltage. Field Value Description 0 Negative Slope VCO/VCXO 1 Positive Slope VCO/VCXO 0 PLL2_CP_TRI TRI-STATEs the output of the PLL2 charge pump. 0: Disabled 1: TRI-STATE 0 PLL2 DLD circuitry is enabled when the PLL2 DLD is used to provide an output to a lock detect status pin. PLL2_DLD_EN allows enabling the PLL2 DLD circuitry without needing to provide PLL2 DLD to a status pin. This enables PLL2 DLD status to be read back using SPI while allowing the Status pins to be used for other purposes. 0: PLL2 DLD circuitry is on only of PLL2 DLD or PLL1 + PLL2 DLD signal is output from a Status_LD_MUX. 1: PLL2 DLD circuitry is forced on. Submit Documentation Feedback Copyright © 2017–2018, Texas Instruments Incorporated Product Folder Links: LMK04832 LMK04832 www.ti.com SNAS688C – FEBRURAY 2017 – REVISED MAY 2018 8.6.2.8.6 PLL2_DLD_CNT Table 75. PLL2_DLD_CNT[13:0] MSB LSB 0x16A[5:0] / PLL2_DLD_CNT[13:8] 0x16B[7:0] / PLL2_DLD_CNT[7:0] This register has the value of the PLL2 DLD counter. Table 76. Registers 0x16A and 0x16B REGISTER BIT NAME POR DEFAULT 0x16A 7 NA 0 0x16A 0x16B 5:0 7:0 PLL2_DLD _CNT[13:8] PLL2_DLD_CNT 32 DESCRIPTION Reserved The reference and feedback of PLL2 must be within the window of phase error as specified by PLL2_WND_SIZE for PLL2_DLD_CNT cycles before PLL2 digital lock detect is asserted. Field Value Divide Value 0 (0x00) Not Valid 1 (0x01) 1 2 (0x02) 2 3 (0x03) 3 ... ... 16,382 (0x3FFE) 16,382 16,383 (0x3FFF) 16,383 0 Submit Documentation Feedback Copyright © 2017–2018, Texas Instruments Incorporated Product Folder Links: LMK04832 85 LMK04832 SNAS688C – FEBRURAY 2017 – REVISED MAY 2018 www.ti.com 8.6.2.8.7 PLL2_LD_MUX, PLL2_LD_TYPE This register sets the output value of the Status_LD2 pin. Table 77. Register 0x16E BIT NAME POR DEFAULT DESCRIPTION This sets the output value of the Status_LD2 pin. 7:3 PLL2_LD_MUX 0 Field Value MUX Value 0 (0x00) Logic Low 1 (0x01) PLL1 DLD 2 (0x02) PLL2 DLD 3 (0x03) PLL1 & PLL2 DLD 4 (0x04) Holdover Status 5 (0x05) DAC Locked 6 (0x06) Reserved 7 (0x07) SPI Readback 8 (0x08) DAC Rail 9 (0x09) DAC Low 10 (0x0A) DAC High 11 (0x0B) PLL1_N 12 (0x0C) PLL1_N/2 13 (0x0D) PLL2_N 14 (0x0E) PLL2_N/2 15 (0x0F) PLL1_R 16 (0x10) PLL1_R/2 17 (0x11) PLL2_R (1) 18 (0x12) PLL2_R/2 (1) Sets the IO type of the Status_LD2 pin. 2:0 (1) 86 PLL2_LD_TYPE 6 Field Value TYPE 0 (0x00) Reserved 1 (0x01) Reserved 2 (0x02) Reserved 3 (0x03) Output (push-pull) 4 (0x04) Output inverted (push-pull) 5 (0x05) Reserved 6 (0x06) Output (open drain) Only valid when PLL1_LD_MUX is not set to 2 (PLL2_DLD) or 3 (PLL1 & PLL2 DLD). Submit Documentation Feedback Copyright © 2017–2018, Texas Instruments Incorporated Product Folder Links: LMK04832 LMK04832 www.ti.com SNAS688C – FEBRURAY 2017 – REVISED MAY 2018 8.6.2.9 (0x16F - 0x555) Misc Registers 8.6.2.9.1 PLL2_PRE_PD, PLL2_PD Table 78. Register 0x173 BIT NAME POR DEFAULT 7 N/A 0 Reserved DESCRIPTION 6 PLL2_PRE_PD 1 Powerdown PLL2 prescaler 0: Normal Operation 1: Powerdown 5 PLL2_PD 1 Powerdown PLL2 0: Normal Operation 1: Powerdown 4:0 N/A 16 Reserved 8.6.2.9.2 PLL1R_RST Refer to PLL1 R Divider Synchronization for more information on synchronizing PLL1 R divider. Table 79. Register 0x177 BIT NAME POR DEFAULT 7:6 NA 0 Reserved DESCRIPTION 5 PLL1R_RST 0 When set, PLL1 R divider will be held in reset. PLL1 will never lock with PLL1R_RST = 1. This bit is used in when synchronizing the PLL1 R divider. 0: PLL1 R divider normal operation. 1: PLL1 R divider held in reset. 4:0 NA 0 Reserved Submit Documentation Feedback Copyright © 2017–2018, Texas Instruments Incorporated Product Folder Links: LMK04832 87 LMK04832 SNAS688C – FEBRURAY 2017 – REVISED MAY 2018 www.ti.com 8.6.2.9.3 CLR_PLL1_LD_LOST, CLR_PLL2_LD_LOST Table 80. Register 0x182 BIT NAME POR DEFAULT 7:2 NA 0 Reserved DESCRIPTION 1 CLR_PLL1_LD_LOST 0 To reset RB_PLL1_LD_LOST, write CLR_PLL1_LD_LOST with 1 and then 0. 0: RB_PLL1_LD_LOST will be set on next falling PLL1 DLD edge. 1: RB_PLL1_LD_LOST is held clear (0). User must clear this bit to allow RB_PLL1_LD_LOST to become set again. 0 CLR_PLL2_LD_LOST 0 To reset RB_PLL2_LD_LOST, write CLR_PLL2_LD_LOST with 1 and then 0. 0: RB_PLL2_LD_LOST will be set on next falling PLL2 DLD edge. 1: RB_PLL2_LD_LOST is held clear (0). User must clear this bit to allow RB_PLL2_LD_LOST to become set again. 8.6.2.9.4 RB_PLL1_LD_LOST, RB_PLL1_LD, RB_PLL2_LD_LOST, RB_PLL2_LD For PLL2 DLD read back to be valid, either PLL2 DLD or PLL1 + PLL2 DLD signal must be output from the status pins, or PLL2_DLD_EN bit must be set = 1. Table 81. Register 0x183 BIT NAME POR DEFAULT 7:4 N/A 0 Reserved 3 RB_PLL1_LD_LOST 0 This is set when PLL1 DLD edge falls. Does not set if cleared while PLL1 DLD is low. 2 RB_PLL1_LD 0 Read back 0: PLL1 DLD is low. Read back 1: PLL1 DLD is high. 1 RB_PLL2_LD_LOST 0 This is set when PLL2 DLD edge falls. Does not set if cleared while PLL2 DLD is low. 0 PLL1_LD_MUX or PLL2_LD_MUX must select setting 2 (PLL2 DLD) for valid reading of this bit. Read back 0: PLL2 DLD is low. Read back 1: PLL2 DLD is high. 0 88 RB_PLL2_LD DESCRIPTION Submit Documentation Feedback Copyright © 2017–2018, Texas Instruments Incorporated Product Folder Links: LMK04832 LMK04832 www.ti.com SNAS688C – FEBRURAY 2017 – REVISED MAY 2018 8.6.2.9.5 RB_DAC_VALUE (MSB), RB_CLKinX_SEL, RB_CLKinX_LOS This register provides read back access to CLKinX selection indicator and CLKinX LOS indicator. The 2 MSBs are shared with the RB_DAC_VALUE. See RB_DAC_VALUE section. Table 82. Register 0x184 BIT NAME 7:6 RB_DAC_VALUE[9:8] POR DEFAULT DESCRIPTION 5 RB_CLKin2_SEL Read back 0: CLKin2 is not selected for input to PLL1. Read back 1: CLKin2 is selected for input to PLL1. 4 RB_CLKin1_SEL Read back 0: CLKin1 is not selected for input to PLL1. Read back 1: CLKin1 is selected for input to PLL1. 3 RB_CLKin0_SEL Read back 0: CLKin0 is not selected for input to PLL1. Read back 1: CLKin0 is selected for input to PLL1. 2 N/A 1 RB_CLKin1_LOS Read back 1: CLKin1 LOS is active. Read back 0: CLKin1 LOS is not active. 0 RB_CLKin0_LOS Read back 1: CLKin0 LOS is active. Read back 0: CLKin0 LOS is not active. See RB_DAC_VALUE section. 8.6.2.9.6 RB_DAC_VALUE Contains the value of the DAC for user readback. Table 83. RB_DAC_VALUE[9:0] MSB LSB 0x184 [7:6] / RB_DAC_VALUE[9:8] 0x185 [7:0] / RB_DAC_VALUE[7:0] Table 84. Registers 0x184 and 0x185 REGISTER 0x184 0x185 BIT NAME POR DEFAULT 7:6 RB_DAC_ VALUE[9:8] 2 7:0 RB_DAC_ VALUE[7:0] 0 DAC value is 512 on power on reset, if PLL1 locks upon power-up the DAC value will change. 8.6.2.9.7 RB_HOLDOVER Table 85. Register 0x188 BIT NAME 7:5 N/A 4 RB_HOLDOVER 3:0 N/A POR DEFAULT DESCRIPTION Reserved Read back 0: Not in HOLDOVER. Read back 1: In HOLDOVER. Reserved 8.6.2.9.8 SPI_LOCK Prevents SPI registers from being written to, except for 0x555. This register cannot be read back. Table 86. Register 0x555 BIT NAME POR DEFAULT 7:0 SPI_LOCK 0 DESCRIPTION 0: Registers unlocked. 1 to 255: Registers locked. Submit Documentation Feedback Copyright © 2017–2018, Texas Instruments Incorporated Product Folder Links: LMK04832 89 LMK04832 SNAS688C – FEBRURAY 2017 – REVISED MAY 2018 www.ti.com 9 Application and Implementation NOTE Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining suitability of components for their purposes. Customers should validate and test their design implementation to confirm system functionality. 9.1 Application Information To assist customers in frequency planning and design of loop filters, Texas Instruments provides Clock Architect and PLLatinum Sim and on ti.com. 9.1.1 Digital Lock Detect Frequency Accuracy The digital lock detect circuit is used to determine PLL1 locked, PLL2 locked, and holdover exit events. A window size and lock count register are programmed to set a ppm frequency accuracy of reference to feedback signals of the PLL for each event to occur. When a PLL digital lock event occurs, the digital lock detect of thePLL is asserted true. When the holdover exit event occurs, the device will exit holdover mode when HOLDOVER_EXIT_MODE = 1 (Exit based on DLD). Table 87. Digital Lock Detect Related Fields EVENT PLL WINDOW SIZE LOCK COUNT PLL1 Locked PLL1 PLL1_WND_SIZE PLL1_DLD_CNT PLL2 Locked PLL2 PLL2_WND_SIZE PLL2_DLD_CNT Holdover exit PLL1 PLL1_WND_SIZE HOLDOVER_DLD_CNT For a digital lock detect event to occur, there must be a lock count number of phase detector cycles of PLLX during which the time and phase error of the PLLX_R reference and PLLX_N feedback signal edges are within the user programmable window size. Because there must be at least one lock count phase detector event before a lock event occurs, a minimum digital lock event time can be calculated as lock count / fPDX where X = 1 for PLL1 or 2 for PLL2. By using Equation 4, values for a lock count and window size can be chosen to set the frequency accuracy required by the system in ppm before the digital lock detect event occurs: ppm = 1e6 × PLLX_WND_SIZE × fPDX PLLX_DLD_CNT (4) The effect of the lock count value is that it shortens the effective lock window size by dividing the window size by lock count. If at any time the PLLX_R reference and PLLX_N feedback signals are outside the time window set by window size, then the lock count value is reset to 0. 9.1.1.1 Minimum Lock Time Calculation Example To calculate the minimum PLL2 digital lock time given a PLL2 phase detector frequency of 40 MHz and PLL2_DLD_CNT = 10,000. Then, the minimum lock time of PLL2 will be 10,000 / 40 MHz = 250 µs. 90 Submit Documentation Feedback Copyright © 2017–2018, Texas Instruments Incorporated Product Folder Links: LMK04832 LMK04832 www.ti.com SNAS688C – FEBRURAY 2017 – REVISED MAY 2018 9.1.2 Driving CLKin AND OSCin Inputs 9.1.2.1 Driving CLKin and OSCin PINS With a Differential Source CLKin and OSCin pins can be driven by differential signals. TI recommends setting the input mode to bipolar (CLKinX_BUF_TYPE = 0) when using differential reference clocks. The LMK04832 internally biases the input pins so the differential interface should be AC-coupled. The recommended circuits for driving the CLKin pins with either LVDS or LVPECL are shown in Figure 21 and Figure 22. 100-: Trace (Differential) LVDS 100 : CLKinX 0.1 PF LMK04832 Input 0.1 PF CLKinX* Copyright © 2017, Texas Instruments Incorporated 240 : Figure 21. CLKinX/X* or OSCin Termination for an LVDS Reference Clock Source LVPECL Ref Clk 0.1 PF 0.1 PF 100-: Trace (Differential) 100 : CLKinX 0.1 PF LMK04832 Input 0.1 PF 240 : CLKinX* Copyright © 2017, Texas Instruments Incorporated Figure 22. CLKinX/X* or OSCin Termination for an LVPECL Reference Clock Source Finally, a reference clock source that produces a differential sine wave output can drive the CLKin pins using the following circuit. Note: the signal level must conform to the requirements for the CLKin pins listed in the Electrical Characteristics. 100-: Trace (Differential) Differential Sinewave Clock Source 100 : CLKinX 0.1 PF 0.1 PF LMK04832 Input CLKinX* Copyright © 2017, Texas Instruments Incorporated Figure 23. CLKinX/X* or OSCin Termination for a Differential Sinewave Reference Clock Source Submit Documentation Feedback Copyright © 2017–2018, Texas Instruments Incorporated Product Folder Links: LMK04832 91 LMK04832 SNAS688C – FEBRURAY 2017 – REVISED MAY 2018 www.ti.com 9.1.2.2 Driving CLKin Pins With a Single-Ended Source The CLKin and OSCin pins of the LMK04832 can be driven using a single-ended reference clock source, for example, either a sine wave source or an LVCMOS/LVTTL source. CLKin supports both AC coupling or DC coupling. OSCin must use AC coupling. In the case of the sine wave source that is expecting a 50-Ω load, TI recommends using AC coupling as shown in Figure 24 with a 50-Ω termination. NOTE The signal level must conform to the requirements for the CLKin or OSCin pins listed in the Electrical Characteristics. To support LOS functionality, CLKinX_BUF_TYPE must be set to MOS mode (CLKinX_BUF_TYPE = 1) when AC-coupled. When AC coupling, if the 100-Ω termination is placed on the IC side of the blocking capacitors, then the LOS functionality will not be valid. 0.1 PF 50-: Trace CLKinX 50 : Clock Source 0.1 PF LMK04832 CLKinX* Copyright © 2017, Texas Instruments Incorporated Figure 24. CLKinX/X* Single-Ended Termination If the CLKin pins are being driven with a single-ended LVCMOS/LVTTL source, either DC coupling or AC coupling may be used. If DC coupling is used, the CLKinX_BUF_TYPE should be set to MOS buffer mode (CLKinX_BUF_TYPE = 1) and the voltage swing of the source must meet the specifications for DC -oupled, MOS-mode clock inputs given in the Electrical Characteristics. If AC coupling is used, the CLKinX_BUF_TYPE should be set to the bipolar buffer mode (CLKinX_BUF_TYPE = 0). The voltage swing at the input pins must meet the specifications for AC-coupled, bipolar mode clock inputs given in the Electrical Characteristics. In this case, some attenuation of the clock input level may be required. A simple resistive divider circuit before the ACcoupling capacitor is sufficient. 50-: Trace CLKinX LMK04832 LVCMOS/LVTTL Clock Source 0.1 PF CLKinX* Copyright © 2017, Texas Instruments Incorporated Figure 25. DC-Coupled LVCMOS/LVTTL Reference Clock 9.1.3 OSCin Doubler for Best Phase Noise Performance PLL2 OSCin input path includes an on-chip Frequency Doubler. To have the best phase noise performance, it is recommended to maximize the PLL2 phase detector frequency. For example, using 122.88MHz VCXO , PLL2 phase detector frequency can be increased to 245.76MHz by setting PLL2_REF_2X_EN. Doubler path is a high performance path for OSCin clock. For configuration where doubler cannot be used, it is recomended to use Doubler and PLL2_RDIV=2. To have deterministic phase relationship between input clock and output clocks, 0delay modes should be used (nested 0-delay mode for dual loop configuration instead of cascaded 0-delay mode). 92 Submit Documentation Feedback Copyright © 2017–2018, Texas Instruments Incorporated Product Folder Links: LMK04832 LMK04832 www.ti.com SNAS688C – FEBRURAY 2017 – REVISED MAY 2018 9.2 Typical Application This design example highlights using the available tools to design loop filters and create programming map for LMK04832. CLKout10 VCXO Recovered ³GLUW\´ FORFN RU clean clock LMX2594 CLKout11 PLL+VCO CLKin0 Backup Reference Clock CLKin1 CLKout0 & CLKout2 ADC CLKout1 & CLKout3 0XOWLSOH ³FOHDQ´ clocks at different frequencies OSCout CLKout8 CLKout9 LMK04832 FPGA CLKout4 & CLKout6 CLKout5 & CLKout7 CLKout12, CLKout13 DAC DAC Serializer/ Deserializer Copyright © 2017, Texas Instruments Incorporated Figure 26. Typical Application 9.2.1 Design Requirements Clocks outputs: • 1x 245.76-MHz clock for JESD204B ADC, LVPECL. – This clock requires the best performance in this example. • 2x 2949.12-MHz clock for JESD204B DAC, CML. • 1x 122.88-MHz clock for JESD204B FPGA block, LVDS • 3x 10.24-MHz SYSREF for ADC (LVPECL), DAC (LVPECL), FPGA (LVDS). • 2x 122.88-MHz clock for FPGA, LVDS For best performance, the highest possible phase detector frequency is used at PLL2. As such, a 122.88-MHz VCXO is used. 9.2.2 Detailed Design Procedure NOTE This information is current as of the date of the release of this datasheet. Design tools receive continuous improvements to add features and improve model accuracy. Refer to the software instructions or training for latest features. 9.2.2.1 Device Selection Enter the required frequencies into the tools. In this design, the LMK04832 VCO0 and LMK04832 VCO1 both meet the design requirements. VCO0 offers a relatively improved VCO performance over VCO1. In this case, choose LMK04832_VCO0 for improved RMS jitter in the 12-kHz to 20-MHz integration range. 9.2.2.1.1 Clock Architect Under the advanced tab of Clock Architect, filtering of specific parts can be done using regular expressions in the Part Filter box. [LMK04832.*] will filter for only the LMK04832 device (without brackets). More detailed filters can be given such as the entire part name LMK04832_VCO0 to force an LMK04832 using VCO0 solution if one is available. Submit Documentation Feedback Copyright © 2017–2018, Texas Instruments Incorporated Product Folder Links: LMK04832 93 LMK04832 SNAS688C – FEBRURAY 2017 – REVISED MAY 2018 www.ti.com Typical Application (continued) 9.2.2.2 Device Configuration and Simulation The tools automatically configure the simulation to meet the input and output frequency requirements given, and make assumptions about other parameters to give some default simulations. However, the user may chose to make adjustments for more accurate simulations to their application. For example: • Entering the VCO Gain of the external VCXO or possible external VCO used device. • Adjust the charge pump current to help with loop filter component selection. Lower charge pump currents result in smaller components but may increase impacts of leakage and at the lowest values reduce PLL phase nosie performance. • Clock Architect allows loading a custom phase noise plot for reference or VCXO block. Typically, a custom phase noise plot is entered for CLKin to match the reference phase noise to device; a phase noise plot for the VCXO can additionally be provided to match the performance of VCXO used. For improved accuracy in simulation and optimum loop filter design, be sure to load these custom noise profiles for use in application. • PLLatinum Sim can also be used to design and simulate a loop filter. 9.2.2.3 Device Programming Using the clock design tools configuration the TICS Pro software is manually updated with this information to meet the required application. Frequency planning for assignment of outputs: • To minimize crosstalk perform frequency planning / CLKout assignments to keep common frequencies on outputs close together. • It is best to place common device clock output frequencies on outputs sharing the same VCC group. For example, these outputs share Vcc4_CG2. Refer to Pin Configuration and Functions to see the VCC groupings the clock outputs. In this example, the 245.76-MHz ADC output needs the best performance. CLKout2 on the LMK04832 provides the best noise floor / performance. The 245.76 MHz is placed on CLKout2 with 10.24-MHz SYSREF on CLKout3. • For best performance the input and output drive level bits may be set. Best noise floor performance is achieved with CLKout2_3_IDL = 1 and CLKout2_3_ODL = 1. • The CLKoutX_Y_ODL bit has no impact on even clock outputs in high performance bypass mode. In this example, the 983.04-MHz DAC output is placed on CLKout4 and CLKout6 with 10.24-MHz SYSREF on paired CLKout5 and CLKout7 outputs. • These outputs share Vcc4_CG2. In this example, the 122.88-MHz FPGA JESD204B output is placed on CLKout10 with 10.24-MHz SYSREF on paired CLKout11 output. Additionally, the 122.88-MHz FPGA non-JESD204B outputs are placed on CLKout8 and CLKout9. • When frequency planning, consider PLL2 as a clock output at the phase detector frequency. As such, these 122.88-MHz outputs have been placed on the outputs close to the PLL2 and Charge Pump power supplies. Once the device programming is completed as desired in the TICS Pro software, it is possible to export the register settings from the Register tab for use in application. 94 Submit Documentation Feedback Copyright © 2017–2018, Texas Instruments Incorporated Product Folder Links: LMK04832 LMK04832 www.ti.com SNAS688C – FEBRURAY 2017 – REVISED MAY 2018 Typical Application (continued) 9.2.3 Application Curves The phase noise plots collected with loop filter values of C1 = open, C2 = 150 nF, R2 = 470 Ω. Figure 27. CLKout0 = 245.76 MHz, VCO = 2457.6 MHz CLKout0_1_IDL = 1, CLKout0_1_ODL = 1 LVPECL20 With 240-Ω Emitter Resistors Figure 28. CLKout0 = 245.76 MHz, VCO = 2949.12 MHz CLKout0_1_IDL = 1, CLKout0_1_ODL = 1 LVPECL20 With 240-Ω Emitter Resistors Figure 29. CLKout2 = 491.52-MHz, VCO = 2949.12 MHz CLKout2_3_IDL = 1, CLKout2_3_ODL = 1 LVPECL16 With 120-Ω Emitter Resistors Figure 30. CLKout2 = 983.04-MHz, VCO = 2949.12 MHz CLKout2_3_IDL = 1, CLKout2_3_ODL = 1 LVPECL16 With 120-Ω Emitter Resistors Submit Documentation Feedback Copyright © 2017–2018, Texas Instruments Incorporated Product Folder Links: LMK04832 95 LMK04832 SNAS688C – FEBRURAY 2017 – REVISED MAY 2018 www.ti.com Typical Application (continued) 96 Figure 31. CLKout4 = 2457.6, VCO = 2457.6 MHz CLKout4_5_IDL = 1, CLKout4_5_ODL = 0 CML 32mA, 68 nH Inductor - 20 Ω Resistor Figure 32. CLKout4 = 2949.12, VCO = 2949.12 MHz CLKout4_5_IDL = 1, CLKout4_5_ODL = 1 LVPECL, 68 nH Inductor - 20 Ω Resistor Figure 33. CLKout3 = 122.88 MHz, VCO = 2949.12 MHz CLKout2_3_IDL = 1, CLKout2_3_ODL = 1 With 120-Ω Emitter Resistors Figure 34. CLKout9 = 122.88 MHz, VCO = 2949.12 MHz, HSDS 8 mA CLKout8_9_IDL = 1, CLKout8_9_ODL = 1 Submit Documentation Feedback Copyright © 2017–2018, Texas Instruments Incorporated Product Folder Links: LMK04832 LMK04832 www.ti.com SNAS688C – FEBRURAY 2017 – REVISED MAY 2018 Typical Application (continued) Figure 35. OSCout, 122.88 MHz, LVCMOS (Norm/Inv) Normal Output Measured, Inverse 50-Ω Termination Figure 36. Direct VCXO Measurement Open-Loop, Holdover Mode Set 9.3 Do's and Don'ts 9.3.1 Pin Connection Recommendations • VCC Pins and Decoupling: all VCC pins must always be connected. • Unused Clock Outputs: leave unused clock outputs floating and powered down. • Unused Clock Inputs: unused clock inputs can be left floating. 10 Power Supply Recommendations 10.1 Current Consumption TI recommends using the TICS Pro software to calculate the current consumption estimate based on programmed configuration. Submit Documentation Feedback Copyright © 2017–2018, Texas Instruments Incorporated Product Folder Links: LMK04832 97 LMK04832 SNAS688C – FEBRURAY 2017 – REVISED MAY 2018 www.ti.com 11 Layout 11.1 Layout Guidelines 11.1.1 Thermal Management Power consumption of the LMK04832 can be high enough to require attention from thermal management. For reliability and performance reasons the die temperature should be limited to a maximum of 125°C. That is, as an estimate, TA (ambient temperature) plus device power consumption times RθJA should not exceed 125°C. 11.2 Layout Example For any pins not connected, ensure that the exposed copper is of the same area as other pins to contribute to healthy solderdown joint For CLKout Vccs in JESD204B application, place ferrite beads then 1 µF capacitor. The 1 µF capacitor supports low frequency SYSREF switching/turning on. For CLKout Vccs in traditional applications, place ferrite bead on top layer close to pins to choke high frequency noise from via. Charge pump output ± shorter traces are better. Place all resistors and caps close to IC. CLKouts/OSCouts ± Differential signals should be routed tightly coupled to minimize PCB crosstalk. For LVPECL/LCPECL/CML place components resistors close to IC. OSCout shares pins with CLKin2 and is programmable for input or output CLKin and OSCin ± If differential input (preferred) route traces tightly coupled. If single ended, have at least 3 trace width (of CLKin/OSCin trace) separation from other RF traces. Place terminations close to IC. CLKin2 and OSCout share pins and is programmable for input or output. Figure 37. LMK04832 Layout Example, Top Layer 98 Submit Documentation Feedback Copyright © 2017–2018, Texas Instruments Incorporated Product Folder Links: LMK04832 LMK04832 www.ti.com SNAS688C – FEBRURAY 2017 – REVISED MAY 2018 Layout Example (continued) Expose copper under the PCB to provide direct copper to air interface to dissipate heat Provide areas of connect copper to allow heat to escape from directly below PCB. Do not let components block all thermal escape from ground pad. A flexible termination / PCB layout for either CML requiring a pull-up to Vcc or LVPECL/LCPECL requiring a pull-down to ground, or for any other format is the H configuration as illustrated in layout above and schematic below. R1/R2 allow connection to Vcc or ground. When using CML with inductors (in position R3 and R4), R1 allows the use of an additional series resistor. Vcc R1 R2 R3 R4 Figure 38. LMK04832 Layout Example, Bottom Layer Submit Documentation Feedback Copyright © 2017–2018, Texas Instruments Incorporated Product Folder Links: LMK04832 99 LMK04832 SNAS688C – FEBRURAY 2017 – REVISED MAY 2018 www.ti.com 12 Device and Documentation Support 12.1 Device Support 12.1.1 Development Support 12.1.1.1 Clock Architect Part selection, loop filter design, simulation. To run the online Clock Architect tool, go to www.ti.com/clockarchitect. 12.1.1.2 PLLatinum Sim Supports loop filter design and simulation. All simulation is for a single loop, to perform dual loop simulations, the result of the first PLL sim must be loaded as a reference to the second PLL sim. To download PLLatinum Sim tool, go to www.ti.com/tool/PLLATINUMSIM-SW 12.1.1.3 TICS Pro EVM programming software. Can also be used to generate register map for programming and calculate current consumption estimate. For TICS Pro, go to www.ti.com/tool/TICSPRO-SW 12.2 Community Resources The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of Use. TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help solve problems with fellow engineers. Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and contact information for technical support. 12.3 Trademarks E2E is a trademark of Texas Instruments. All other trademarks are the property of their respective owners. 12.4 Electrostatic Discharge Caution These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates. 12.5 Glossary SLYZ022 — TI Glossary. This glossary lists and explains terms, acronyms, and definitions. 13 Mechanical, Packaging, and Orderable Information The following pages include mechanical, packaging, and orderable information. This data is subject to change without notice and revision of this document. 100 Submit Documentation Feedback Copyright © 2017–2018, Texas Instruments Incorporated Product Folder Links: LMK04832 PACKAGE OPTION ADDENDUM www.ti.com 10-Dec-2020 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan (2) Lead finish/ Ball material MSL Peak Temp Op Temp (°C) Device Marking (3) (4/5) (6) LMK04832NKDR ACTIVE WQFN NKD 64 2000 RoHS & Green SN Level-3-260C-168 HR -40 to 85 K04832NKD LMK04832NKDT ACTIVE WQFN NKD 64 250 RoHS & Green SN Level-3-260C-168 HR -40 to 85 K04832NKD (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of