LMK04906 Evaluation Board
User's Guide
January 2012
Literature Number SNAU126A
Revised – December 2013
LMK04906 Family
Low-Noise Clock Jitter Cleaner with Dual Loop PLLs
Evaluation Board Instructions
2
SNAU126A
LMK04906 Family: Low-Noise Clock Jitter with Dual Loop PLLs
Copyright © 2013, Texas Instruments Incorporated
Revised - December 2013
Table of Contents
TABLE OF CONTENTS ..............................................................................................................................................................3
GENERAL DESCRIPTION ..........................................................................................................................................................5
Evaluation Board Kit Contents .................................................................................................................. 5
Available LMK04906 Evaluation Boards ................................................................................................. 5
Available LMK04906 Family Devices ...................................................................................................... 5
QUICK START ..........................................................................................................................................................................6
Default CodeLoader Modes for Evaluation Boards................................................................................... 7
EXAMPLE: USING CODELOADER TO PROGRAM THE LMK04906B ............................................................................................8
1. Start CodeLoader 4 Application ............................................................................................................ 8
2. Select Device ......................................................................................................................................... 8
3. Program/Load Device ............................................................................................................................ 9
4. Restoring a Default Mode ...................................................................................................................... 9
5. Visual Confirmation of Frequency Lock ............................................................................................. 10
6. Enable Clock Outputs .......................................................................................................................... 10
PLL LOOP FILTERS AND LOOP PARAMETERS .........................................................................................................................12
PLL 1 Loop Filter .................................................................................................................................... 12
25 MHz VCXO PLL ............................................................................................................................ 12
PLL2 Loop Filter ..................................................................................................................................... 13
EVALUATION BOARD INPUTS AND OUTPUTS........................................................................................................................14
RECOMMENDED TEST EQUIPMENT ......................................................................................................................................21
APPENDIX A: CODELOADER USAGE.......................................................................................................................................22
Port Setup Tab.......................................................................................................................................... 22
Clock Outputs Tab ................................................................................................................................... 23
PLL1 Tab ................................................................................................................................................. 26
Setting the PLL1 VCO Frequency and PLL2 Reference Frequency ................................................... 27
PLL2 Tab ................................................................................................................................................. 28
Bits/Pins Tab ............................................................................................................................................ 29
Registers Tab ........................................................................................................................................... 34
APPENDIX B: TYPICAL PHASE NOISE PERFORMANCE PLOTS..................................................................................................35
PLL1 ........................................................................................................................................................ 35
25 MHz VCXO Phase Noise ............................................................................................................... 35
Clock Output Measurement Technique ............................................................................................... 36
Clock Outputs (CLKout).......................................................................................................................... 37
Revised - December 2013
LMK04906 Family: Low-Noise Clock Jitter with Dual Loop PLLs
SNAU126A 3
Copyright © 2013, Texas Instruments Incorporated
LMK04906B CLKout Phase Noise ..................................................................................................... 37
APPENDIX C: SCHEMATICS .................................................................................................................................................... 38
Power Supplies......................................................................................................................................... 38
LMK04906B Device with Loop Filter and Crystal Circuits ................................................................... 39
Reference Inputs (CLKin0, CLKin1 & CLKin2), External VCXO (OSCin) & VCO Circuits............... 40
Clock Outputs (OSCout0, CLKout0 to CLKout5) .................................................................................. 41
uWire Header, Logic I/O Ports and Status LEDs .................................................................................... 42
APPENDIX D: BILL OF MATERIALS .........................................................................................................................................43
APPENDIX E: PCB LAYERS STACKUP .....................................................................................................................................47
APPENDIX F: PCB LAYOUT ..................................................................................................................................................... 48
Layer #1 – Top ......................................................................................................................................... 48
Layer #2 – RF Ground Plane (Inverted) .................................................................................................. 49
Layer #3 – Vcc Planes ............................................................................................................................. 50
Layer #4 – Ground Plane (Inverted) ........................................................................................................ 51
Layer # 5 – Vcc Planes 2 ......................................................................................................................... 52
Layer #6 – Bottom ................................................................................................................................... 53
Layers #1 and 6 – Top and Bottom (Composite)..................................................................................... 54
APPENDIX G: PROPERLY CONFIGURING LPT PORT ................................................................................................................55
LPT Driver Loading................................................................................................................................. 55
Correct LPT Port/Address........................................................................................................................ 55
Correct LPT Mode ................................................................................................................................... 56
Legacy Board Port Setup ......................................................................................................................... 56
APPENDIX H: TROUBLESHOOTING INFORMATION ................................................................................................................57
1)
Confirm Communications ................................................................................................................ 57
2)
Confirm PLL1 operation/locking..................................................................................................... 57
3)
Confirm PLL2 operation/locking..................................................................................................... 58
APPENDIX I: EVM SOFTWARE AND COMMUNICATION .........................................................................................................59
OPTION 1 ................................................................................................................................................ 59
OPTION 2 ................................................................................................................................................ 59
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SNAU126A
LMK04906 Family: Low-Noise Clock Jitter with Dual Loop PLLs
Copyright © 2013, Texas Instruments Incorporated
Revised - December 2013
General Description
The LMK04906 Evaluation Board simplifies evaluation of the LMK04906B Low-Noise Clock
Jitter Cleaner with Dual Loop PLLs. Texas Instrument’s CodeLoader software can be used to
program the internal registers of the LMK04906B device through the USB2ANY-uWIRE
interface. The CodeLoader software will run on a Windows 2000/XP or Windows 7 PC and can
be downloaded from http://www.ti.com/tool/codeloader.
Evaluation Board Kit Contents
The evaluation board kit includes:
• (1) LMK04906 Evaluation Board from Table 1
• (1) CodeLoader and USB2ANY-uWIRE Interface uWire header on EVM
Available LMK04906 Evaluation Boards
The LMK04906 Evaluation Board supports any of the four devices offered in the LMK04906
Family. All evaluation boards use the same PCB layout and bill-of-materials, except for the
corresponding LMK04906B device affixed to the board. A commercial-quality VCXO is also
mounted to the board to provide a known reference point for evaluating device performance and
functionality.
Table 1: Available Evaluation Board Configurations
Evaluation Board ID
Device
LMK04906BEVAL
LMK04906B
PLL1 VCXO
25 MHz Epson VCXO
Model VG-4231CA 25.0000M-FGRC3
Available LMK04906 Family Devices
Table 2: LMK04906B Devices
Device
Reference
Inputs
LMK04906B
3
Revised
- December 2013
Buffered/
Divided
OSCin
Outputs
1
Programmable
LVDS/LVPECL/
LVCMOS
Outputs
6
VCO Frequency
2370 to 2600 MHz
LMK04906 Family: Low-Noise Clock Jitter with Dual Loop PLLs
Copyright © 2013, Texas Instruments Incorporated
SNAU126A
5
Quick Start
Full evaluation board instructions are downloadable from the LMK04906B device product folder
at www.ti.com/product/LMK04906.
1. Connect a power supply voltage of 5 V to the Vcc SMA connector. The onboard LP3878ADJ LDO regulator will output a low-noise 3.3 V supply to operate the device.
2. Connect a reference clock from a signal source to the CLKin1 SMA port. Use 125 MHz
for default. The reference frequency depends on the device programming.
3. Connect the uWire header to a PC USB port using the USB2ANY-uWIRE interface.
4. Program the device with a default mode using CodeLoader. Ctrl+L must be pressed at
least once to load all registers. Alternatively click menu “Keyboard Controls” “Load
Device”. CodeLoader can be downloaded from www.ti.com/tool/codeloader.
5. Measurements may be made on an active output clock port via its SMA connector.
125 MHz
(Default)
Figure 1: Quick Start Diagram
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LMK04906 Family: Low-Noise Clock Jitter with Dual Loop PLLs
Copyright © 2013, Texas Instruments Incorporated
Revised - December 2013
Default CodeLoader Modes for Evaluation Boards
CodeLoader saves the state of the selected LMK04906B device when exiting the software. To
ensure a common starting point, the following modes listed in Table 3 may be restored by
clicking “Mode” and selecting the appropriate device configuration, as shown in Figure 2 in the
case of the LMK04906B device. Similar default modes are available for each LMK04906B
device in CodeLoader. Choose a mode with CLKin0 or CLKin2 for differential clock signal or
CLKin1 for a single ended signal.
Figure 2: Selecting a Default Mode for the LMK04906 Device
After restoring a default mode, press Ctrl+L to program the device. The default modes also
disable certain outputs, so make sure to enable the output under test to make measurements.
Table 3: Default CodeLoader Modes for LMK04906
Default CodeLoader Mode
122.88 MHz CLKin1, 122.88 MHz
VCXO
125 MHz CLKin1, 25 MHz VCXO
Device Mode
Dual PLL, Internal VCO
Dual PLL, Internal VCO
CLKin
Frequency
122.88
MHz
125 MHz
OSCin
Frequency
122.88
MHz
25 MHz
The next section outlines step-by-step procedures for using the evaluation board with the
LMK04906B. For boards with another part number, make sure to select the corresponding part
number under the “Device” menu.
Revised
- December 2013
LMK04906 Family: Low-Noise Clock Jitter with Dual Loop PLLs
Copyright © 2013, Texas Instruments Incorporated
SNAU126A
7
Example: Using CodeLoader to Program the LMK04906B
The purpose of this section is to walk the user through using CodeLoader 4 to make some
measurements with the LMK04906B device as an example. For more information on
CodeLoader refer to Appendix A: CodeLoader Usage or the CodeLoader 4 instructions located
at http://www.ti.com/tool/codeloader.
Before proceeding, be sure to follow the Quick Start section above to ensure proper
connections.
1. Start CodeLoader 4 Application
Click “Start” “Programs” “CodeLoader 4” “CodeLoader 4”
The CodeLoader 4 program is installed by default to the CodeLoader 4 application group.
2. Select Device
Click “Select Device” “Clock Conditioners”
“LMK04906B”
Once started CodeLoader 4 will load the last
used device. To load a new device, click
“Select Device” from the menu bar. Then,
select the subgroup and finally device to
load. In this example, the LMK04906B is
chosen. Selecting the device does cause
the device to be programmed.
Figure 3 – Selecting the LMK04906B device
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SNAU126A
LMK04906 Family: Low-Noise Clock Jitter with Dual Loop PLLs
Copyright © 2013, Texas Instruments Incorporated
Revised - December 2013
3. Program/Load Device
Assuming the Port Setup settings are
correct, press the “Ctrl+L” shortcut or click
“Keyboard Controls” “Load Device” from
the menu to program the device to the
current state of the newly loaded
LMK04906 file.
Once the device has been initially loaded,
Figure 4 – Loading the Device
CodeLoader will automatically program
changed registers so it is not necessary to re-load the device upon subsequent changes in the
device configuration. It is possible to disable this functionality by ensuring there is no
checkmark by the “Options” “AutoReload with Changes.”
Because a default mode will be restored in the next step, this step is not really needed but is
included to emphasize the importance of pressing “Ctrl+L” to load the device at least once after
starting CodeLoader, restoring a mode, or restoring a saved setup using the File menu.
See Appendix A: CodeLoader Usage or the CodeLoader 4 instructions located at
http://www.ti.com/tool/codeloader for more information on Port Setup. Appendix H:
Troubleshooting Information contains information on troubleshooting communications.
4. Restoring a Default Mode
Click “Mode” “125 MHz CLKin1, 25 MHz VCXO”; then press Ctrl+L.
Figure 5: Setting the Default mode for LMK04906
For the purpose of this walkthrough, a default mode will be loaded to ensure a common starting
point. This is important because when CodeLoader is closed, it remembers the last settings
used for a particular device. Again, remember to press Ctrl+L as the first step after loading a
default mode.
Revised
- December 2013
LMK04906 Family: Low-Noise Clock Jitter with Dual Loop PLLs
Copyright © 2013, Texas Instruments Incorporated
SNAU126A
9
5. Visual Confirmation of Frequency Lock
After a default mode is restored and loaded, LED D5 should illuminate when PLL1 and PLL2 are
locked to the reference clock applied to CLKin1. This assumes LD_MUX = PLL1/2 DLD and
LD_TYPE = Active High, which are the default settings.
6. Enable Clock Outputs
While the LMK04906B offers programmable clock output buffer formats, the evaluation board is shipped
with preconfigured output terminations to match the default buffer type for each output. Refer to the
CLKout port description in the Evaluation Board Inputs and Outputs section.
To measure phase noise at one of the clock outputs, for example, CLKout0:
1. Click on the Clock Outputs tab,
2. Uncheck “Powerdown” in the Digital Delay box to enable the channel,
3. Set the following settings as needed:
a. Digital Delay value
b. Clock Divider value
c. Analog Delay select and Analog Delay value (if not “Bypassed”)
d. Clock Output type.
Figure 6: Setting Digital Delay, Clock Divider, Analog Delay, and Output Format for CLKout0
4. Depending on the configured output type, the clock output SMAs can be interfaced to a test
instrument with a single-ended 50-ohm input as follows.
a. For LVDS:
i. A balun (like ADT2-1T) is recommended for differential-to-single-ended
conversion.
b. For LVPECL:
i. A balun can be used, or
ii. One side of the LVPECL signal can be terminated with a 50-ohm load and the
other side can be run single-ended to the instrument.
c. For LVCMOS:
i. There are two single-ended outputs, CLKoutX
and CLKoutX*, and each output can be set to
Normal, Inverted, or Off. There are nine (9)
combinations of LVCMOS modes in the Clock
Output list.
ii. One side of the LVCMOS signal can be
terminated with a 50-ohm load and the other
side can be run single-ended to the
instrument.
iii. A balun may also be used. Ensure CLKoutX
and CLKoutX* states are complementary to
each other. That is, Norm/Inv or Inv/Norm.
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Figure 7: Setting LVCMOS modes
LMK04906 Family: Low-Noise Clock Jitter with Dual Loop PLLs
Copyright © 2013, Texas Instruments Incorporated
Revised - December 2013
5. The phase noise may be measured with a spectrum analyzer or signal source analyzer.
See Appendix B: Typical Phase Noise Performance Plots for phase noise plots of the clock
outputs.
National’s Clock Design Tool can be used to calculate divider values to achieve desired clock
output frequencies. See: http://www.ti.com/tool/clockdesigntool.
Revised
- December 2013
LMK04906 Family: Low-Noise Clock Jitter with Dual Loop PLLs
Copyright © 2013, Texas Instruments Incorporated
SNAU126A
11
PLL Loop Filters and Loop Parameters
In jitter cleaning applications that use a cascaded or dual PLL architecture, the first PLL’s
purpose is to substitute the phase noise of a low-noise oscillator (VCXO or crystal resonator) for
the phase noise of a “dirty” reference clock. The first PLL is typically configured with a narrow
loop bandwidth in order to minimize the impact of the reference clock phase noise. The
reference clock consequently serves only as a frequency reference rather than a phase
reference.
The loop filters on the LMK04906 evaluation board are setup using the approach above. The
loop filter for PLL1 has been configured for a narrow loop bandwidth (< 100 Hz), while the loop
filter of PLL2 has been configured for a wide loop bandwidth (> 100 kHz). The specific loop
bandwidth values depend on the phase noise performance of the oscillator mounted on the
board. The following tables contain the parameters for PLL1 and PLL2 for each oscillator option.
National’s Clock Design Tool can be used to optimize PLL phase noise/jitter for given
specifications. See: http://www.ti.com/tool/clockdesigntool.
PLL 1 Loop Filter
Table 4: PLL1 Loop Filter Parameters for Epson 25 MHz VCXO
25 MHz VCXO PLL
Phase Margin
49˚
Kφ (Charge Pump)
400 uA
Loop Bandwidth
21 Hz
Phase Detector Freq
2083.33 MHz
VCO Gain
4.5 kHz/Volt
Reference Clock
Frequency
125 MHz
Output Frequency
25 MHz (To PLL 2)
Loop Filter
Components
C1_VCXO = 3300
nF
C2_VCXO = 10000 nF
C2A_VCXO = 10000 nF
R2_VCXO = 1 kΩ
Note: PLL Loop Bandwidth is a function of Kφ, Kvco, N as well as loop components. Changing
Kφ and N will change the loop bandwidth.
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LMK04906 Family: Low-Noise Clock Jitter with Dual Loop PLLs
Copyright © 2013, Texas Instruments Incorporated
Revised - December 2013
PLL2 Loop Filter
Table 5: PLL2 Loop Filter Parameters for LMK04906B
C1_VCO
C2_VCO
C3 (internal)
C4 (internal)
R2_VCO
R3 (internal)
R4 (internal)
Charge Pump
Current, Kφ
Phase
Detector
Frequency
Frequency
Kvco
N
LMK04906B
0.082
5.6
0.01
0.01
0.68
0.2
0.2
nF
nF
nF
nF
kΩ
kΩ
kΩ
3.2
mA
50
MHz
2500
18.5
50
MHz
MHz/V
Phase Margin
69
degree
s
Loop
Bandwidth
132
kHz
Note: PLL Loop Bandwidth is a function of Kφ, Kvco, N as well as loop components. Changing
Kφ and N will change the loop bandwidth.
Revised
- December 2013
LMK04906 Family: Low-Noise Clock Jitter with Dual Loop PLLs
Copyright © 2013, Texas Instruments Incorporated
SNAU126A
13
Evaluation Board Inputs and Outputs
The following table contains descriptions of the inputs and outputs for the evaluation board.
Unless otherwise noted, the connectors described can be assumed to be populated by default.
Additionally, some applicable CodeLoader programming controls are noted for convenience.
Refer to the LMK04906 Family Datasheet for complete register programming information.
Table 6: Evaluation Board Inputs and Outputs
Signal Type,
Connector Name
Description
Input/Output
Clock outputs with programmable output buffers.
The output terminations by default on the evaluation board
are shown below, and the output type selected by default in
CodeLoader is indicated by an asterisk (*):
Populated:
CLKout0, CLKout0*,
CLKout1, CLKout1*,
CLKout2, CLKout2*,
CLKout3, CLKout3*,
CLKout4, CLKout4*,
CLKout5, CLKout5*
Clock output pair
CLKout0
CLKout1
CLKout2
CLKout3
CLKout4
CLKout5
Analog, Output
Default Board Termination
LVPECL*
LVPECL
LVDS* / LVCMOS
LVDS / LVCMOS
LVDS* / LVCMOS
LVPECL
Each CLKout pair has a programmable LVDS, LVPECL, or
LVCMOS buffer. The output buffer type can be selected in
CodeLoader in the Clock Outputs tab via the
CLKoutX_TYPE control.
All clock outputs are AC-coupled to allow safe testing with
RF test equipment.
All LVPECL clock outputs are source-terminated using 240ohm resistors.
If an output pair is programmed to LVCMOS, each output
can be independently configured (normal, inverted, or off/tristate).
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LMK04906 Family: Low-Noise Clock Jitter with Dual Loop PLLs
Copyright © 2013, Texas Instruments Incorporated
Revised - December 2013
Connector Name
Signal Type,
Input/Output
Description
Buffered outputs of OSCin port.
The output terminations on the evaluation board are shown
below, the output type selected by default in CodeLoader is
indicated by an asterisk (*):
OSC output pair
Default Board Termination
OSCout0
LVDS* / LVCMOS
Populated:
OSCout0, OSCout0*,
Analog,
Output
OSCout0 has a programmable LVDS, LVPECL, or LVCMOS
output buffer. The OSCout0 buffer type can be selected in
CodeLoader on the Clock Outputs tab via the
OSCout0_TYPE control.
OSCout0 is AC-coupled to allow safe testing with RF test
equipment.
If OSCout0 is programmed as LVCMOS, each output can be
independently configured (normal, inverted, inverted, and
off/tri-state).
Main power supply input for the evaluation board.
A 3.9 V DC power source applied to this SMA will, by
default, source the onboard LDO regulators that power the
inner layer planes that supply the LMK04906B and its
auxiliary circuits (e.g. VCXO).
Vcc
Power,
Input
Populated:
J1
Power,
Input
Unpopulated:
VccVCO/Aux
Power,
Input
Revised
- December 2013
The LMK04906B contains internal voltage regulators for the
VCO, PLL and other internal blocks. The clock outputs do
not have an internal regulator, so a clean power supply with
sufficient output current capability is required for optimal
performance.
On-board LDO regulators and 0
r
flexibility to supply and route power to various devices. See
schematics for more details.
Alternative power supply input for the evaluation board using
two unshielded wires (Vcc and GND).
Apply power to either Vcc SMA or J1, but not both.
Optional Vcc input to power the VCO circuit if separated
voltage rails are needed. The VccVCO/Aux input can power
these circuits directly or supply the on-board LDO
regulators. 0 Ω resistor options provide flexibility to route
power.
LMK04906 Family: Low-Noise Clock Jitter with Dual Loop PLLs
Copyright © 2013, Texas Instruments Incorporated
SNAU126A
15
Connector Name
Signal Type,
Input/Output
Description
Reference Clock Inputs for PLL1 (CLKin0, 1, 2).
CLKin1 can alternatively be used as an External
Feedback Clock Input (FBCLKin) in 0-delay mode
or an RF Input (Fin) in External VCO mode.
Reference Clock Inputs for PLL1 (CLKin0, 1)
FBCLKin/CLKin1* is configured by default for a
single-ended reference clock input from a 50-ohm
source. The non-driven input pin
(FBCLKin/CLKin1) is connected to GND with a 0.1
uF. CLKin0/CLKin0* is configured by default for a
differential reference clock input from a 50-ohm
source.
Populated:
CLKin0, CLKin0*,
FBCLKin*/CLKin1*
CLKin2, CLKin2*
Not Populated:
FBCLKin/CLKin1
CLKin1* is the default reference clock input
selected in CodeLoader. The clock input selection
mode can be programmed on the Bits/Pins tab
via the CLKin_Select_MODE control. Refer to the
LMK04906 Family Datasheet section “Input Clock
Switching” for more information.
Analog,
Input
AC coupled Input Clock Swing Levels
Input
Mode
Min Max
Differential Bipolar or 0.5
3.1
CMOS
Single
0.25 2.4
Ended
Units
Vpp
Vpp
External Feedback Input (FBCLKin) for 0-Delay
CLKin1 is shared for use with FBCLKin as an
external feedback clock input to PLL1 for 0-delay
mode. See section, Error! Reference source
not found. Error! Reference source not found.,
for more details on using 0-delay mode with the
evaluation board and the evaluation board
software.
RF Input (Fin) for External VCO
CLKin1 is also shared for use with Fin as an RF
input for external VCO mode using the onboard
VCO footprint (U3) or add-on VCO board. To
enable Dual PLL mode with External VCO, the
following registers must be properly configured in
CodeLoader:
• MODE = (3) Dual PLL, Ext VCO (Fin), (5)
Dual PLL, Ext VCO, 0-Delay, (11) PLL2,
Ext VCO (Fin)
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LMK04906 Family: Low-Noise Clock Jitter with Dual Loop PLLs
Copyright © 2013, Texas Instruments Incorporated
Revised - December 2013
Connector Name
Signal Type,
Input/Output
Description
Feedback VCXO clock input to PLL1 and
Reference clock input to PLL2.
By default, these SMAs are not connected to the
traces going to the OSCin/OSCin* pins of the
LMK04906B. Instead, the single-ended output of
the onboard VCXO (U2) drives the OSCin* input
of the device and the OSCin input of the device is
connected to GND with 0.1 uF.
Not populated:
OSCin, OSCin*
Analog,
Input
A VCXO add-on board may be optionally attached
via these SMA connectors with minor modification
to the components going to the OSCin/OSCin*
pins of device. This is useful if the VCXO footprint
does not accommodate the desired VCXO device.
A single-ended or differential signal may be used
to drive the OSCin/OSCin* pins and must be AC
coupled. If operated in single-ended mode, the
unused input must be connected to GND with 0.1
uF.
Test point:
VTUNE1_TP
Test point:
VTUNE2_TP
Analog,
Output
Analog,
Output
Revised
- December 2013
Tuning voltage output from the loop filter for PLL2.
10-pin header for uWire programming interface
and programmable logic I/O pins for the
LMK04906B.
Populated:
uWire
Test points:
DATAuWire_TP
CLKuWIRE_TP
LEuWIRE_TP
Refer to the LMK04906 Family Datasheet section
“Electrical Characteristics” for PLL2 Reference
Input (OSCin) specifications.
Tuning voltage output from the loop filter for PLL1.
CMOS,
Input/Output
The uWire interface includes CLKuWire,
DATAuWire, and LEuWire signals.
The programmable logic I/O signals accessible
through this header include: SYNC,
Status_Holdover, Status_LD, Status_CLKin0, and
Status_CLKin1. These logic I/O signals also have
dedicated SMAs and test points.
LMK04906 Family: Low-Noise Clock Jitter with Dual Loop PLLs
Copyright © 2013, Texas Instruments Incorporated
SNAU126A
17
Connector Name
Signal Type,
Input/Output
Description
Programmable status output pin. By default, set
to output the digital lock detect status signal for
PLL1 and PLL2 combined.
In the default CodeLoader modes, LED D5 will
illuminate green when PLL lock is detected by the
LMK04906B (output is high) and turn off when
lock is lost (output is low).
Test point:
LD_TP
Not populated:
Status_LD
CMOS,
Output
The status output signal for the Status_LD pin can
be selected on the Bits/Pins tab via the LD_MUX
control.
Refer to the LMK04906 Family Datasheet section
“Status Pins” and “Digital Lock Detect” for more
information.
Note: Before a high-frequency internal signal (e.g.
PLL divider output signal) is selected by LD_MUX,
it is suggested to first remove the 270 ohm
resistor to prevent the LED from loading the
output.
Programmable status output pin. By default, set
to the output holdover mode status signal.
In the default CodeLoader mode, LED D8 will
illuminate red when holdover mode is active
(output is high) and turn off when holdover mode
is not active (output is low).
Test point:
Holdover_TP
CMOS,
Output
Refer to the LMK04906 Family Datasheet section
“Status Pins” and “Holdover Mode” for more
information.
Note: Before a high-frequency internal signal (e.g.
PLL divider output signal) is selected by
HOLDOVER_MUX, it is suggested to first remove
the 270 ohm resistor to prevent the LED from
loading the output.
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LMK04906 Family: Low-Noise Clock Jitter with Dual Loop PLLs
Copyright © 2013, Texas Instruments Incorporated
Revised - December 2013
Connector Name
Signal Type,
Input/Output
Description
Programmable status I/O pins. By default, set as input
pins for controlling input clock switching of CLKin0 and
CLKin1.
These inputs will not be functional because
CLKin_Select_MODE is set to 0 (CLKin0 Manual) by
default in the Bits/Pins tab in CodeLoader. To enable
input clock switching, CLKin_Select_MODE must be 3
or 6 and Status_CLKinX_TYPE must be 0 to 3 (pin
enabled as an input).
Test point:
CLKin0_SEL_TP
CLKin1_SEL_TP
Input Clock Switching – Pin Select Mode
When CLKin_SELECT_MODE is 3, the
Status_CLKinX pins select which clock input is active
as follows:
Status_CLKin1 Status_CLKin0 Active Clock
0
0
CLKin0
0
1
CLKin1
1
0
CLKin2
1
1
Holdover
CMOS,
Input/Output
Input Clock Switching – Auto with Pin Select
When CLKin_SELECT_MODE is 6, the active clock is
selected using the Status_CLKinX pins upon an input
clock switch event as follows:
Active
Status_CLKin1 Status_CLKin0
Clock
X
0
CLKin0
1
0
CLKin1
0
0
Reserved
Refer to the LMK04906 Family Datasheet section
“Input Clock Switching” for more information.
Status Outputs
When Status_CLKinX_TYPE is 3 to 6 (pin enabled as
an output), the status output signal for the
corresponding Status_CLKinX pin can be programmed
on the Bits/Pins tab via the Status_CLKinX_MUX
control.
Refer to the LMK04906 Family Datasheet section
“Status Pins” for more information.
Revised
- December 2013
LMK04906 Family: Low-Noise Clock Jitter with Dual Loop PLLs
Copyright © 2013, Texas Instruments Incorporated
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Connector Name
Signal Type,
Input/Output
Description
Programmable status I/O pin. By default, set as
an input pin for synchronize the clock outputs with
a fixed and known phase relationship between
each clock output selected for SYNC. A SYNC
event also causes the digital delay values to take
effect.
Test point:
SYNC_TP
CMOS,
Input/Output
In the default CodeLoader mode, SYNC will
asserted when the SYNC pin is low and the
outputs to be synchronized will be held in a logic
low state. When SYNC is unasserted, the clock
outputs to be synchronized are activated and will
be initially phase aligned with each other except
for outputs programmed with different digital delay
values.
A SYNC event can also be programmed by
toggling the SYNC_POL_INV bit in the Bits/Pins
tab in CodeLoader.
Refer to the LMK04906 Family Datasheet section
“Clock Output Synchronization” for more
information.
Status Output
When SYNC_MUX is 3 to 6 (pin enabled as
output), a status signal for the SYNC pin can be
selected on the Bits/Pins tab via the SYNC_MUX
control.
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LMK04906 Family: Low-Noise Clock Jitter with Dual Loop PLLs
Copyright © 2013, Texas Instruments Incorporated
Revised - December 2013
Recommended Test Equipment
Power Supply
The Power Supply should be a low noise power supply, particularly when the devices on the
board are being directly powered (onboard LDO regulators bypassed).
Phase Noise / Spectrum Analyzer
To measure phase noise and RMS jitter, an Agilent E5052 Signal Source Analyzer is
recommended. An Agilent E4445A PSA Spectrum Analyzer with the Phase Noise option is also
usable although the architecture of the E5052 is superior for phase noise measurements. At
frequencies less than 100 MHz the local oscillator noise of the E4445A is too high and
measurements will reflect the E4445A’s internal local oscillator performance, not the device
under test.
Oscilloscope
To measure the output clocks for AC performance, such as rise time or fall time, propagation
delay, or skew, it is suggested to use a real-time oscilloscope with at least 1 GHz analog input
bandwidth (2.5+ GHz recommended) with 50 ohm inputs and 10+ Gsps sample rate. To
evaluate clock synchronization or phase alignment between multiple clock outputs, it’s
recommended to use phase-matched, 50-ohm cables to minimize external sources of skew or
other errors/distortion that may be introduced if using oscilloscope probes.
Revised
- December 2013
LMK04906 Family: Low-Noise Clock Jitter with Dual Loop PLLs
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Appendix A: CodeLoader Usage
Code Loader is used to program the evaluation board via USB using the USB2ANYuWIRE interface. .
Port Setup Tab
Figure 8: Port Setup tab
On the Port Setup tab, the user may select the type of communication port (LPT or
USB) that will be used to program the device on the evaluation board. If parallel port is
selected, the user should ensure that the correct port address is entered.
The Pin Configuration field is hardware dependent and needs to be configured for use
with the USB2ANY-uWIRE interface. Figure 8 shows the settings required for this
configuration. Legacy board or use with a LPT cable can be configured with the use of
Appendix G: Properly Configuring LPT Port.
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LMK04906 Family: Low-Noise Clock Jitter with Dual Loop PLLs
Copyright © 2013, Texas Instruments Incorporated
Revised - December 2013
Clock Outputs Tab
Figure 9: Clock Outputs Tab
The Clock Outputs tab allows the user to control the output channel blocks, including:
• Clock Group Source from either VCO or OSCin (via OSC Mux1 and OSC Mux2)
• Channel Powerdown (affects digital and analog delay, clock divider, and buffer
blocks)
• Digital Delay value and Half Step
• Clock Divide value
• Analog Delay value and Delay bypass/enable (per output)
• Clock Output format (per output)
Revised
- December 2013
LMK04906 Family: Low-Noise Clock Jitter with Dual Loop PLLs
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23
This tab also allows the user to select the VCO Divider value (2 to 8). Note that the total
PLL2 N divider value is the product of the VCO Divider value and the PLL N Prescaler
and N Counter values (shown in the PLL2 tab), and is given by:
PLL2 N Total = VCO Divider * PLL2 N Prescaler * PLL2 N Counter
Clicking on the cyan-colored PLL2 block that contains R, PDF and N values will bring
the PLL2 tab into focus where these values may be modified, if needed.
Clicking on the values in the box containing the Internal Loop Filter component (R3, C3,
R4, C4) allow one to step through the possible values. Left click to increase the
component value, and right click to decrease the value. These values can also be
changed in the Bits/Pins tab.
The Reference Oscillator value field may be changed in either the Clock Outputs tab or
the PLL2 tab. The PLL2 Reference frequency should match the frequency of the
onboard VCXO or Crystal (i.e., VCO frequency in the PLL1 tab); if not, a warning
message will appear to indicate that the PLL(s) may be out of lock, as highlighted by the
red box in Figure 10.
24
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LMK04906 Family: Low-Noise Clock Jitter with Dual Loop PLLs
Copyright © 2013, Texas Instruments Incorporated
Revised - December 2013
Figure 10: Warning message indicating mismatch between
Revised
- December 2013
LMK04906 Family: Low-Noise Clock Jitter with Dual Loop PLLs
Copyright © 2013, Texas Instruments Incorporated
SNAU126A
25
PLL1 VCO frequency (25 MHz) and PLL2 reference frequency (25 MHz)
PLL1 Tab
Figure 11: PLL1 tab
The PLL1 tab allows the user to change the following parameters in Table 7.
Table 7: Registers Controls and Descriptions in PLL1 tab
Control Name
Reference Oscillator
Frequency (MHz)
Phase Detector
Frequency (MHz)
26
SNAU126A
Register Name
n/a
n/a
Description
CLKin frequency of the selected
reference clock.
PLL1 Phase Detector Frequency (PDF).
This value is calculated as:
PLL1 PDF = CLKin Frequency / (PLL1_R
* CLKinX_PreR_DIV), where
CLKinX_PreR_DIV is the predivider
value of the selected input clock.
LMK04906 Family: Low-Noise Clock Jitter with Dual Loop PLLs
Copyright © 2013, Texas Instruments Incorporated
Revised - December 2013
VCO Frequency (MHz)
n/a
R Counter
N Counter
Phase Detector Polarity
PLL1_R
PLL1_N
PLL1_CP_POL
Charge Pump Gain
PLL1_CP_GAIN
Charge Pump State
PLL1_CP_TRI
The VCO Frequency should be the
OSCin frequency, except when operating
in Dual PLL with 0-delay feedback. This
value is calculated as:
VCO Freq (OSCin freq) = PLL1 PDF *
PLL1_N.
In Dual PLL mode with 0-delay feedback,
the VCO frequency should be set to the
feedback clock input frequency. See the
section Setting the PLL1 VCO
Frequency and PLL2 Reference
Frequency for details.
PLL1 R Counter value (1 to 16383).
PLL1 N Counter value (1 to 16383).
PLL1 Phase Detector Polarity.
Click on the polarity sign to toggle
polarity “+” or “–”.
PLL1 Charge Pump Gain.
Left-click/right-click to increase/decrease
charge pump gain (100, 200, 400, 1600
uA).
PLL1 Charge Pump State.
Click to toggle between Active and TriState.
Setting the PLL1 VCO Frequency and PLL2 Reference Frequency
When operating in Dual PLL mode without 0-delay feedback, the VCO frequency value
on the PLL1 tab must match the Reference Oscillator (OSCin) frequency value on the
PLL2 tab; otherwise, the one or both PLLs may be out of lock. Updating the Reference
Oscillator frequency on the PLL2 tab will automatically update the value of
OSCin_FREQ on the Bits/Pins tab.
Revised
- December 2013
LMK04906 Family: Low-Noise Clock Jitter with Dual Loop PLLs
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27
PLL2 Tab
Figure 12: PLL2 tab
The PLL2 tab allows the user to change the following parameters in Table 8.
Table 8: Registers Controls and Descriptions in PLL2 tab
Control Name
Reference Oscillator
Frequency (MHz)
Phase Detector
Frequency (MHz)
Register Name
OSCin_FREQ
VCO Frequency (MHz)
Doubler
R Counter
N Counter
PLLN Prescaler
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Description
OSCin frequency from the External
VCXO or Crystal.
n/s
PLL2 Phase Detector Frequency (PDF).
This value is calculated as:
PLL2 PDF = OSCin Frequency
*(2EN_PLL2_REF_2X) / PLL2_R.
n/a
Internal VCO Frequency should be
within the allowable range of the
LMK04906B device.
This value is calculated as:
VCO Frequency = PLL2 PDF * (PLL2_N
* PLL2_P * VCO divider value).
EN_PLL2_REF_2X PLL2 Doubler.
0 = Bypass Doubler
1 = Enable Doubler
PLL2_R
PLL2 R Counter value (1 to 4095).
PLL2_N
PLL2 N Counter value (1 to 262143).
PLL2_P
PLL2 N Prescaler value (2 to 8).
LMK04906 Family: Low-Noise Clock Jitter with Dual Loop PLLs
Copyright © 2013, Texas Instruments Incorporated
Revised - December 2013
Phase Detector Polarity
PLL2_CP_POL
Charge Pump Gain
PLL2_CP_GAIN
Charge Pump State
PLL2_CP_TRI
PLL2 Phase Detector Polarity.
Click on the polarity sign to toggle
polarity “+” or “–”.
PLL2 Charge Pump Gain.
Left-click/right-click to increase/decrease
charge pump gain (100, 400, 1600, 3200
uA).
PLL2 Charge Pump State.
Click to toggle between Active and TriState.
Changes made on this tab will be reflected in the Clock Outputs tab. The VCO
Frequency should conform to the specified internal VCO frequency range for the
LMK04906B device (per Table 2).
Bits/Pins Tab
Figure 13: Bits/Pins tab
The Bits/Pins tab allows the user to program bits directly, many of which are not
available on other tabs. Brief descriptions for the controls on this tab are provided in
Table 9 to supplement the datasheet. Refer to the LMK04906 Family Datasheet for
more information.
Revised
- December 2013
LMK04906 Family: Low-Noise Clock Jitter with Dual Loop PLLs
Copyright © 2013, Texas Instruments Incorporated
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TIP: Right-clicking any register name in the Bits/Pins tab will display a Help prompt
with the register address, data bit location/length, and a brief register description.
Table 9: Register Controls and Descriptions on Bits/Pins tab
Group
Register Name
RESET
POWERDOWN
MODE
Mode Control
PD_OSCin
FEEDBACK_MUX
OSCin_FREQ
VCO_MUX
uWire_LOCK
CLKin_Select_MODE
EN_CLKin1
CLKin
EN_CLKin0
CLKinX_BUF_TYPE
EN_LOS
IO Control
Crystal
30
SNAU126A
Description
Resets the device to default register values.
RESET must be cleared for normal operation to
prevent an unintended reset every time R0 is
programmed.
Places the device in powerdown mode.
Selects the operating mode (topology) for the
LMK04906 device.
Powers down the OSCin buffer. For use in Clock
Distribution mode if OSCin path is not used.
Selects the feedback source for 0-delay mode.
Must be set to the OSCin frequency range for
PLL2. Used for proper operation of the internal
VCO calibration routine.
Entering a reference oscillator frequency on PLL2
tab will automatically update OSCin_FREQ to the
proper frequency range.
Selects between VCO and VCO divider to drive the
clock distribution path. The VCO divider is only
valid if MODE is selecting the Internal VCO.
When checked, no other uWire programming will
have effect. Must be unchecked to enable uWire
programming of registers R0 to R30.
Selects operational mode for how the device
selects the reference clock for PLL1.
Enables CLKin1 as a usable reference input during
auto switching mode.
Enables CLKin0 as a usable reference input during
auto switching mode.
Selects the CLKinX input buffer to Bipolar (internal
0 mV offset) or MOS (internal 55 mV offset).
Enable the Loss-Of-Signal (LOS) detect circuitry.
LOS_TIMEOUT
Sets the timeout value for the LOS detect circuitry
to assert a loss of signal state on a clock input.
EN_PLL2_XTAL
XTAL_LVL
Enables Crystal Oscillator
Sets peak amplitude on the tunable crystal.
Values listed are for a 20.48 MHz crystal.
Sets the selected signal on the Status_LD pin.
Sets I/O pin type on the Status_LD pin.
Sets the selected signal on the
Status_HOLDOVER pin.
Sets I/O pin type on the Status_Holdover pin.
LD_MUX
LD_TYPE
HOLDOVER_MUX
HOLDOVER_TYPE
LMK04906 Family: Low-Noise Clock Jitter with Dual Loop PLLs
Copyright © 2013, Texas Instruments Incorporated
Revised - December 2013
DAC/Holdover
IO Control – Sync
Status_CLKin0 _MUX
Revised
Sets the selected signal on the Status_CLKin0
pin.
Status_CLKin0_TYPE
Sets I/O pin type on the Status_CLKin0 pin.
Status_CLKin1_MUX
Sets the selected signal on the Status_CLKin1
pin.
Status_CLKin1_TYPE
Sets I/O pin type on the Status_CLKin1 pin.
CLKin_Sel_INV
Inverts the Status_CLKin0/1 pin polarity when
set to an input type. Significant when
CLKin_SELECT_MODE is 3 or 6.
SYNC_MUX
Sets the selected signal on the SYNC pin.
SYNC_TYPE
Sets I/O pin type on the SYNC pin.
SYNC_POL_INV
Sets polarity on SYNC input to active low
when checked. Toggling this bit will initiate a
SYNC event.
SYNC_PLL1_DLD
Engage SYNC mode until PLL1 DLD is true
SYNC_PLL2_DLD
Engage SYNC mode until PLL2 DLD is true
NO_SYNC_CLKoutX_Y Synchronization will not affect selected clock
outputs, where X = even-numbered output and
Y = odd-numbered output.
SYNC_QUAL
Sets the SYNC to qualify mode for dynamic
digital delay.
EN_SYNC
Must be set when using SYNC, but may be
cleared after the SYNC event. When using
dynamic digital delay (SYNC_QUAL = 1),
EN_SYNC must always be set.
Changing this value from 0 to 1 can cause a
SYNC event, so clocks which should not be
SYNCed when setting this bit should have the
NO_SYNC_CLKoutX_Y bit set.
NOTE: This bit is not a valid method of
generating a SYNC event. Use one of the
other SYNC generation methods to ensure a
proper SYNC occurs.
SYNC_EN_AUTO
Enable auto SYNC when R0 to R5 is written.
HOLDOVER_MODE
Sets holdover mode to be disabled or enabled.
FORCE_HOLDOVER
Engages holdover when checked regardless of
HOLDOVER_MODE value. Turns the DAC
on.
EN_TRACK
Enables DAC tracking. DAC tracks the PLL1
Vtune to provide for an accurate HOLDOVER
mode. DAC_CLK_DIV should also be set so
that DAC update rate is
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