LMK1C1106, LMK1C1108
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LMK1C110x 1.8V、2.5V 和 3.3V LVCMOS 时钟缓冲器系列
1 特性
3 说明
• 高性能 1:6 和 1:8 LVCMOS 时钟缓冲器
• 输出偏斜极低，< 55ps
• 附加抖动极低，标称值 < 25fs
– VDD = 3.3 V 时，典型值为 12fs
– VDD = 2.5 V 时，典型值为 15fs
– VDD = 1.8V 时，典型值为 28fs
• 传播延迟极低，< 3ns
• 同步输出使能
• 电源电压：3.3V、2.5V 或 1.8V
– 在电源电压范围内输入端耐受 3.3V 电压
– 失效防护输入
• 9000V HBM 的工业高 ESD 等级
• fmax = 250MHz (3.3V)
fmax = 200MHz（2.5V 和 1.8V）
• 工作温度范围：–40°C 至 125°C
• 采用 14 引脚和 16 引脚 TSSOP 封装
LMK1C110x 是德州仪器 (TI) 的一款模块化、高性能、
低偏斜、通用时钟缓冲器系列器件。整个系列采用模块
化方法设计。提供五个不同的扇出选项：1:2、1:3、
1:4、1:6 和 1:8。
2 应用
•
•
•
•
•
•
工厂自动化与控制
电信设备
数据中心和企业计算
电网基础设施
电机驱动器
医疗成像
该系列所有器件均互相引脚兼容，并与 CDCLVC110x
系列向后兼容，从而易于处理。
该系列所有器件均具有相同的高性能特性，如低附加抖
动、低偏斜和宽工作温度范围。
LMK1C110x 具有同步输出使能控制端 (1G)，可在 1G
处于低电平时将输出切换为低电平状态。这些器件具有
失效防护输入，可防止在没有输入信号的情况下输出发
生振荡并允许在提供 VDD 之前提供输入信号。
LMK1C110x 系列可在 1.8V、2.5V 和 3.3V 电压下工
作，额定工作温度范围为 –40°C 至 125°C。
器件信息
器件型号
封装
封装尺寸（标称值）
LMK1C1106
TSSOP (14)
5.00mm x 4.40mm
LMK1C1108
TSSOP (16)
5.00mm x 4.40mm
CLKIN
LVCMOS
LVCMOS
Y0
LVCMOS
Y1
LVCMOS
Y2
LVCMOS
Y3
LVCMOS
Y4
LVCMOS
Y5
LVCMOS
Y6
LVCMOS
Y7
1G
功能方框图
本文档旨在为方便起见，提供有关 TI 产品中文版本的信息，以确认产品的概要。有关适用的官方英文版本的最新信息，请访问
www.ti.com，其内容始终优先。TI 不保证翻译的准确性和有效性。在实际设计之前，请务必参考最新版本的英文版本。
English Data Sheet: SNAS814
LMK1C1106, LMK1C1108
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ZHCSLS7A – DECEMBER 2020 – REVISED JANUARY 2022
Table of Contents
1 特性................................................................................... 1
2 应用................................................................................... 1
3 说明................................................................................... 1
4 Revision History.............................................................. 2
5 Pin Configuration and Functions...................................3
6 Specifications.................................................................. 4
6.1 Absolute Maximum Ratings........................................ 4
6.2 ESD Ratings............................................................... 4
6.3 Recommended Operating Conditions.........................4
6.4 Thermal Information....................................................4
6.5 Electrical Characteristics.............................................5
6.6 Timing Requirements.................................................. 6
6.7 Typical Characteristics................................................ 7
7 Parameter Measurement Information............................ 8
8 Detailed Description......................................................10
8.1 Overview................................................................... 10
8.2 Functional Block Diagram......................................... 10
8.3 Feature Description...................................................11
8.4 Device Functional Modes..........................................11
9 Application and Implementation.................................. 12
9.1 Application Information............................................. 12
9.2 Typical Application.................................................... 12
10 Power Supply Recommendations..............................14
11 Layout........................................................................... 15
11.1 Layout Guidelines................................................... 15
11.2 Layout Example...................................................... 15
12 Device and Documentation Support..........................16
12.1 Documentation Support.......................................... 16
12.2 接收文档更新通知................................................... 16
12.3 支持资源..................................................................16
12.4 Trademarks............................................................. 16
12.5 Electrostatic Discharge Caution..............................16
12.6 术语表..................................................................... 16
13 Mechanical, Packaging, and Orderable
Information.................................................................... 16
4 Revision History
注：以前版本的页码可能与当前版本的页码不同
Changes from Revision * (December 2020) to Revision A (January 2022)
•
•
•
•
2
Page
向说明 部分中添加失效防护输入详细信息.......................................................................................................... 1
更改了第一页的重要图形.................................................................................................................................... 1
Changed part-to-part skew maximum from 950 ps to 280 ps.............................................................................5
Added the Fail-Safe Inputs section................................................................................................................... 11
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5 Pin Configuration and Functions
CLKIN
1
16
Y1
1G
2
15
Y3
Y0
3
14
VDD
GND
VDD
4
5
13
12
Y2
GND
Y5
LMK1C 1106
Y4
6
11
GND
7
10
Y6
8
LMK1C 1108
9
VDD
Y7
Not to scale
图 5-1. LMK1C1106 and LMK1C1108 PW Package 14-Pin TSSOP and 16-Pin TSSOP Top View
表 5-1. Pin Functions
PIN
NAME
LMK1C
1106
LMK1C
1108
TYPE
DESCRIPTION
1
Input
Single-ended clock input with internal 300-kΩ (typical) pulldown resistor to
GND. Typically connected to a single-ended clock input.
2
Input
Global Output Enable with internal 300-kΩ (typical) pulldown resistor to GND.
Typically connected to VDD with external pullup resistor.
HIGH: outputs enabled
LOW: outputs disabled
LVCMOS CLOCK INPUT
CLKIN
1
CLOCK OUTPUT ENABLE
1G
2
LVCMOS CLOCK OUTPUT
Y0
3
3
Y1
14
16
Y2
11
13
Y3
13
15
Y4
6
6
Y5
9
11
Y6
–
8
Y7
–
9
5
5
8
10
12
14
4
4
Output
LVCMOS output. Typically connected to a receiver. Unused outputs can be
left floating.
Power
Power supply terminal. Typically connected to a 3.3-V, 2.5-V, or 1.8-V supply.
The VDD pin is typically connected to an external 0.1-μF capacitor near the
pin.
SUPPLY VOLTAGE
VDD
GROUND
GND
7
7
10
12
GND
Device ground.
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6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)(1)
MIN
MAX
–0.5
3.6
UNIT
VDD
Supply voltage
VCLKIN
Input voltage (CLKIN)
VIN
Input voltage (1G)
VYn
Output pins (Yn)
–0.5
VDD + 0.3
IIN
Input current
–20
20
mA
IO
Continuous output current
–50
50
mA
Tstg
Storage temperature
–65
150
°C
(1)
V
Operation outside the Absolute Maximum Ratings may cause permanent device damage. Absolute Maximum Ratings do not imply
functional operation of the device at these or any other conditions beyond those listed under Recommended Operating Conditions. If
used outside the Recommended Operating Conditions but within the Absolute Maximum Ratings, the device may not be fully
functional, and this may affect device reliability, functionality, performance, and shorten the device lifetime.
6.2 ESD Ratings
VALUE
V(ESD)
(1)
(2)
Electrostatic discharge
Human body model (HBM), per ANSI/ESDA/
JEDEC JS-001, all pins(1)
±9000
Charged device model (CDM), per JEDEC
specification JESD22-C101, all pins(2)
±1500
UNIT
V
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
6.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
VDD
Core supply voltage
MIN
NOM
MAX
3.3-V supply
3.135
3.3
3.465
2.5-V supply
2.375
2.5
2.625
1.8-V supply
1.71
1.8
1.89
UNIT
V
TA
Operating free-air temperature
–40
125
°C
TJ
Operating junction temperature
–40
150
°C
6.4 Thermal Information
THERMAL METRIC(1)
LMK1C1108
PW(TSSOP)
UNIT
14 PINS
16 PINS
RqJA
Junction-to-ambient thermal resistance
114.4
123.4
°C/W
RqJC(top)
Junction-to-case (top) thermal resistance
45.2
53.1
°C/W
RqJB
Junction-to-board thermal resistance
60.6
66.4
°C/W
YJT
Junction-to-top characterization parameter
5.9
8.9
°C/W
YJB
Junction-to-board characterization parameter
60
65.8
°C/W
(1)
4
LMK1C1106
PW (TSSOP)
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
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6.5 Electrical Characteristics
VDD = 3.3 V ± 5 %, –40°C ≤ TA ≤ 125°C. Typical values are at VDD = 3.3 V, 25°C (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
CURRENT CONSUMPTION
IDD
Core supply current, static
All-outputs disabled, fIN = 0 V
25
45
µA
IDD
Core supply current
All-outputs disabled, fIN = 100 MHz, VDD =
1.8 V
2
6
mA
IDD
Core supply current
All-outputs disabled, fIN = 100 MHz, VDD =
2.5 V
6.5
10
mA
IDD
Core supply current
All-outputs disabled, fIN = 100 MHz, VDD =
3.3 V
15
21
Per output, fIN = 100 MHz, CL = 5pF, VDD =
1.8 V
3.2
3.5
Per output, fIN = 100 MHz, CL = 5pF, VDD =
2.5 V
4.6
5.5
Per output, fIN = 100 MHz, CL = 5pF, VDD =
3.3 V
6
7
IDD
Output current
mA
CLOCK INPUT
fIN_SE
Input frequency
VIH
Input high voltage
VIL
Input low voltage
dVIN/dt
Input slew rate
IIN_LEAK
Input leakage current
CIN_SE
Input capacitance
VDD = 3.3 V
DC
250
VDD = 2.5 V and 1.8 V
DC
200
0.7 x VDD
0.3 x VDD
20% - 80% of input swing
0.1
V
V/ns
50
–50
at 25°C
MHz
7
uA
pF
CLOCK OUTPUT FOR ALL VDD LEVELS
fOUT
Output frequency
ODC
Output duty cycle
VDD = 3.3 V
250
VDD = 2.5 V and 1.8 V
200
With 50% duty cycle input
55
%
(1)
5
cycles
5
cycles
t1G_ON
Output enable time
See
t1G_OFF
Output disable time
See (2)
45
MHz
CLOCK OUTPUT FOR VDD = 3.3 V ± 5%
VOH
Output high voltage
IOH = 1 mA
VOL
Output low voltage
IOL = 1 mA
tRISE-FALL
Output rise and fall time
20/80%, CL= 5 pF, fIN = 156.25 MHz
0.3
0.7
tOUTPUT-
Output-output skew
See (3)
35
55
SKEW
tPART-SKEW
2.8
0.2
Part-to-part skew
V
ns
ps
280
tPROP-DELAY Propagation delay
See (4)
1.3
2.2
tJITTER-ADD
Additive Jitter
fIN = 156.25 MHz, Input slew rate = 1.6
V/ns, Integration range = 12 kHz - 20 MHz
12
20 fs, RMS
ROUT
Output impedance
50
ns
Ω
CLOCK OUTPUT FOR VDD = 2.5 V ± 5%
VOH
Output high voltage
IOH = 1 mA
VOL
Output low voltage
IOL = 1 mA
tRISE-FALL
Output rise and fall time
20/80%, CL= 5 pF, fIN = 156.25 MHz
tOUTPUT-
Output-output skew
See (3)
SKEW
tPART-SKEW
0.8 x VDD
0.2 x VDD
0.33
55
Part-to-part skew
tPROP-DELAY Propagation delay
0.8
V
ns
ps
450
See (4)
1.5
2.5
ns
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VDD = 3.3 V ± 5 %, –40°C ≤ TA ≤ 125°C. Typical values are at VDD = 3.3 V, 25°C (unless otherwise noted)
PARAMETER
tJITTER-ADD
Additive Jitter
ROUT
Output impedance
TEST CONDITIONS
MIN
fIN = 156.25 MHz, Input slew rate = 1.2
V/ns, Integration range = 12 kHz - 20 MHz
TYP
15
MAX
UNIT
27 fs, RMS
55
Ω
CLOCK OUTPUT FOR VDD = 1.8 V ± 5%
VOH
Output high voltage
IOH = 1 mA
VOL
Output low voltage
IOL = 1 mA
tRISE-FALL
Output rise and fall time
20/80%, CL= 5 pF, fIN = 156.25 MHz
tOUTPUT-
Output-output skew
See (3)
SKEW
tPART-SKEW
0.8 x VDD
0.2 x VDD
0.38
Part-to-part skew
(4)
tPROP-DELAY Propagation delay
See
tJITTER-ADD
Additive Jitter
fIN = 156.25 MHz, Input slew rate = 1.2
V/ns, Integration range = 12 kHz - 20 MHz
ROUT
Output impedance
1.5
28
V
1
ns
55
ps
930
ps
3
ns
60 fs, RMS
64
Ω
GENERAL PURPOSE INPUT (1G)
0.75 x
VDD
VIH
High-level input voltage
VIL
Low-level input voltage
IIH
Input high-level current
VIH = VDD_REF
–50
50
IIL
Input low-level current
VIL = GND
–50
50
(1)
(2)
(3)
(4)
0.25 x
VDD
V
µA
Measured from 1G rising edge crossing VIH to first rising edge of Yn.
Measured from 1G falling edge crossing VIL to last falling edge of Yn.
Measured from rising edge of any Yn output to any other Ym output.
Measured from rising edge of CLKIN to any Yn output.
6.6 Timing Requirements
VDD = 3.3 V ± 5 %, –40°C ≤ TA ≤ 125°C
MIN
NOM
MAX
UNIT
50
V/ms
POWER SUPPLY
V/tRAMP
6
VDD ramp rate
0.1
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6.7 Typical Characteristics
140
120
Current (mA)
100
80
60
40
VDD = 1.8 V
VDD = 2.5 V
VDD = 3.3 V
20
0
0
25
50
75
100 125 150 175
Frequency (MHz)
200
225
250
Device Power Consumption vs. Clock Frequency (Load 5 pF)
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7 Parameter Measurement Information
VDD = 3.3-V, 2.5-V,
or 1.8-V
LVCMOS
Output
Zo = 50
R = 50 Ÿ
C = 2 pF
Parasitic capacitance
From measurement
equipment
图 7-1. Test Load Circuit
VDD
VDD = 3.3-V, 2.5-V,
or 1.8-V
R = 100 Ÿ
LVCMOS
Output
Zo = 50
Parasitic capacitance
R = 100 Ÿ
图 7-2. Application Load With 50-Ω Termination
VDD = 3.3-V, 2.5-V,
or 1.8-V
LVCMOS
Output
Zo = 50
Parasitic capacitance
图 7-3. Application Load With Termination
CLKIN
1G
tt1G_ONt
Yn
图 7-4. t1G_ON Output Enable Time
8
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CLKIN
1G
tt1G_OFFt
Yn
图 7-5. t1G_OFF Output Disable Time
CLKIN
Yn
tPROP-DELAY
tOUTPUT-SKEW
Yn+1
图 7-6. Propagation Delay tPROP-DELAY and Output Skew tOUTPUT-SKEW
80% x VDD
Yn
20% x VDD
tRISE-FALL
tRISE-FALL
图 7-7. Rise and Fall Time tRISE-FALL
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8 Detailed Description
8.1 Overview
The LMK1C110x family of devices is part of a low-jitter and low-skew LVCMOS fan-out buffer solution. For best
signal integrity, it is important to match the characteristic impedance of the LMK1C110x's output driver with that
of the transmission line.
8.2 Functional Block Diagram
CLKIN
LVCMOS
LVCMOS
Y0
LVCMOS
Y1
LVCMOS
Y2
LVCMOS
Y3
LVCMOS
Y4
LVCMOS
Y5
LVCMOS
Y6
LVCMOS
Y7
1G
10
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8.3 Feature Description
The outputs of the LMK1C110x can be disabled by driving the synchronous output enable pin (1G) low. Unused
output can be left floating to reduce overall system component cost. Supply and ground pins must be connected
to VDD and GND, respectively.
8.3.1 Fail-Safe Inputs
The LMK1C110x family of devices is designed to support fail-safe input operation. This feature allows the user to
drive the device inputs before VDD is applied without damaging the device. Refer to Absolute Maximum Ratings
for more information on the maximum input supported by the device. The device also incorporates an input
hysteresis that prevents random oscillation in absence of an input signal, allowing the input pins to be left open.
8.4 Device Functional Modes
The LMK1C110x operates from 1.8-V, 2.5-V, or 3.3-V supplies. 表 8-1 shows the output logics of the
LMK1C110x.
表 8-1. Output Logic Table
INPUTS
CLKIN
OUTPUTS
1G
Yn
X
L
L
L
H
L
H
H
H
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9 Application and Implementation
备注
以下应用部分中的信息不属于 TI 器件规格的范围，TI 不担保其准确性和完整性。TI 的客 户应负责确定
器件是否适用于其应用。客户应验证并测试其设计，以确保系统功能。
9.1 Application Information
The LMK1C110x family is a low additive jitter LVCMOS buffer solution that can operate up to 250-MHz at VDD =
3.3 V and 200 MHz at VDD = 2.5 V to 1.8 V. Low output skew as well as the ability for synchronous output enable
is featured to simultaneously enable or disable buffered clock outputs as necessary in the application.
9.2 Typical Application
100-MHz
LVCMOS Oscillator
50VDD
Trace
Y0
CMOS
CPU Clock
Y1
CMOS
FPGA Clock
CLKIN
50-
1G
Trace
100
PLL
Reference
Yn
From CPU
GND
100
图 9-1. System Configuration Example
9.2.1 Design Requirements
The LMK1C110x shown in 图 9-1 is configured to fan out a 100-MHz signal from a local LVCMOS oscillator. The
CPU is configured to control the output state through 1G.
The configuration example is driving three LVCMOS receivers in a backplane application with the following
properties:
• The CPU clock can accept a full swing DC-coupled LVCMOS signal. A series resistor is placed near the
LMK1C110x to closely match the characteristic impedance of the trace to minimize reflections.
• The FPGA clock is similarly DC-coupled with an appropriate series resistor placed near the LMK1C110x.
• The PLL in this example can accept a lower amplitude signal, so a Thevenin's equivalent termination is used.
The PLL receiver features internal biasing, so AC coupling can be used when common-mode voltage is
mismatched.
9.2.2 Detailed Design Procedure
Unused outputs can be left floating. See Power Supply Recommendations for recommended filtering techniques.
9.2.3 Application Curves
The low additive jitter of the LMK1C110x is shown in 图 9-2.
图 9-3 shows the low-noise 156.25-MHz reference source with 24.8-fs RMS jitter driving the LMK1C110x,
resulting in 27.3-fs RMS jitter when integrated from 12 kHz to 20 MHz at 3.3-V supply. The resultant additive
jitter measured is a low 11.4-fs RMS for this configuration.
图 9-4 shows the low-noise 156.25-MHz reference source with 24.8-fs RMS jitter driving the LMK1C110x,
resulting in 29-fs RMS jitter when integrated from 12 kHz to 20 MHz at 2.5-V supply. The resultant additive jitter
measured is a low 15-fs RMS for this configuration.
12
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图 9-5 shows the low-noise 156.25-MHz reference source with 24.8-fs RMS jitter driving the LMK1C110x,
resulting in 34-fs RMS jitter when integrated from 12 kHz to 20 MHz at 1.8-V supply. The resultant additive jitter
measured is a low 23.25-fs RMS for this configuration.
图 9-2. LMK1C110x Reference Phase Noise 24.8-fs
(12 kHz to 20 MHz)
图 9-3. LMK1C110x 3.3-V Output Phase Noise 27.3fs (12 kHz to 20 MHz)
图 9-4. LMK1C110x 2.5-V Output Phase Noise 29-fs 图 9-5. LMK1C110x 1.8-V Output Phase Noise 34-fs
(12 kHz to 20 MHz)
(12 kHz to 20 MHz)
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10 Power Supply Recommendations
High-performance clock buffers can be sensitive to noise on the power supply, which may dramatically increase
the additive jitter of the buffer. Thus, it is essential to manage any excessive noise from the system power
supply, especially for applications where the jitter and phase noise performance is critical.
Filter capacitors are used to eliminate the low-frequency noise from the power supply, where the bypass
capacitors provide the very low impedance path for high-frequency noise and guard the power supply system
against induced fluctuations. These bypass capacitors also provide instantaneous current surges as required by
the device and should have low equivalent series resistance (ESR). To properly bypass the supply, the
decoupling capacitors must be placed very close to the power-supply terminals, be connected directly to the
ground plane, and laid out with short loops to minimize inductance. TI recommends adding as many highfrequency (for example, 0.1 µF) bypass capacitors, as there are supply terminals in the package. TI
recommends, but does not require, inserting a ferrite bead between the board power supply and the chip power
supply that isolates the high-frequency switching noises generated by the clock buffer; these beads prevent the
switching noise from leaking into the board supply. It is imperative to choose an appropriate ferrite bead with
very low DC resistance to provide adequate isolation between the board supply and the chip supply, as well as
to maintain a voltage at the supply terminals that is greater than the minimum voltage required for proper
operation.
图 10-1 shows this recommended power supply decoupling method.
V
Board
Supply
CC
Chip
Supply
Ferrite Bead
C
10 …F
C
1 …F
C
0.1 …F
GND
GND
GND
图 10-1. Power Supply Decoupling
14
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LMK1C1106, LMK1C1108
www.ti.com.cn
ZHCSLS7A – DECEMBER 2020 – REVISED JANUARY 2022
11 Layout
11.1 Layout Guidelines
图 11-1 shows a conceptual layout detailing recommended placement of power supply bypass capacitors. For
component side mounting, use 0402 body size capacitors to facilitate signal routing. Keep the connections
between the bypass capacitors and the power supply on the device as short as possible. Ground the other side
of the capacitor using a low-impedance connection to the ground plane.
11.2 Layout Example
图 11-1. PCB Conceptual Layout
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Product Folder Links: LMK1C1106 LMK1C1108
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ZHCSLS7A – DECEMBER 2020 – REVISED JANUARY 2022
www.ti.com.cn
12 Device and Documentation Support
12.1 Documentation Support
12.1.1 Related Documentation
For related documentation, see the following:
LMK1C1108EVM User Guide
12.2 接收文档更新通知
要接收文档更新通知，请导航至 ti.com 上的器件产品文件夹。点击订阅更新 进行注册，即可每周接收产品信息更
改摘要。有关更改的详细信息，请查看任何已修订文档中包含的修订历史记录。
12.3 支持资源
TI E2E™ 支持论坛是工程师的重要参考资料，可直接从专家获得快速、经过验证的解答和设计帮助。搜索现有解
答或提出自己的问题可获得所需的快速设计帮助。
链接的内容由各个贡献者“按原样”提供。这些内容并不构成 TI 技术规范，并且不一定反映 TI 的观点；请参阅
TI 的《使用条款》。
12.4 Trademarks
TI E2E™ is a trademark of Texas Instruments.
所有商标均为其各自所有者的财产。
12.5 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled
with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may
be more susceptible to damage because very small parametric changes could cause the device not to meet its published
specifications.
12.6 术语表
TI 术语表
本术语表列出并解释了术语、首字母缩略词和定义。
13 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
16
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Product Folder Links: LMK1C1106 LMK1C1108
PACKAGE OPTION ADDENDUM
www.ti.com
18-Nov-2021
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
(4/5)
(6)
LMK1C1106PWR
ACTIVE
TSSOP
PW
14
3000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
LMK1C6
LMK1C1108PWR
ACTIVE
TSSOP
PW
16
3000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
LMK1C8
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of
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