LMK1D1208IRHAT

LMK1D1208I SNAS828A – FEBRUARY 2022 – REVISED JUNE 2023 LMK1D1208I I2C-Configurable, Low-Additive Jitter LVDS Buffer 1 Features 3 Description • The LMK1D1208I is an I2C-programmable LVDS clock buffer. The device has two inputs and eight pairs of differential LVDS clock outputs (OUT0 through OUT7) with minimum skew for clock distribution. The inputs can either be LVDS, LVPECL, LVCMOS, HCSL, or CML. • • • • • • • • • • • • High-performance LVDS clock buffer family with 2 inputs and 8 outputs Output frequency up to 2 GHz Supply voltage: 1.8 V / 2.5 V / 3.3 V ± 5% Device configurability through I2C programming – Individual input and output enable/disable – Individual output amplitude select (standard or boosted) – Bank input multiplexer Four programmable I2C addresses through IDX pins Low additive jitter: < 60 fs RMS maximum in 12-kHz to 20-MHz at 156.25 MHz – Very low phase noise floor: -164 dBc/Hz (typical) Very low propagation delay: < 575 ps maximum Output skew: 20 ps maximum Universal inputs accept LVDS, LVPECL, LVCMOS, HCSL and CML Fail-safe inputs LVDS reference voltage, VAC_REF, available for capacitive coupled inputs Industrial temperature range: –40°C to 105°C Packages available – 6-mm × 6-mm, 40-Pin VQFN (RHA) 2 Applications • • • • • Telecommunications and networking Medical imaging Test and measurement equipment Wireless communications Pro audio/video The LMK1D1208I is specifically designed for driving 50-Ω transmission lines. When driving inputs in single-ended mode, apply the appropriate bias voltage to the unused negative input pin (see Figure 9-6). I2C programming enables this device to be configured as a single bank buffer (one of the two inputs is distributed to eight output pairs) or as a dual bank buffer (each input is distributed to four outputs pairs). Each output can be configured to have either a standard (350 mV) or boosted (500 mV) swing. This device also incorporates individual output channel enable or disable through I2C programming. The LMK1D1208I has fail-safe inputs that prevent oscillation at the outputs in the absence of an input signal and allows for input signals before VDD is supplied. The device operates in a 1.8-V, 2.5-V, or 3.3-V supply environment and is characterized from –40°C to 105°C (ambient temperature). Package Information PACKAGE(1) PART NUMBER LMK1D1208I (1) (2) VQFN (40) PACKAGE SIZE (NOM)(2) 6.00 mm × 6.00 mm For all available packages, see the orderable addendum at the end of the data sheet. The package size (length × width) is a nominal value and includes pins, where applicable. ADC CLOCK 200 MHz 100
156.25 MHz Oscillator LMK1D1208I LVDS Buffer SDA FPGA CLOCK SCL IDX1 IDX0 100 Application Example An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. PRODUCTION DATA. LMK1D1208I www.ti.com SNAS828A – FEBRUARY 2022 – REVISED JUNE 2023 Table of Contents 1 Features............................................................................1 2 Applications..................................................................... 1 3 Description.......................................................................1 4 Revision History.............................................................. 2 5 Device Comparison......................................................... 3 6 Pin Configuration and Functions...................................4 7 Specifications.................................................................. 6 7.1 Absolute Maximum Ratings........................................ 6 7.2 ESD Ratings............................................................... 6 7.3 Recommended Operating Conditions.........................6 7.4 Thermal Information....................................................7 7.5 Electrical Characteristics.............................................7 7.6 Typical Characteristics.............................................. 11 8 Parameter Measurement Information.......................... 12 9 Detailed Description......................................................14 9.1 Overview................................................................... 14 9.2 Functional Block Diagram......................................... 14 9.3 Feature Description...................................................15 9.4 Device Functional Modes..........................................18 9.5 Programming............................................................ 20 9.6 Register Maps...........................................................21 10 Application and Implementation................................ 25 10.1 Application Information........................................... 25 10.2 Typical Application.................................................. 25 10.3 Power Supply Recommendations...........................28 10.4 Layout..................................................................... 29 11 Device and Documentation Support..........................31 11.1 Documentation Support.......................................... 31 11.2 Receiving Notification of Documentation Updates.. 31 11.3 Support Resources................................................. 31 11.4 Trademarks............................................................. 31 11.5 Electrostatic Discharge Caution.............................. 31 11.6 Glossary.................................................................. 31 12 Mechanical, Packaging, and Orderable Information.................................................................... 31 12.1 Package Option Addendum.................................... 32 12.2 Tape and Reel Information......................................34 4 Revision History NOTE: Page numbers for previous revisions may differ from page numbers in the current version. Changes from Revision * (February 2022) to Revision A (June 2023) Page • Changed table title from: Device Information to: Package Information.............................................................. 1 • Added the Device Comparison table for the LMK1Dxxxx buffer device family................................................... 3 • Moved the Power Supply Recommendations and Layout sections to the Application and Implementation section.............................................................................................................................................................. 28 2 Submit Document Feedback Copyright © 2023 Texas Instruments Incorporated Product Folder Links: LMK1D1208I LMK1D1208I www.ti.com SNAS828A – FEBRUARY 2022 – REVISED JUNE 2023 5 Device Comparison DEVICE DEVICE TYPE FEATURES OUTPUT SWING LMK1D2108 Dual 1:8 Global output enable and swing control through pin control 350 mV LMK1D2106 Dual 1:6 Global output enable and swing control through pin control 350 mV LMK1D2104 Dual 1:4 Global output enable and swing control through pin control 350 mV LMK1D2102 Dual 1:2 Global output enable and swing control through pin control 350 mV LMK1D1216 2:16 Global output enable control through pin control 350 mV LMK1D1212 2:12 Global output enable control through pin control 350 mV LMK1D1208P 2:8 Individual output enable control through pin control 350 mV LMK1D1208I 2:8 Individual output enable control through I2C 350 mV LMK1D1208 2:8 Global output enable control through pin control LMK1D1204P 2:4 LMK1D1204 2:4 PACKAGE BODY SIZE VQFN (48) 7.00 mm × 7.00 mm VQFN (40) 6.00 mm × 6.00 mm VQFN (28) 5.00 mm × 5.00 mm VQFN (16) 3.00 mm × 3.00 mm VQFN (48) 7.00 mm × 7.00 mm VQFN (40) 6.00 mm × 6.00 mm VQGN (40) 6.00 mm × 6.00 mm VQFN (40) 6.00 mm × 6.00 mm 350 mV VQFN (28) 5.00 mm × 5.00 mm Individual output enable control through pin control 350 mV VQGN (28) 5.00 mm × 5.00 mm Global output enable control through pin control 350 mV VQFN (16) 3.00 mm × 3.00 mm 500 mV 500 mV 500 mV 500 mV 500 mV 500 mV 500 mV 500 mV Submit Document Feedback Copyright © 2023 Texas Instruments Incorporated Product Folder Links: LMK1D1208I 3 LMK1D1208I www.ti.com SNAS828A – FEBRUARY 2022 – REVISED JUNE 2023 NC OUT3_N OUT3_P NC NC OUT2_N OUT2_P OUT1_N OUT1_P NC 6 Pin Configuration and Functions 30 29 28 27 26 25 24 23 22 21 NC 31 20 VDD OUT4_P 32 19 OUT0_N OUT4_N 33 18 OUT0_P OUT5_P 34 17 NC 16 IDX1 OUT5_N 35 6mm x 6mm 40 pin QFN NC 36 15 IDX0 NC 37 14 VAC_REF0 OUT6_P 38 13 IN0_N OUT6_N 39 12 IN0_P VDD 40 11 VDD 2 3 4 5 6 7 8 9 10 OUT7_N NC SDA SCL NC IN1_P IN1_N VAC_REF1 NC 1 OUT7_P Thermal Pad Figure 6-1. LMK1D1208I: RHA Package 40-Pin VQFN (Top View) Table 6-1. Pin Functions PIN NAME LMK1D1208I TYPE(1) DESCRIPTION DIFFERENTIAL/SINGLE-ENDED CLOCK INPUT IN0_P, IN0_N 12, 13 I Primary: Differential input pair or single-ended input IN1_P, IN1_N 8, 9 I Secondary: Differential input pair or single-ended input. SDA 5 I/O I2C data SCL 6 I I2C clock IDX0 15 I,S,PU I2C address bit[0]. This is a 2-level input that is decoded in conjunction with pin 15 to set the I2C address. It has internal 670-kΩ pullup. IDX1 16 I,S, PU I2C address bit[1]. This is a 2-level input that is decoded in conjunction with pin 16 to set the I2C address. It has internal 670-kΩ pullup. 14, 10 O Bias voltage output for capacitive coupled inputs. If used, TI recommends using a 0.1-µF capacitor to GND on this pin. OUT0_P, OUT0_N 18, 19 O Differential LVDS output pair number 0 OUT1_P, OUT1_N 22, 23 O Differential LVDS output pair number 1 OUT2_P, OUT2_N 24, 25 O Differential LVDS output pair number 2 OUT3_P, OUT3_N 28, 29 O Differential LVDS output pair number 3 OUT4_P, OUT4_N 32, 33 O Differential LVDS output pair number 4 OUT5_P, OUT5_N 34, 35 O Differential LVDS output pair number 5 OUT6_P, OUT6_N 38, 39 O Differential LVDS output pair number 6 OUT7_P, OUT7_N 2, 3 O Differential LVDS output pair number 7 I2C PROGRAMMING BIAS VOLTAGE OUTPUT VAC_REF0, VAC_REF1 DIFFERENTIAL CLOCK OUTPUT 4 Submit Document Feedback Copyright © 2023 Texas Instruments Incorporated Product Folder Links: LMK1D1208I LMK1D1208I www.ti.com SNAS828A – FEBRUARY 2022 – REVISED JUNE 2023 Table 6-1. Pin Functions (continued) PIN NAME TYPE(1) LMK1D1208I DESCRIPTION SUPPLY VOLTAGE VDD 11, 20, 40 P Device power supply (1.8 V, 2.5 V, or 3.3 V) DAP DAP G Die Attach Pad. Connect to the printed circuit board (PCB) ground plane for heat dissipation. 1, 4, 7, 17, 21, 26, 27, 30, 31, 36, 37 — No connection. Leave floating. GROUND NO CONNECT NC (1) The definitions below define the I/O type for each pin. • • • • • • • I = Input O = Output I / O = Input / Output PU = Internal 670-kΩ Pullup S = Hardware Configuration Pin P = Power Supply G = Ground Submit Document Feedback Copyright © 2023 Texas Instruments Incorporated Product Folder Links: LMK1D1208I 5 LMK1D1208I www.ti.com SNAS828A – FEBRUARY 2022 – REVISED JUNE 2023 7 Specifications 7.1 Absolute Maximum Ratings over operating free-air temperature range (unless otherwise noted)(1) MIN MAX UNIT VDD Supply voltage –0.3 3.6 V VIN Input voltage –0.3 3.6 V VO Output voltage –0.3 VDD + 0.3 IIN Input current –20 20 mA IO Continuous output current –50 TJ Junction temperature Tstg (1) (2) Storage temperature (2) –65 V 50 mA 135 °C 150 °C Operation outside the Absolute Maximum Ratings may cause permanent device damage. Absolute Maximum Ratings do not imply functional operation of the device at these or any other conditions beyond those listed under Recommended Operating Conditions. If used outside the Recommended Operating Conditions but within the Absolute Maximum Ratings, the device may not be fully functional, and this may affect device reliability, functionality, performance, and shorten the device lifetime. Device unpowered 7.2 ESD Ratings VALUE V(ESD) (1) (2) Electrostatic discharge Human body model (HBM), per ANSI/ESDA/ JEDEC JS-001, all pins(1) ±3000 Charged device model (CDM), per ANSI/ESDA/ JEDEC JS-002, all pins(2) ±1000 UNIT V JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process. 7.3 Recommended Operating Conditions over operating free-air temperature range (unless otherwise noted) VDD 6 Core supply voltage Supply Ramp Supply voltage ramp TA TJ MIN NOM MAX 3.3-V supply 3.135 3.3 3.465 2.5-V supply 2.375 2.5 2.625 1.8-V supply 1.71 1.8 1.89 Requires monotonic ramp (10-90% of VDD) UNIT V 0.1 20 ms Operating free-air temperature –40 105 °C Operating junction temperature –40 135 °C Submit Document Feedback Copyright © 2023 Texas Instruments Incorporated Product Folder Links: LMK1D1208I LMK1D1208I www.ti.com SNAS828A – FEBRUARY 2022 – REVISED JUNE 2023 7.4 Thermal Information LMK1D1208I THERMAL METRIC(1) UNIT VQFN 40 PINS RθJA Junction-to-ambient thermal resistance 39.1 °C/W RθJC(top) Junction-to-case (top) thermal resistance 32.4 °C/W RθJB Junction-to-board thermal resistance 20.2 °C/W ΨJT Junction-to-top characterization parameter 1 °C/W ΨJB Junction-to-board characterization parameter 20.2 °C/W RθJC(bot) Junction-to-case (bottom) thermal resistance 8.3 °C/W (1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report. 7.5 Electrical Characteristics VDD = 1.8 V ± 5 %, –40°C ≤ TA ≤ 105°C. Typical values are at VDD = 1.8 V, 25°C (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT POWER SUPPLY CHARACTERISTICS IDDSTAT LMK1D1208I All-outputs enabled and unterminated, f = 0 Hz (AMP_SEL =1) 55 IDD100M LMK1D1208I All-outputs enabled, RL = 100 Ω, f =100 MHz (AMP_SEL = 0, default) 75 IDD100M LMK1D1208I All-outputs enabled, RL = 100 Ω, f =100 MHz, AMP_SEL = 1 mA 95 mA 110 mA IDX INPUT CHARACTERISTICS (Applies to VDD = 1.8 V ± 5%, 2.5 V ± 5% and 3.3 V ± 5%) VIH Input high voltage Minimum input voltage for a logical "1" state 0.7 × VCC VCC + 0.3 V VIL Input low voltage Maximum input voltage for a logical "0" state –0.3 0.3 × VCC V IIH Input high current VDD can be 1.8V/2.5V/3.3V with VIH = VDD 30 µA IIL Input low current VDD can be 1.8V/2.5V/3.3V with VIH = VDD Rpull-up(IDX) Input pullup resistor I2C –30 µA 670 kΩ INTERFACE CHARACTERISTICS (Applies to VDD = 1.8 V ± 5%, 2.5 V ± 5% and 3.3 V ± 5%) VIH Input high voltage VIL Input low voltage IIH Input high current IIL Input low current CIN_SE Input capacitance at 25°C VOL Output low voltage IOL = 3 mA 0.3 Standard 100 fSCL I2C clock rate 0.7 × VCC VCC + 0.3 –0.3 0.3 × VCC V 30 µA –30 µA 2 Fast mode pF 400 Ultra Fast mode V V kHz 1000 tSU(START) START condition setup time SCL high before SDA low 0.6 us tH(START) START condition hold time SCL low after SDA low 0.6 us tW(SCLH) SCL pulse width high 0.6 us tW(SCLL) SCL pulse width low 1.3 us tSU(SDA) SDA setup time 100 ns Submit Document Feedback Copyright © 2023 Texas Instruments Incorporated Product Folder Links: LMK1D1208I 7 LMK1D1208I www.ti.com SNAS828A – FEBRUARY 2022 – REVISED JUNE 2023 VDD = 1.8 V ± 5 %, –40°C ≤ TA ≤ 105°C. Typical values are at VDD = 1.8 V, 25°C (unless otherwise noted) PARAMETER TEST CONDITIONS SDA valid after SCL low MIN TYP 0 MAX UNIT tH(SDA) SDA hold time 0.9 us tR(IN) tF(IN) SDA/SCL input rise time 300 ns SDA/SCL input fall time 300 ns tF(OUT) SDA output fall time tSU(STOP) STOP condition setup time 0.6 300 ns us tBUS Bus free time between STOP and START 1.3 us CBUS 0.4 V (VDD = 1.8 V/2.5/3.3 V) 0.25 2.3 V IIH Input high current VDD = 3.465 V, VINP = 2.4 V, VINN = 1.2 V 30 µA IIL Input low current VDD = 3.465 V, VINP = 0 V, VINN = 1.2 V CIN_S-E Input capacitance (Single-ended) at 25°C –30 GHz VPP µA 3.5 pF LVDS DC OUTPUT CHARACTERISTICS |VOD| Differential output voltage magnitude | VOUTP - VOUTN| VIN,DIFF(P-P) = 0.3 V, RLOAD = 100 Ω, AMP_SEL = 0 250 350 450 mV |VOD| Differential output voltage magnitude | VOUTP - VOUTN| VIN,DIFF(P-P) = 0.3 V, RLOAD = 100 Ω, AMP_SEL = 1 400 500 650 mV ΔVOD Change in differential output voltage magnitude. Per output, defined as the difference between VOD in logic hi/lo states. VIN,DIFF(P-P) = 0.3 V, RLOAD = 100 Ω, AMP_SEL = 0 –15 15 mV ΔVOD Change in differential output voltage magnitude VIN,DIFF(P-P) = 0.3 V, RLOAD = 100 Ω, AMP_SEL = 1 –20 20 mV VIN,DIFF(P-P) = 0.3 V, RLOAD = 100 Ω (VDD = 1.8 V) 1 1.2 VOC(SS) Steady-state common mode output voltage VIN,DIFF(P-P) = 0.3 V, RLOAD = 100 Ω (VDD = 2.5 V/3.3 V) 1.1 1.375 VIN,DIFF(P-P) = 0.3 V, RLOAD = 100 Ω (VDD = 1.8 V), AMP_SEL = 1 0.8 1 VIN,DIFF(P-P) = 0.3 V, RLOAD = 100 Ω (VDD = 2.5 V/3.3 V), AMP_SEL = 1 0.9 1.1 VOC(SS) Steady-state common mode output voltage V V ΔVOC(SS) Change in steady-state common mode V = 0.3 V, RLOAD = 100 output voltage. Per output, defined as the IN,DIFF(P-P) Ω, AMP_SEL = 0 difference in VOC in logic hi/lo states. –15 15 mV ΔVOC(SS) Change in steady-state common mode output voltage –20 20 mV VIN,DIFF(P-P) = 0.3 V, RLOAD = 100 Ω, AMP_SEL = 1 LVDS AC OUTPUT CHARACTERISTICS 8 Submit Document Feedback Copyright © 2023 Texas Instruments Incorporated Product Folder Links: LMK1D1208I LMK1D1208I www.ti.com SNAS828A – FEBRUARY 2022 – REVISED JUNE 2023 VDD = 1.8 V ± 5 %, –40°C ≤ TA ≤ 105°C. Typical values are at VDD = 1.8 V, 25°C (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT 0.1 VOD Vring Output overshoot and undershoot VIN,DIFF(P-P) = 0.3 V, RLOAD = 100 Ω, fOUT = 491.52 MHz VOS Output AC common mode VIN,DIFF(P-P) = 0.3 V, RLOAD = 100 Ω , AMP_SEL = 0 50 100 mVpp VOS Output AC common mode VIN,DIFF(P-P) = 0.3 V, RLOAD = 100 Ω, AMP_SEL = 1 75 150 mVpp IOS Short-circuit output current (differential) VOUTP = VOUTN –12 12 mA IOS(cm) Short-circuit output current (commonmode) VOUTP = VOUTN = 0 –24 24 mA tPD Propagation delay VIN,DIFF(P-P) = 0.3 V, RLOAD = 100 Ω (2) 0.3 0.575 ns tSK, O Output skew Skew between outputs with the same load conditions (4 and 8 channel) (3) 20 ps tSK, PP Part-to-part skew Skew between outputs on different parts subjected to the same operating conditions with the same input and output loading. 250 ps tSK, P Pulse skew 20 ps 60 fs, RMS tRJIT(ADD) 50% duty cycle input, crossing point-to-crossing-point distortion (4) –0.1 –20 fIN = 156.25 MHz with 50% dutycycle, Input slew rate = 1.5V/ns, Integration range = 12 kHz – 20 MHz, with output load RLOAD = 100 Ω Random additive Jitter (rms) Phase Noise for a carrier frequency of 156.25 MHz with 50% duty-cycle, Input Phase noise slew rate = 1.5V/ns with output load RLOAD = 100 Ω 50 PN1kHz –143 PN10kHz –152 PN100kHz –157 PN1MHz –160 PNfloor –164 dBc/Hz MUXISO Mux Isolation fIN = 156.25 MHz. The difference in power level at fIN when the selected clock is active and the unselected clock is static versus when the selected clock is inactive and the unselected clock is active. ODC Output duty cycle With 50% duty cycle input 55 % tR/tF Output rise and fall time 20% to 80% with RLOAD = 100 Ω 300 ps tR/tF Output rise and fall time 20% to 80% with RLOAD = 100 Ω (AMP_SEL= 1) 300 ps ten/disable Output Enable and Disable Time Time taken for outputs to go from disable state to enable state and vice versa. (5) (6) 1 us IleakZ Output leakage current in High Z Outputs are held in high Z mode with OUTP = OUTN (max applied external voltage is the lesser of VDD or 1.89V and minimum applied external voltage is 0V 50 uA VAC_REF Reference output voltage VDD = 2.5 V, ILOAD = 100 µA 1.375 V 80 45 0.9 1.25 dB POWER SUPPLY NOISE REJECTION (PSNR) VDD = 2.5 V/ 3.3 V Submit Document Feedback Copyright © 2023 Texas Instruments Incorporated Product Folder Links: LMK1D1208I 9 LMK1D1208I www.ti.com SNAS828A – FEBRUARY 2022 – REVISED JUNE 2023 VDD = 1.8 V ± 5 %, –40°C ≤ TA ≤ 105°C. Typical values are at VDD = 1.8 V, 25°C (unless otherwise noted) PARAMETER PSNR (1) (2) (3) (4) (5) 10 TEST CONDITIONS Power Supply Noise Rejection (fcarrier = 156.25 MHz) MIN TYP 10 kHz, 100 mVpp ripple injected on VDD –70 1 MHz, 100 mVpp ripple injected on VDD –50 MAX UNIT dBc Measured between single-ended/differential input crossing point to the differential output crossing point. For the dual bank devices, the inputs are phase aligned and have 50% duty cycle. Defined as the magnitude of the time difference between the high-to-low and low-to-high propagation delay times at an output. Applies to the dual bank family. Time starts after the acknowledge bit Submit Document Feedback Copyright © 2023 Texas Instruments Incorporated Product Folder Links: LMK1D1208I LMK1D1208I www.ti.com SNAS828A – FEBRUARY 2022 – REVISED JUNE 2023 7.6 Typical Characteristics Figure 7-1 captures the variation of the LMK1D1208I current consumption with input frequency and supply voltage. Figure 7-2 shows the variation of the differential output voltage (VOD) swept across frequency. It is important to note that Figure 7-1 and Figure 7-2 serve as a guidance to the users on what to expect for the range of operating frequency supported by LMK1D1208I. These graphs were plotted for a limited number of frequencies and load conditions which may not represent the customer system. 90 85 Current Consumption (mA) 80 75 70 65 VDD VDD VDD VDD VDD VDD VDD VDD VDD 60 = = = = = = = = = 1.8 1.8 1.8 2.5 2.5 2.5 3.3 3.3 3.3 V, TA = -40 V, TA = 25 V,TA = 105 V, TA = -40 V, TA = 25 V,TA = 105 V, TA = -40 V, TA = 25 V,TA =105 55 0 100 200 300 400 500 600 700 800 900 1000 1100 1200 1300 1400 1500 1600 1700 1800 1900 2000 Frequency (MHz) Figure 7-1. LMK1D1208I Current Consumption vs. Frequency 380 VDD = 1.8 V, T A = -40 VDD = 1.8 V, T A = 25 VDD = 1.8 V, T a = 105 VDD = 2.5 V, T A = -40 VDD = 2.5 V, T A = 25 370 360 350 VDD = 2.5 V, T A = 105 VDD = 3.3 V, T A = -40 VDD = 3.3 V, T A = 25 VDD = 3.3 V, T A = 105 340 VOD (mV) 330 320 310 300 290 280 270 260 250 240 100 200 300 400 500 Frequency (MHz) 600 700 800 900 1000 2000 Figure 7-2. LMK1D1208I VOD vs. Frequency Submit Document Feedback Copyright © 2023 Texas Instruments Incorporated Product Folder Links: LMK1D1208I 11 LMK1D1208I www.ti.com SNAS828A – FEBRUARY 2022 – REVISED JUNE 2023 8 Parameter Measurement Information Oscilloscope 100 W LVDS Figure 8-1. LVDS Output DC Configuration During Device Test 100 LMK1D1208I Phase Noise/ Spectrum Analyzer Balun
Figure 8-2. LVDS Output AC Configuration During Device Test VIH Vth IN VIL IN Vth Figure 8-3. DC-Coupled LVCMOS Input During Device Test VOH OUTNx VOD OUTPx VOL 80% VOUT,DIFF,PP (= 2 x VOD) 20% 0V tr tf Figure 8-4. Output Voltage and Rise/Fall Time 12 Submit Document Feedback Copyright © 2023 Texas Instruments Incorporated Product Folder Links: LMK1D1208I LMK1D1208I www.ti.com SNAS828A – FEBRUARY 2022 – REVISED JUNE 2023 INNx INPx tPLH0 tPHL0 tPLH1 tPHL1 OUTN0 OUTP0 OUTN1 OUTP1 tPLH2 tPHL2 OUTN2 OUTP2 tPHL7 tPLH7 OUTN7 OUTP7 A. B. Output skew is calculated as the greater of the following: the difference between the fastest and the slowest tPLHn or the difference between the fastest and the slowest tPHLn (n = 0, 1, 2, ..7) Part-to-part skew is calculated as the greater of the following: the difference between the fastest and the slowest tPLHn or the difference between the fastest and the slowest tPHLn across multiple devices (n = 0, 1, 2, ..7) Figure 8-5. Output Skew and Part-to-Part Skew Vring OUTNx VOD 0 V Differential OUTPx Figure 8-6. Output Overshoot and Undershoot VOS GND Figure 8-7. Output AC Common Mode Submit Document Feedback Copyright © 2023 Texas Instruments Incorporated Product Folder Links: LMK1D1208I 13 LMK1D1208I www.ti.com SNAS828A – FEBRUARY 2022 – REVISED JUNE 2023 9 Detailed Description 9.1 Overview The LMK1D1208I is a low-additive jitter, I2C-programmable, LVDS output clock buffer that uses CMOS transistors to control the output current. Therefore, proper biasing and termination are required to ensure correct operation of the device and to maximize signal integrity. The LMK1D1208I also includes status and control registers for configuring the different modes in the device. The proper LVDS termination for signal integrity over two 50-Ω lines is 100 Ω between the outputs on the receiver end. Either DC-coupled termination or AC-coupled termination can be used for LVDS outputs. TI recommends placing a termination resistor close to the receiver. If the receiver is internally biased to a voltage different than the output common-mode voltage of the LMK1D1208I, AC coupling must be used.If the LVDS receiver has internal 100-Ω termination, external termination must be omitted. 9.2 Functional Block Diagram VDD VDD Rpull-up IDX0, IDX1 2 SDA I2C Logic OUTx_AMP_SEL SCL OUTx_EN Input Selection IN1 BANKx_IN_SEL INx_EN IN0 Output Swing Control OUT[0:N/2-1] Bank Control OUT[N/2:N-1] VAC_REF Reference Voltage GND 14 Submit Document Feedback Copyright © 2023 Texas Instruments Incorporated Product Folder Links: LMK1D1208I LMK1D1208I www.ti.com SNAS828A – FEBRUARY 2022 – REVISED JUNE 2023 9.3 Feature Description The LMK1D1208I is an I2C-programmable, low-additive jitter, LVDS fan-out buffer that can generate up to eight copies of two selectable LVPECL, LVDS, HCSL, CML, or LVCMOS inputs. This feature-rich device allows the user to have flexibility on the configuration based on their application use-case. 9.3.1 Fail-Safe Input The LMK1D120x family of devices is designed to support fail-safe input operation. This feature allows the user to drive the device inputs before VDD is applied without damaging the device. Refer to Specifications for more information on the maximum input supported by the device. The device also incorporates an input hysteresis, which prevents random oscillation in absence of an input signal, allowing the input pins to be left open. 9.3.2 Input Stage Configurability The LMK1D1208I has an input stage that accepts up to two clock inputs and can be configured as either a 2:1 mux or as a dual bank. When configured as a 2:1 mux, the LMK1D1208I device can select one of the two clock inputs and then distribute it to the eight LVDS output pairs. In the dual bank mode, the LMK1D1208I can assign each clock input to fan out four LVDS output pairs per bank. Refer to the Device Functional Modes for how to configure the two input stages. Unused inputs can be left floating to reduce overall component cost. Both AC and DC coupling schemes can be used with the LMK1D1208I to provide greater system flexibility. 9.3.3 Dual Output Bank LMK1D1208I has eight LVDS output pairs which are grouped into two banks, each with four LVDS output pairs. The Table 9-1 outlines this mapping. Table 9-1. Output Bank Map BANK CLOCK OUTPUTS 0 OUT0, OUT1, OUT2, OUT3 1 OUT4, OUT5, OUT6, OUT7 9.3.4 I2C The I2C control is used to configure the different features in the LMK1D1208I. These features include individual input and output channel enable or disable, input mux select in each bank, bank muting (setting bank outputs to logic low), and individual output amplitude control. The I2C logic is also capable of fast mode where the frequency is 400 kHz. 9.3.4.1 I2C Address Assignment The I2C address is assigned by the two pins, IDX0 and IDX1. Each IDX pin supports two levels allowing the LMK1D1208I to assume four different I2C addresses. See Table 9-2 for address pin assignment. Table 9-2. I2C Address Assignment I2C ADDRESS 0x68 IDX1 IDX0 L L 0x69 L H 0x6A H L 0x6B H H Submit Document Feedback Copyright © 2023 Texas Instruments Incorporated Product Folder Links: LMK1D1208I 15 LMK1D1208I www.ti.com SNAS828A – FEBRUARY 2022 – REVISED JUNE 2023 9.3.5 LVDS Output Termination TI recommends that unused outputs are terminated differentially with a 100-Ω resistor for optimum performance. Unterminated outputs are also okay, but this will result in a slight degradation in performance (Output AC common-mode VOS) in the outputs being used. Figure 9-1 and Figure 9-2 show how the LMK1D1208I can be connected to LVDS receiver inputs with DC and AC coupling, respectively. Z = 50 W 100 W LMK1D12XX LVDS Z = 50 W Figure 9-1. Output DC Termination 100 nF Z = 50 W 100 W LMK1D12XX LVDS Z = 50 W 100 nF Figure 9-2. Output AC Termination (With the Receiver Internally Biased) 9.3.6 Input Termination The LMK1D1208I inputs can be interfaced with LVDS, LVPECL, HCSL or LVCMOS drivers. Figure 9-3 and Figure 9-4 show how LVDS drivers can be connected to LMK1D1208I inputs with DC coupling and AC coupling, respectively. Z = 50 W 100 W LVDS LMK1D12XX Z = 50 W Figure 9-3. LVDS Clock Driver Connected to LMK1D1208I Input (DC-Coupled) 100 nF Z = 50 W LVDS LMK1D12XX Z = 50 W 100 nF 50 W 50 W VAC_REF Figure 9-4. LVDS Clock Driver Connected to LMK1D1208I Input (AC-Coupled) Figure 9-5 shows how to connect LVPECL inputs to the LMK1D1208I. The series resistors are required to reduce the LVPECL signal swing if the signal swing is >1.6 VPP. 16 Submit Document Feedback Copyright © 2023 Texas Instruments Incorporated Product Folder Links: LMK1D1208I LMK1D1208I www.ti.com SNAS828A – FEBRUARY 2022 – REVISED JUNE 2023 75 W 100 nF Z = 50 W LMK1D12XX LVPECL Z = 50 W 100 nF 75 W 150 W 150 W 50 W 50 W VAC_REF Figure 9-5. LVPECL Clock Driver Connected to LMK1D1208I Input Figure 9-6 shows how to couple a LVCMOS clock input to the LMK1D1208I directly. LVCMOS (1.8/2.5/3.3 V) R S Z = 50 : LMK1D12XX V th V IH V IL 2 Figure 9-6. 1.8-V, 2.5-V, or 3.3-V LVCMOS Clock Driver Connected to LMK1D1208I Input For unused input, TI recommends grounding both input pins (INP, INN) using 1-kΩ resistors. Submit Document Feedback Copyright © 2023 Texas Instruments Incorporated Product Folder Links: LMK1D1208I 17 LMK1D1208I www.ti.com SNAS828A – FEBRUARY 2022 – REVISED JUNE 2023 9.4 Device Functional Modes The outputs of Bank 0 and Bank 1 can be one of three options: logic low, buffered IN0, or buffered IN1. These output types should only be attained by maintaining the register setting combination outlined in Table 9-3. The LMK1D1208I registers must be programmed within these possible logic states to ensure proper device functionality. Using the device outside the intended logic can result in degraded performance. Table 9-3. Register Control Logic Table BANKx OUTPUTS BANKx_IN_SEL BANKx_MUTE IN0_EN IN1_EN Logic low X 1 X X IN0 1 0 1 X IN1 0 0 X 1 9.4.1 Input Enable Control The LMK1D1208I allows for individual input channel enable or disable through the INx_EN register field. The inputs should be disabled when not in use to reduce the power consumption. Table 9-4 describes the control of this function. INx_EN is set by register 0x02 (R2). See R2 Register for more information on this register. Table 9-4. Input Control INx_EN ACTIVE CLOCK INPUT 0 INx_P, INx_N disabled 1 INx_P, INx_N enabled 9.4.2 Bank Input Selection Bank 0 and Bank 1 can choose between the two inputs to fanout four LVDS output pairs each. In the 2:1 input mux mode, each bank must select the same clock input to output eight identical clocks. With the dual bank mode, each bank can select a different clock input to distribute both inputs separately; this is analogous to having two 1:4 buffers. When operating in dual bank mode, TI recommends that Bank 0 not select IN1 and Bank 1 not select IN0 to avoid crosstalk and degraded performance. The BANKx_IN_SEL register field configures this function described in Table 9-5. BANKx_IN_SEL is set by register 0x02 (R2). See R2 Register for more information on this register. Table 9-5. Bank Input Selection BANKx_IN_SEL BANK CLOCK INPUT 0 BANKx selects IN1_P, IN1_N 1 BANKx selects IN0_P, IN0_N 9.4.3 Bank Mute Control Each bank, Bank 0 or Bank 1, can be individually muted such that the bank outputs are set to logic low (OUTx_P is low and OUTx_N is high). Table 9-6 describes the control of this function. The BANKx_MUTE register field is set by register 0x02 (R2). See R2 Register for more information on this register. Table 9-6. Bank Mute Control 18 BANKx_MUTE BANK CLOCK OUTPUTS 0 BANKx outputs selected INx 1 BANKx outputs logic low Submit Document Feedback Copyright © 2023 Texas Instruments Incorporated Product Folder Links: LMK1D1208I LMK1D1208I www.ti.com SNAS828A – FEBRUARY 2022 – REVISED JUNE 2023 9.4.4 Output Enable Control The outputs of the LMK1D1208I can be individually enabled or disabled through the OUTx_EN register field. The disabled state of the outputs is high impedance as this reduces the power consumption and also prevents back-biasing of the devices connected to these outputs. Unused outputs should be disabled to eliminate the need for a termination resistor. In the case of enabled unused outputs, TI recommends a 100-Ω termination for optimal performance. Table 9-7 describes the control of this function. OUTx_EN is set by register 0x00 (R0). See R0 Register for more information on this register. Table 9-7. Output Control OUTx_EN CLOCK OUTPUTS 0 OUTx_P, OUTx_N disabled in Hi-Z state 1 OUTx_P, OUTx_N enabled 9.4.5 Output Amplitude Selection The amplitude of the LMK1D1208I outputs can be individually programmed through the OUTx_AMP_SEL register field. The boosted LVDS swing mode can be used in applications which require a higher output swing for better noise performance (higher slew rate) or for swing requirements in the receiver that the standard LVDS swing cannot meet. Table 9-8 describes the control of this function. OUTx_AMP_SEL is set by register 0x01 (R1). See R1 Register for more information on this register. Table 9-8. Output Amplitude Selection Table OUTx_AMP_SEL OUTPUT AMPLITUDE (VOD) 0 Standard LVDS swing (350 mV) 1 Boosted LVDS swing (500 mV) Submit Document Feedback Copyright © 2023 Texas Instruments Incorporated Product Folder Links: LMK1D1208I 19 LMK1D1208I www.ti.com SNAS828A – FEBRUARY 2022 – REVISED JUNE 2023 9.5 Programming The LMK1D1208I uses I2C to program the states of its eight output drivers. See I2C for more information on the I2C features and address assignment, and Register Maps for the list of programmable registers. Table 9-9. Command Code Definition BIT DESCRIPTION 0 = Block Read or Block Write operation 1 = Byte Read or Byte Write operation 7 (6:0) Register address for Byte operations, or starting register address for Block, operations 1 S 7 Peripheral Address 1 R/W MSB LSB S Start Condition Sr Repeated Start Condition R/W 1 A 8 Data Byte MSB 1 A 1 P LSB 1 = Read (Rd); 0 = Write (Wr) A Acknowledge (ACK = 0 and NACK =1) P Stop Condition Controller-to-Peripheral Transmission Peripheral-to-Controller Transmission Figure 9-7. Generic Programming Sequence 1 S 7 Peripheral Address 1 Wr 1 A 8 CommandCode 1 A 8 Data Byte 1 A 1 P Figure 9-8. Byte Write Protocol 1 S 7 Peripheral Address 1 Wr 1 A 1 A 1 P 8 Data Byte 1 A 8 CommandCode 1 S 7 Peripheral Address 1 Rd 1 A 1 Figure 9-9. Byte Read Protocol 1 S 7 Peripheral Address 1 Wr 8 Data Byte 0 1 A 1 A 8 CommandCode 8 Data Byte 1 1 A 1 A 8 Byte Count = N 1 A 8 Data Byte N-1 … 1 A 1 P Figure 9-10. Block Write Protocol 1 S 7 Peripheral Address 1 Wr 8 Data Byte N 1 A 1 1 A 1 A 8 CommandCode 8 Data Byte 0 1 S 1 A 1 7 Peripheral Address 8 Data Byte N-1 1 Rd 1 A 1 A 1 P 1 Figure 9-11. Block Read Protocol 20 Submit Document Feedback Copyright © 2023 Texas Instruments Incorporated Product Folder Links: LMK1D1208I LMK1D1208I www.ti.com SNAS828A – FEBRUARY 2022 – REVISED JUNE 2023 9.6 Register Maps 9.6.1 LMK1D1208I Registers Table 9-10 lists the LMK1D1208I registers. All register locations not listed should be considered as reserved locations and the register contents should not be modified. TI highly suggests that the user only operates within the logic states listed in Table 9-3 for optimum performance. Table 9-10. LMK1D1208I Registers Address Acronym 0h R0 Output Enable Control Go 1h R1 Output Amplitude Control Go 2h R2 Input Enable and Bank Setting Control Go 5h R5 Device/Revision Identification Go R14 I2C Go Eh Register Fields Section Address Readback Complex bit access types are encoded to fit into small table cells. Table 9-11 shows the codes that are used for access types in this section. Table 9-11. LMK1D1208I Access Type Codes Access Type Code Description R Read W Write Read Type R Write Type W Reset or Default Value -n Reset/default value in hexadecimal 9.6.1.1 R0 Register (Address = 0h) [reset = 0h] R0 is shown in Table 9-12. The R0 register contains bits that enable or disable individual output clock channels [7:0]. Return to the Summary Table. Table 9-12. R0 Register Field Descriptions Bit Field Type Reset Description 7 OUT7_EN R/W 0h This bit controls the output enable signal for output channel OUT7_P/OUT7_N. 0h = Output Disabled (Hi-Z) 1h = Output Enabled 6 OUT6_EN R/W 0h This bit controls the output enable signal for output channel OUT6_P/OUT6_N. 0h = Output Disabled (Hi-Z) 1h = Output Enabled 5 OUT5_EN R/W 0h This bit controls the output enable signal for output channel OUT5_P/OUT5_N. 0h = Output Disabled (Hi-Z) 1h = Output Enabled 4 OUT4_EN R/W 0h This bit controls the output enable signal for output channel OUT4_P/OUT4_N. 0h = Output Disabled (Hi-Z) 1h = Output Enabled Submit Document Feedback Copyright © 2023 Texas Instruments Incorporated Product Folder Links: LMK1D1208I 21 LMK1D1208I www.ti.com SNAS828A – FEBRUARY 2022 – REVISED JUNE 2023 Table 9-12. R0 Register Field Descriptions (continued) Bit Field Type Reset Description 3 OUT3_EN R/W 0h This bit controls the output enable signal for output channel OUT3_P/OUT3_N. 0h = Output Disabled (Hi-Z) 1h = Output Enabled 2 OUT2_EN R/W 0h This bit controls the output enable signal for output channel OUT2_P/OUT2_N. 0h = Output Disabled (Hi-Z) 1h = Output Enabled 1 OUT1_EN R/W 0h This bit controls the output enable signal for output channel OUT1_P/OUT1_N. 0h = Output Disabled (Hi-Z) 1h = Output Enabled 0 OUT0_EN R/W 0h This bit controls the output enable signal for output channel OUT0_P/OUT0_N. 0h = Output Disabled (Hi-Z) 1h = Output Enabled 9.6.1.2 R1 Register (Address = 1h) [reset = 0h] R1 is shown in Table 9-13. The R1 register contains bits that set the output amplitude to a standard or boosted LVDS swing. Return to the Summary Table. Table 9-13. R1 Register Field Descriptions Bit 22 Field Type Reset Description 7 OUT7_AMP_SEL R/W 0h This bit sets the output amplitude for output channel OUT7_P/ OUT7_N. 0h = Standard LVDS Swing (350 mV) 1h = Boosted LVDS Swing (500 mV) 6 OUT6_AMP_SEL R/W 0h This bit sets the output amplitude for output channel OUT6_P/ OUT6_N. 0h = Standard LVDS Swing (350 mV) 1h = Boosted LVDS Swing (500 mV) 5 OUT5_AMP_SEL R/W 0h This bit sets the output amplitude for output channel OUT5_P/ OUT5_N. 0h = Standard LVDS Swing (350 mV) 1h = Boosted LVDS Swing (500 mV) 4 OUT4_AMP_SEL R/W 0h This bit sets the output amplitude for output channel OUT4_P/ OUT4_N. 0h = Standard LVDS Swing (350 mV) 1h = Boosted LVDS Swing (500 mV) 3 OUT3_AMP_SEL R/W 0h This bit sets the output amplitude for output channel OUT3_P/ OUT3_N. 0h = Standard LVDS Swing (350 mV) 1h = Boosted LVDS Swing (500 mV) 2 OUT2_AMP_SEL R/W 0h This bit sets the output amplitude for output channel OUT2_P/ OUT2_N. 0h = Standard LVDS swing (350 mV) 1h = Boosted LVDS swing (500 mV) Submit Document Feedback Copyright © 2023 Texas Instruments Incorporated Product Folder Links: LMK1D1208I LMK1D1208I www.ti.com SNAS828A – FEBRUARY 2022 – REVISED JUNE 2023 Table 9-13. R1 Register Field Descriptions (continued) Bit Field Type Reset Description 1 OUT1_AMP_SEL R/W 0h This bit sets the output amplitude for output channel OUT1_P/ OUT1_N. 0h = Standard LVDS Swing (350 mV) 1h = Boosted LVDS Swing (500 mV) 0 OUT0_AMP_SEL R/W 0h This bit sets the output amplitude for output channel OUT0_P/ OUT0_N. 0h = Standard LVDS Swing (350 mV) 1h = Boosted LVDS Swing (500 mV) 9.6.1.3 R2 Register (Address = 2h) [reset = F1h] R2 is shown in Table 9-14. The R2 register contains bits that enable/disable the input channels and control the banks. Return to the Summary Table. Table 9-14. R2 Register Field Descriptions Bit Field Type Reset Description 7 Reserved R/W 1h Register bit can be written to 1. Writing a different value than 1 will affect device functionality. 6 Reserved R/W 1h Register bit can be written to 1. Writing a different value than 1 will affect device functionality. 5 BANK1_IN_SEL R/W 1h This bit sets the input channel for Bank 1. 0h = IN1_P/IN1_N 1h = IN0_P/IN0_N 4 BANK0_IN_SEL R/W 1h This bit sets the input channel for Bank 0. 0h = IN1_P/IN1_N 1h = IN0_P/IN0_N 3 BANK1_MUTE R/W 0h This bit sets the outputs in Bank 1 to logic low level. 0h = INx_P/INx_N 1h = Logic low 2 BANK0_MUTE R/W 0h This bit sets the outputs in Bank 0 to logic low level. 0h = INx_P/INx_N 1h = Logic low 1 IN1_EN R/W 0h This bit controls the input enable signal for input channel IN1_P/ IN1_N. 0h = Input Disabled (reduces power consumption) 1h = Input Enabled 0 IN0_EN R/W 1h This bit controls the input enable signal for input channel IN0_P/ IN0_N. 0h = Input Disabled (reduces power consumption) 1h = Input Enabled Submit Document Feedback Copyright © 2023 Texas Instruments Incorporated Product Folder Links: LMK1D1208I 23 LMK1D1208I www.ti.com SNAS828A – FEBRUARY 2022 – REVISED JUNE 2023 9.6.1.4 R5 Register (Address = 5h) [reset = 20h] R5 is shown in Table 9-15. The R5 register contains the silicon revision code and the device identification code. Return to the Summary Table. Table 9-15. R5 Register Field Descriptions Bit Field Type Reset Description 7:4 REV_ID R 2h These bits provide the silicon revision code. 3:0 DEV_ID R 0h These bits provide the device identification code. 9.6.1.5 R14 Register (Address = Eh) [reset = 0h] R14 is shown in Table 9-16. The R14 register contains the bits that report the current state of the I2C address based on the IDX0 and IDX1 input pins. Return to the Summary Table. Table 9-16. R14 Register Field Descriptions 24 Bit Field Type Reset Description 7:0 IDX_RB R 0h These bits report the I2C address state. Submit Document Feedback Copyright © 2023 Texas Instruments Incorporated Product Folder Links: LMK1D1208I LMK1D1208I www.ti.com SNAS828A – FEBRUARY 2022 – REVISED JUNE 2023 10 Application and Implementation Note Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining suitability of components for their purposes, as well as validating and testing their design implementation to confirm system functionality. 10.1 Application Information The LMK1D1208I is a low-additive jitter universal to LVDS fan-out buffer with two selectable inputs. The small package, low output skew, and low additive jitter make for a flexible device in demanding applications. 10.2 Typical Application 1.8V/ 2.5V/ 3.3V FPGA IN0_P 156.25 MHz LVDS from Backplane 100  IN0_N 50
50 CPU 100  156.25 MHz LVCMOS Oscillator IN1_P PHY 2.5V 1 k 100  IN1_N 1 k ASIC SDA 100  SCL IDX1 IDX0 Figure 10-1. Fan-Out Buffer for Line Card Application Submit Document Feedback Copyright © 2023 Texas Instruments Incorporated Product Folder Links: LMK1D1208I 25 LMK1D1208I www.ti.com SNAS828A – FEBRUARY 2022 – REVISED JUNE 2023 10.2.1 Design Requirements The LMK1D1208I shown in Figure 10-1 is configured to select two inputs: a 156.25-MHz LVDS clock from the backplane at IN0, or a secondary 156.25-MHz LVCMOS 2.5-V oscillator at IN1. The LVDS clock is AC-coupled and biased using the integrated reference voltage generator. A resistor divider is used to set the threshold voltage correctly for the LVCMOS clock. 0.1-µF capacitors are used to reduce noise on both VAC_REF and IN1_N. Either input signal can be then fanned out to desired devices via register control. The configuration example is driving four LVDS receivers in a line card application with the following properties: • The PHY device is capable of DC coupling with an LVDS driver such as the LMK1D1208I. This PHY device features internal termination so no additional components are required for proper operation • The ASIC LVDS receiver features internal termination and operates at the same common-mode voltage as the LMK1D1208I. Again, no additional components are required. • The FPGA requires external AC coupling, but has internal termination. 0.1-µF capacitors are placed to provide AC coupling. Similarly, the CPU is internally terminated, and requires only external AC-coupling capacitors. • The unused outputs of the LMK1D1208I can be disabled by clearing the corresponding OUTx_EN register through I2C. This results in a lower power consumption. 10.2.2 Detailed Design Procedure See Input Termination for proper input terminations, dependent on single-ended or differential inputs. See LVDS Output Termination for output termination schemes depending on the receiver application. Unused outputs should be terminated differentially with a 100-Ω resistor or disabled through OUTx_EN register control (see Table 9-7) for optimum performance. Outputs may be left unterminated, but will result in slight degradation in performance (Output AC common-mode VOS ) in the outputs being used. In this example, the PHY, ASIC, and FPGA or CPU require different schemes. Power-supply filtering and bypassing is critical for low-noise applications. See Power Supply Recommendations for recommended filtering techniques. A reference layout is provided in Low-Additive Jitter, Four LVDS Outputs Clock Buffer Evaluation Board (SCAU043). 26 Submit Document Feedback Copyright © 2023 Texas Instruments Incorporated Product Folder Links: LMK1D1208I LMK1D1208I www.ti.com SNAS828A – FEBRUARY 2022 – REVISED JUNE 2023 10.2.3 Application Curves The following graphs show the low additive noise of the LMK1D1208I. The low noise 156.25-MHz source with 24-fs RMS jitter shown in Figure 10-2 drives the LMK1D1208I, resulting in 46.4-fs RMS when integrated from 12 kHz to 20 MHz (Figure 10-3). The resultant additive jitter is a low 39.7-fs RMS for this configuration. Reference signal is low-noise Rohde and Schwarz SMA100B Figure 10-2. LMK1D1208I Reference Phase Noise, 156.25 MHz, 24-fs RMS (12 kHz to 20 MHz) Figure 10-3. LMK1D1208I Output Phase Noise, 156.25 MHz, 46.4-fs RMS (12 kHz to 20 MHz) Submit Document Feedback Copyright © 2023 Texas Instruments Incorporated Product Folder Links: LMK1D1208I 27 LMK1D1208I www.ti.com SNAS828A – FEBRUARY 2022 – REVISED JUNE 2023 Figure 10-4 shows the low close-in phase noise of the LMK1D1208I device. The LMK1D1208I has excellent flicker noise as a result of superior process technology and design. This enables their use for clock distribution in radar systems, medical imaging systems etc which require ultra-low close-in phase noise clocks. Figure 10-4. LMK1D1208I Output Phase Noise, 100 MHz, 1-kHz Offset: –147 dBc/Hz 10.3 Power Supply Recommendations High-performance clock buffers are sensitive to noise on the power supply, which can dramatically increase the additive jitter of the buffer. Thus, it is essential to reduce noise from the system power supply, especially when jitter or phase noise is critical to applications. Filter capacitors are used to eliminate the low-frequency noise from the power supply, where the bypass capacitors provide the low impedance path for high-frequency noise and guard the power-supply system against the induced fluctuations. These bypass capacitors also provide instantaneous current surges as required by the device and must have low equivalent series resistance (ESR). To properly use the bypass capacitors, they must be placed close to the power-supply pins and laid out with short loops to minimize inductance. TI recommends adding as many high-frequency (for example, 0.1-µF) bypass capacitors as there are supply pins in the package. TI recommends, but does not require, inserting a ferrite bead between the board power supply and the chip power supply that isolates the high-frequency switching noises generated by the clock driver. These beads prevent the switching noise from leaking into the board supply. Choose an appropriate ferrite bead with low DC resistance, because it is imperative to provide adequate isolation between the board supply and the chip supply, as well as to maintain a voltage at the supply pins that is greater than the minimum voltage required for proper operation. Figure 10-5 shows this recommended power-supply decoupling method. 28 Submit Document Feedback Copyright © 2023 Texas Instruments Incorporated Product Folder Links: LMK1D1208I LMK1D1208I www.ti.com SNAS828A – FEBRUARY 2022 – REVISED JUNE 2023 Board Supply Chip Supply Ferrite Bead 1 µF 10µF 0.1 µF (x3) Figure 10-5. Power Supply Decoupling 10.4 Layout 10.4.1 Layout Guidelines For reliability and performance reasons, the die temperature must be limited to a maximum of 135°C. The device package has an exposed pad that provides the primary heat removal path to the printed circuit board (PCB). To maximize the heat dissipation from the package, a thermal landing pattern including multiple vias to a ground plane must be incorporated into the PCB within the footprint of the package. The thermal pad must be soldered down to ensure adequate heat conduction to of the package. Figure 10-6 and Figure 10-7 show the LMK1D1208I top and bottom PCB layer examples. 10.4.2 Layout Example Figure 10-6. Recommended PCB Layout, Top Layer Submit Document Feedback Copyright © 2023 Texas Instruments Incorporated Product Folder Links: LMK1D1208I 29 LMK1D1208I www.ti.com SNAS828A – FEBRUARY 2022 – REVISED JUNE 2023 Figure 10-7. Recommended PCB Layout Bottom Layer 30 Submit Document Feedback Copyright © 2023 Texas Instruments Incorporated Product Folder Links: LMK1D1208I LMK1D1208I www.ti.com SNAS828A – FEBRUARY 2022 – REVISED JUNE 2023 11 Device and Documentation Support 11.1 Documentation Support 11.1.1 Related Documentation For related documentation see the following: • Texas Instruments, Power Consumption of LVPECL and LVDS Analog Design Journal • Texas Instruments, Semiconductor and IC Package Thermal Metrics application note • Texas Instruments, Using Thermal Calculation Tools for Analog Components application note 11.2 Receiving Notification of Documentation Updates To receive notification of documentation updates, navigate to the device product folder on ti.com. Click on Subscribe to updates to register and receive a weekly digest of any product information that has changed. For change details, review the revision history included in any revised document. 11.3 Support Resources TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straight from the experts. Search existing answers or ask your own question to get the quick design help you need. Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of Use. 11.4 Trademarks TI E2E™ is a trademark of Texas Instruments. All trademarks are the property of their respective owners. 11.5 Electrostatic Discharge Caution This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications. 11.6 Glossary TI Glossary This glossary lists and explains terms, acronyms, and definitions. 12 Mechanical, Packaging, and Orderable Information The following pages include mechanical, packaging, and orderable information. This information is the most current data available for the designated devices. This data is subject to change without notice and revision of this document. For browser-based versions of this data sheet, refer to the left-hand navigation. Submit Document Feedback Copyright © 2023 Texas Instruments Incorporated Product Folder Links: LMK1D1208I 31 LMK1D1208I www.ti.com SNAS828A – FEBRUARY 2022 – REVISED JUNE 2023 12.1 Package Option Addendum Packaging Information Orderable Device Status(1) Package Type Package Drawing Pins Package Qty Eco Plan(2) LMK1D1208IR HAR ACTIVE VQFN RHA 40 2500 Green (RoHS& NIPDAU no Sb/Br) Level-2-260C-1 -40 to 85 YEAR LMK1D1208I LMK1D1208IR HAT ACTIVE VQFN RHA 40 250 Green (RoHS& NIPDAU no Sb/Br) Level-2-260C-1 -40 to 85 YEAR LMK1D1208I (1) Lead/Ball Finish(6) MSL Peak Temp(3) Op Temp (°C) Device Marking(4) (5) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PRE_PROD Unannounced device, not in production, not available for mass market, nor on the web, samples not available. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material). (3) (4) (5) (6) 32 MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. Multiple Device markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device. Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish value exceeds the maximum column width. Submit Document Feedback Copyright © 2023 Texas Instruments Incorporated Product Folder Links: LMK1D1208I LMK1D1208I www.ti.com SNAS828A – FEBRUARY 2022 – REVISED JUNE 2023 Important Information and Disclaimer: The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. Submit Document Feedback Copyright © 2023 Texas Instruments Incorporated Product Folder Links: LMK1D1208I 33 LMK1D1208I www.ti.com SNAS828A – FEBRUARY 2022 – REVISED JUNE 2023 12.2 Tape and Reel Information REEL DIMENSIONS TAPE DIMENSIONS K0 P1 B0 W Reel Diameter Cavity A0 B0 K0 W P1 A0 Dimension designed to accommodate the component width Dimension designed to accommodate the component length Dimension designed to accommodate the component thickness Overall width of the carrier tape Pitch between successive cavity centers Reel Width (W1) QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE Sprocket Holes Q1 Q2 Q1 Q2 Q3 Q4 Q3 Q4 User Direction of Feed Pocket Quadrants 34 Device Package Type Package Drawing Pins SPQ Reel Diameter (mm) Reel Width W1 (mm) A0 (mm) B0 (mm) K0 (mm) P1 (mm) W (mm) Pin1 Quadrant LMK1D1208IRHAR VQFN RHA 40 2500 330.0 16.4 6.3 6.3 1.1 12.0 13.3 Q2 LMK1D1208IRHAT VQFN RHA 40 250 180.0 16.4 6.3 6.3 1.1 12.0 13.3 Q2 Submit Document Feedback Copyright © 2023 Texas Instruments Incorporated Product Folder Links: LMK1D1208I LMK1D1208I www.ti.com SNAS828A – FEBRUARY 2022 – REVISED JUNE 2023 TAPE AND REEL BOX DIMENSIONS Width (mm) W L H Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) LMK1D1208IRHAR VQFN RHA 40 2500 367.0 367.0 35.0 LMK1D1208IRHAT VQFN RHA 40 250 210.0 185.0 35.0 Submit Document Feedback Copyright © 2023 Texas Instruments Incorporated Product Folder Links: LMK1D1208I 35 PACKAGE OPTION ADDENDUM www.ti.com 10-Apr-2023 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan (2) Lead finish/ Ball material MSL Peak Temp Op Temp (°C) Device Marking (3) Samples (4/5) (6) LMK1D1208IRHAR ACTIVE VQFN RHA 40 2500 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 105 LMK1D 1208I Samples LMK1D1208IRHAT ACTIVE VQFN RHA 40 250 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 105 LMK1D 1208I Samples (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of