LMK1D2106, LMK1D2108
SNAS829A – OCTOBER 2021 – REVISED JANUARY 2022
LMK1D210x Low Additive Jitter LVDS Buffer
1 Features
3 Description
•
The LMK1D210x clock buffer distributes two clock
inputs (IN0 and IN1) to a total of 16 pairs of
differential LVDS clock outputs (OUT0 to OUT15) in
the LMK1D2108 and 12 pairs of clock outputs (OUT0
to OUT11) in the LMK1D2106 with minimum skew
for clock distribution. Each buffer block consists of
one input and a maximum of 6 (LMK1D2106) or 8
(LMK1D2108) LVDS outputs. The inputs can either be
LVDS, LVPECL, HCSL, CML, or LVCMOS.
•
•
•
•
•
•
•
•
•
•
•
High-performance LVDS clock buffer family: up to
2 GHz
– Dual 1:6 differential buffer
– Dual 1:8 differential buffer
Supply voltage: 1.71 V to 3.465 V
Low additive jitter: < 60 fs RMS maximum in 12kHz to
20-MHz at 156.25 MHz
– Very low phase noise floor: -164 dBc/Hz
(typical)
Very low propagation delay: < 575 ps maximum
Output skew: 20 ps maximum
High-swing LVDS (boosted mode): 500-mV VOD
typical when AMP_SEL = 1
Bank enable/disable using the EN pin
Fail-safe input operation
Universal inputs accept LVDS, LVPECL, LVCMOS,
HCSL and CML signal levels
LVDS reference voltage, VAC_REF, available for
capacitive-coupled inputs
Industrial temperature range: –40°C to 105°C
Packaged in
– LMK1D2106: 6-mm × 6-mm, 40-pin VQFN
(RHA)
– LMK1D2108: 7-mm × 7-mm, 48-pin VQFN
(RGZ)
2 Applications
•
•
•
•
•
Telecommunications and networking
Medical imaging
Test and measurement
Wireless infrastructure
Pro audio, video and signage
The LMK1D210x is specifically designed for driving
50-Ω transmission lines. When driving inputs in
single-ended mode, apply the appropriate bias
voltage to the unused negative input pin (see Figure
8-6).
Using the control pin (EN), output banks can either be
enable or disabled. If this pin is left open, both bank
outputs are enabled. If the control pin is switched to a
logic "0", both bank outputs are disabled (static logic
"0"). If the control pin is switched to a logic "1", the
outputs of one bank are disabled while the outputs of
the other bank are enabled. The part also supports a
fail-safe function. The device further incorporates an
input hysteresis which prevents random oscillation of
the outputs in the absence of an input signal.
The device operates in a 1.8-V, 2.5-V, or 3.3-V
supply environment and is characterized from –40°C
to 105°C (ambient temperature).
Device Information
PART
NUMBER(1)
BODY SIZE (NOM)
VQFN (40)
6.00 mm × 6.00 mm
LMK1D2108
VQFN (48)
7.00 mm × 7.00 mm
(1)
For all available packages, see the orderable addendum at
the end of the data sheet.
491.52 MHz
EN
PACKAGE
LMK1D2106
AFE DEVICE
CLOCK
LMK1D21XX
LVDS Buffer
7.68 MHz
AFE
AFE SYSREF
CLOCK
Application Example
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
LMK1D2106, LMK1D2108
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SNAS829A – OCTOBER 2021 – REVISED JANUARY 2022
Table of Contents
1 Features............................................................................1
2 Applications..................................................................... 1
3 Description.......................................................................1
4 Revision History.............................................................. 2
5 Pin Configuration and Functions...................................3
6 Specifications.................................................................. 4
6.1 Absolute Maximum Ratings........................................ 4
6.2 ESD Ratings............................................................... 4
6.3 Recommended Operating Conditions.........................5
6.4 Thermal Information....................................................5
6.5 Electrical Characteristics.............................................5
6.6 Typical Characteristics................................................ 9
7 Parameter Measurement Information.......................... 12
8 Detailed Description......................................................14
8.1 Overview................................................................... 14
8.2 Functional Block Diagram......................................... 14
8.3 Feature Description...................................................15
8.4 Device Functional Modes..........................................15
9 Application and Implementation.................................. 18
9.1 Application Information............................................. 18
9.2 Typical Application.................................................... 18
10 Power Supply Recommendations..............................22
11 Layout........................................................................... 23
11.1 Layout Guidelines................................................... 23
11.2 Layout Examples.....................................................23
12 Device and Documentation Support..........................24
12.1 Documentation Support.......................................... 24
12.2 Receiving Notification of Documentation Updates..24
12.3 Support Resources................................................. 24
12.4 Trademarks............................................................. 24
12.5 Electrostatic Discharge Caution..............................24
12.6 Glossary..................................................................24
13 Mechanical, Packaging, and Orderable
Information.................................................................... 24
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision * (October 2021) to Revision A (January 2022)
Page
• Added Fail-safe input operation to the Features ................................................................................................1
• Added Fail-Safe Input section...........................................................................................................................15
2
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SNAS829A – OCTOBER 2021 – REVISED JANUARY 2022
V
DDB
31
V
DDA
OUT8_P
32
19
OUT3_N
33
18
OUT3_P
OUT9_P
34
17
OUT9_N
35
OUT10_P
OUT6_P
OUT5_N
OUT5_P
26
25
OUT6_N
28
27
OUT7_N
OUT7_P
29
OUT8_P
31
30
OUT9_P
OUT8_N
32
OUT9_N
34
33
OUT10_N
OUT10_P
GND
37
24
V
OUT11_P
38
23
OUT4_N
DDB
OUT8_N
35
OUT4_P
22
21
V
20
36
OUT5_P
OUT4_N
23
OUT5_N
25
24
OUT6_N
OUT6_P
28
26
OUT7_P
29
27
GND
OUT7_N
30
5 Pin Configuration and Functions
DDA
OUT11_N
39
22
OUT4_P
OUT12_P
40
21
OUT3_N
OUT2_N
OUT12_N
41
20
OUT3_P
16
OUT2_P
OUT13_P
42
19
OUT2_N
36
15
OUT1_N
OUT13_N
43
18
OUT2_P
OUT10_N
37
14
OUT1_P
OUT14_P
44
17
OUT1_N
OUT11_P
38
13
OUT0_N
OUT14_N
45
16
OUT1_P
OUT11_N
39
12
OUT0_P
OUT15_P
46
15
OUT0_N
OUT15_N
47
14
OUT0_P
48
13
V
Figure 5-1. LMK1D2106: RHA Package 40-Pin
VQFN Top View
3
4
5
6
7
8
9
10
11
12
V
AC_REF1
V
DDB
V
DDA
V
AC_REF0
IN0_P
IN0_N
AMP_SEL
GND
Not to scale
IN1_P
9
IN0_N
IN1_N
8
IN0_P
DDB
1
7
V
2
6
V
DDA
V
AC_REF0
EN
5
V
DDB
DAP
GND
4
DDA
10
3
IN1_N
V
AC_REF1
V
AMP_SEL
1
2
11
EN
40
IN1_P
V
DDB
DAP
DDA
Not to scale
Figure 5-2. LMK1D2108: RGZ Package 48-Pin
VQFN Top View
Table 5-1. Pin Functions
PIN
NAME
LMK1D2106
LMK1D2108
TYPE(1)
DESCRIPTION
DIFFERENTIAL/SINGLE-ENDED CLOCK INPUT
IN0_P, IN0_N
8, 9
9, 10
I
Primary: Differential input pair or single-ended input
IN1_P, IN1_N
2, 3
3, 4
I
1
2
I
Output bank enable/disable with an internal 500-kΩ pullup and
320-kΩ pulldown. See Table 8-2.
10
11
I
Output amplitude swing select with an internal 500-kΩ pullup and
320-kΩ pulldown. See Table 8-3.
7, 4
8, 5
O
Bias voltage output for capacitive coupled inputs. If used, TI
recommends using a 0.1-µF capacitor to GND on this pin.
Secondary: Differential input pair or single-ended input
Note that INP0, INN0 are used indistinguishably with IN0_P,
IN0_N.
BANK ENABLE
EN
AMPLITUDE SELECT
AMP_SEL
BIAS VOLTAGE OUTPUT
VAC_REF0,VAC_REF1
DIFFERENTIAL CLOCK OUTPUT
OUT0_P, OUT0_N
12, 13
14, 15
O
Differential LVDS output pair number 0
OUT1_P, OUT1_N
14, 15
16, 17
O
Differential LVDS output pair number 1
OUT2_P, OUT2_N
16, 17
18, 19
O
Differential LVDS output pair number 2
OUT3_P, OUT3_N
18, 19
20, 21
O
Differential LVDS output pair number 3
OUT4_P, OUT4_N
22, 23
22, 23
O
Differential LVDS output pair number 4
OUT5_P, OUT5_N
24, 25
25, 26
O
Differential LVDS output pair number 5
OUT6_P, OUT6_N
26, 27
27, 28
O
Differential LVDS output pair number 6
OUT7_P, OUT7_N
28, 29
29, 30
O
Differential LVDS output pair number 7
OUT8_P, OUT8_N
32, 33
31, 32
O
Differential LVDS output pair number 8
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Table 5-1. Pin Functions (continued)
PIN
NAME
TYPE(1)
DESCRIPTION
LMK1D2106
LMK1D2108
OUT9_P, OUT9_N
34, 35
33, 34
O
Differential LVDS output pair number 9
OUT10_P, OUT10_N
36, 37
35, 36
O
Differential LVDS output pair number 10
OUT11_P, OUT11_N
38, 39
38, 39
O
Differential LVDS output pair number 11
OUT12_P, OUT12_N
—
40, 41
O
Differential LVDS output pair number 12
OUT13_P, OUT13_N
—
42, 43
O
Differential LVDS output pair number 13
OUT14_P, OUT14_N
—
44, 45
O
Differential LVDS output pair number 14
OUT15_P, OUT15_N
—
46, 47
O
Differential LVDS output pair number 15
VDDA
6, 11, 20
7, 13, 24
P
Device power supply (1.8 V, 2.5 V, or 3.3 V) for Bank 0
VDDB
5, 31, 40
6, 37, 48
P
Device power supply (1.8 V, 2.5 V, or 3.3 V) for Bank 1
21, 30
1, 12
G
Ground
DAP
DAP
G
Die Attach Pad. Connect to the printed circuit board (PCB)
ground plane for heat dissipation.
SUPPLY VOLTAGE
GROUND
GND
MISC
DAP
(1)
G = Ground, I = Input, O = Output, P = Power
6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)(1)
MIN
MAX
VDD
Supply voltage
–0.3
3.6
V
VIN
Input voltage
–0.3
3.6
V
VO
Output voltage
–0.3
VDD + 0.3
V
IIN
Input current
–20
20
mA
IO
Continuous output current
–50
50
mA
TJ
Junction temperature
135
°C
Tstg
Storage temperature (2)
150
°C
(1)
(2)
–65
UNIT
Stresses beyond those listed under Absolute Maximum Rating may cause permanent damage to the device. These are stress
ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated
under Recommended Operating Condition. Exposure to absolute-maximum-rated conditions for extended periods may affect device
reliability.
Device unpowered
6.2 ESD Ratings
VALUE
V(ESD)
(1)
(2)
4
Electrostatic discharge
Human body model (HBM), per ANSI/ESDA/
JEDEC JS-001, all pins(1)
±3000
Charged device model (CDM), per ANSI/ESDA/
JEDEC JS-002, all pins(2)
±1000
UNIT
V
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
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6.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
VDD
Core supply voltage
Supply
Ramp
Supply voltage ramp
TA
TJ
MIN
NOM
MAX
3.3-V supply
3.135
3.3
3.465
2.5-V supply
2.375
2.5
2.625
1.8-V supply
1.71
1.8
1.89
Requires monotonic ramp (10-90 % of
VDD)
UNIT
V
0.1
20
ms
Operating free-air temperature
–40
105
°C
Operating junction temperature
–40
135
°C
6.4 Thermal Information
THERMAL METRIC(1)
LMK1D2106
LMK1D2108
RHA (VQFN)
RGZ (VQFN)
UNIT
40 PINS
48 PINS
RθJA
Junction-to-ambient thermal resistance
30.3
30.5
°C/W
RθJC(top)
Junction-to-case (top) thermal resistance
21.6
21.2
°C/W
RθJB
Junction-to-board thermal resistance
13.1
12.9
°C/W
ΨJT
Junction-to-top characterization parameter
0.4
0.4
°C/W
ΨJB
Junction-to-board characterization parameter
13
12.8
°C/W
RθJC(bot)
Junction-to-case (bottom) thermal resistance
4.5
4.5
°C/W
(1)
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
6.5 Electrical Characteristics
VDD = 1.8 V ± 5 %, –40°C ≤T_A ≤ 105°C. Typical values are at VDD = 1.8 V, 25°C (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
POWER SUPPLY CHARACTERISTICS
IDDSTAT
All outputs enabled and
Core supply current, static (LMK1D2106) unterminated, f = 0 Hz, AMP_SEL
= Open (default)
75
mA
IDDSTAT
All outputs enabled and
Core supply current, static (LMK1D2108) unterminated, f = 0 Hz, AMP_SEL
= Open (default)
80
mA
IDD100M
Core supply current (LMK1D2106)
All outputs enabled, RL = 100 Ω,
f =100 MHz, AMP_SEL = Open
(default)
113
140
mA
IDD100M
Core supply current (LMK1D2108)
All outputs enabled, RL = 100 Ω,
f =100 MHz, AMP_SEL = Open
(default)
134
160
mA
IDDSTAT
All outputs enabled and
Core supply current, static (LMK1D2106) unterminated, f = 0 Hz, AMP_SEL
=1
75
mA
IDDSTAT
All outputs enabled and
Core supply current, static (LMK1D2108) unterminated, f = 0 Hz, AMP_SEL
=1
80
mA
IDD100M
Core supply current (LMK1D2106)
All outputs enabled, RL = 100 Ω, f
=100 MHz, AMP_SEL = 1
130
IDD100M
Core supply current (LMK1D2108)
All outputs enabled, RL = 100 Ω, f
=100 MHz, AMP_SEL = 1
165
mA
185
mA
EN/AMP_SEL CONTROL INPUT CHARACTERISTICS (Applies to VDD = 1.8 V ± 5%, 2.5 V ± 5% and 3.3 V ± 5%)
VdI3
Tri-state input
Open
0.4 × VCC
V
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VDD = 1.8 V ± 5 %, –40°C ≤T_A ≤ 105°C. Typical values are at VDD = 1.8 V, 25°C (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
0.7 × VCC
VCC + 0.3
V
–0.3
0.3 × VCC
V
30
µA
VIH
Input high voltage
Minimum input voltage for a
logical "1" state in table 1
VIL
Input low voltage
Maximum input voltage for a
logical "0" state in table 1
IIH
Input high current
VDD can be 1.8V, 2.5V, or 3.3V
with VIH = VDD
IIL
Input low current
VDD can be 1.8V, 2.5V, or 3.3V
with VIH = VDD
Rpull-up
Input pullup resistor
500
kΩ
Rpull-down
Input pulldown resistor
320
kΩ
–30
µA
SINGLE-ENDED LVCMOS/LVTTL CLOCK INPUT (Applies to VDD = 1.8 V ± 5%, 2.5 V ± 5% and 3.3 V ± 5%)
fIN
Input frequency
Clock input
DC
250
VIN_S-E
Single-ended Input Voltage Swing
Assumes a square wave input
with two levels
0.4
3.465
dVIN/dt
Input Slew Rate (20% to 80% of the
amplitude)
IIH
Input high current
VDD = 3.465 V, VIH = 3.465 V
IIL
Input low current
VDD = 3.465 V, VIL = 0 V
CIN_SE
Input capacitance
at 25°C
0.05
MHz
V
V/ns
60
–30
µA
µA
3.5
pF
DIFFERENTIAL CLOCK INPUT (Applies to VDD = 1.8 V ± 5%, 2.5 V ± 5% and 3.3 V ± 5%)
fIN
Input frequency
Clock input
2
VIN,DIFF(p-p)
Differential input voltage peak-to-peak {2
× (VINP – VINN)}
VICM = 1 V (VDD = 1.8 V)
0.3
2.4
VICM = 1.25 V (VDD = 2.5 V/3.3 V)
0.3
2.4
VICM
Input common-mode voltage
VIN,DIFF(P-P) > 0.4 V (VDD = 1.8
V/2.5 V/3.3 V)
0.25
2.3
V
IIH
Input high current
VDD = 3.465 V, VINP = 2.4 V, VINN
= 1.2 V
30
µA
IIL
Input low current
VDD = 3.465 V, VINP = 0 V, VINN =
1.2 V
CIN_SE
Input capacitance (Single-ended)
at 25°C
–30
GHz
VPP
µA
3.5
pF
LVDS DC OUTPUT CHARACTERISTICS
|VOD|
Differential output voltage magnitude |
VOUTP - VOUTN|
VIN,DIFF(P-P) = 0.3 V, RLOAD = 100
Ω
250
350
450
mV
|VOD|
Differential output voltage magnitude |
VOUTP - VOUTN|
VIN,DIFF(P-P) = 0.3 V, RLOAD = 100
Ω, AMP_SEL = 1
400
500
650
mV
ΔVOD
Change in differential output voltage
magnitude
VIN,DIFF(P-P) = 0.3 V, RLOAD = 100
Ω
–15
15
mV
ΔVOD
Change in differential output voltage
magnitude
VIN,DIFF(P-P) = 0.3 V, RLOAD = 100
Ω, AMP_SEL = 1
–20
20
mV
VIN,DIFF(P-P) = 0.3 V, RLOAD = 100
Ω (VDD = 1.8 V)
1
1.2
VOC(SS)
Steady-state, common-mode output
voltage
VIN,DIFF(P-P) = 0.3 V, RLOAD = 100
Ω (VDD = 2.5 V/3.3 V)
1.1
1.375
VIN,DIFF(P-P) = 0.3 V, RLOAD = 100 Ω
(VDD = 1.8 V), AMP_SEL = 1
0.8
1.05
VIN,DIFF(P-P) = 0.3 V, RLOAD = 100 Ω
(VDD = 2.5 V/3.3 V), AMP_SEL = 1
0.9
1.15
VOC(SS)
6
Steady-state, common-mode output
voltage
V
V
ΔVOC(SS)
Change in steady-state, common-mode
output voltage
VIN,DIFF(P-P) = 0.3 V, RLOAD = 100
Ω
–15
15
mV
ΔVOC(SS)
Change in steady-state, common-mode
output voltage
VIN,DIFF(P-P) = 0.3 V, RLOAD = 100
Ω, AMP_SEL = 1
–20
20
mV
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VDD = 1.8 V ± 5 %, –40°C ≤T_A ≤ 105°C. Typical values are at VDD = 1.8 V, 25°C (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
0.1
VOD
LVDS AC OUTPUT CHARACTERISTICS
Vring
Output overshoot and undershoot
VIN,DIFF(P-P) = 0.3 V, RLOAD = 100
Ω, fOUT = 491.52 MHz
VOS
Output AC common-mode voltage
VIN,DIFF(P-P) = 0.3 V, RLOAD = 100
Ω
50
100
mVpp
VOS
Output AC common-mode voltage
VIN,DIFF(P-P) = 0.3 V, RLOAD = 100
Ω, AMP_SEL = 1
75
150
mVpp
IOS
Short-circuit output current (differential)
VOUTP = VOUTN
–12
12
mA
IOS(cm)
Short-circuit output current (commonmode)
VOUTP = VOUTN = 0
–24
24
mA
tPD
Propagation delay
VIN,DIFF(P-P) = 0.3 V, RLOAD = 100
Ω (1)
0.3
0.575
ns
tSK, O
Output skew
Skew between outputs with the
same load conditions (12 and 16
channels) (2)
20
ps
tSK, b
Output bank skew
Skew between the outputs within
the same bank (2106/2108) (3)
17.5
ps
tSK, PP
Part-to-part skew
Skew between outputs on
different parts subjected to the
same operating conditions with
the same input and output
loading.
200
ps
tSK, P
Pulse skew
20
ps
60
fs, RMS
tRJIT(ADD)
50% duty cycle input, crossing
point-to-crossing-point distortion
(4)
–20
fIN = 156.25 MHz with 50% dutycycle, Input slew rate = 1.5V/ns,
Integration range = 12 kHz to 20
MHz, with output load RLOAD =
100 Ω
Random additive Jitter (rms)
Phase Noise for a carrier frequency of
156.25 MHz with 50% duty-cycle, Input
Phase noise
slew rate = 1.5V/ns with output load
RLOAD = 100 Ω
SPUR
–0.1
Spurious suppression between dual
banks
45
PN1kHz
–143
PN10kHz
–150
PN100kHz
–157
PN1MHz
–160
PNfloor
–164
FIN0 = 491.52 MHz, FIN1 =
61.44 MHz; Measured between
neighboring outputs
–60
FIN0 = 491.52 MHz, FIN1 =
15.36 MHz; Measured between
neighboring outputs
–70
ODC
Output duty cycle
With 50% duty cycle input
tR/tF
Output rise and fall time
tR/tF
VAC_REF
dBc/Hz
dB
45
55
%
20% to 80% with RLOAD = 100 Ω
300
ps
Output rise and fall time
20% to 80% with RLOAD = 100 Ω
(AMP_SEL= 1)
300
ps
Reference output voltage
VDD = 2.5 V, ILOAD = 100 μA
1.375
V
0.9
1.25
POWER SUPPLY NOISE REJECTION (PSNR) VDD = 2.5 V/ 3.3 V
PSNR
(1)
(2)
(3)
Power Supply Noise Rejection (fcarrier =
156.25 MHz)
10 kHz, 100 mVpp ripple injected
on VDD
–70
1 MHz, 100 mVpp ripple injected
on VDD
–50
dBc
Measured between single-ended/differential input crossing point to the differential output crossing point.
For the dual bank devices, the inputs are phase aligned and have 50% duty cycle.
Applies to the dual bank family.
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(4)
8
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Defined as the magnitude of the time difference between the high-to-low and low-to-high propagation delay times at an output.
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6.6 Typical Characteristics
Figure 6-1 (LMK1D2106) and Figure 6-3 (LMK1D2108) capture the variation of the current consumption with input frequency
and supply voltage when AMP_SEL = 0. Figure 6-2 (LMK1D2106) and Figure 6-4 (LMK1D2108) show the current
consumption variation when AMP_SEL = 1. Figure 6-5 and Figure 6-6 portray the variation of the differential output voltage
(VOD) swept across frequency.
190
185
180
175
170
Current Consumption (mA)
165
160
155
150
145
140
135
130
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
125
120
115
110
0
100
200
300
400
500
600
700
800
=
=
=
=
=
=
=
=
=
1.8
1.8
1.8
2.5
2.5
2.5
3.3
3.3
3.3
V, TA = -40
V, TA = 25
V,TA = 105
V, TA = -40
V, TA = 25
V,TA = 105
V, TA = -40
V, TA = 25
V,TA =105
900 1000 1100 1200 1300 1400 1500 1600 1700 1800 1900 2000
Frequency (MHz)
Figure 6-1. LMK1D2106 Current Consumption vs. Frequency, AMP_SEL = 0
210
205
200
195
190
Current Consumption (mA)
185
180
175
170
165
160
155
150
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
145
140
135
130
125
0
100
200
300
400
500
600
700
800
=
=
=
=
=
=
=
=
=
1.8
1.8
1.8
2.5
2.5
2.5
3.3
3.3
3.3
V, TA = -40
V, TA = 25
V,TA = 105
V, TA = -40
V, TA = 25
V,TA = 105
V, TA = -40
V, TA = 25
V,TA =105
900 1000 1100 1200 1300 1400 1500 1600 1700 1800 1900 2000
Frequency (MHz)
Figure 6-2. LMK1D2106 Current Consumption vs. Frequency, AMP_SEL = 1
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6.6 Typical Characteristics
Figure 6-1 (LMK1D2106) and Figure 6-3 (LMK1D2108) capture the variation of the current consumption with input frequency
and supply voltage when AMP_SEL = 0. Figure 6-2 (LMK1D2106) and Figure 6-4 (LMK1D2108) show the current
consumption variation when AMP_SEL = 1. Figure 6-5 and Figure 6-6 portray the variation of the differential output voltage
(VOD) swept across frequency.
235
230
225
220
215
210
205
Current Consumption (mA)
200
195
190
185
180
175
170
165
160
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
155
150
145
140
135
130
0
100
200
300
400
500
600
700
800
=
=
=
=
=
=
=
=
=
1.8
1.8
1.8
2.5
2.5
2.5
3.3
3.3
3.3
V, TA = -40
V, TA = 25
V,TA = 105
V, TA = -40
V, TA = 25
V,TA = 105
V, TA = -40
V, TA = 25
V,TA =105
900 1000 1100 1200 1300 1400 1500 1600 1700 1800 1900 2000
Frequency (MHz)
Figure 6-3. LMK1D2108 Current Consumption vs. Frequency, AMP_SEL = 0
260
255
250
245
240
235
230
Current Consumption (mA)
225
220
215
210
205
200
195
190
185
180
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
175
170
165
160
155
150
0
100
200
300
400
500
600
700
800
=
=
=
=
=
=
=
=
=
1.8
1.8
1.8
2.5
2.5
2.5
3.3
3.3
3.3
V, TA = -40
V, TA = 25
V,TA = 105
V, TA = -40
V, TA = 25
V,TA = 105
V, TA = -40
V, TA = 25
V,TA =105
900 1000 1100 1200 1300 1400 1500 1600 1700 1800 1900 2000
Frequency (MHz)
Figure 6-4. LMK1D2108 Current Consumption vs. Frequency, AMP_SEL = 1
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6.6 Typical Characteristics
Figure 6-1 (LMK1D2106) and Figure 6-3 (LMK1D2108) capture the variation of the current consumption with input frequency
and supply voltage when AMP_SEL = 0. Figure 6-2 (LMK1D2106) and Figure 6-4 (LMK1D2108) show the current
consumption variation when AMP_SEL = 1. Figure 6-5 and Figure 6-6 portray the variation of the differential output voltage
(VOD) swept across frequency.
400
VDD = 1.8 V, TA = -40
VDD = 1.8 V, TA = 25
VDD = 1.8 V,TA = 105
VDD = 2.5 V, TA = -40
VDD = 2.5 V, TA = 25
VDD = 2.5 V,TA = 105
VDD = 3.3 V, TA = -40
VDD = 3.3 V, TA = 25
VDD = 3.3 V,TA =105
390
380
370
360
350
VOD (mV)
340
330
320
310
300
290
280
270
260
250
25
30
40
50
60 70 80
100
200
300
Frequency (MHz)
400
500 600 700800 1000
2000
Figure 6-5. LMK1D210x VOD vs. Frequency, AMP_SEL = 0
530
VDD = 1.8 V, TA = -40
VDD = 1.8 V, TA = 25
VDD = 1.8 V,TA = 105
VDD = 2.5 V, TA = -40
VDD = 2.5 V, TA = 25
VDD = 2.5 V,TA = 105
VDD = 3.3 V, TA = -40
VDD = 3.3 V, TA = 25
VDD = 3.3 V,TA =105
520
510
500
490
480
470
460
VOD (mV)
450
440
430
420
410
400
390
380
370
360
350
340
330
25
30
40
50
60 70 80
100
200
300
Frequency (MHz)
400
500 600 700800 1000
2000
Figure 6-6. LMK1D210x VOD vs. Frequency, AMP_SEL = 1
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7 Parameter Measurement Information
Oscilloscope
100 W
LVDS
Figure 7-1. LVDS Output DC Configuration During Device Test
LMK1D21XX
Phase Noise/
Spectrum Analyzer
Balun
100 Ω
Figure 7-2. LVDS Output AC Configuration During Device Test
VIH
Vth
IN
VIL
IN
Vth
Figure 7-3. DC-Coupled LVCMOS Input During Device Test
VOH
OUTNx
VOD
OUTPx
VOL
80%
VOUT,DIFF,PP (= 2 x VOD)
20%
0V
tr
tf
Figure 7-4. Output Voltage and Rise/Fall Time
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INNx
INPx
tPLH0
tPHL0
tPLH1
tPHL1
OUTN0
OUTP0
OUTN1
OUTP1
tPLH2
tPHL2
OUTN2
OUTP2
tPHL7
tPLH7
OUTN7
OUTP7
A.
B.
Output skew is calculated as the greater of the following: the difference between the fastest and the slowest tPLHn or the difference
between the fastest and the slowest tPHLn (n = 0, 1, 2, ..7)
Part-to-part skew is calculated as the greater of the following: the difference between the fastest and the slowest tPLHn or the difference
between the fastest and the slowest tPHLn across multiple devices (n = 0, 1, 2, ..7)
Figure 7-5. Output Skew and Part-to-Part Skew
Vring
OUTNx
VOD
0 V Differential
OUTPx
Figure 7-6. Output Overshoot and Undershoot
VOS
GND
Figure 7-7. Output AC Common Mode
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8 Detailed Description
8.1 Overview
The LMK1D210x LVDS drivers use CMOS transistors to control the output current. Therefore, proper biasing
and termination are required to ensure correct operation of the device and to maximize signal integrity.
The proper LVDS termination for signal integrity over two 50-Ω lines is 100 Ω between the outputs on the
receiver end. Either DC-coupled termination or AC-coupled termination can be used for LVDS outputs. TI
recommends placing a termination resistor close to the receiver. If the receiver is internally biased to a voltage
different than the output common-mode voltage of the LMK1D210x, AC coupling must be used. If the LVDS
receiver has internal 100-Ω termination, external termination must be omitted.
8.2 Functional Block Diagram
VDD
1.8 to 3.3V
VAC_REF0
Reference
Generator
VAC_REF1
IN0
LVDS
OUT[0:N/2-1]
IN1
LVDS
OUT[N/2:N-1]
VDD
Rpull-up
EN
Rpull-down
VDD
Rpull-up
AMP_SEL
Output Swing
Control
Rpull-down
GND
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8.3 Feature Description
The LMK1D210x is a low additive jitter LVDS fan-out buffer that can generate up to 6 (LMK1D2106) or 8
(LMK1D2108) LVDS copies of a single input that is either LVDS, LVPECL, HCSL, CML, or LVCMOS on each of
its banks. The device has two banks, therefore this translates to a total of 12 (LMK1D2106) or 16 (LMK1D2108)
pairs of outputs. Refer to the Table 8-1 for output bank mapping. The reference clock frequencies can go up to 2
GHz.
Table 8-1. Output Bank
Bank
LMK1D2106
LMK1D2108
0
OUT0 to OUT5
OUT0 to OUT7
1
OUT6 to OUT11
OUT8 to OUT15
Apart from providing a very low additive jitter and low output skew, the LMK1D210x has an output bank enable/
disable control pin (EN) and an output amplitude control pin (AMP_SEL).
8.3.1 Fail-Safe Input
The LMK1D210x family of devices is designed to support fail-safe input operation. This feature allows the user
to drive the device inputs before VDD is applied without damaging the device. Refer to the Absolute Maximum
Ratings for more information on the maximum input supported by the device. The device also incorporates an
input hysteresis, which prevents random oscillation in absence of an input signal, allowing the input pins to be
left open.
8.4 Device Functional Modes
The output banks of the LMK1D210x can be selected through the control pin (see Table 8-2). Unused inputs
can be left floating to reduce overall component cost. Both AC- and DC-coupling schemes can be used with the
LMK1D210x to provide greater system flexibility.
Table 8-2. Output Control
EN
CLOCK OUTPUTS
0
All bank outputs disabled (static logic "0")
1
Bank 0 outputs enabled and Bank 1 outputs
disabled
OPEN
All bank outputs enabled
The output amplitude of the banks of the LMK1D210x can be selected through the amplitude selection pin
(see Table 8-3). The higher output amplitude mode (boosted swing LVDS mode) can be used in applications
which require higher amplitude either for better noise performance (higher slew rate) or if the receiver has swing
requirements which the standard LVDS swing cannot meet.
Table 8-3. Amplitude Selection
AMP_SEL
OUTPUT AMPLITUDE (mV)
0
Bank 0: boosted LVDS swing (500 mV)
Bank 1: standard LVDS swing (350 mV)
OPEN
Bank 0: standard LVDS swing (350 mV)
Bank 1: standard LVDS swing (350 mV)
1
Bank 0: boosted LVDS swing (500 mV)
Bank 1: boosted LVDS swing (500 mV)
8.4.1 LVDS Output Termination
TI recommends unused outputs to be terminated differentially with a 100-Ω resistor for optimum performance,
although unterminated outputs are also okay but will result in slight degradation in performance (Output AC
common-mode VOS) in the outputs being used.
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The LMK1D210x can be connected to LVDS receiver inputs with DC and AC coupling as shown in Figure 8-1
and Figure 8-2, respectively.
Z = 50 W
100 W
LMK1D21XX
LVDS
Z = 50 W
Figure 8-1. Output DC Termination
100 nF
Z = 50 W
100 W
LMK1D21XX
LVDS
Z = 50 W
100 nF
Figure 8-2. Output AC Termination (With the Receiver Internally Biased)
8.4.2 Input Termination
The LMK1D210x inputs can be interfaced with LVDS, LVPECL, HCSL, or LVCMOS drivers.
LVDS drivers can be connected to LMK1D210x inputs with DC and AC coupling as shown Figure 8-3 and Figure
8-4, respectively.
Z = 50 W
100 W
LVDS
LMK1D21XX
Z = 50 W
Figure 8-3. LVDS Clock Driver Connected to LMK1D210x Input (DC-Coupled)
100 nF
Z = 50 W
LVDS
LMK1D21XX
Z = 50 W
100 nF
50 W
50 W
VAC_REF
Figure 8-4. LVDS Clock Driver Connected to LMK1D210x Input (AC-Coupled)
Figure 8-5 shows how to connect LVPECL inputs to the LMK1D210x. The series resistors are required to reduce
the LVPECL signal swing if the signal swing is >1.6 VPP.
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75 W
100 nF
Z = 50 W
LMK1D21XX
LVPECL
Z = 50 W
100 nF
75 W
150 W
150 W
50 W
50 W
VAC_REF
Figure 8-5. LVPECL Clock Driver Connected to LMK1D210x Input
Figure 8-6 shows how to couple a LVCMOS clock input to the LMK1D210x directly.
LVCMOS
(1.8/2.5/3.3 V)
RS
Z = 50
LMK1D21XX
VTH = 0.5*(VIH + VIL)
Figure 8-6. 1.8-V, 2.5-V, or 3.3-V LVCMOS Clock Driver Connected to LMK1D210x Input
For unused input, TI recommends grounding both input pins (INP, INN) using 1-kΩ resistors.
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9 Application and Implementation
Note
Information in the following applications sections is not part of the TI component specification,
and TI does not warrant its accuracy or completeness. TI’s customers are responsible for
determining suitability of components for their purposes, as well as validating and testing their design
implementation to confirm system functionality.
9.1 Application Information
The LMK1D210x is a low additive jitter universal to LVDS fan-out buffer with dual inputs which fan-out to
dual outputs banks. Each input can fan-out to six outputs in case of LMK1D2106 and eight outputs in case
of LMK1D2108. The small package size, 1.8-V power supply operation, low output skew, and low additive
jitter is desgined for applications that require high-performance clock distribution as well as for low-power and
space-constraint applications.
9.2 Typical Application
ADC CLOCK
ADC CLOCK
Digital control
IN0
EN
100
JESD204B/C AFE
LMK1D21XX
LVDS Buffer
SYSREF CLOCK
SYSREF CLOCK
IN1
100
Figure 9-1. Fan-Out Buffer for ADC Device Clock and SYSREF Distribution
9.2.1 Design Requirements
The LMK1D210x shown in Figure 9-1 is configured to fan-out an ADC clock on the first output bank and
SYSREF clock on the second output bank for a system using the JESD204B/C ADC. The low output-to-output
skew, very low additive jitter and superior spurious suppression between dual banks makes the LMK1D210x
a simple, robust and low-cost solution for distributing various clocks to JESD204B/C AFE systems. The
configuration example can drive up to 4 ADC clocks and 4 SYSREF clocks for a JESD204B/C receiver with
the following properties:
• The ADC clock receiver module is typically AC-coupled with an LVDS driver such as the LMK1D210x due
to differences in common-mode voltage between the driver and receiver. Depending on the receiver, there
maybe an option for internal 100-Ω differential termination in which case an external termination would not be
required for the LMK1D210x.
• The SYSREF clock receiver module is typically DC-coupled provided the common-mode voltage of the
LMK1D210x outputs match with the receiver. An external termination may not be needed in case of an
internal termination in the receiver.
• Unused outputs of the LMK1D210x device are terminated differentially with a 100-Ω resistor for optimum
performance.
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9.2.2 Detailed Design Procedure
See Input Termination for proper input terminations, dependent on single-ended or differential inputs.
See LVDS Output Termination for output termination schemes depending on the receiver application.
TI recommends unused outputs to be terminated differentially with a 100-Ω resistor for optimum performance,
although unterminated outputs are also okay but will result in slight degradation in performance (Output AC
common-mode VOS) in the outputs being used.
In this application example, the ADC clock and SYSREF clocks require different output interfacing schemes.
Power-supply filtering and bypassing is critical for low-noise applications.
In case of common-mode mismatch between the output voltage of the LMK1D210x and the receiver, one can
use AC coupling to get around this. It might not be possible in certain applications, however, to AC-couple
the LMK1D210x outputs to the receiver due to the settling time associated with this AC-coupling network (Highpass filter), which can result in non-deterministic behavior during the initial transients. For such applications,
DC-coupling the outputs is necessary and thus requires a scheme which can overcome the inherent mismatch
between the common-mode voltage of the driver and receiver.
The application report Interfacing LVDS Driver With a Sub-LVDS Receiver discusses how to interface between a
LVDS driver and sub-LVDS receiver. The same concept can be applied to interface the LMK1D210x outputs to a
receiver which has a lower common-mode voltage.
1.8 V
R1
R3
R2
OUTX_P
IN_P
LMK1D21xx
SYSREF AFE
OUTX_N
IN_N
R2
R3
R1
1.8 V
Figure 9-2. Schematic for DC-Coupling LMK1D21xx With Lower Common-Mode Receiver
Figure 9-2 shows the resistor divider network for stepping down the common-mode voltage as explained in
the above application report. The resistors R1, R2 and R3 are chosen according to the input common-mode
voltage requirements of the receiver. As highlighted before, make sure that the reduced swing is able to meet
the requirements of the receiver. Higher swing mode (boosted LVDS swing mode) can be selected using the
AMP_SEL pin highlighted in Table 8-3 to compensate for the reduced swing as the result of the resistor voltage
divider.
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9.2.3 Application Curves
The low additive noise of the LMK1D2108. The low noise 156.25-MHz source with 25-fs RMS jitter, shown in
Figure 9-3, drives the LMK1D2108, resulting in 46.9-fs RMS when integrated from 12 kHz to 20 MHz (Figure
9-4). The resultant additive jitter is a low 39.7-fs RMS for this configuration. Note that this result applies to the
LMK1D2106 device as well.
Note: Reference signal is a low-noise Rhode and Schwarz SMA100B
Figure 9-3. LMK1D2108 Reference Phase Noise, 156.25 MHz, 25-fs RMS (12 kHz to 20 MHz)
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Figure 9-4. LMK1D2108 Output Phase Noise, 156.25 MHz, 46.9-fs RMS (12 kHz to 20 MHz)
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10 Power Supply Recommendations
High-performance clock buffers are sensitive to noise on the power supply, which can dramatically increase the
additive jitter of the buffer. Thus, it is essential to reduce noise from the system power supply, especially when
jitter or phase noise is critical to applications.
Filter capacitors are used to eliminate the low-frequency noise from the power supply, where the bypass
capacitors provide the low impedance path for high-frequency noise and guard the power-supply system against
the induced fluctuations. These bypass capacitors also provide instantaneous current surges as required by the
device and must have low equivalent series resistance (ESR). To properly use the bypass capacitors, they must
be placed close to the power-supply pins and laid out with short loops to minimize inductance. TI recommends
adding as many high-frequency (for example, 0.1-µF) bypass capacitors as there are supply pins in the package.
TI recommends, but does not require, inserting a ferrite bead between the board power supply and the chip
power supply that isolates the high-frequency switching noises generated by the clock driver. These ferrite beads
prevent the switching noise from leaking into the board supply. Choose an appropriate ferrite bead with low DC
resistance because it is imperative to provide adequate isolation between the board supply and the chip supply,
as well as to maintain a voltage at the supply pins that is greater than the minimum voltage required for proper
operation.
Figure 10-1 shows this recommended power-supply decoupling method.
Figure 10-1. Power Supply Decoupling
22
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11 Layout
11.1 Layout Guidelines
For reliability and performance reasons, the die temperature must be limited to a maximum of 135°C.
The device package has an exposed pad that provides the primary heat removal path to the printed circuit board
(PCB). To maximize the heat dissipation from the package, a thermal landing pattern including multiple vias to
a ground plane must be incorporated into the PCB within the footprint of the package. The thermal pad must
be soldered down to ensure adequate heat conduction to of the package. Figure 11-1 and Figure 11-2 show the
recommended top layer and via patterns for the 40-pin package (LMK1D2106).
11.2 Layout Examples
Figure 11-1. PCB layout example for LMK1D2106, Top Layer
Figure 11-2. PCB Layout Example for LMK1D2106, GND layer
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12 Device and Documentation Support
12.1 Documentation Support
12.1.1 Related Documentation
For related documentation see the following:
• Texas Instruments, Low-Additive Jitter, Four LVDS Outputs Clock Buffer Evaluation Board user's guide
• Texas Instruments, Power Consumption of LVPECL and LVDS Analog design journal
• Texas Instruments, Using Thermal Calculation Tools for Analog Components application report
12.2 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. Click on
Subscribe to updates to register and receive a weekly digest of any product information that has changed. For
change details, review the revision history included in any revised document.
12.3 Support Resources
TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straight
from the experts. Search existing answers or ask your own question to get the quick design help you need.
Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do
not necessarily reflect TI's views; see TI's Terms of Use.
12.4 Trademarks
TI E2E™ is a trademark of Texas Instruments.
All trademarks are the property of their respective owners.
12.5 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled
with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may
be more susceptible to damage because very small parametric changes could cause the device not to meet its published
specifications.
12.6 Glossary
TI Glossary
This glossary lists and explains terms, acronyms, and definitions.
13 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
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Copyright © 2022 Texas Instruments Incorporated
Product Folder Links: LMK1D2106 LMK1D2108
PACKAGE OPTION ADDENDUM
www.ti.com
25-Jan-2022
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
(4/5)
(6)
LMK1D2106RHAR
ACTIVE
VQFN
RHA
40
2500
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 105
LMK1D
2106
LMK1D2106RHAT
ACTIVE
VQFN
RHA
40
250
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 105
LMK1D
2106
LMK1D2108RGZR
ACTIVE
VQFN
RGZ
48
2500
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 105
LMK1D
2108
LMK1D2108RGZT
ACTIVE
VQFN
RGZ
48
250
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 105
LMK1D
2108
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of
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