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LMK60E2-150M, LMK60E0-156257
LMK60A0-148351, LMK60A0-148M
SNAS687C – JUNE 2016 – REVISED NOVEMBER 2017
LMK60XX High-Performance Low Jitter Oscillator
1 Features
3 Description
•
The LMK60XX device is a low jitter oscillator that
generates a commonly used reference clock. The
device is pre-programmed in factory to support any
reference clock frequency; supported output formats
are LVPECL, and LVDS up to 800 MHz, and HCSL
up to 400 MHz. Internal power conditioning provide
excellent power supply ripple rejection (PSRR),
reducing the cost and complexity of the power
delivery network. The device operates from a single
3.3-V ±5% supply.
1
•
•
•
•
•
Low Noise, High Performance
– Jitter: 150 fs RMS typical Fout > 100 MHz
– PSRR: –60 dBc, Robust Supply Noise
Immunity
Supported Output Format
– LVPECL and LVDS up to 800 MHz
– HCSL up to 400 MHz
Total Frequency Tolerance of ±50 ppm
(LMK60X2) and ±25 ppm (LMK60X0)
3.3-V Operating Voltage
Industrial Temperature Range (–40ºC to +85ºC)
7-mm × 5-mm 6-pin Package That is PinCompatible With Industry Standard 7050 XO
Package
Device Information(1)
2 Applications
•
•
•
•
•
High-Performance Replacement for Crystal-,
SAW-, or Silicon-based Oscillators
Switches, Routers, Network Line Cards, Base
Band Units (BBU), Servers, Storage/SAN
Test and Measurement
Medical Imaging
FPGA, Processor Attach
PART
NUMBER
OUTPUT FREQ
(MHz) AND
FORMAT
TOTAL FREQ
STABILITY
(ppm)
LMK60E2150M
150 LVPECL
±50
LMK60E0156257
156.257
LVPECL
±25
LMK60A0148351
148 + 32/91
LVDS
±25
LMK60A0148M
148.5 LVDS
±25
PACKAGE /
SIZE
6-pin QFM,
7 mm × 5 mm
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
Pinout
6
OE
1
6
VDD
NC
2
5
OUTN
GND
3
4
OUTP
1
2
5
4
3
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
LMK60E2-150M, LMK60E0-156257
LMK60A0-148351, LMK60A0-148M
SNAS687C – JUNE 2016 – REVISED NOVEMBER 2017
www.ti.com
Table of Contents
1
2
3
4
5
6
Features ..................................................................
Applications ...........................................................
Description .............................................................
Revision History.....................................................
Pin Configuration and Functions .........................
Specifications.........................................................
1
1
1
2
3
3
6.1
6.2
6.3
6.4
6.5
6.6
6.7
6.8
6.9
6.10
6.11
3
3
4
4
4
4
5
5
5
5
6
Absolute Maximum Ratings ......................................
ESD Ratings ............................................................
Recommended Operating Conditions.......................
Thermal Information ..................................................
Electrical Characteristics - Power Supply .................
LVPECL Output Characteristics................................
LVDS Output Characteristics ....................................
HCSL Output Characteristics....................................
OE Input Characteristics ...........................................
Frequency Tolerance Characteristics .....................
Power-On/Reset Characteristics (VDD)..................
6.12
6.13
6.14
6.15
PSRR Characteristics .............................................
PLL Clock Output Jitter Characteristics ..................
Additional Reliability and Qualification ....................
Typical Characteristics ............................................
6
6
6
7
7
Parameter Measurement Information .................. 8
8
9
Power Supply Recommendations...................... 10
Layout ................................................................... 10
7.1 Device Output Configurations ................................... 8
9.1 Layout Guidelines ................................................... 10
10 Device and Documentation Support ................. 12
10.1
10.2
10.3
10.4
10.5
10.6
Related Links ........................................................
Receiving Notification of Documentation Updates
Community Resources..........................................
Trademarks ...........................................................
Electrostatic Discharge Caution ............................
Glossary ................................................................
12
12
12
12
12
12
11 Mechanical, Packaging, and Orderable
Information ........................................................... 12
4 Revision History
Changes from Revision B (December 2016) to Revision C
Page
•
New release of LMK60A0-148351.......................................................................................................................................... 1
•
New release of LMK60A0-148M............................................................................................................................................. 1
Changes from Revision A (August 2016) to Revision B
Page
•
Changed LMK60E2-150M00 to LMK60E2-150M .................................................................................................................. 1
•
Removed LMK60E2-156M and moved to separate datasheet .............................................................................................. 1
Changes from Original (June 2016) to Revision A
•
2
Page
New release of LMK60E0-156257.......................................................................................................................................... 1
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SNAS687C – JUNE 2016 – REVISED NOVEMBER 2017
5 Pin Configuration and Functions
SIA Package
6-pin QFM
Top View
OE
1
6
VDD
NC
2
5
OUTN
GND
3
4
OUTP
Pin Functions
PIN
NAME
I/O
NO.
DESCRIPTION
POWER
GND
3
Ground
Device ground
VDD
6
Analog
3.3-V power supply
4, 5
Universal
OUTPUT BLOCK
OUTP,
OUTN
Differential output pair (LVPECL, LVDS or HCSL).
DIGITAL CONTROL / INTERFACES
NC
2
N/A
OE
1
LVCMOS
No connect
Output enable (internal pullup). When set to low, output pair is disabled and set at high
impedance.
6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted) (1)
MIN
MAX
UNIT
VDD
Device supply voltage
–0.3
3.6
V
VIN
Output voltage for logic inputs
–0.3
VDD + 0.3
V
VOUT
Output voltage for clock outputs
–0.3
VDD + 0.3
V
TJ
Junction temperature
150
°C
TSTG
Storage temperature
125
°C
(1)
–40
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute maximum-rated conditions for extended periods may affect device reliability.
6.2 ESD Ratings
VALUE
V(ESD)
(1)
(2)
Electrostatic discharge
Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001 (1)
±2000
Charged-device model (CDM), per JEDEC specification JESD22-C101 (2)
±500
UNIT
V
JEDEC document JEP155 states that 500 V HBM allows safe manufacturing with a standard ESD control process.
JEDEC document JEP157 states that 250 V CDM allows safe manufacturing with a standard ESD control process.
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6.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
VDD
Device supply voltage
TA
Ambient temperature
TJ
Junction temperature
tRAMP
VDD power-up ramp time
MIN
NOM
MAX
3.135
3.3
3.465
V
–40
25
85
°C
0.1
UNIT
120
°C
100
ms
6.4 Thermal Information
LMK60XX
SIA (QFM)
THERMAL METRIC (1)
RθJA
(2) (3) (4)
UNIT
6 PINS
Airflow (LFM) 200
Airflow (LFM) 400
55.2
46.4
43.7
°C/W
RθJC(top) Junction-to-case (top) thermal resistance
34.6
n/a
n/a
°C/W
RθJB
Junction-to-board thermal resistance
37.7
n/a
n/a
°C/W
ψJT
Junction-to-top characterization parameter
11.3
17.6
22.5
°C/W
ψJB
Junction-to-board characterization parameter
37.7
41.5
40.1
°C/W
RθJC(bot) Junction-to-case (bottom) thermal resistance
n/a
n/a
n/a
°C/W
(1)
(2)
(3)
(4)
Junction-to-ambient thermal resistance
Airflow (LFM) 0
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
The package thermal resistance is calculated on a 4 layer JEDEC board.
Connected to GND with 3 thermal vias (0.3-mm diameter).
ψJB (junction to board) is used when the main heat flow is from the junction to the GND pad. See the Layout Guidelines section for
more information on ensuring good system reliability and quality.
6.5 Electrical Characteristics - Power Supply (1)
VDD = 3.3 V ± 5%, TA = -40C to 85°C
PARAMETER
IDD
Device current consumption
IDD-PD
(1)
(2)
Device current consumption
when output is disabled
TYP
MAX
LVPECL (2)
TEST CONDITIONS
MIN
162
208
LVDS
152
196
HCSL
155
196
OE = GND
136
UNIT
mA
mA
Refer to Parameter Measurement Information for relevant test conditions.
On-chip power dissipation should exclude 40 mW, dissipated in the 150 Ω termination resistors, from total power dissipation.
6.6 LVPECL Output Characteristics (1)
VDD = 3.3 V ± 5%, TA = -40C to 85°C
PARAMETER
fOUT
Output frequency (2)
VOD
Output voltage swing (VOH – VOL) (2)
VOUT, DIFF, PP
Differential output peak-to-peak swing
VOS
Output common-mode voltage
tR / tF
Output rise/fall time (20% to 80%) (3)
ODC
Output duty cycle (3)
(1)
(2)
(3)
4
TEST CONDITIONS
MIN
TYP
10
700
800
MAX
UNIT
800
MHz
1200
mV
2 × |VOD|
V
VDD – 1.55
150
45%
V
250
ps
55%
Refer to Parameter Measurement Information for relevant test conditions.
An output frequency over fOUT max spec is possible, but output swing may be less than VOD min spec.
Ensured by characterization.
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SNAS687C – JUNE 2016 – REVISED NOVEMBER 2017
6.7 LVDS Output Characteristics (1)
VDD = 3.3 V ± 5%, TA = -40°C to 85°C
PARAMETER
TEST CONDITIONS
(1)
MIN
TYP
fOUT
Output frequency
VOD
Output voltage swing
(VOH - VOL) (1)
VOUT, DIFF, PP
Differential output peak-to-peak swing
VOS
Output common-mode voltage
1.2
tR / tF
Output rise/fall time (20% to 80%) (2)
150
ODC
Output duty cycle (2)
ROUT
Differential output impedance
(1)
(2)
10
300
390
MAX
UNIT
800
MHz
480
mV
2 × |VOD|
V
V
250
45%
ps
55%
125
Ω
An output frequency over fOUT max spec is possible, but output swing may be less than VOD min spec.
Ensured by characterization.
6.8 HCSL Output Characteristics (1)
VDD = 3.3 V ± 5%, TA = -40°C to 85°C
PARAMETER
MAX
UNIT
10
400
MHz
Output high voltage
600
850
mV
VOL
Output low voltage
–100
100
mV
VCROSS
Absolute crossing voltage (2) (3)
250
475
mV
0
140
mV
0.8
2
V/ns
45%
55%
fOUT
Output frequency
VOH
TEST CONDITIONS
VCROSS-DELTA Variation of VCROSS (2) (3)
dV/dt
Slew rate (4)
ODC
Output duty cycle (4)
(1)
(2)
(3)
(4)
MIN
TYP
Refer to Parameter Measurement Information for relevant test conditions.
Measured from -150 mV to +150 mV on the differential waveform with the 300 mVpp measurement window centered on the differential
zero crossing.
Ensured by design.
Ensured by characterization.
6.9 OE Input Characteristics
VDD = 3.3 V ± 5%, TA = -40°C to 85°C
PARAMETER
TEST CONDITIONS
MIN
VIH
Input high voltage
VIL
Input low voltage
IIH
Input high current
VIH = VDD
–40
IIL
Input low current
VIL = GND
–40
CIN
Input capacitance
TYP
MAX
UNIT
1.4
V
0.6
V
40
µA
40
µA
2
pF
6.10 Frequency Tolerance Characteristics (1)
VDD = 3.3 V ± 5%, TA = -40°C to 85°C
PARAMETER
fT
(1)
Total frequency tolerance
TEST CONDITIONS
MIN
LMK60X2: All output formats, frequency
bands and device junction temperature up to
125°C; includes initial freq tolerance,
temperature & supply voltage variation, solder
reflow and aging (10 years)
LMK60X0: All output formats, frequency
bands and device junction temperature up to
115°C; includes initial freq tolerance,
temperature & supply voltage variation, solder
reflow and aging (5 years at 40°C)
TYP
MAX
UNIT
–50
50
ppm
–25
25
ppm
Ensured by characterization.
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6.11 Power-On/Reset Characteristics (VDD)
VDD = 3.3 V ± 5%, TA = -40°C to 85°C
PARAMETER
TEST CONDITIONS
MIN
MAX
UNIT
2.95
V
0.1
V
Time elapsed from VDD at 3.135 V to output
enabled
10
ms
(1)
VTHRESH
Threshold voltage
VDROOP
Allowable voltage droop (2)
(1)
TYP
2.72
tSTARTUP
Start-up time
tOE-EN
Output enable time (2)
Time elapsed from OE at VIH to output enabled
50
µs
tOE-DIS
Output disable time (2)
Time elapsed from OE at VIL to output disabled
50
µs
(1)
(2)
Ensured by characterization.
Ensured by design.
6.12 PSRR Characteristics (1)
VDD = 3.3 V, TA = 25°C, FS[1:0] = NC, NC
PARAMETER
PSRR
(1)
(2)
(3)
Spurs induced by 50-mV
power supply ripple (2) (3) at
156.25-MHz output, all
output types
TEST CONDITIONS
MIN
TYP
Sine wave at 50 kHz
–60
Sine wave at 100 kHz
–60
Sine wave at 500 kHz
–60
Sine wave at 1 MHz
–60
MAX
UNIT
dBc
Refer to Parameter Measurement Information for relevant test conditions.
Measured max spur level with 50 mVpp sinusoidal signal between 50 kHz and 1 MHz applied on VDD pin
DJSPUR (ps, pk-pk) = [2*10(SPUR/20) / (π*fOUT)]*1e6, where PSRR or SPUR in dBc and fOUT in MHz.
6.13 PLL Clock Output Jitter Characteristics (1) (2)
VDD = 3.3 V ± 5%, TA = -40°C to 85°C
PARAMETER
RJ
(1)
(2)
(3)
RMS phase jitter (3)
(12 kHz – 20 MHz)
TEST CONDITIONS
fOUT ≥ 100 MHz, All output types
MIN
TYP
MAX
UNIT
150
250
fs RMS
Refer to Parameter Measurement Information for relevant test conditions.
Phase jitter measured with Agilent E5052 signal source analyzer using a differential-to-single ended converter (balun or buffer).
Ensured by characterization.
6.14 Additional Reliability and Qualification
6
PARAMETER
CONDITION / TEST METHOD
Mechanical Shock
MIL-STD-202, Method 213
Mechanical Vibration
MIL-STD-202, Method 204
Moisture Sensitivity Level
J-STD-020, MSL3
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6.15 Typical Characteristics
0.9
1.7
Output Differential Swing (Vp-p)
Output Differential Swing (Vp-p)
1.8
1.6
1.5
1.4
1.3
1.2
1.1
0.8
0.7
0.6
0.5
0
200
400
600
Output Frequency (MHz)
800
1000
0
200
D013
Figure 1. LVPECL Differential Output Swing vs Frequency
400
600
Output Frequency (MHz)
800
1000
D014
Figure 2. LVDS Differential Output Swing vs Frequency
Output Differential Swing (Vp-p)
1.5
1.48
1.46
1.44
1.42
1.4
0
100
200
300
Output Frequency (MHz)
400
500
D015
Figure 3. HCSL Differential Output Swing vs Frequency
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7 Parameter Measurement Information
7.1 Device Output Configurations
High impedance differential probe
LMK60XX
LVPECL
150
Oscilloscope
150
Figure 4. LVPECL Output DC Configuration During Device Test
High impedance differential probe
LMK60XX
LVDS
Oscilloscope
Figure 5. LVDS Output DC Configuration During Device Test
High impedance differential probe
HCSL
LMK60XX
50
Oscilloscope
50
Figure 6. HCSL Output DC Configuration During Device Test
LMK60XX
Balun/
Buffer
LVPECL
150
Phase Noise/
Spectrum
Analyzer
150
Figure 7. LVPECL Output AC Configuration During Device Test
LMK60XX
LVDS
Balun/
Buffer
Phase Noise/
Spectrum
Analyzer
Figure 8. LVDS Output AC Configuration During Device Test
8
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Device Output Configurations (continued)
LMK60XX
Balun/
Buffer
HCSL
50
Phase Noise/
Spectrum
Analyzer
50
Figure 9. HCSL Output AC Configuration During Device Test
Sine wave
Modulator
Power Supply
LMK60XX
Balun
150 (LVPECL)
Open (LVDS)
50 (HCSL)
Phase Noise/
Spectrum
Analyzer
150 (LVPECL)
Open (LVDS)
50 (HCSL)
Figure 10. PSRR Test Setup
OUT_P
VOD
OUT_N
80%
VOUT,DIFF,PP = 2 x VOD
0V
20%
tR
tF
Figure 11. Differential Output Voltage and Rise/Fall Time
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8 Power Supply Recommendations
For best electrical performance of LMK60XX, TI recommends using a combination of 10 µF, 1 µF and 0.1 µF on
its power supply bypass network. TI also recommends using component side mounting of the power supply
bypass capacitors, and it is best to use 0201 or 0402 body size capacitors to facilitate signal routing. Keep the
connections between the bypass capacitors and the power supply on the device as short as possible. Ground the
other side of the capacitor using a low impedance connection to the ground plane. Figure 12 shows the layout
recommendation for power supply decoupling of LMK60XX.
9 Layout
9.1 Layout Guidelines
The following sections provides recommendations for board layout, solder reflow profile and power supply
bypassing when using LMK60XX to ensure good thermal / electrical performance and overall signal integrity of
entire system.
9.1.1 Ensuring Thermal Reliability
The LMK60XX is a high performance device. Therefore pay careful attention to device configuration and printedcircuit board (PCB) layout with respect to power consumption. The ground pin needs to be connected to the
ground plane of the PCB through three vias or more, as shown in Figure 12, to maximize thermal dissipation out
of the package.
Equation 1 describes the relationship between the PCB temperature around the LMK60XX and its junction
temperature.
TB = TJ – ΨJB * P
where
•
•
•
•
TB: PCB temperature around the LMK60XX
TJ: Junction temperature of LMK60XX
ΨJB: Junction-to-board thermal resistance parameter of LMK60XX (37.7°C/W without airflow)
P: On-chip power dissipation of LMK60XX
(1)
To ensure that the maximum junction temperature of LMK60XX is below 120°C, it can be calculated that the
maximum PCB temperature without airflow should be at 90°C or below when the device is optimized for best
performance resulting in maximum on-chip power dissipation of 0.68 W.
9.1.2 Best Practices for Signal Integrity
For best electrical performance and signal integrity of entire system with LMK60XX, TI recommends routing vias
into decoupling capacitors and then into the LMK60XX. TI also recommends increasing the via count and width
of the traces wherever possible. These steps ensure lowest impedance and shortest path for high-frequency
current flow. Figure 12 shows the layout recommendation for LMK60XX.
10
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Layout Guidelines (continued)
Figure 12. LMK60XX Layout Recommendation for Power Supply and Ground
9.1.3 Recommended Solder Reflow Profile
TI recommends following the solder paste supplier's recommendations to optimize flux activity and to achieve
proper melting temperatures of the alloy within the guidelines of J-STD-20. It is preferable for the LMK60XX to be
processed with the lowest peak temperature possible while also remaining below the components peak
temperature rating as listed on the MSL label. The exact temperature profile would depend on several factors
including maximum peak temperature for the component as rated on the MSL label, Board thickness, PCB
material type, PCB geometries, component locations, sizes, densities within PCB, as well solder manufactures
recommended profile, and capability of the reflow equipment to as confirmed by the SMT assembly operation.
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10 Device and Documentation Support
10.1 Related Links
The table below lists quick access links. Categories include technical documents, support and community
resources, tools and software, and quick access to sample or buy.
Table 1. Related Links
PARTS
PRODUCT FOLDER
SAMPLE & BUY
TECHNICAL
DOCUMENTS
TOOLS &
SOFTWARE
SUPPORT &
COMMUNITY
LMK60E2-150M
Click here
Click here
Click here
Click here
Click here
LMK60E0-156257
Click here
Click here
Click here
Click here
Click here
10.2 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper
right corner, click on Alert me to register and receive a weekly digest of any product information that has
changed. For change details, review the revision history included in any revised document.
10.3 Community Resources
The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.
10.4 Trademarks
E2E is a trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
10.5 Electrostatic Discharge Caution
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
10.6 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
11 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
12
Submit Documentation Feedback
Copyright © 2016–2017, Texas Instruments Incorporated
Product Folder Links: LMK60E2-150M LMK60E0-156257 LMK60A0-148351 LMK60A0-148M
LMK60E2-150M, LMK60E0-156257
LMK60A0-148351, LMK60A0-148M
www.ti.com
SNAS687C – JUNE 2016 – REVISED NOVEMBER 2017
PACKAGE OUTLINE
SIA0006A
QFM - 1.15 mm max height
SCALE 2.200
QUAD FLAT MODULE
5.1
4.9
A
B
PIN 1 INDEX
AREA
7.1
6.9
C
1.15 MAX
0.1 C
3X 3.7
6X (0.15)
3
4
4X (0.26)
SYMM
2X
5.08
4X
2.54
6X
0.1
0.05
6
1
SYMM
1.43
1.37
6X
C A
C
B
1.03
0.97
4222361/B 10/2015
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
www.ti.com
Copyright © 2016–2017, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Links: LMK60E2-150M LMK60E0-156257 LMK60A0-148351 LMK60A0-148M
13
LMK60E2-150M, LMK60E0-156257
LMK60A0-148351, LMK60A0-148M
SNAS687C – JUNE 2016 – REVISED NOVEMBER 2017
www.ti.com
EXAMPLE BOARD LAYOUT
SIA0006A
QFM - 1.15 mm max height
QUAD FLAT MODULE
SYMM
6X (1)
1
6
6X (1.4)
SYMM
4X (2.54)
4
3
(R0.05) TYP
(3.7)
LAND PATTERN EXAMPLE
1:1 RATIO WITH PACKAGE SOLDER PADS
SCALE:8X
0.07 MIN
ALL AROUND
METAL
SOLDER MASK
OPENING
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
SOLDER MASK
DEFINED
NON SOLDER MASK
DEFINED
SOLDER MASK DETAILS
NOT TO SCALE
4222361/B 10/2015
NOTES: (continued)
3. For more information, see Texas Instruments literature number SLUA271 (www.ti.com/lit/slua271).
www.ti.com
14
Submit Documentation Feedback
Copyright © 2016–2017, Texas Instruments Incorporated
Product Folder Links: LMK60E2-150M LMK60E0-156257 LMK60A0-148351 LMK60A0-148M
LMK60E2-150M, LMK60E0-156257
LMK60A0-148351, LMK60A0-148M
www.ti.com
SNAS687C – JUNE 2016 – REVISED NOVEMBER 2017
EXAMPLE STENCIL DESIGN
SIA0006A
QFM - 1.15 mm max height
QUAD FLAT MODULE
SYMM
12X (1)
1
6
12X (0.6)
METAL TYP
(R0.05)
SYMM
4X (2.54)
4
3
(0.4) TYP
(3.7)
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
PRINTED SOLDER COVERAGE BY AREA
ALL PADS: 86%
SCALE:10X
4222361/B 10/2015
NOTES: (continued)
4. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
www.ti.com
Copyright © 2016–2017, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Links: LMK60E2-150M LMK60E0-156257 LMK60A0-148351 LMK60A0-148M
15
PACKAGE OPTION ADDENDUM
www.ti.com
28-Nov-2019
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
Lead/Ball Finish
MSL Peak Temp
(2)
(6)
(3)
Op Temp (°C)
Device Marking
(4/5)
LMK60A0-148M35SIAR
ACTIVE
QFM
SIA
6
2500
Green (RoHS
& no Sb/Br)
NIAU
Level-3-260C-168 HR
-40 to 85
LMK60A0
148M35
LMK60A0-148M35SIAT
ACTIVE
QFM
SIA
6
250
Green (RoHS
& no Sb/Br)
NIAU
Level-3-260C-168 HR
-40 to 85
LMK60A0
148M35
LMK60A0-148M50SIAR
ACTIVE
QFM
SIA
6
2500
Green (RoHS
& no Sb/Br)
NIAU
Level-3-260C-168 HR
-40 to 85
LMK60A0
148M50
LMK60A0-148M50SIAT
ACTIVE
QFM
SIA
6
250
Green (RoHS
& no Sb/Br)
NIAU
Level-3-260C-168 HR
-40 to 85
LMK60A0
148M50
LMK60E0-156257SIAR
ACTIVE
QFM
SIA
6
2500
Green (RoHS
& no Sb/Br)
NIAU
Level-3-260C-168 HR
-40 to 85
LMK60E0
156257
LMK60E0-156257SIAT
ACTIVE
QFM
SIA
6
250
Green (RoHS
& no Sb/Br)
NIAU
Level-3-260C-168 HR
-40 to 85
LMK60E0
156257
LMK60E2-150M00SIAR
ACTIVE
QFM
SIA
6
2500
Green (RoHS
& no Sb/Br)
NIAU
Level-3-260C-168 HR
-40 to 85
LMK60E2
150M00
LMK60E2-150M00SIAT
ACTIVE
QFM
SIA
6
250
Green (RoHS
& no Sb/Br)
NIAU
Level-3-260C-168 HR
-40 to 85
LMK60E2
150M00
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of
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