LMK61E2EVM, LMK61E0MEVM
User's Guide
Literature Number: SNAU188B
October 2015 – Revised August 2017
Contents
1
2
3
4
5
6
7
8
9
10
11
12
13
14
Overview ............................................................................................................................ 5
Features ............................................................................................................................. 5
Configuring the EVM ............................................................................................................ 6
Configuring the Power Supply .............................................................................................. 6
Configuring the Control Pins ................................................................................................. 8
Configuring the Clock Output .............................................................................................. 10
Using the USB Interface Connection ..................................................................................... 11
EVM Quick Start Guide........................................................................................................ 11
Recommended Test Instruments .......................................................................................... 11
Example Performance Measurements ................................................................................... 12
EVM Layout ....................................................................................................................... 15
EVM Schematic .................................................................................................................. 18
LMK61E2EVM Bill of Materials ............................................................................................. 21
LMK61E0MEVM Bill of Materials ........................................................................................... 22
Revision History .......................................................................................................................... 24
Revision History .......................................................................................................................... 24
2
Table of Contents
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List of Figures
1
LMK61E2EVM Photo ........................................................................................................ 4
2
EVM Board Layout........................................................................................................... 6
3
Power Terminals and Jumpers............................................................................................. 7
4
Control Pin Interfaces (Default Jumper Settings Shown)
5
EVM Termination Schematic
6
7
8
9
10
11
12
13
14
15
.............................................................. 8
............................................................................................. 10
156.25-MHz LVPECL Differential Phase Noise ........................................................................ 12
156.25-MHz LVDS Differential Phase Noise ........................................................................... 13
161.1328125-MHz HCSL Differential Phase Noise .................................................................... 14
Top Overlay ................................................................................................................. 15
Top Solder Mask ........................................................................................................... 15
Layer 1 (Top Side) ......................................................................................................... 15
Layer 4 (Bottom Side, View From Bottom) ............................................................................. 16
Bottom Solder Mask ....................................................................................................... 16
Bottom Overlay ............................................................................................................. 16
Drill Drawing ................................................................................................................ 17
List of Tables
1
2
3
4
5
6
........................................................................................................ 4
Power Configurations ....................................................................................................... 7
Control Pin Interfaces ....................................................................................................... 9
Output Termination Schemes............................................................................................. 10
Recommended Device Configurations .................................................................................. 11
Typical Output RMS Jitter Summary..................................................................................... 12
Ordering Information
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List of Figures
3
User's Guide
SNAU188B – October 2015 – Revised August 2017
LMK61E2EVM, LMK61E0MEVM User's Guide
Figure 1. LMK61E2EVM Photo
Table 1. Ordering Information
4
EVM ID
DEVICE ID
DEVICE PACKAGE
LMK61E2EVM
LMK61E2-SIA
5 mm × 7 mm 8-pin QFM (SIA)
LMK61E0MEVM
LMK61E0M-SIA
5 mm × 7 mm 8-pin QFM (SIA)
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Overview
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1
Overview
The LMK61E2EVM and LMK61E0MEVM evaluation modules provide a complete evaluation platform to
evaluate the clock performance and flexibility of the Texas Instruments LMK61XX Ultra-Low Jitter Crystal
Oscillator family, with integrated tunable 50-MHz crystal, low noise PLL, universal output, and integrated
EEPROM.
The EVM can be used as a flexible clock source for compliance testing, performance evaluation, and
initial system prototyping. The onboard edge-launch SMA ports provide access to the LMK61XX’s
configurable clock output for interfacing to test equipment and reference boards using commercially
available coaxial cables, adapters, or baluns (not included). This connectivity enables integrated system
level testing between TI’s LMK61XX and third-party FPGA/ASIC/SoC reference boards. A software
graphical user interface (GUI) platform can be installed on a Host PC to access the LMK61XX’s device
registers and EEPROM through the onboard USB-to-I2C interface.
2
Features
•
•
•
•
•
•
•
•
•
•
Integrated low-noise, 50-MHz tunable crystal
– Fine frequency margining in ppm steps through the I2C
Coarse frequency margining in percentage steps through the I2C
Configurable output format
– LMK61E2EVM supports LVPECL, LVDS, or HCSL
– LMK61E0MEVM supports dual LVCMOS
Programmable Output Enable polarity
EEPROM allows for custom configuration for power-up defaults
Footprint compatible with industry standard 5 mm × 7 mm XO package
– 2 additional pins allow for optional I2C programing
GUI platform for full access to device registers and EEPROM
Onboard USB-to-I2C programming interface
External power supply inputs or powered over USB
LEDs indicators: Device Power and USB / I2C activity
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Configuring the EVM
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Configuring the EVM
The LMK61XX is a highly-configurable crystal oscillator with simple power supply requirements and
flexible clock output formats. To support a wide range of evaluation use cases, the EVM was designed for
maximum flexibility so various configurations or options that are not required in all typical system
applications have been included.
This section describes the jumpers and connectors on the EVM, as well as how to connect, set up, and
use the EVM. When operating the EVM, the power supply and clock outputs can be connected to the
SMA ports shown in Figure 2. Additionally, the USB port can be used to power the entire EVM without the
need for external power supplies. These SMA ports are labeled in the top silkscreen layer.
Figure 2. EVM Board Layout
4
Configuring the Power Supply
The LMK61XX features a single VDD supply pin that operates from 3.3 V (+5%). This supply can be
powered directly from an external supply or through an on-board LDO regulator. Although the LMK61XX
has integrated LDO regulators for excellent power-supply-ripple-rejection (PSRR), the EVM’s onboard
regulator (U2) can allow a higher supply voltage (like 5 V) to power the EVM. The direct external supply or
onboard regulator can be independently routed for the VDD supply pin by configuring the power terminals
and jumpers shown in Figure 3. J1 (USB mini connector) is the default power supply for the EVM,
featuring a low noise regulator for voltage step-down. Power SMA Port EXTIN (P1) provides an alternative
connector style to apply power using coax cables. Using EXTIN while connected to USB power is not
required but can be useful when testing with externally regulated supplies.
6
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Figure 3. Power Terminals and Jumpers
Table 2 summarizes the EVM power configurations to connect and route power to the onboard LDOs and
LMK61XX. Refer to the EVM schematic for more details.
Table 2. Power Configurations
MODE
USB Powered
EXTIN VOLTAGE
(2)
J2 SETTING
(1)
J3 SETTING
USB PWR
External Power + LDO
4.3 V to 5.5 V
EXT PWR
REG
External Power
3.3 V
Remove Jumper
EXT PWR
(1)
(2)
(1)
Markings left of J2 indicate the orientation of jumper settings EXT PWR (pins 1 and 2 of jumper) and USB PWR / REG (pins 2
and 3 of jumper)
USB cable must be connected to J1 for operation
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Configuring the Control Pins
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Configuring the Control Pins
The LMK61XX has several control pins dedicated for control of I2C communications, device I2C address,
and output enable control. These control pins can be configured through the jumpers shown in .
Figure 4. Control Pin Interfaces (Default Jumper Settings Shown)
Jumpers J9 and J10 can be used to configure the corresponding control pin to either high or low state by
strapping the center pin to VDD position (tie pins 1-2) or GND position (tie pins 2-3), respectively.
Connections from the VDD position to the device supply or from the GND position to the ground plane are
connected by 4.7-kΩ resistors.
Jumpers J5 and J6 can be configured in a static configuration through a high or low state by strapping the
center pin to VDD position or to the GND position. Similarly, these connections are made through a 4.7-kΩ
resistor to the respective supply and ground planes. The third position, U2A, allows for control of the
respective control pins over software through the onboard microcontroller. Biasing is established externally
and is default set to a high state.
The LMK61XX control pins serve several functions unique to device pins. For a description of each pin’s
functionality and the device configuration based on their power-up state, refer to Table 3.
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Table 3. Control Pin Interfaces
COMPONENT
NAME (TYPE)
DESCRIPTION
J5
OE (passive or software control)
Output Enable Pin Output Enable Pin
OE state controls the differential output operation in LMK61E2EVM and
OUTP operation in LMK61E0MEVM. Polarity can be adjusted in the
LMK61XX’s register settings. OUTN in LMK61E0MEVM is controlled by
register R24[4] and is disabled by default.
J6
OE STATE
OPERATING MODE (BASED ON
DEFAULT)
GND
Differential Output Disabled in
LMK61E2EVM, OUTP DIsabled in
LMK61E0MEVM
VDD (JP Default)
Differential Output Enabled in
LMK61E2EVM, OUTP Enabled in
LMK61E0MEVM
ADD (passive or software control) I2C Slave Address LSB Select pin
ADD is sampled on POR to configure the lower 2 bits of the 7-bit slave
address. The upper 5 bits of the slave address are initialized from
EEPROM (SLAVEADR[7:3] = 10110b). By configuring ADD, the
composite slave address can be selected as follows:
J9 J10
J1
ADD STATE
7-BIT SLAVE ADDRESS (EXCLUDES
W/R BIT)
GND
1011000b / 0x58
High Z (no connect)
1011001b / 0x59
VDD (JP Default)
1011010b / 0x5A
SCL SDA
(I2C inputs)
I2C Serial Interface Pins
USB (not shown in Figure 4)
USB port (Mini-B type) USB port (Mini-B type)
An I2C master device can interface with the LMK61XX over the I2C clock
line (SCL) and data line (SDA). The open-drain topology of the SCL and
SDA pins require an external pullup resistor. J9 and J10 should always be
set in the VDD position to ensure proper I2C communication. The SCL
and SDA lines are connected with the onboard microcontroller, which is
controlled by the GUI.
Using the GUI platform, USB controller (U4) provides the USB-to-I2C
interface to manage the LMK61XX device registers and EEPROM. When
USB communication is established with a Host PC running the GUI, LED
D5 should be lit solid green.
The USB port powers LDO regulator U1 to supply 3.3-V power for the
MCU and its peripheral circuitry.
J4 (not populated)
Optional Test Point Access to I2C and Control pins
U2A
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Pin 1: SDA
Pin 2: SCL
Pin 4: N/C
Pin 3: N/C
Pin 5: GND
Pin 6: N/C
Pin 7: OE
Pin 8: ADD
Pin 9: N/C
Pin 10: N/C
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Configuring the Clock Output
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Configuring the Clock Output
The LMK61E2’s differential output is routed through 50-Ω, single-ended traces to SMA ports (OUTN and
OUTP) through AC-coupling capacitors. The LMK61E0M's dual LVCMOS outputs are DC coupled and
routed directly to the SMA ports through the 50-Ω traces. The output also has a series resistor (0 Ω
populated by default, R25 ad R28) and emitter resistors (150 Ω populated by default for LVPECL, R26
and R29). Common output format terminations are shown in Table 3. The output termination schematic is
shown in Figure 5.
Table 4. Output Termination Schemes
OUTPUT FORMAT
COUPLING
COMPONENT
VALUE
LVPECL
AC
(LMK61E2EVM default
configuration)
R25, R28
0Ω
R26, R29
150 Ω
C24, C25
0.01 uF
R27, R30, R31
DNP
R25, R28, C24, C25
0Ω
R26, R27, R29, R30, R31
DNP
R25, R27, R28, R30
0Ω
R31
100 Ω
C24, C25
0.01 uF
R26, R29
DNP
R25, R27, R28, R30, C24, C25
0Ω
R31
100 Ω
R25, R28
0 Ω (22 Ω optional)
R26, R29
50 Ω
C24, C25
0Ω
R27, R30, R31
DNP
R25, R28
0 Ω (22 Ω optional)
R26, R29
50 Ω
C24, C25
0.01 uF
R27, R30, R31
DNP
R25, R28
0Ω
C24, C25
0.01 uF
R26, R27, R29, R30, R31
DNP
R25, R28, C24, C25
0Ω
R26, R27, R29, R30, R31
DNP
DC (1)
LVDS (2)
AC
DC
HCSL
AC
DC
LVCMOS
AC
DC (LMK61E0MEVM
default configuration)
(1)
(2)
50 Ω to Vcc-2 V termination is required on receiver.
100-Ω differential termination (R31) is provided on the LMK61E2EVM. Removing the differential termination on the EVM is
possible if the differential termination is available on the receiver.
P2
C24
0.1µF
OUT_P
R25
OUTP
0
R31
100
R26
150
R29
150
OUT_N
R28
R30
0
C25
R_OUT_N
P3
1
0.1µF
5
4
3
2
0
R27
0
R_OUT_P
5
4
3
2
1
OUTN
Figure 5. EVM Termination Schematic
10
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Using the USB Interface Connection
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7
Using the USB Interface Connection
The onboard MSP430F5529 USB microcontroller (U4) provides an I2C host interface to the LMK61XX
slave device. The device registers can be controlled through USB using the GUI platform running on a
Host PC.
8
EVM Quick Start Guide
The following guide allows the user to quickly configure the LMK61XX to evaluate performance and device
flexibility
• 1. Set the Control Pin jumpers to the default configuration as noted in Table 1 and Table 3.
• 2. Confirm the EVM Default power configuration is set per Table 2 to power the LMK61XX in USB
POWER mode using the onboard LDO regulators and power supplied over USB.
• 3. Observe any active output clock on OUTN and OUTP SMA ports.
– 3.1. Default LMK61E2EVM configuration is AC-coupled LVPECL as noted in Table 4.
– 3.1. Default LMK61E0MEVM configuration is DC-coupled LVCMOS as noted in Table 4. By default
OUTP is enabled and OUTN is disabled.
– 3.2. Use 50-Ω coax cables to connect the test equipment to the output SMA ports. If making a
single-ended measurement, terminate the unused SMA port with a 50-Ω load.
– 3.3. Power LEDs, D3, and D5 should be illuminated when the EVM is connected to power
– 3.4. I2C activity can be seen on LED D4 (active with activity).
• 4. Refer to Table 5 for recommended device configurations configurable through the GUI.
Table 5. Recommended Device Configurations (1)
156.25 MHz (2)
PARAMETER
PLL
Reference Doubler
Enabled
N Divider
50
100 MHz
161.1328125 MHz
48
51
Fractional Numerator
22500
Fractional Denominator
Loop Filter
(1)
(2)
9
40000
VCO frequency
5000 MHz
4800 MHz
5162.25 MHz
Output Divider
32
16
32
Charge Pump Gain
6.4 mA
2.8 mA
Loop Filter Order
2nd Order
3rd Order
C1
5 pF
105 pF
C2
10 nF
C3
0 pF
35 pF
R2
800 Ω
1.1 kΩ
R3
18 Ω
1.3 kΩ
Modulator Order
Integer Mode
1st Order
Dithering
Disable
Weak
Charge Pump Bleed
None
8.5 kΩ 1 ns
Termination schemes should match device settings. See Table 4.
LMK61E2EVM Device default
Recommended Test Instruments
For making accurate measurements on ultra-low noise/jitter, high-speed clock signals, the following
instruments are recommended:
• Source Signal Analyzer: Keysight/Agilent E5052 for phase noise and jitter measurements
• Oscilloscope: Agilent DSA90000A series (or equivalent) for AC measurements and time-domain jitter
analysis with jitter software package
• Balun: M/A-COM H-183-4 (30-3000 MHz) 180° coupler, or equivalent
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Example Performance Measurements
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Example Performance Measurements
RMS Jitter and phase noise measurements were taken on the differential output clock was measured
using a balun to a Keysight/Agilent E5052B. Some phase noise plots are provided below.
Table 6. Typical Output RMS Jitter Summary
OUTPUT FREQUENCY
OUTPUT FORMAT (1)
RMS JITTER (fs),12k-20M
BAND, SPURS OFF
REFERENCE PLOT
156.25 MHz
LVPECL
90
Figure 6
LVDS
100
Figure 7
HCSL
100
LVPECL
150
LVDS
150
HCSL
150
161.1328125 MHz
(1)
Figure 8
All measurements are AC coupled with recommended board terminations as in Table 4.
Figure 6. 156.25-MHz LVPECL Differential Phase Noise
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Figure 7. 156.25-MHz LVDS Differential Phase Noise
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Example Performance Measurements
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Figure 8. 161.1328125-MHz HCSL Differential Phase Noise
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EVM Layout
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EVM Layout
Figure 9. Top Overlay
Figure 10. Top Solder Mask
Figure 11. Layer 1 (Top Side)
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EVM Layout
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Figure 12. Layer 4 (Bottom Side, View From Bottom)
Figure 13. Bottom Solder Mask
Figure 14. Bottom Overlay
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EVM Layout
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Figure 15. Drill Drawing
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EVM Schematic
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EVM Schematic
LMK61XX Evaluation Module (EVM)
DIMENSIONS:
-- Rectangular shape with height minimized (SMA spacing + board stand offs)
-- Final PCB thickness 62 mil +/- 10% ****
STACKUP:
-- Layer 1: Device layer, Power/GPIO Jumper/Switches, RF microstrip from DUT
to SMA, USB connector, Silkscreens + Labeling
===== FR4: 8 mil
-- Layer 2: Ground Plane
===== FR4: 38 mil
-- Layer 3: Split Power planes for USB circuitry and DUT circuitry
===== FR4: 8
-- Layer 4: USB circuitry
HARDWARE AND MARKINGS
LAYOUT NOTE:
PLace 4 standoffs at corners of board.
H1
H2
H3
H4
TCBS-6-01
TCBS-6-01
TCBS-6-01
TCBS-6-01
FID1
Controlled Impedance Traces
-- TOP: 13 mil traces to be 50 ohm Zo +/- 5% reference to L2
FID2
PCB
LOGO
Pb-Free Symbol
PCB
LOGO
PCB
LOGO
FCC disclaimer
LBL1
PCB Label
Texas Instruments Size: 0.65" x 0.20 "
Label Tab le
Variant
001
Label Text
LMK61E2 EVM
PCB Number: SV601195
PCB Rev: A
ASSEMBLY NOTES
ZZ1
Label Assembly Note
This Assembly Note is for PCB labels only
ZZ2
Assembly Note
These assemblies are ESD sensitive, ESD precautions shall be observed.
ZZ3
Assembly Note
These assemblies must be clean and free from flux and all contaminants. Use of no clean flux is not acceptable.
ZZ4
Assembly Note
These assemblies must comply with workmanship standards IPC-A-610 Class 2, unless otherwise specified.
ZZ5
Assembly Note
Default Shunt settings: SH1_2-3 means short Pins 2-3of J2 jumper. For 3-way jumpers, Pin 4 is the 1-pin header.
ZZ6
Assembly Note
Default Shunt settings: SH2_2-3 means short Pins 2-3 of J3 jumper. For 3-way jumpers, Pin 4 is the 1-pin header.
ZZ7
Assembly Note
Default Shunt settings: SH3_2-3 means short Pins 2-3 of J5 jumper. For 3-way jumpers, Pin 4 is the 1-pin header.
ZZ8
Assembly Note
Default Shunt settings: SH4_2-3 means short Pins 2-3 of J6 jumper. For 3-way jumpers, Pin 4 is the 1-pin header.
ZZ9
Assembly Note
Default Shunt settings: SH5_2-3 means short Pins 2-3 of J9 jumper. For 3-way jumpers, Pin 4 is the 1-pin header.
ZZ10
Assembly Note
Default Shunt settings: SH6_2-3 means short Pins 2-3 of J10 jumper. For 3-way jumpers, Pin 4 is the 1-pin header.
18
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EVM Schematic
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6
2
1
1
2
5
4
IO4
IO3
GND
33k
3
PUR
R7
1.2Meg
TPD4E004DRYR
3.3 V, 250 mA REGULATOR FOR LMK61XX
VBUS_FILT
R2
33k
FB1
60 ohm
IO2
IO1
VCC
R5
3.3 V, 150 mA REGULATOR FOR USB2ANY
VBUS
D_N
D_P
0402
0402
R4
1.5k
0402
C1
0.1µF
U3
1734035-2
R1
R3
C2
10µF
D1
1SMB5922BT3G
7.5V
C5
22µF
0805
VBUS_FILT
4
7
IN
EN
DAP
U2A_3V3
OUT
NC
NC
GND
2
5
3
C3
10µF
VUSB
3
4
BSL
C9
0.1µF
SH1_2_3
P1
LABEL SW: BSL
1
VIN
3
4
C6
10µF
D2
B220A-13-F
20V
GND
GND
C8
0.1µF
C10
1µF
GND
VDD_REG
TP2
N/C
GND
C4
1µF
2
J3
IC SUP
LP5907MFX-3.3/NOPB
LAYOUT NOTE:
Place C10 and C4 on the same side as U
C12 and as close to the package as possible. Use
0.1µF wide and short traces.
VDD
SH2_2_3
R8
510
2
I=5mA
GND
C7
1µF
R6
33k
EXTIN
VOUT
5
EN
REG SUP
EXTIN
1
EXTIN
C11
220pF
U2
3
2
1
1
LP5900SD-3.3/NOPB
S1
VDD
J2
U1
6
1
33
33
2
3
4
5
1
2 USB_N
3 USB_P
4
5
3
2
1
USB MINI-B CONNECTOR
J1
U2A_3V3
USB2ANY HEADER (VERTICAL)
ON-BOARD USB2ANY/MSP430
DNP
U2A_GPIO5
U2A_GPIO6
U2A_GPIO7
J7 connects to J5 of USB2ANY module via Ribbon cable
LABEL PINS:
1 = SDA
2 = SCL
5 = GND
6 = 3.3V
8 = OE
10 = ADD
C13
1
TP3
I2CPU
C14
2
30pF
Y1
ECS-240-20-5PX-TR
24MHz
30pF
VDD
R17
1.5k
3
2
1
U2A_GPIO4 1
OE
R16
100k
VDD
OE
R19
1.5k
LABEL PINS:
1 = GND
2 =
3 = VDD
4 = U2A
J6
ADD
9
10
69
70
12
13
55
56
P5.0/A8/VREF+/VEREF+
P5.1/A9/VREF-/VEREFP5.2/XT2IN
P5.3/XT2OUT
P5.4/XIN
P5.5/XOUT
P5.6/TB0.0
P5.7/TB0.1
P7.0/CB8/A12
P7.1/CB9/A13
P7.2/CB10/A14
P7.3/CB11/A15
P7.4/TB0.2
P7.5/TB0.3
P7.6/TB0.4
P7.7/TB0CLK/MCLK
C15
0.1µF
R18
1.5k
3
2
1
U2A_GPIO5 1
P3.0/UCB0SIMO/UCB0SDA
P3.1/UCB0SOMI/UCB0SCL
P3.2/UCB0CLK/UCA0STE
P3.3/UCA0TXD/UCA0SIMO
P3.4/UCA0RXD/UCA0SOMI
P3.5/TB0.5
P3.6/TB0.6
P3.7/TB0OUTH/SVMOUT
5
6
7
8
EXT5V_EN
57
EXT5V_FAULT 58
EXT3.3V_EN
59
EXT3.3V_FAULT 60
OE / ADD JUMPERS
LABEL PINS:
1 = GND
2 =
3 = VDD
4 = U2A
J5
37
38
39
40
41
42
43
44
V18
67
20
VCORE
C17
220pF
ADD
C18
0.47µF
VBUS
VUSB
65
66
VBUS
VUSB
11
18
50
AVCC1
DVCC1
DVCC2
U2A_3V3
R20
1.5k
V18
VCORE
SH4_2_3
GND
GND
C19
0.1µF
C20
0.1µF
2
R9
270
P4.0/PM_UCB1STE/PM_UCA1CLK
P4.1/PM_UCB1SIMO/PM_UCB1SDA
P4.2/PM_UCB1SOMI/PM_UCB1SCL
P4.3/PM_UCB1CLK/PM_UCA1STE
P4.4/PM_UCA1TXD/PM_UCA1SIMO
P4.5/PM_UCA1RXD/PM_UCA1SOMI
P4.6/PM_NONE
P4.7/PM_NONE
45
46
47
48
51
52
53
54
P6.0/CB0/A0
P6.1/CB1/A1
P6.2/CB2/A2
P6.3/CB3/A3
P6.4/CB4/A4
P6.5/CB5/A5
P6.6/CB6/A6
P6.7/CB7/A7
77
78
79
80
1
2
3
4
P8.0
P8.1
P8.2
15
16
17
PJ.0/TDO
PJ.1/TDI/TCLK
PJ.2/TMS
PJ.3/TCK
72
73
74
75
RST/NMI/SBWTDIO
TEST/SBWTCK
76
71
PU.0/DP
PU.1/DM
62
64
D_P
D_N
PUR
63
PUR
VSSU
AVSS1
AVSS2
DVSS1
DVSS2
61
14
68
19
49
MSP430F5529IPN
SH3_2_3
C21
0.1µF
SNAU188B – October 2015 – Revised August 2017
Submit Documentation Feedback
D4
Orange
I2C
0 R10 SDA
0 R12
U2A_GPIO4
0 R13
U2A_GPIO5
U2A_3V3
0 R11 SCL
SDA
SCL
1
U2A_GPIO4
U2A_GPIO3
2
4
6
8
10
29
30
31
32
33
34
35
36
2
1
3
5
7
9
P2.0/TA1.1
P2.1/TA1.2
P2.2/TA2CLK/SMCLK
P2.3/TA2.0
P2.4/TA2.1
P2.5/TA2.2
P2.6/RTCCLK/DMAE0
P2.7/UCB0STE/UCA0CLK
LAYOUT NOTE:
D5
MSP_LED Place LED on L1, other components can be on L4
Green
R14
270
3
U2A_GPIO2
P1.0/TA0CLK/ACLK
P1.1/TA0.0
P1.2/TA0.1
P1.3/TA0.2
P1.4/TA0.3
P1.5/TA0.4
P1.6/TA1CLK/CBOUT
P1.7/TA1.0
Q1
BSS138
1
U2A_3V3
R15
33k
C16
2200pF
2
21
22
23
24
25
26
27
28
SCL
J4
1
U4
SDA
D3
VDD
Green
LAYOUT NOTE:
Place 0-ohm footprints close to USB2ANY Header pins to minimize trace stubs
when 0-ohm resistors are de-populated (to disconnect the on-board MSP430).
USER NOTE:
De-populate the 0-ohm resistors connected to "U2A_GPIOx" and "U2A_3V3"
nets before attaching the External USB2ANY module to the USB2ANY Header.
USER NOTE:
Features not supported by On-board or External USB2ANY circuiry
- Switched +3.3V_EXT supply
- Switched +5V_EXT supply
- ADCs 0-4
- DACs 0-1
- PWMs 0-3
- SPI interface (I2C/SMBus only)
LMK61E2EVM, LMK61E0MEVM User's Guide
Copyright © 2015–2017, Texas Instruments Incorporated
19
EVM Schematic
www.ti.com
LMK61XX
LABEL PINS:
1 = VDD
2 =
3 = GND
VDD
LABEL PINS:
1 = VDD
2 =
3 = GND
VDD
R21
4.7k
R22
4.7k
3
2
1
SH5_2_3
VDD
J10
3
2
1
SH6_2_3
FS0
C22
0.01µF
LAYOUT NOTE:
Place shunt resistors
near the output pins.
C23
4.7µF
FS1
R23
4.7k
R24
4.7k
GND
OUT_P
GND
R25
1
6
OUTP
GND
GND
7
SDA
8
SCL
1
OUTP
SDA
OUTN
SCL
OE
5
R29
150
ADD
2
GND
3
OUT_N
R28
R30
DNP
0
P3
C25
R_OUT_N
0
1
0.1µF
5
4
3
2
OE
VCC
R31
100
R26
150
4
R27
DNP
0
R_OUT_P
0
U5
P2
C24
0.1µF
5
4
3
2
J9
ADD
LMK06001SIA
GND
20
LAYOUT NOTE:
Individual vias to
GND on shunt
resistors.
LMK61E2EVM, LMK61E0MEVM User's Guide
LAYOUT NOTE:
Place close to SMA
ports.
OUTN
SNAU188B – October 2015 – Revised August 2017
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Copyright © 2015–2017, Texas Instruments Incorporated
LMK61E2EVM Bill of Materials
www.ti.com
13
LMK61E2EVM Bill of Materials
DESIGNATOR
MFR
PART NUMBER
QTY
C1, C8, C9, C12, C15, C19, C20, CAP, CERM, 0.1 µF, 16 V, ±5%,
C21, C24, C25
X7R, 0603
DESCRIPTION
Kemet
C0603C104J4RACTU
10
C2, C3, C6
CAP, CERM, 10 µF, 10 V, ±20%,
X5R, 0603
TDK
C1608X5R1A106M
3
C4, C7, C10
CAP, CERM, 1 µF, 10 V, ±10%,
X5R, 0603
Kemet
C0603C105K8PACTU
3
C5
CAP, CERM, 22 µF, 10 V, ±20%,
X5R, 0805
Taiyo Yuden
LMK212BJ226MG-T
1
C11, C17
CAP, CERM, 220 pF, 50 V, ±1%,
C0G/NP0, 0603
AVX
06035A221FAT2A
2
C13, C14
CAP, CERM, 30 pF, 50 V, ±5%,
C0G/NP0, 0603
AVX
06035A300JAT2A
2
C16
CAP, CERM, 2200 pF, 50 V, ±10%,
X7R, 0603
Kemet
C0603C222K5RACTU
1
C18
CAP, CERM, 0.47 µF, 10 V, ±10%,
X7R, 0603
MuRata
GRM188R71A474KA61D
1
C22
CAP, CERM, 0.01 µF, 100 V, ±5%,
X7R, 0603
AVX
06031C103JAT2A
1
C23
CAP, CERM, 4.7 µF, 10 V, ±10%,
X5R, 0603
Kemet
C0603C475K8PACTU
1
D1
Diode, Zener, 7.5 V, 550 mW, SMB
ON Semiconductor
1SMB5922BT3G
1
D2
Diode, Schottky, 20 V, 2 A, SMA
Diodes Inc.
B220A-13-F
1
D3, D5
LED, Green, SMD
Lite-On
LTST-C190GKT
2
D4
LED, Orange, SMD
Lite-On
LTST-C190KFKT
1
FB1
Ferrite Bead, 60 Ω at 100 MHz, 3.5
A, 0603
TDK
MPZ1608S600A
1
H1, H2, H3, H4
HEX STANDOFF SPACER, 9.53
mm
Richco Plastics
TCBS-6-01
4
J1
Connector, Receptacle, Mini-USB
Type B, R/A, Top Mount SMT
TE Connectivity
1734035-2
1
J2, J3, J5, J6
Header, 100 mil, 3x1, Gold, TH
Samtec
TSW-103-07-G-S
4
J7, J8
Header, 100 mil, 1pos, Gold, TH
Samtec
TSW-101-07-G-S
2
J9, J10
Header, 100 mil, 3x1, Tin, TH
TE Connectivity
5-146278-3
2
P1, P2, P3
Connector, End launch SMA, 50 Ω,
SMT
Emerson Network Power
142-0701-851
3
PCB1
Printed-Circuit Board
Any
SV601195
1
Q1
MOSFET, N-CH, 50 V, 0.22 A,
SOT-23
Fairchild Semiconductor
BSS138
1
R1, R3
RES, 33 Ω, 5%, 0.063 W, 0402
Vishay-Dale
CRCW040233R0JNED
2
R2, R5, R6, R15
RES, 33 kΩ, 5%, 0.1 W, 0603
Vishay-Dale
CRCW060333K0JNEA
4
R4
RES, 1.5 kΩ, 5%, 0.063 W, 0402
Vishay-Dale
CRCW04021K50JNED
1
R7
RES, 1.2 MΩ, 5%, 0.1W, 0603
Vishay-Dale
CRCW06031M20JNEA
1
R8
RES, 510, 5%, 0.1 W, 0603
Vishay-Dale
CRCW0603510RJNEA
1
R9, R14
RES, 270 Ω, 5%, 0.1 W, 0603
Vishay-Dale
CRCW0603270RJNEA
2
R10, R11, R12, R13, R25, R28
RES, 0 ohm, 5%, 0.1 W, 0603
Vishay-Dale
CRCW06030000Z0EA
6
R16
RES, 100 kΩ, 5%, 0.1 W, 0603
Vishay-Dale
CRCW0603100KJNEA
1
R17, R18, R19, R20
RES, 1.5 kΩ, 5%, 0.1 W, 0603
Vishay-Dale
CRCW06031K50JNEA
4
R21, R22, R23, R24
RES, 4.7 k, 5%, 0.1 W, 0603
Vishay-Dale
CRCW06034K70JNEA
4
R26, R29
RES, 150, 5%, 0.1 W, 0603
Vishay-Dale
CRCW0603150RJNEA
2
R31
RES, 100, 1%, 0.1 W, 0603
Vishay-Dale
CRCW0603100RFKEA
1
S1
Switch, Tactile, SPST-NO, 0.05 A,
12 V, SMT
TE Connectivity
4-1437565-1
1
SNAU188B – October 2015 – Revised August 2017
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LMK61E2EVM, LMK61E0MEVM User's Guide
Copyright © 2015–2017, Texas Instruments Incorporated
21
LMK61E0MEVM Bill of Materials
www.ti.com
DESIGNATOR
DESCRIPTION
MFR
PART NUMBER
QTY
SH1_2_3, SH2_2_3, SH3_2_3,
SH4_2_3, SH5_2_3, SH6_2_3
Shunt, 100 mil, Gold plated, Black
3M
969102-0000-DA
6
TP2
Test Point, Miniature, Red, TH
Keystone
5000
1
TP3
Test Point, Miniature, Black, TH
Keystone
5001
1
U1
Ultra-Low Noise, 150-mA Linear
Regulator for RF/Analog Circuits
Requires No Bypass Capacitor, 6pin LLP, Pb-Free
Texas Instruments
LP5900SD-3.3/NOPB
1
U2
ULTRA-LOW NOISE, 250-mA
LINEAR REGULATOR FOR RF
AND ANALOG CIRCUITS
REQUIRES NO BYPASS
CAPACITOR, DBV0005A
Texas Instruments
LP5907MFX-3.3/NOPB
1
U3
ESD-Protection Array for HighSpeed Data Interfaces, 4 Channels,
–40 to +85 °C, 6-pin SON (DRY),
Green (RoHS & no Sb/Br)
Texas Instruments
TPD4E004DRYR
1
U4
Mixed Signal MicroController,
PN0080A
Texas Instruments
MSP430F5529IPN
1
U5
LMK61E2SIA, SIA0008B
Texas Instruments
LMK61E2-SIA
1
Y1
Crystal, 24.000 MHz, 20 pF, SMD
ECS Inc.
ECS-240-20-5PX-TR
1
MFR
PART NUMBER
QTY
C1, C8, C9, C12, C15, C19, C20, CAP, CERM, 0.1 µF, 16 V, ±5%,
C21
X7R, 0603
Kemet
C0603C104J4RACTU
8
C2, C3, C6
CAP, CERM, 10 µF, 10 V, ±20%,
X5R, 0603
TDK
C1608X5R1A106M
3
C4, C7, C10
CAP, CERM, 1 µF, 10 V, +/-10%,
X5R, 0603
Kemet
C0603C105K8PACTU
3
C5
CAP, CERM, 22 µF, 10 V, +/-20%,
X5R, 0805
Taiyo Yuden
LMK212BJ226MG-T
1
C11, C17
CAP, CERM, 220 pF, 50 V, +/-1%,
C0G/NP0, 0603
AVX
06035A221FAT2A
2
C13, C14
CAP, CERM, 30 pF, 50 V, +/- 5%,
C0G/NP0, 0603
AVX
06035A300JAT2A
2
C16
CAP, CERM, 2200 pF, 50 V, +/10%, X7R, 0603
Kemet
C0603C222K5RACTU
1
C18
CAP, CERM, 0.47 µF, 10 V, +/10%, X7R, 0603
MuRata
GRM188R71A474KA61D
1
C22
CAP, CERM, 0.01 µF, 100 V, +/5%, X7R, 0603
AVX
06031C103JAT2A
1
C23
CAP, CERM, 4.7 µF, 10 V, +/- 10%, Kemet
X5R, 0603
C0603C475K8PACTU
1
D1
Diode, Zener, 7.5 V, 550 mW, SMB
ON Semiconductor
1SMB5922BT3G
1
D2
Diode, Schottky, 20 V, 2 A, SMA
Diodes Inc.
B220A-13-F
1
D3, D5
LED, Green, SMD
Lite-On
LTST-C190GKT
2
D4
LED, Orange, SMD
Lite-On
LTST-C190KFKT
1
FB1
Ferrite Bead, 60 Ω at 100 MHz, 3.5
A, 0603
TDK
MPZ1608S600A
1
H1, H2, H3, H4
HEX STANDOFF SPACER, 9.53
mm
Richco Plastics
TCBS-6-01
4
J1
Connector, Receptacle, Mini-USB
Type B, R/A, Top Mount SMT
TE Connectivity
1734035-2
1
J2, J3, J5, J6
Header, 100 mil, 3x1, Gold, TH
Samtec
TSW-103-07-G-S
4
14
LMK61E0MEVM Bill of Materials
DESIGNATOR
22
DESCRIPTION
LMK61E2EVM, LMK61E0MEVM User's Guide
SNAU188B – October 2015 – Revised August 2017
Submit Documentation Feedback
Copyright © 2015–2017, Texas Instruments Incorporated
LMK61E0MEVM Bill of Materials
www.ti.com
DESIGNATOR
DESCRIPTION
MFR
PART NUMBER
QTY
J7, J8
Header, 100 mil, 1 pos, Gold, TH
Samtec
TSW-101-07-G-S
2
J9, J10
Header, 100 mil, 3x1, Tin, TH
TE Connectivity
5-146278-3
2
P1, P2, P3
Connector, End launch SMA, 50 Ω,
SMT
Emerson Network Power
142-0701-851
3
PCB1
Printed-Circuit Board
Any
SV601195
1
Q1
MOSFET, N-CH, 50 V, 0.22 A,
SOT-23
Fairchild Semiconductor
BSS138
1
R1, R3
RES, 33 Ω, 5%, 0.063 W, 0402
Vishay-Dale
CRCW040233R0JNED
2
R2, R5, R6, R15
RES, 33 kΩ, 5%, 0.1 W, 0603
Vishay-Dale
CRCW060333K0JNEA
4
R4
RES, 1.5 kΩ, 5%, 0.063 W, 0402
Vishay-Dale
CRCW04021K50JNED
1
R7
RES, 1.2 MΩ, 5%, 0.1 W, 0603
Vishay-Dale
CRCW06031M20JNEA
1
R8
RES, 510, 5%, 0.1 W, 0603
Vishay-Dale
CRCW0603510RJNEA
1
R9, R14
RES, 270 Ω, 5%, 0.1 W, 0603
Vishay-Dale
CRCW0603270RJNEA
2
R10, R11, R12, R13, R25, R28,
C24, C25
RES, 0 Ω, 5%, 0.1 W, 0603
Vishay-Dale
CRCW06030000Z0EA
8
R16
RES, 100 kΩ, 5%, 0.1 W, 0603
Vishay-Dale
CRCW0603100KJNEA
1
R17, R18, R19, R20
RES, 1.5 kΩ, 5%, 0.1 W, 0603
Vishay-Dale
CRCW06031K50JNEA
4
R21, R22, R23, R24
RES, 4.7 k, 5%, 0.1 W, 0603
Vishay-Dale
CRCW06034K70JNEA
4
R31
RES, 100, 1%, 0.1 W, 0603
Vishay-Dale
CRCW0603100RFKEA
1
S1
Switch, Tactile, SPST-NO, 0.05 A,
12 V, SMT
TE Connectivity
4-1437565-1
1
SH1_2_3, SH2_2_3, SH3_2_3,
SH4_2_3, SH5_2_3, SH6_2_3
Shunt, 100 mil, Gold plated, Black
3M
969102-0000-DA
6
TP2
Test Point, Miniature, Red, TH
Keystone
5000
1
TP3
Test Point, Miniature, Black, TH
Keystone
5001
1
U1
Ultra-Low Noise, 150-mA Linear
Regulator for RF/Analog Circuits
Requires No Bypass Capacitor, 6pin LLP, Pb-Free
Texas Instruments
LP5900SD-3.3/NOPB
1
U2
ULTRA-LOW NOISE, 250-mA
LINEAR REGULATOR FOR RF
AND ANALOG CIRCUITS
REQUIRES NO BYPASS
CAPACITOR, DBV0005A
Texas Instruments
LP5907MFX-3.3/NOPB
1
U3
ESD-Protection Array for HighSpeed Data Interfaces, 4 Channels,
–40 to +85°C, 6-pin SON (DRY),
Green (RoHS and no Sb/Br)
Texas Instruments
TPD4E004DRYR
1
U4
Mixed Signal MicroController,
PN0080A
Texas Instruments
MSP430F5529IPN
1
U5
LMK61E0MSIA, SIA0008B
Texas Instruments
LMK61E0M-SIA
1
Y1
Crystal, 24.000 MHz, 20 pF, SMD
ECS Inc.
ECS-240-20-5PX-TR
1
SNAU188B – October 2015 – Revised August 2017
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LMK61E2EVM, LMK61E0MEVM User's Guide
Copyright © 2015–2017, Texas Instruments Incorporated
23
Revision History
www.ti.com
Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from A Revision (January 2017) to B Revision ............................................................................................... Page
•
Changed J6 VDD (JP Default) From: 1011011b / 0x5B To: 1011010b / 0x5A in Table 3....................................... 9
Revision History
Changes from Original (October 2015) to A Revision .................................................................................................... Page
•
24
Added LMK61E0MEVM .................................................................................................................. 4
Revision History
SNAU188B – October 2015 – Revised August 2017
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Copyright © 2015–2017, Texas Instruments Incorporated
STANDARD TERMS FOR EVALUATION MODULES
1.
Delivery: TI delivers TI evaluation boards, kits, or modules, including any accompanying demonstration software, components, and/or
documentation which may be provided together or separately (collectively, an “EVM” or “EVMs”) to the User (“User”) in accordance
with the terms set forth herein. User's acceptance of the EVM is expressly subject to the following terms.
1.1 EVMs are intended solely for product or software developers for use in a research and development setting to facilitate feasibility
evaluation, experimentation, or scientific analysis of TI semiconductors products. EVMs have no direct function and are not
finished products. EVMs shall not be directly or indirectly assembled as a part or subassembly in any finished product. For
clarification, any software or software tools provided with the EVM (“Software”) shall not be subject to the terms and conditions
set forth herein but rather shall be subject to the applicable terms that accompany such Software
1.2 EVMs are not intended for consumer or household use. EVMs may not be sold, sublicensed, leased, rented, loaned, assigned,
or otherwise distributed for commercial purposes by Users, in whole or in part, or used in any finished product or production
system.
2
Limited Warranty and Related Remedies/Disclaimers:
2.1 These terms do not apply to Software. The warranty, if any, for Software is covered in the applicable Software License
Agreement.
2.2 TI warrants that the TI EVM will conform to TI's published specifications for ninety (90) days after the date TI delivers such EVM
to User. Notwithstanding the foregoing, TI shall not be liable for a nonconforming EVM if (a) the nonconformity was caused by
neglect, misuse or mistreatment by an entity other than TI, including improper installation or testing, or for any EVMs that have
been altered or modified in any way by an entity other than TI, (b) the nonconformity resulted from User's design, specifications
or instructions for such EVMs or improper system design, or (c) User has not paid on time. Testing and other quality control
techniques are used to the extent TI deems necessary. TI does not test all parameters of each EVM.
User's claims against TI under this Section 2 are void if User fails to notify TI of any apparent defects in the EVMs within ten (10)
business days after delivery, or of any hidden defects with ten (10) business days after the defect has been detected.
2.3 TI's sole liability shall be at its option to repair or replace EVMs that fail to conform to the warranty set forth above, or credit
User's account for such EVM. TI's liability under this warranty shall be limited to EVMs that are returned during the warranty
period to the address designated by TI and that are determined by TI not to conform to such warranty. If TI elects to repair or
replace such EVM, TI shall have a reasonable time to repair such EVM or provide replacements. Repaired EVMs shall be
warranted for the remainder of the original warranty period. Replaced EVMs shall be warranted for a new full ninety (90) day
warranty period.
3
Regulatory Notices:
3.1 United States
3.1.1
Notice applicable to EVMs not FCC-Approved:
FCC NOTICE: This kit is designed to allow product developers to evaluate electronic components, circuitry, or software
associated with the kit to determine whether to incorporate such items in a finished product and software developers to write
software applications for use with the end product. This kit is not a finished product and when assembled may not be resold or
otherwise marketed unless all required FCC equipment authorizations are first obtained. Operation is subject to the condition
that this product not cause harmful interference to licensed radio stations and that this product accept harmful interference.
Unless the assembled kit is designed to operate under part 15, part 18 or part 95 of this chapter, the operator of the kit must
operate under the authority of an FCC license holder or must secure an experimental authorization under part 5 of this chapter.
3.1.2
For EVMs annotated as FCC – FEDERAL COMMUNICATIONS COMMISSION Part 15 Compliant:
CAUTION
This device complies with part 15 of the FCC Rules. Operation is subject to the following two conditions: (1) This device may not
cause harmful interference, and (2) this device must accept any interference received, including interference that may cause
undesired operation.
Changes or modifications not expressly approved by the party responsible for compliance could void the user's authority to
operate the equipment.
FCC Interference Statement for Class A EVM devices
NOTE: This equipment has been tested and found to comply with the limits for a Class A digital device, pursuant to part 15 of
the FCC Rules. These limits are designed to provide reasonable protection against harmful interference when the equipment is
operated in a commercial environment. This equipment generates, uses, and can radiate radio frequency energy and, if not
installed and used in accordance with the instruction manual, may cause harmful interference to radio communications.
Operation of this equipment in a residential area is likely to cause harmful interference in which case the user will be required to
correct the interference at his own expense.
FCC Interference Statement for Class B EVM devices
NOTE: This equipment has been tested and found to comply with the limits for a Class B digital device, pursuant to part 15 of
the FCC Rules. These limits are designed to provide reasonable protection against harmful interference in a residential
installation. This equipment generates, uses and can radiate radio frequency energy and, if not installed and used in accordance
with the instructions, may cause harmful interference to radio communications. However, there is no guarantee that interference
will not occur in a particular installation. If this equipment does cause harmful interference to radio or television reception, which
can be determined by turning the equipment off and on, the user is encouraged to try to correct the interference by one or more
of the following measures:
•
•
•
•
Reorient or relocate the receiving antenna.
Increase the separation between the equipment and receiver.
Connect the equipment into an outlet on a circuit different from that to which the receiver is connected.
Consult the dealer or an experienced radio/TV technician for help.
3.2 Canada
3.2.1
For EVMs issued with an Industry Canada Certificate of Conformance to RSS-210 or RSS-247
Concerning EVMs Including Radio Transmitters:
This device complies with Industry Canada license-exempt RSSs. Operation is subject to the following two conditions:
(1) this device may not cause interference, and (2) this device must accept any interference, including interference that may
cause undesired operation of the device.
Concernant les EVMs avec appareils radio:
Le présent appareil est conforme aux CNR d'Industrie Canada applicables aux appareils radio exempts de licence. L'exploitation
est autorisée aux deux conditions suivantes: (1) l'appareil ne doit pas produire de brouillage, et (2) l'utilisateur de l'appareil doit
accepter tout brouillage radioélectrique subi, même si le brouillage est susceptible d'en compromettre le fonctionnement.
Concerning EVMs Including Detachable Antennas:
Under Industry Canada regulations, this radio transmitter may only operate using an antenna of a type and maximum (or lesser)
gain approved for the transmitter by Industry Canada. To reduce potential radio interference to other users, the antenna type
and its gain should be so chosen that the equivalent isotropically radiated power (e.i.r.p.) is not more than that necessary for
successful communication. This radio transmitter has been approved by Industry Canada to operate with the antenna types
listed in the user guide with the maximum permissible gain and required antenna impedance for each antenna type indicated.
Antenna types not included in this list, having a gain greater than the maximum gain indicated for that type, are strictly prohibited
for use with this device.
Concernant les EVMs avec antennes détachables
Conformément à la réglementation d'Industrie Canada, le présent émetteur radio peut fonctionner avec une antenne d'un type et
d'un gain maximal (ou inférieur) approuvé pour l'émetteur par Industrie Canada. Dans le but de réduire les risques de brouillage
radioélectrique à l'intention des autres utilisateurs, il faut choisir le type d'antenne et son gain de sorte que la puissance isotrope
rayonnée équivalente (p.i.r.e.) ne dépasse pas l'intensité nécessaire à l'établissement d'une communication satisfaisante. Le
présent émetteur radio a été approuvé par Industrie Canada pour fonctionner avec les types d'antenne énumérés dans le
manuel d’usage et ayant un gain admissible maximal et l'impédance requise pour chaque type d'antenne. Les types d'antenne
non inclus dans cette liste, ou dont le gain est supérieur au gain maximal indiqué, sont strictement interdits pour l'exploitation de
l'émetteur
3.3 Japan
3.3.1
Notice for EVMs delivered in Japan: Please see http://www.tij.co.jp/lsds/ti_ja/general/eStore/notice_01.page 日本国内に
輸入される評価用キット、ボードについては、次のところをご覧ください。
http://www.tij.co.jp/lsds/ti_ja/general/eStore/notice_01.page
3.3.2
Notice for Users of EVMs Considered “Radio Frequency Products” in Japan: EVMs entering Japan may not be certified
by TI as conforming to Technical Regulations of Radio Law of Japan.
If User uses EVMs in Japan, not certified to Technical Regulations of Radio Law of Japan, User is required to follow the
instructions set forth by Radio Law of Japan, which includes, but is not limited to, the instructions below with respect to EVMs
(which for the avoidance of doubt are stated strictly for convenience and should be verified by User):
1.
2.
3.
Use EVMs in a shielded room or any other test facility as defined in the notification #173 issued by Ministry of Internal
Affairs and Communications on March 28, 2006, based on Sub-section 1.1 of Article 6 of the Ministry’s Rule for
Enforcement of Radio Law of Japan,
Use EVMs only after User obtains the license of Test Radio Station as provided in Radio Law of Japan with respect to
EVMs, or
Use of EVMs only after User obtains the Technical Regulations Conformity Certification as provided in Radio Law of Japan
with respect to EVMs. Also, do not transfer EVMs, unless User gives the same notice above to the transferee. Please note
that if User does not follow the instructions above, User will be subject to penalties of Radio Law of Japan.
【無線電波を送信する製品の開発キットをお使いになる際の注意事項】 開発キットの中には技術基準適合証明を受けて
いないものがあります。 技術適合証明を受けていないもののご使用に際しては、電波法遵守のため、以下のいずれかの
措置を取っていただく必要がありますのでご注意ください。
1.
2.
3.
電波法施行規則第6条第1項第1号に基づく平成18年3月28日総務省告示第173号で定められた電波暗室等の試験設備でご使用
いただく。
実験局の免許を取得後ご使用いただく。
技術基準適合証明を取得後ご使用いただく。
なお、本製品は、上記の「ご使用にあたっての注意」を譲渡先、移転先に通知しない限り、譲渡、移転できないものとします。
上記を遵守頂けない場合は、電波法の罰則が適用される可能性があることをご留意ください。 日本テキサス・イ
ンスツルメンツ株式会社
東京都新宿区西新宿６丁目２４番１号
西新宿三井ビル
3.3.3
Notice for EVMs for Power Line Communication: Please see http://www.tij.co.jp/lsds/ti_ja/general/eStore/notice_02.page
電力線搬送波通信についての開発キットをお使いになる際の注意事項については、次のところをご覧ください。http:/
/www.tij.co.jp/lsds/ti_ja/general/eStore/notice_02.page
3.4 European Union
3.4.1
For EVMs subject to EU Directive 2014/30/EU (Electromagnetic Compatibility Directive):
This is a class A product intended for use in environments other than domestic environments that are connected to a
low-voltage power-supply network that supplies buildings used for domestic purposes. In a domestic environment this
product may cause radio interference in which case the user may be required to take adequate measures.
4
EVM Use Restrictions and Warnings:
4.1 EVMS ARE NOT FOR USE IN FUNCTIONAL SAFETY AND/OR SAFETY CRITICAL EVALUATIONS, INCLUDING BUT NOT
LIMITED TO EVALUATIONS OF LIFE SUPPORT APPLICATIONS.
4.2 User must read and apply the user guide and other available documentation provided by TI regarding the EVM prior to handling
or using the EVM, including without limitation any warning or restriction notices. The notices contain important safety information
related to, for example, temperatures and voltages.
4.3 Safety-Related Warnings and Restrictions:
4.3.1
User shall operate the EVM within TI’s recommended specifications and environmental considerations stated in the user
guide, other available documentation provided by TI, and any other applicable requirements and employ reasonable and
customary safeguards. Exceeding the specified performance ratings and specifications (including but not limited to input
and output voltage, current, power, and environmental ranges) for the EVM may cause personal injury or death, or
property damage. If there are questions concerning performance ratings and specifications, User should contact a TI
field representative prior to connecting interface electronics including input power and intended loads. Any loads applied
outside of the specified output range may also result in unintended and/or inaccurate operation and/or possible
permanent damage to the EVM and/or interface electronics. Please consult the EVM user guide prior to connecting any
load to the EVM output. If there is uncertainty as to the load specification, please contact a TI field representative.
During normal operation, even with the inputs and outputs kept within the specified allowable ranges, some circuit
components may have elevated case temperatures. These components include but are not limited to linear regulators,
switching transistors, pass transistors, current sense resistors, and heat sinks, which can be identified using the
information in the associated documentation. When working with the EVM, please be aware that the EVM may become
very warm.
4.3.2
EVMs are intended solely for use by technically qualified, professional electronics experts who are familiar with the
dangers and application risks associated with handling electrical mechanical components, systems, and subsystems.
User assumes all responsibility and liability for proper and safe handling and use of the EVM by User or its employees,
affiliates, contractors or designees. User assumes all responsibility and liability to ensure that any interfaces (electronic
and/or mechanical) between the EVM and any human body are designed with suitable isolation and means to safely
limit accessible leakage currents to minimize the risk of electrical shock hazard. User assumes all responsibility and
liability for any improper or unsafe handling or use of the EVM by User or its employees, affiliates, contractors or
designees.
4.4 User assumes all responsibility and liability to determine whether the EVM is subject to any applicable international, federal,
state, or local laws and regulations related to User’s handling and use of the EVM and, if applicable, User assumes all
responsibility and liability for compliance in all respects with such laws and regulations. User assumes all responsibility and
liability for proper disposal and recycling of the EVM consistent with all applicable international, federal, state, and local
requirements.
5.
Accuracy of Information: To the extent TI provides information on the availability and function of EVMs, TI attempts to be as accurate
as possible. However, TI does not warrant the accuracy of EVM descriptions, EVM availability or other information on its websites as
accurate, complete, reliable, current, or error-free.
6.
Disclaimers:
6.1 EXCEPT AS SET FORTH ABOVE, EVMS AND ANY MATERIALS PROVIDED WITH THE EVM (INCLUDING, BUT NOT
LIMITED TO, REFERENCE DESIGNS AND THE DESIGN OF THE EVM ITSELF) ARE PROVIDED "AS IS" AND "WITH ALL
FAULTS." TI DISCLAIMS ALL OTHER WARRANTIES, EXPRESS OR IMPLIED, REGARDING SUCH ITEMS, INCLUDING BUT
NOT LIMITED TO ANY EPIDEMIC FAILURE WARRANTY OR IMPLIED WARRANTIES OF MERCHANTABILITY OR FITNESS
FOR A PARTICULAR PURPOSE OR NON-INFRINGEMENT OF ANY THIRD PARTY PATENTS, COPYRIGHTS, TRADE
SECRETS OR OTHER INTELLECTUAL PROPERTY RIGHTS.
6.2 EXCEPT FOR THE LIMITED RIGHT TO USE THE EVM SET FORTH HEREIN, NOTHING IN THESE TERMS SHALL BE
CONSTRUED AS GRANTING OR CONFERRING ANY RIGHTS BY LICENSE, PATENT, OR ANY OTHER INDUSTRIAL OR
INTELLECTUAL PROPERTY RIGHT OF TI, ITS SUPPLIERS/LICENSORS OR ANY OTHER THIRD PARTY, TO USE THE
EVM IN ANY FINISHED END-USER OR READY-TO-USE FINAL PRODUCT, OR FOR ANY INVENTION, DISCOVERY OR
IMPROVEMENT, REGARDLESS OF WHEN MADE, CONCEIVED OR ACQUIRED.
7.
USER'S INDEMNITY OBLIGATIONS AND REPRESENTATIONS. USER WILL DEFEND, INDEMNIFY AND HOLD TI, ITS
LICENSORS AND THEIR REPRESENTATIVES HARMLESS FROM AND AGAINST ANY AND ALL CLAIMS, DAMAGES, LOSSES,
EXPENSES, COSTS AND LIABILITIES (COLLECTIVELY, "CLAIMS") ARISING OUT OF OR IN CONNECTION WITH ANY
HANDLING OR USE OF THE EVM THAT IS NOT IN ACCORDANCE WITH THESE TERMS. THIS OBLIGATION SHALL APPLY
WHETHER CLAIMS ARISE UNDER STATUTE, REGULATION, OR THE LAW OF TORT, CONTRACT OR ANY OTHER LEGAL
THEORY, AND EVEN IF THE EVM FAILS TO PERFORM AS DESCRIBED OR EXPECTED.
8.
Limitations on Damages and Liability:
8.1 General Limitations. IN NO EVENT SHALL TI BE LIABLE FOR ANY SPECIAL, COLLATERAL, INDIRECT, PUNITIVE,
INCIDENTAL, CONSEQUENTIAL, OR EXEMPLARY DAMAGES IN CONNECTION WITH OR ARISING OUT OF THESE
TERMS OR THE USE OF THE EVMS , REGARDLESS OF WHETHER TI HAS BEEN ADVISED OF THE POSSIBILITY OF
SUCH DAMAGES. EXCLUDED DAMAGES INCLUDE, BUT ARE NOT LIMITED TO, COST OF REMOVAL OR
REINSTALLATION, ANCILLARY COSTS TO THE PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES, RETESTING,
OUTSIDE COMPUTER TIME, LABOR COSTS, LOSS OF GOODWILL, LOSS OF PROFITS, LOSS OF SAVINGS, LOSS OF
USE, LOSS OF DATA, OR BUSINESS INTERRUPTION. NO CLAIM, SUIT OR ACTION SHALL BE BROUGHT AGAINST TI
MORE THAN TWELVE (12) MONTHS AFTER THE EVENT THAT GAVE RISE TO THE CAUSE OF ACTION HAS
OCCURRED.
8.2 Specific Limitations. IN NO EVENT SHALL TI'S AGGREGATE LIABILITY FROM ANY USE OF AN EVM PROVIDED
HEREUNDER, INCLUDING FROM ANY WARRANTY, INDEMITY OR OTHER OBLIGATION ARISING OUT OF OR IN
CONNECTION WITH THESE TERMS, , EXCEED THE TOTAL AMOUNT PAID TO TI BY USER FOR THE PARTICULAR
EVM(S) AT ISSUE DURING THE PRIOR TWELVE (12) MONTHS WITH RESPECT TO WHICH LOSSES OR DAMAGES ARE
CLAIMED. THE EXISTENCE OF MORE THAN ONE CLAIM SHALL NOT ENLARGE OR EXTEND THIS LIMIT.
9.
Return Policy. Except as otherwise provided, TI does not offer any refunds, returns, or exchanges. Furthermore, no return of EVM(s)
will be accepted if the package has been opened and no return of the EVM(s) will be accepted if they are damaged or otherwise not in
a resalable condition. If User feels it has been incorrectly charged for the EVM(s) it ordered or that delivery violates the applicable
order, User should contact TI. All refunds will be made in full within thirty (30) working days from the return of the components(s),
excluding any postage or packaging costs.
10. Governing Law: These terms and conditions shall be governed by and interpreted in accordance with the laws of the State of Texas,
without reference to conflict-of-laws principles. User agrees that non-exclusive jurisdiction for any dispute arising out of or relating to
these terms and conditions lies within courts located in the State of Texas and consents to venue in Dallas County, Texas.
Notwithstanding the foregoing, any judgment may be enforced in any United States or foreign court, and TI may seek injunctive relief
in any United States or foreign court.
Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265
Copyright © 2017, Texas Instruments Incorporated
IMPORTANT NOTICE FOR TI DESIGN INFORMATION AND RESOURCES
Texas Instruments Incorporated (‘TI”) technical, application or other design advice, services or information, including, but not limited to,
reference designs and materials relating to evaluation modules, (collectively, “TI Resources”) are intended to assist designers who are
developing applications that incorporate TI products; by downloading, accessing or using any particular TI Resource in any way, you
(individually or, if you are acting on behalf of a company, your company) agree to use it solely for this purpose and subject to the terms of
this Notice.
TI’s provision of TI Resources does not expand or otherwise alter TI’s applicable published warranties or warranty disclaimers for TI
products, and no additional obligations or liabilities arise from TI providing such TI Resources. TI reserves the right to make corrections,
enhancements, improvements and other changes to its TI Resources.
You understand and agree that you remain responsible for using your independent analysis, evaluation and judgment in designing your
applications and that you have full and exclusive responsibility to assure the safety of your applications and compliance of your applications
(and of all TI products used in or for your applications) with all applicable regulations, laws and other applicable requirements. You
represent that, with respect to your applications, you have all the necessary expertise to create and implement safeguards that (1)
anticipate dangerous consequences of failures, (2) monitor failures and their consequences, and (3) lessen the likelihood of failures that
might cause harm and take appropriate actions. You agree that prior to using or distributing any applications that include TI products, you
will thoroughly test such applications and the functionality of such TI products as used in such applications. TI has not conducted any
testing other than that specifically described in the published documentation for a particular TI Resource.
You are authorized to use, copy and modify any individual TI Resource only in connection with the development of applications that include
the TI product(s) identified in such TI Resource. NO OTHER LICENSE, EXPRESS OR IMPLIED, BY ESTOPPEL OR OTHERWISE TO
ANY OTHER TI INTELLECTUAL PROPERTY RIGHT, AND NO LICENSE TO ANY TECHNOLOGY OR INTELLECTUAL PROPERTY
RIGHT OF TI OR ANY THIRD PARTY IS GRANTED HEREIN, including but not limited to any patent right, copyright, mask work right, or
other intellectual property right relating to any combination, machine, or process in which TI products or services are used. Information
regarding or referencing third-party products or services does not constitute a license to use such products or services, or a warranty or
endorsement thereof. Use of TI Resources may require a license from a third party under the patents or other intellectual property of the
third party, or a license from TI under the patents or other intellectual property of TI.
TI RESOURCES ARE PROVIDED “AS IS” AND WITH ALL FAULTS. TI DISCLAIMS ALL OTHER WARRANTIES OR
REPRESENTATIONS, EXPRESS OR IMPLIED, REGARDING TI RESOURCES OR USE THEREOF, INCLUDING BUT NOT LIMITED TO
ACCURACY OR COMPLETENESS, TITLE, ANY EPIDEMIC FAILURE WARRANTY AND ANY IMPLIED WARRANTIES OF
MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, AND NON-INFRINGEMENT OF ANY THIRD PARTY INTELLECTUAL
PROPERTY RIGHTS.
TI SHALL NOT BE LIABLE FOR AND SHALL NOT DEFEND OR INDEMNIFY YOU AGAINST ANY CLAIM, INCLUDING BUT NOT
LIMITED TO ANY INFRINGEMENT CLAIM THAT RELATES TO OR IS BASED ON ANY COMBINATION OF PRODUCTS EVEN IF
DESCRIBED IN TI RESOURCES OR OTHERWISE. IN NO EVENT SHALL TI BE LIABLE FOR ANY ACTUAL, DIRECT, SPECIAL,
COLLATERAL, INDIRECT, PUNITIVE, INCIDENTAL, CONSEQUENTIAL OR EXEMPLARY DAMAGES IN CONNECTION WITH OR
ARISING OUT OF TI RESOURCES OR USE THEREOF, AND REGARDLESS OF WHETHER TI HAS BEEN ADVISED OF THE
POSSIBILITY OF SUCH DAMAGES.
You agree to fully indemnify TI and its representatives against any damages, costs, losses, and/or liabilities arising out of your noncompliance with the terms and provisions of this Notice.
This Notice applies to TI Resources. Additional terms apply to the use and purchase of certain types of materials, TI products and services.
These include; without limitation, TI’s standard terms for semiconductor products http://www.ti.com/sc/docs/stdterms.htm), evaluation
modules, and samples (http://www.ti.com/sc/docs/sampterms.htm).
Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265
Copyright © 2017, Texas Instruments Incorporated
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