LMK6EVM

www.ti.com User’s Guide LMK6EVM User's Guide ABSTRACT The LMK6EVM provides a complete evaluation platform to evaluate the clock performance and flexibility of the Texas Instruments LMK6x Ultra-Low Jitter BAW Oscillator family. This EVM can be used as a flexible clock source for compliance testing, performance evaluation, and initial system prototyping. The onboard edge-launch SMA ports provide access to the configurable clock output of the LMK6x, which allows the device to interface with test equipment and reference boards using commercially available coaxial cables, adapters, or baluns (not included). The LMK6x is a lower-power clock oscillator using TI's BAW technology. The LMK6x is available in two package sizes, DLE (3.2 mm × 2.5 mm) and DLF (2.5 mm × 2.0 mm), and four different output formats: LVCMOS, LVPECL, LVDS, and HCSL. Both footprints are included on the EVM with independent termination networks. The termination scheme can be modified by the user for the desired output format. The LMK6EVM is not populated with an LMK6x device, so the user can choose the desired variant for evaluation. Figure 1-1. LMK6EVM Evaluation Board SNAU277A – APRIL 2022 – REVISED DECEMBER 2022 Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated LMK6EVM User's Guide 1 Table of Contents www.ti.com Table of Contents 1 Introduction.............................................................................................................................................................................3 1.1 Evaluation Module Contents.............................................................................................................................................. 3 1.2 Evaluation Setup Requirement.......................................................................................................................................... 3 1.3 Resources.......................................................................................................................................................................... 3 2 Setup........................................................................................................................................................................................4 2.1 Connection Diagram.......................................................................................................................................................... 4 2.2 Power Supply..................................................................................................................................................................... 4 2.3 Clock Output...................................................................................................................................................................... 4 2.4 EVM Strap Options............................................................................................................................................................ 5 2.5 Configuring the Clock Output Termination......................................................................................................................... 5 3 Typical Measurement..............................................................................................................................................................7 3.1 Phase Noise.......................................................................................................................................................................7 4 Schematic................................................................................................................................................................................8 5 PCB Layout and Layer Stack-Up...........................................................................................................................................9 5.1 PCB Layer Stack-Up.......................................................................................................................................................... 9 5.2 PCB Layout........................................................................................................................................................................ 9 6 Bill of Materials..................................................................................................................................................................... 10 7 Revision History....................................................................................................................................................................11 2 LMK6EVM User's Guide SNAU277A – APRIL 2022 – REVISED DECEMBER 2022 Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated www.ti.com Trademarks Trademarks All trademarks are the property of their respective owners. 1 Introduction 1.1 Evaluation Module Contents The box contains: • One LMK6EVM board (DCC222A) 1.2 Evaluation Setup Requirement The evaluation requires the following hardware: • A DC power supply • An oscilloscope • A signal analyzer (optional) • A LMK6x Device 1.3 Resources See the LMK6x Low Jitter, High-Performance BAW Oscillator data sheet for more information about the LMK6x devices. SNAU277A – APRIL 2022 – REVISED DECEMBER 2022 Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated LMK6EVM User's Guide 3 Setup www.ti.com 2 Setup 2.1 Connection Diagram Figure 2-1 shows the LMK6EVM (DCC222A) connection diagram. To test LMK6xDLF variants (DLF 2.5 mm × 2.0 mm package), the device should be soldered on Y1 and P1, and P2 can be connected to an oscilloscope or phase noise analyzer to evaluate the device output. Similarly for LMK6xDLE variants (DLE 3.2 mm × 2.5 mm package), the device should be soldered on Y2 and P3, and P4 will be used accordingly to measure the output. Note that for LMK6C variants with an LVCMOS output format, only the positive clock output connection will be used. The 4-pin LMK6C variants can share the same footprint as the 6-pin LMK6D/P/H variants. The corner pins are shared, but the middle pins are left unused for the LMK6C devices. Figure 2-1. Connection Diagram 2.2 Power Supply Apply 4 V to the VDDin SMA connector (P5). The onboard voltage regulator will provide 1.8 V, 2.5 V, or 3.3 V to the LMK6X devices based on the jumper selection on J6. 2.3 Clock Output To test the clock output of Y1, connect P1 (+) and P2 (–) SMA connectors to an oscilloscope or phase noise analyzer. To test the clock output of Y2, use P3 (–) and P4 (+). The output frequency, amplitude, and common-mode voltage will depend on the LMK6x variant that is attached to the board, as well as the termination scheme. 4 LMK6EVM User's Guide SNAU277A – APRIL 2022 – REVISED DECEMBER 2022 Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated www.ti.com Setup 2.4 EVM Strap Options 2.4.1 J1 Header Put the short across J1 to provide the supply voltage to Y1. 2.4.2 J2 Header J2 is used to pull pin 1 and pin 2 of Y1 to VDD/GND to select the output enable (OE) pin of the LMK6x device. LMK6PA/LMK6DA/LMK6HA variants use pin 1 for OE, and LMK6PB/ LMK6DB/LMK6HB variants use pin 2. All 4-pin LMK6C variants use pin 1 for OE. 2.4.3 J3 Header Put the short across J3 to provide the supply voltage to Y2. 2.4.4 J4 Header J4 is used to pull pin 1 and pin 2 of Y2 to VDD/Gnd to select the output enable (OE) pin of the LMK6x device. The LMK6PA/LMK6DA/LMK6HA variants use pin 1 for OE, and the LMK6PB/ LMK6DB/LMK6HB variants use pin 2. All 4-pin LMK6C variants use pin 1 for OE. 2.4.5 J5 Header To use the onboard voltage regulator for the LMK6x device, put the short across pin 1 and pin 2 of the J5 header. Otherwise, put the short across pin 2 and pin 3 of the J5 header to use the external power supply directly. 2.4.6 J6 Header J6 is used to select the output voltage of the onboard voltage regulator. 2.5 Configuring the Clock Output Termination The LMK6EVM comes pre-populated with an AC-coupled LVCMOS termination. The termination can be modified by the user to support LVPECL, LVDS, and HCSL output formats according to the component values in the table below. Table 2-1. Output Termination Schemes for Y1 OUTPUT FORMAT COUPLING LVPECL AC DC(1) LVDS (2) AC DC COMPONENT VALUE R1, R5 0Ω R2, R4 150 Ω C1, C4 0.01 uF R3 DNP R1, R5, C1, C4 0Ω R2, R3, R4 DNP R1, R5 0Ω R3 100 Ω C1, C4 0.01 uF R2, R4 DNP R1, R5, C1, C4 0Ω R3 100 Ω R2, R4 DNP SNAU277A – APRIL 2022 – REVISED DECEMBER 2022 Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated LMK6EVM User's Guide 5 Setup www.ti.com Table 2-1. Output Termination Schemes for Y1 (continued) OUTPUT FORMAT COUPLING HCSL AC DC (1) (2) COMPONENT VALUE R1, R5 0Ω R2, R4 50 Ω C1, C4 0.01 uF R3 DNP R1, R5, C1, C4 0Ω R2, R4 50 Ω R3 DNP 50 Ω to Vcc – 2 V termination is required on the receiver 100-Ω differential termination (R3) is provided on the LMK6EVM. Removing the differential termination on the EVM is possible if the differential termination is available on the receiver Table 2-2. Output Termination Schemes for Y2 OUTPUT FORMAT COUPLING LVPECL AC DC(1) LVDS(2) AC DC HCSL AC DC (1) (2) 6 COMPONENT VALUE R10, R16 0Ω R11, R15 150 Ω C5, C8 0.01 uF R12 DNP R10, R16, C5, C8 0Ω R11, R12, R15 DNP R10, R16 0Ω R12 100 Ω C5, C8 0.01 uF R11, R15 DNP R10, R16, C5, C8 0Ω R12 100 Ω R11, R15 DNP R10, R16 0Ω R11, R15 50 Ω C5, C10 0.01 uF R12 DNP R10, R16, C5, C8 0Ω R11, R15 50 Ω R12 DNP 50 Ω to Vcc - 2 V termination is required on the receiver 100-Ω differential termination (R3) is provided on the LMK6EVM. Removing the differential termination on the EVM is possible if the differential termination is available on the receiver LMK6EVM User's Guide SNAU277A – APRIL 2022 – REVISED DECEMBER 2022 Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated www.ti.com Typical Measurement 3 Typical Measurement 3.1 Phase Noise Figure 3-1 shows the typical phase noise for the LMK6EVM populated with the 156.25-MHz variant of the LMK6H/LMK6P. Figure 3-1. LMK6E6EVM Phase Noise SNAU277A – APRIL 2022 – REVISED DECEMBER 2022 Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated LMK6EVM User's Guide 7 Schematic www.ti.com 4 Schematic Figure 4-1. Schematic 8 LMK6EVM User's Guide SNAU277A – APRIL 2022 – REVISED DECEMBER 2022 Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated www.ti.com PCB Layout and Layer Stack-Up 5 PCB Layout and Layer Stack-Up 5.1 PCB Layer Stack-Up Figure 5-1. PCB Layer Stack-Up 5.2 PCB Layout Figure 5-2. Top Layer Figure 5-3. GND Layer Figure 5-4. GND Layer Figure 5-5. Bottom Layer SNAU277A – APRIL 2022 – REVISED DECEMBER 2022 Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated LMK6EVM User's Guide 9 Bill of Materials www.ti.com 6 Bill of Materials Designator Description C1, C4, C8, C12, C14 Manufacturer PartNumber Quantity CAP, CERM, 0.1 uF, 16 V, Kemet +/- 5%, X7R, 0603 C0603C104J4RACTU 5 C2, C7 CAP, CERM, 0.01 uF, 100 AVX V, +/- 5%, X7R, 0603 06031C103JAT2A 2 C3, C6, C11 CAP, CERM, 1 µF, 16 V,+/10%, X7R, AEC-Q200 TDK Grade 1, 0603 CGA3E1X7R1C105K080A 3 C C9, C10 CAP, CERM, 10 uF, 16 V, +/- 20%, X7R, 0805 Taiyo Yuden EMK212BB7106MG-T 2 C13 CAP, CERM, 0.01 uF, 50 V, +/- 5%, X7R, 0603 Kemet C0603C103J5RACTU 1 D1, D2 LED, Green, SMD Lite-On LTST-C190GKT 2 H1, H2, H3, H4 Machine Screw, Round, #4-40 x 1/4, Nylon, Philips B&F Fastener Supply panhead NY PMS 440 0025 PH 4 H5, H6, H7, H8 Standoff, Hex, 0.5"L #4-40 Keystone Nylon 1902C 4 J1, J3 Header, 100mil, 2x1, Gold, Samtec TH TSW-102-07-G-S 2 J2, J4, J6 Header, 2.54mm, 3x2, Gold, Black, SMT GBC03DABN-M30 3 J5 Header, 100mil, 3x1, Gold, Samtec TH TSW-103-07-G-S 1 LBL1 Thermal Transfer Printable Labels, 0.650" W x 0.200" Brady H - 10,000 per roll THT-14-423-10 1 P1, P2, P3, P4, P5 Connector, End launch SMA, 50 ohm, SMT Cinch Connectivity 142-0701-851 5 Vishay-Dale CRCW06030000Z0EA 8 R6, R7, R13, R14 RES, 220, 5%, 0.1 W, Vishay-Dale AEC-Q200 Grade 0, 0603 CRCW0603220RJNEA 4 R19, R20 RES, 120, 5%, 0.1 W, Vishay-Dale AEC-Q200 Grade 0, 0603 CRCW0603120RJNEA 2 R21 RES, 1.87 k, 1%, 0.1 W, Vishay-Dale AEC-Q200 Grade 0, 0603 CRCW06031K87FKEA 1 R22 RES, 2.43 k, 1%, 0.1 W, Vishay-Dale AEC-Q200 Grade 0, 0603 CRCW06032K43FKEA 1 R23 RES, 3.57 k, 1%, 0.1 W, Vishay-Dale AEC-Q200 Grade 0, 0603 CRCW06033K57FKEA 1 R24 RES, 1.50 k, 1%, 0.1 W, Vishay-Dale AEC-Q200 Grade 0, 0603 CRCW06031K50FKEA 1 R25, R26 RES, 1.15 k, 1%, 0.1 W, Vishay-Dale AEC-Q200 Grade 0, 0603 CRCW06031K15FKEA 2 R1, R5, R8, R9, R10, R16, RES, 0, 5%, 0.1 W, AECR17, R18 Q200 Grade 0, 0603 10 LMK6EVM User's Guide Sullins Connector Solutions SNAU277A – APRIL 2022 – REVISED DECEMBER 2022 Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated www.ti.com Designator Revision History Description SH-J1, SH-J2, SH-J3, SH- Shunt, 100mil, Gold J4, SH-J5, SH-J6 plated, Black Manufacturer PartNumber Quantity Samtec SNT-100-BK-G 6 5019 6 TPS7A9001DSKR 1 TP1, TP2, TP3, TP4, TP5, Test Point, Miniature, SMT Keystone TP6 U1 500mA High-Accuracy Low-Noise Low-Dropout (LDO) Voltage Regulator, DSK0010A (WSON-10) C5 CAP, CERM, 0.1 uF, 16 V, Kemet +/- 5%, X7R, 0603 C0603C104J4RACTU 0 FID1, FID2, FID3 Fiducial mark. There is nothing to buy or mount. N/A 0 R2, R4, R11, R15 RES, 150, 5%, 0.1 W, Vishay-Dale AEC-Q200 Grade 0, 0603 CRCW0603150RJNEA 0 R3, R12 RES, 100, 1%, 0.1 W, Vishay-Dale AEC-Q200 Grade 0, 0603 CRCW0603100RFKEA 0 Y1 High-Performance BAW Oscillator;