LMP7312
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SNOSB32B – MARCH 2010 – REVISED MARCH 2013
LMP7312 Precision SPI-Programmable AFE with Differential/Single-Ended Input/Output
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FEATURES
DESCRIPTION
1
•
•
•
2
•
•
•
•
•
•
•
•
•
•
+
-
Typical Values, TA = 25°C, V =5V, V =0V.
Gain Bandwidth 1 MHz
Input Voltage Range (G= 0.096 V/V) -15V to
+15V
Core Op-Amp Input Offset Voltage 100 µV
(Max)
Supply Current 2 mA (Max)
Gain (Attenuation Mode) 0.096 V/V, 0.192
V/V0.384 V/V, 0.768 V/V
Gain (Amplification Mode) 1 V/V, 2 V/V
Gain Error 0.035% (Max)
Core Op-Amp PSRR 90 dB (Min)
CMRR 80 dB (min)
Adjustable Output Common Mode 1V to 4V
Temperature Range −40 to 125°C
Package 14-Pin SOIC
APPLICATIONS
•
•
•
•
•
•
Signal Conditioning AFE
– ±10V; ±5V; 0-5V; 0-10V; 0-20mA; 4-20mA
Data Acquisition Systems
Motor Control
Instrument and Process Control
Remote Sensing
Programmable Automation Control
The LMP7312 is a digitally programmable variable
gain amplifier/attenuator. Its wide input voltage range
and superior precision make it a prime choice for
applications requiring high accuracy such as data
acquisition systems for IO modules in programmable
logic control (PLC). The LMP7312 provides a
differential output to maximize dynamic range and
signal to noise ratio, thereby reducing the overall
system error. It can also be configured to handle
single ended input data converters by means of the
VOCM pin (see Application Section for details). The
inputs of LMP7312 can be configured in attenuation
mode to handle large input signals of up to +/- 15V,
as well as in amplification mode to handle current
loops of 0-20mA and 4-20mA.The LMP7312 is
equipped with a null switch to evaluate the offset of
the internal amplifier. A ensured 0.035% maximum
gain error (for all gains) and a maximum gain drift of
5ppm over the extended industrial temperature range
(-40° to 125°C) make the LMP7312 very attractive for
high precision systems even under harsh conditions.
A low input offset voltage of 100µV and low voltage
noise of 3µVpp give the LMP7312 a superior
performance. The LMP7312 is fully specified from 40° to 125°C and is available in SOIC-14 package.
1
2
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
All trademarks are the property of their respective owners.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2010–2013, Texas Instruments Incorporated
LMP7312
SNOSB32B – MARCH 2010 – REVISED MARCH 2013
www.ti.com
Typical Application
+
V
VIO
SCK
CS
SDI
SDO
Sensor
-VIN
-IN
R1N
RFP
R2N
VREF
+VOUT
+
V ADC
-
+
-
Driver
SPI
Controller
RS
ADC
+IN
IS 4-20 mA
+VIN
+
-VOUT/VR
R2P
R1P
V
VCM
+
RF
100 k:
N
VOCM
100 k:
-
V
-
V
+
LMP™ is a trademark of Texas Instruments Corporation.
2
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These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
Absolute Maximum Ratings
ESD Rating
(1) (2)
(3)
Human Body Model
2000V
Machine Body Model
150V
Charge device Model
1000V
Analog Supply Voltage (VS = V+ - V-)
6V
DigitaI Supply Voltage (VDIO=VIO-V-)
6V
-
Attenuation pins -VIN, +VIN referred to V
±17.5V
Amplification pins -IN, +IN referred to V-
±10V
Voltage at all other pins referred to V-
6V
Storage Temperature Range
For soldering specification:
-65°C to 150°C
http://www.ti.com/lit/SNOA549
Junction Temperature
(1)
150°C
Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for
which the device is intended to be functional, but for which specific performance is not ensured. For ensured specifications and the test
conditions, see Electrical Characteristics.
If Military/Aerospace specified devices are required, please contact the Texas Instruments Sales Office/ Distributors for availability and
specifications.
Human Body Model, applicable std. MIL-STD-883, Method 3015.7. Machine Model, applicable std. JESD22–A115–A (ESD MM std. of
JEDEC). Field-Induced Charge-Device Model, applicable std. JESD22–C101–C (ESD FICDM std. of JEDEC).
(2)
(3)
Operating Ratings
(1)
Analog Supply Voltage (VS = V+ – V-), V-=0V
4.5V to 5.5V
Digital Supply Voltage (VDIO = VIO– V-), V-=0V
2.7V to 5.5V
Attenuation pins -VIN, +VIN referred to V-
-15V to 15V
-
Amplification pins -IN, +IN referred to V
Temperature Range
-2.35V to 7.35V
(2)
Package Thermal Resistance
−40°C to 125°C
(2)
SOIC-14
(1)
(2)
145°C/W
Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for
which the device is intended to be functional, but for which specific performance is not ensured. For ensured specifications and the test
conditions, see Electrical Characteristics.
The maximum power dissipation is a function of TJ(max), θJA. The maximum allowable power dissipation at any ambient temperature
is: PD(max) = (TJ(max) – TA)/ θJA. All numbers apply for packages soldered directly onto a PC Board.
5V Electrical Characteristics
(1)
Unless otherwise specified, all limits ensured for TA = 25°C, V+ = 5V, VIO = 5V, V− = 0V, G = 0.192 V/V, VCM_ATT=(+VIN+(VIN))/2, VCM_AMP=(+IN+(-IN))/2. Differential output configuration. SE = Single Ended Output, DE = Differential Output.Boldface
limits apply at the temperature extremes.
Symbol
VOS
(1)
(2)
(3)
Parameter
Core op-amp Input
Offset Voltage
Conditions
Min
(2)
Typ
(3)
Max
(2)
Nulling Switch Mode, DE, VOCM = 1V;
Nulling switch Mode, SE, -VOUT/VR = 1V
–100
–250
100
250
Nulling Switch Mode, DE, VOCM = 4V;
Nulling Switch Mode, SE, -VOUT/VR = 4V
–100
–250
100
250
Units
µV
Electrical Table values apply only for factory testing conditions at the temperature indicated. Factory testing conditions result in very
limited self-heating of the device such that TJ = TA. No ensured specification of parametric performance is indicated in the electrical
tables under conditions of internal self-heating where TJ > TA.
All limits are specified by testing, design, or statistical analysis.
Typical values represent the most likely parametric norm at the time of characterization. Actual typical values may vary over time and
will also depend on the application and configuration. The typical values are not tested and are not ensured on shipped production
material.
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5V Electrical Characteristics (1) (continued)
Unless otherwise specified, all limits ensured for TA = 25°C, V+ = 5V, VIO = 5V, V− = 0V, G = 0.192 V/V, VCM_ATT=(+VIN+(VIN))/2, VCM_AMP=(+IN+(-IN))/2. Differential output configuration. SE = Single Ended Output, DE = Differential Output.Boldface
limits apply at the temperature extremes.
Symbol
TCVOS
Parameter
Conditions
Core op-amp Input
Offset Voltage (4)
Max
3
Nulling Switch Mode, DE, VOCM = 4V;
Nulling Switch Mode, SE, -VOUT/VR = 4V
-3
±1.5
3
SE / DE
Core op-amp Voltage
Noise Density
RTI, Nulling Switch Mode, f = 10 kHz
Core op-amp Peak to
Peak Voltage Noise
RTI, Nulling Switch Mode, f= 0.1Hz to 10Hz
IVA
Analog Supply Current
+VIN = −VIN = VOCM
IVIO
Digital Supply Current
Without any load connected to SDO pin
RIN_CM
CM Input Resistance
G= 0.192 V/V
–0.035
–0.045
-5
(2)
Units
µV/°C
0.035
0.045
%
5
ppm/°C
±1
7.25
nV/√Hz
3
µVPP
2
mA
120
μA
62.08
G= 1 V/V
Differential Input
Resistance
(3)
±1.5
Gain Drift
RIN_DIFF
Typ
-3
All gains, RL = 10 kΩ, CL = 50pF, SE / DE
en
(2)
Nulling Switch Mode, DE, VOCM = 1V;
Nulling Switch Mode, SE, -VOUT/VR = 1V
Gain Error
Av
Min
kΩ
40
G= 0.192 V/V
248.3
G= 1 V/V
kΩ
160
G= 0.096V/V, -15V < VCM_ATT < 15V, SE / DE
G= 0.192V/V, -11.4V < VCM_ATT < 15V, SE / DE
G= 0.384V/V, -6V < VCM_ATT < 11V, SE / DE
DC Common Mode
Rejection Ratio
CMRR
G= 0.768V/V, -3V < VCM_ATT < 8V, SE / DE
80
77
dB
90
dB
G= 1V/V, -2.3V < VCM_AMP < 7.3V, SE / DE
G= 2V/V, -1.15V < VCM_AMP < 6.15V, SE / DE.
PSRR
Core op-amp DC
Nulling Switch Mode, 4.5V 0 , VAC 0
Where VAC = -VIN ± (+VIN)
-
V
Figure 36. Unipolar Input Signal to Single-Ended ADC Interface
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INPUT VOLTAGE RANGE
The LMP7312 has an internal OpAmp with rail-to-rail input voltage range capability. The requirement to stay
within the V-and V+ rail at the OpAmp input translates in an Input Voltage Range specification as explained in this
application section.
Differential Output
Considering a single positive supply (V-= GND, V+ = VS) the Input Common mode voltage, VCM_ATT = (+VIN + (VIN))/2 for the Attenuation inputs and VCM_AMP = (+IIN + (-IIN))/2 for the Amplification inputs, has to stay between
the MIN and MAX values determined by these formulas:
CMMAX = VS + 1/KV*(VS - VOCM)
CMMIN = -1/KV*VOCM
KV is a function of the Gain according to the table below:
Gain
0.096 V/V
0.192 V/V
0.384 V/V
0.768 V/V
1 V/V
2 V/V
KV
0.12
0.218
0.414
0.806
1.065
2.096
Regardless to the values derived by the formula, the voltage on each input pin must never exceed the specified
Absolute Maximum Ratings.
Below are some typical values:
Table 1. Differential Input, Differential Output, VS= 5V, VOCM = 2.5V
VCM_ATT
(1)
VCM_AMP
Gain
Min
Max
0.096 V/V
-15 V (1)
+15 V (1)
Min
Max
0.192 V/V
-11.5 V
+15 V
0.384 V/V
-6 V
+11 V
0.768 V/V
1 V/V
-3.1 V
+8.1 V
-2.3 V
+7.3 V
2 V/V
-1.2 V
+6.2 V
Limited by the operating ratings on input pins
In the case of a single ended input referred to ground (-VIN = GND, -IN = GND) the table below summarizes the
voltage range allowed on the +VIN and +IIN inputs.
Table 2. Single Ended Input, Differential Output, VS= 5V, VOCM = 2.5V, -VIN = GND, -IIN = GND
+VIN
Gain
(1)
(2)
16
Min
(1)
+IN
Max
+15 V
Min
Max
(1)
0.096 V/V
-15 V
0.192 V/V
-15 V (1)
+15 V (1)
0.384 V/V
-12 V
(2)
+12 V (2)
0.768 V/V
-6 V (2)
+6 V (2)
1 V/V
-4.6 V (2)
+4.6 V (2)
2 V/V
(2)
+2.3 V (2)
-2.3 V
Limited by the operating ratings on input pins.
Limited by the output voltage swing (0.2V to VS-0.2V on both + VOUT and -VOUT)
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Single Ended Output
In this mode the LMP7312 behaves as a Difference Amplifier, with -VOUT/VR being the reference output voltage
when a zero volt differential input signal is applied. The voltages at the OpAmp inputs are determined by +VIN
and -VOUT/VR voltages. The voltage range of +VIN and +IIN inputs is as follows:
VMAX = VS + 1/ KV * (VS – (-VOUT/VR))
VMIN = -1/KV * (-VOUT/VR)
Regardless of the values derived by the formula, the voltage on each input pin must never exceed the specified
Absolute Maximum Ratings.
Below are some typical values:
Table 3. Differential Input, Single Ended Output, VS = 5V, VOCM = GND, and -VOUT/VR = 2.5V
+VIN
Gain
Min
Max
1 V/V
-2.3 V
+7.3 V
2 V/V
-1.2 V
+6.2 V
0.096 V/V
(1)
+IIN
Min
-15 V
Max
(1)
+15 V
(1)
0.192 V/V
-11.5 V (1)
0.384 V/V
-6 V
+11 V
0.768 V/V
-3.1 V
+8.1 V
+15 V
Limited by the operating ratings on input pins
In the case of a single ended input referred to ground (-VIN = GND, -IN = GND) this table summarize the voltage
ranges allowed on the +VIN and +IIN inputs.
Table 4. Single Ended Input, Single Ended Output, VS = 5V, VOCM = GND, -VOUT/VR = 2.5V, -VIN = GND, -IIN =
GND
+VIN
Gain
+IIN
Min
(1)
0.096 V/V
-15 V
0.192 V/V
-11.5 V
(2)
0.384 V/V
-6 V
0.768 V/V
-3 V**
Max
+15 V
Min
Max
(1)
+12 V (2)
+6 V (2)
+3 V (2)
1 V/V
-2.3 V (2)
+2.3 V (2)
2 V/V
(2)
+1.1 V (2)
(1)
(2)
-1.1 V
Limited by the operating ratings on input pins.
Limited by the output voltage swing (0.2V to VS-0.2V on +VOUT )
SERIAL INTERFACE CONTROL OPERATION
The serial interface control of the LMP7312 can be supplied with a voltage between 2.7V and 5.5V through the
VIO pin for compatibility with different logic families present in the market.
The LMP7312 Attenuation, Amplification, Null switch and HiZ modes are controlled by a register. Data to be
written into the control register is first loaded into the LMP7312 via the serial interface. The serial interface
employs a 5-bit shift register. Data is loaded through the serial data input, SDI. Data passing through the shift
register is obtained through the serial data output, SDO. The serial clock, SCK controls the serial loading
process. All five data bits are required to correctly program the device. The falling edge of CS enables the shift
register to receive data. The SCK signal must be high during the falling edge of CS. Each data bit is clocked into
the shift register on the rising edge of SCK. Data is transferred from the shift register to the holding register on
the rising edge of CS. Operation is shown in the Timing Diagram.
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SPI Registers
MSB
Gain_1
LSB
Gain_0
EN_CL
Null_SW
Hi_Z
Gain_0, Gain_1 bit:Gain Values
Different gains are available in Attenuation Mode or Amplification Mode according to the following Gain Table.
Gain_1
Gain_0
EN_CL
Gain Value (V/V)
0
0
0
0.096
0
1
0
0.192
1
0
0
0.384
1
1
0
0.768
1
0
1
1
1
1
1
2
EN_CL bit:Enable Amplification Mode
This register selects which input pair is processed.
EN_CL
Mode
0
Attenuation Mode
Description
1
Amplification Mode
±VIN inputs are processed through the 104.16k input resistors
±IN inputs are processed through the 40k input resistors
NULL_SW bit: Input Offset Nulling Switch Mode
This register selects a mode in which the amplifier is not processing any input but it is configured in unity gain to
allow system level amplifier offset calibration. The Nulling Switch mode is available in both single ended and fully
differential output mode. The LMP7312 in Nulling Switch and fully differential mode has he following
configuration.
18
NULL_SW
Mode
Description
0
Normal Operation Mode
±VIN and ±IN inputs are processed depending on EN_CL register
setting.
1
Nulling Switch Mode
Enables to evaluate the offset of the internal amplifier for system
level calibration
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VIO
+
V
R1N
-VIN
R2 N
RFP
-IN
+IN
-
+VOUT
+
-VOUT/VR
R2 P
+VIN
V
+
RF
R1 P
N
100 k:
VOCM
100 k:
-
V
-
V
Figure 37. LMP7312 in Nulling Switch Mode
In this condition at the Output pins is possible to measure the input voltage offset of the op-amp:
Output Mode
Differential
Single-Ended
+VOUT
−VOUT/VR
VCM_out+VOS/2
VCM_out -VOS/2
VR+VOS
VR
Hi_Z bit:High Impedance
In this mode both outputs +VOUT and -VOUT/VR of the LMP7312 are in tri-state Figure 38.
HI_Z
Mode
0
Normal Operation Mode
Description
1
High Impedance Mode
The LMP7312 is configured according to value of the other 4 bits of the
register.
The LMP7312 output is in high impedance
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+
VIO
V
R1N
-VIN
RFP
R2 N
-IN
+IN
-
+VOUT
+
-VOUT/VR
R2 P
+VIN
V
+
R1 P
RF
N
100 k:
VOCM
100 k:
-
V
-
V
Figure 38. LMP7312 in High Impedance Mode
In each case the SPI registers require 5 bits. The table below is a summary of all allowed configurations.
MSB
LSB
Gain_1
Gain_0
EN_CL
Null_SW
Hi_Z
Gain Value (V/V)
Mode of Operation
0
0
0
0
0
0.096
Attenuation Mode
0
1
0
0
0
0.192
Attenuation Mode
1
0
0
0
0
0.384
Attenuation Mode
1
1
0
0
0
0.768
Attenuation Mode
1
0
1
0
0
1
Amplification Mode
1
1
1
0
0
2
Amplification Mode
x
x
x
x
1
–
High Impedance Output
x
x
x
1
0
1
Null Switch Mode
Daisy Chain
The LMP7312 supports daisy chaining of the serial data stream between multiple chips. To use this feature serial
data is clocked into the first chip SDI pin, and the next chip SDI pin is connected to the SDO pin of the first chip.
Both chips may share a chip select signal, or the second chip can be enabled separately. When the chip select
pin goes low on both chips and 5 bits have been clocked into the first chip the next 5 clock cycle begins moving
new configuration data into the second chip. With a full 10 clock cycles both chips have valid data and the chip
select pin of both chips should be brought high to prevent the data from overshooting.
20
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CS
CS
CS
LMP7312
LMP7312
éController
MOSI
SDI
SDO
SDO
SDI
SCK
SCK
SCK
MISO
Figure 39. Daisy Chain
Shared 4-wire SPI with ADC
The LMP7312 is a good choice when interfacing to differential analog to digital converters ADC141S626 and
ADC161S626 of PowerWise® Family. Its SPI interface has been designed to enable sharing CSB with the ADC.
LMP7312 register access happens only when CSB is asserted low while SCK is high. However, the ADC starts
conversion under any of the following conditions:
1. CSB goes low while SCK is high
2. CSB goes low while SCK is low
3. CSB and SCK both going low
Therefore, if a system uses timing condition #2 above, LMP7312 and ADC1x1S626 can share CSB and SCK as
shown in Figure 40. The only side-effect would be that writing to LMP7312 triggers an ADC conversion, but then
the result can be ignored. At other times, the LMP7312 is not affected by the CSB assertions used to initiate
normal ADC conversions.
CS
CS
CS
LMP7312
ADC1x1S626
éController
MOSI
SDI
SDO
SCK
SCK
SCK
MISO
Figure 40. 4-wire SPI with ADC interface
LMP7312 IN 4-20mA CURRENT LOOP APPLICATION
The 4-20mA current loop shown in Figure 41 is a common method of transmitting sensor information in many
industrial process-monitoring applications. Transmitting sensor information via a current loop is particularly useful
when the information has to be sent to a remote location over long distances (1000 feet, or more). The loop’s
operation is straightforward: a sensor’s output voltage is first converted to a proportional current, with 4mA
normally representing the sensor’s zero-level output, and 20mA representing the sensor’s full-scale output. Then,
a receiver at the remote end converts the 4-20mA current back into a voltage which in turn can be further
processed by a computer or display module. A typical 4-20mA current-loop circuit is made up of four individual
elements: a sensor/transducer; a voltage-to-current converter (commonly referred to as a transmitter and/or
signal conditioner); a loop power supply; and a receiver/monitor. In loop powered applications, all four elements
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are connected in a closed, series circuit, loop configuration (Figure 41). Sensors provide an output voltage whose
value represents the physical parameter being measured. The transmitter amplifies and conditions the sensor’s
output, and then converts this voltage to a proportional 4-20mA dc-current that circulates within the closed
series-loop. The loop power-supply generally provides all operating power to the transmitter and receiver, and
any other loop components that require a well-regulated dc voltage. In loop-powered applications, the power
supply’s internal elements also furnish a path for closing the series loop. The receiver/monitor, normally a
subsection of a panel meter or data acquisition system, converts the 4-20mA current back into a voltage which
can be further processed and/or displayed. The high DC performance of the LMP7312 makes this difference
amplifier an ideal choice for use in current loop AFE receiver. The LMP7312 has a low input offset voltage and
low input offset voltage drift when configured in amplification mode. In the circuit shown in Figure 41 the
LMP7312 is in amplification mode with a gain of 2V/V and differential output in order to well match the input
stage of the ADC141S626 (SAR ADC with differential input). The shunt resistor is 100ohm in order to have a
max voltage drop of 2V when 20mA flows in the loop. The first order filter between the LMP7312 and the
ADC141S626 reduces the noise bandwidth and allows handling input signal up to 2kHz. That frequency has
been calculated taking in account the roll off of the filter and ensuring a gain error less than 1LSB of the
ADC141S626. In order to utilize the maximum number of bits of the ADC141S626 in this configuration, a 4.1V
reference voltage is used. With this system, the current of the 4-20mA loop is accurately gained to the full scale
of the ADC and then digitized for further processing.
+5V
+
0.1 PF
10 PF
+
VIO
V
+5V
-VIN
+
+VOUT
-
SENSOR
T
R
A
N
S
M
I
T
T
E
R
100:
-
-IN
+
1.1k:
VA
+
I_LOOP
-VOUT/VR
V
+VIN
0.1 PF
VOCM
V
+5V
LM4132-4.1
+
+
4.7 PF
4.7 PF
100 k:
-
REF
0.1 PF
100 k:
10 PF
1.1k:
Fs = 70 kS/s
+
0.1 PF
ADC141S626
680 pF
+IN
VIO
-
AMPLIFICATION MODE
G = 2 V/V
V
Figure 41. LMP7312 in 4-20mA Current Loop application
LAYOUT CONSIDERATIONS
Power supply bypassing
In order to preserve the gain accuracy of the LMP7312, power supply stability requires particular attention. The
LMP7312 ensures minimum PSRR of 90dB (or 31.62 µV/V). However, the dynamic range, the gain accuracy and
the inherent low-noise of the amplifier can be compromised by introducing and amplifying power supply noise. To
decouple the LMP7312 from supply line AC noise, a 0.1 µF ceramic capacitor should be located on the supply
line, close to the LMP7312. Adding a 10 µF tantalum capacitor in parallel with the 0.1 µF ceramic capacitor will
reduce the noise introduced to the LMP7312 even further by providing an AC path to ground for most frequency
ranges.
22
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LMP7312
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SNOSB32B – MARCH 2010 – REVISED MARCH 2013
APPENDIX
Offset Voltage and Offset Voltage Drift calculation
Listed in the table below are the calculated values for Offset Voltage and Offset Voltage Drift based on the max
specifications of these parameters for the core op-amp (for all gain configurations).
Parameter
Unit
Value
Gain
V/V
0.096
0.192
0.384
0.768
1
2
Total Offset Input Referred (MAX)
µV
±1141
±620
±360
±230
±200
±150
Total Offset Output Referred (MAX)
µV
±109
±119
±138
±176
±200
±300
TCVOS Input Referred @ 25°C (MAX)
µV/°C
±32.3
±18.6
±10.8
±6.9
±6
±4.5
TCVOS Output Referred @ 25°C (MAX)
µV/°C
±3.3
±3.6
±4.1
±5.3
±6
±9
Noise calculation
Listed in the table below are the calculated values for Voltage Noise based on the spectral density of the core
op-amp at 10kHz (for all gain configurations).
Parameter
Unit
Gain
Value
V/V
0.096
0.192
0.384
0.768
1
2
Total Noise Referred to Input
nV/√Hz
211
150
112
89
53
46
Total Noise Referred to Output
nV/√Hz
20
29
43
68
53
92
Input resistance calculation
The common mode input resistance is the resistance seen from node “A” when ΔV1 = ΔV2 = 0 and a common
mode voltage ΔVCM is applied to both inputs of the LMP7312. The differential input resistance is the resistance
seen from the nodes “B” and “C” when ΔVCM=0 and a differential voltage ΔV1 = ΔV2 = V/2 is applied to the
inputs of the LMP7312.
B
+
A
+
-
+
-
ÂV1
-
ÂV2
+
ÂVCM
C
Figure 42. Circuit for Input Resistance calculation
Mode of Operation
Unit
Attenuation Mode
Gains
0.096
0.192
0.384
Common Mode Resistance
kΩ
57.08
62.08
72.08
92.08
Differential Resistance
kΩ
228.30
248.30
288.30
368.30
1
2
Common Mode Resistance
kΩ
40.0
60.0
Differential Resistance
kΩ
160.0
240.0
Amplification Mode
0.768
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23
LMP7312
SNOSB32B – MARCH 2010 – REVISED MARCH 2013
www.ti.com
REVISION HISTORY
Changes from Revision A (March 2013) to Revision B
•
24
Page
Changed layout of National Data Sheet to TI format .......................................................................................................... 23
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PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
(4/5)
(6)
LMP7312MA/NOPB
ACTIVE
SOIC
D
14
55
RoHS & Green
SN
Level-1-260C-UNLIM
-40 to 125
LMP7312
MA
LMP7312MAX/NOPB
ACTIVE
SOIC
D
14
2500
RoHS & Green
SN
Level-1-260C-UNLIM
-40 to 125
LMP7312
MA
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of
