LMP7712MM

National Semiconductor is now part of Texas Instruments. Search http://www.ti.com/ for the latest technical information and details on our current products and services. LMP7711/LMP7712 Single and Dual Precision, 17 MHz, Low Noise, CMOS Input Amplifiers General Description Features The LMP7711/LMP7712 are single and dual low noise, low offset, CMOS input, rail-to-rail output precision amplifiers with a high gain bandwidth product and an enable pin. The LMP7711/LMP7712 are part of the LMP® precision amplifier family and are ideal for a variety of instrumentation applications. Utilizing a CMOS input stage, the LMP7711/LMP7712 achieve an input bias current of 100 fA, an input referred voltage noise of 5.8 nV/√Hz, and an input offset voltage of less than ±150 μV. These features make the LMP7711/LMP7712 superior choices for precision applications. Consuming only 1.15 mA of supply current, the LMP7711 offers a high gain bandwidth product of 17 MHz, enabling accurate amplification at high closed loop gains. The LMP7711/LMP7712 have a supply voltage range of 1.8V to 5.5V, which makes these ideal choices for portable low power applications with low supply voltage requirements. In order to reduce the already low power consumption the LMP7711/LMP7712 have an enable function. Once in shutdown, the LMP7711/LMP7712 draw only 140 nA of supply current. The LMP7711/LMP7712 are built with National’s advanced VIP50 process technology. The LMP7711 is offered in a 6-pin TSOT23 package and the LMP7712 is offered in a 10-pin MSOP. Unless otherwise noted, typical values at VS = 5V. ±150 μV (max) ■ Input offset voltage 100 fA ■ Input bias current 5.8 nV/√Hz ■ Input voltage noise 17 MHz ■ Gain bandwidth product 1.15 mA ■ Supply current (LMP7711) 1.30 mA ■ Supply current (LMP7712) 1.8V to 5.5V ■ Supply voltage range 0.001% ■ THD+N @ f = 1 kHz −40°C to 125°C ■ Operating temperature range ■ Rail-to-rail output swing ■ Space saving TSOT23 package (LMP7711) ■ 10-pin MSOP package (LMP7712) Applications ■ Active filters and buffers ■ Sensor interface applications ■ Transimpedance amplifiers Typical Performance Offset Voltage Distribution Input Referred Voltage Noise 20150322 20150339 LMP® is a registered trademark of National Semiconductor Corporation. © 2008 National Semiconductor Corporation 201503 www.national.com LMP7711/LMP7712 Precision, 17 MHz, Low Noise, CMOS Input Amplifiers July 3, 2008 LMP7711/LMP7712 Soldering Information Infrared or Convection (20 sec) Wave Soldering Lead Temp. (10 sec) Absolute Maximum Ratings (Note 1) If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/ Distributors for availability and specifications. ESD Tolerance (Note 2) Human Body Model Machine Model Charge-Device Model VIN Differential Supply Voltage (VS = V+ – V−) Voltage on Input/Output Pins Storage Temperature Range Junction Temperature (Note 3) Operating Ratings (Note 1) Temperature Range (Note 3) Supply Voltage (VS = V+ – V−) 2000V 200V 1000V ±0.3V 6.0V V+ +0.3V, V− −0.3V −65°C to 150°C +150°C 235°C 260°C −40°C to 125°C 0°C ≤ TA ≤ 125°C 1.8V to 5.5V −40°C ≤ TA ≤ 125°C 2.0V to 5.5V Package Thermal Resistance (θJA(Note 3)) 6-Pin TSOT23 10-Pin MSOP 170°C/W 236°C/W 2.5V Electrical Characteristics Unless otherwise specified, all limits are guaranteed for TA = 25°C, V+ = 2.5V, V− = 0V ,VO = VCM = V+/2, VEN = V+. Boldface limits apply at the temperature extremes. Symbol Parameter Conditions VOS Input Offset Voltage TC VOS Input Offset Voltage Temperature Drift LMP7711 (Notes 6, 8) LMP7712 IB Input Bias Current Min (Note 5) Typ (Note 4) Max (Note 5) Units ±20 ±180 ±480 μV ±4 μV/°C –1 –1.75 VCM = 1.0V (Notes 7, 8) −40°C ≤ TA ≤ 85°C 0.05 1 25 −40°C ≤ TA ≤ 125°C 0.05 1 100 0.006 0.5 50 IOS Input Offset Current VCM = 1.0V (Note 8) CMRR Common Mode Rejection Ratio 0V ≤ VCM ≤ 1.4V 83 80 100 PSRR Power Supply Rejection Ratio 2.0V ≤ V+ ≤ 5.5V V− = 0V, VCM = 0 85 80 100 1.8V ≤ V+ ≤ 5.5V V− = 0V, VCM = 0 85 98 CMVR Common Mode Voltage Range CMRR ≥ 80 dB −0.3 –0.3 CMRR ≥ 78 dB AVOL Open Loop Voltage Gain LMP7711, VO = 0.15 to 2.2V RL = 2 kΩ to V+/2 LMP7712, VO = 0.15 to 2.2V RL = 2 kΩ to V+/2 LMP7711, VO = 0.15 to 2.2V RL = 10 kΩ to V+/2 LMP7712, VO = 0.15 to 2.2V RL = 10 kΩ to V+/2 VOUT Output Voltage Swing High Output Voltage Swing Low www.national.com 98 84 80 92 92 88 110 90 86 95 dB V dB RL = 2 kΩ to V+/2 25 70 77 RL = 10 kΩ to V+/2 20 60 66 RL = 2 kΩ to V+/2 30 70 73 RL = 10 kΩ to V+/2 15 60 62 2 pA dB 1.5 1.5 88 82 pA mV from either rail IOUT IS Parameter Output Current Supply Current Conditions Min (Note 5) Typ (Note 4) Sourcing to V− VIN = 200 mV (Note 9) 36 30 52 Sinking to V+ VIN = −200 mV (Note 9) 7.5 5.0 15 LMP7711 1.30 1.65 1.10 1.50 1.85 0.03 1 4 Enable Mode VEN ≥ 2.1 Shutdown Mode (per channel) VEN ≤ 0.4 SR Slew Rate GBW Gain Bandwidth en Input Referred Voltage Noise Density AV = +1, Rising (10% to 90%) 8.3 AV = +1, Falling (90% to 10%) 10.3 f = 400 Hz 6.8 f = 1 kHz 5.8 f = 1 kHz 0.01 Units mA 0.95 Enable Mode VEN ≥ 2.1 LMP7712 (per channel) Max (Note 5) mA μA V/μs 14 MHz nV/ in Input Referred Current Noise Density ton Turn-on Time 140 ns toff Turn-off Time 1000 ns VEN Enable Pin Voltage Range Enable Mode 2.1 Shutdown Mode IEN THD+N Enable Pin Input Current Total Harmonic Distortion + Noise pA/ 2 - 2.5 0 - 0.5 0.4 1.5 3.0 VEN = 0V (Note 7) 0.003 0.1 f = 1 kHz, AV = 1, RL = 100 kΩ VO = 0.9 VPP 0.003 f = 1 kHz, AV = 1, RL = 600Ω VO = 0.9 VPP 0.004 VEN = 2.5V (Note 7) V μA % 5V Electrical Characteristics Unless otherwise specified, all limits are guaranteed for TA = 25°C, V+ = 5V, V− = 0V, VCM = V+/2, VEN = V+. Boldface limits apply at the temperature extremes. Symbol Parameter Conditions VOS Input Offset Voltage TC VOS Input Offset Voltage Temperataure Drift LMP7711 (Notes 6, 8) LMP7712 IB Input Bias Current Min (Note 5) Typ (Note 4) Max (Note 5) Units ±10 ±150 ±450 μV ±4 μV/°C –1 –1.75 VCM = 2.0V (Notes 7, 8) −40°C ≤ TA ≤ 85°C 0.1 1 25 −40°C ≤ TA ≤ 125°C 0.1 1 100 0.01 0.5 50 IOS Input Offset Current VCM = 2.0V (Note 8) CMRR Common Mode Rejection Ratio 0V ≤ VCM ≤ 3.7V 85 82 100 PSRR Power Supply Rejection Ratio 2.0V ≤ V+ ≤ 5.5V V− = 0V, VCM = 0 85 80 100 1.8V ≤ V+ ≤ 5.5V V− = 0V, VCM = 0 85 98 3 pA pA dB dB www.national.com LMP7711/LMP7712 Symbol LMP7711/LMP7712 Symbol CMVR Parameter Common Mode Voltage Range Conditions CMRR ≥ 80 dB Open Loop Voltage Gain LMP7711, VO = 0.3 to 4.7V RL = 2 kΩ to V+/2 LMP7712, VO = 0.3 to 4.7V RL = 2 kΩ to V+/2 LMP7711, VO = 0.3 to 4.7V RL = 10 kΩ to V+/2 LMP7712, VO = 0.3 to 4.7V RL = 10 kΩ to V+/2 VOUT Output Voltage Swing High Output Voltage Swing Low IOUT IS Output Current Supply Current Typ (Note 4) −0.3 –0.3 CMRR ≥ 78 dB AVOL Min (Note 5) 4 4 88 82 107 84 80 90 92 88 110 90 86 95 32 70 77 RL = 10 kΩ to V+/2 22 60 66 RL = 2 kΩ to V+/2 (LMP7711) 42 70 73 RL = 2 kΩ to V+/2 (LMP7712) 50 75 78 RL = 10 kΩ to V+/2 20 60 62 Sourcing to V− VIN = 200 mV (Note 9) 46 38 66 Sinking to V+ VIN = −200 mV (Note 9) 10.5 6.5 23 LMP7711 1.40 1.75 1.30 1.70 2.05 0.14 1 4 Enable Mode VEN ≥ 4.6 Shutdown Mode VEN ≤ 0.4 (per channel) Slew Rate GBW Gain Bandwidth en Input Referred Voltage Noise Density AV = +1, Rising (10% to 90%) 6.0 9.5 AV = +1, Falling (90% to 10%) 7.5 11.5 7.0 f = 1 kHz 5.8 f = 1 kHz 0.01 mV from either rail mA μA V/μs 17 f = 400 Hz V mA 1.15 Enable Mode VEN ≥ 4.6 Units dB RL = 2 kΩ to V+/2 LMP7712 (per channel) SR Max (Note 5) MHz nV/ in Input Referred Current Noise Density ton Turn-on Time 110 ns toff Turn-off Time 800 ns VEN Enable Pin Voltage Range Enable Mode 4.6 Shutdown Mode IEN THD+N Enable Pin Input Current Total Harmonic Distortion + Noise www.national.com pA/ 4.5 – 5 0 – 0.5 0.4 VEN = 5V (Note 7) 5.6 10 VEN = 0V (Note 7) 0.005 0.2 f = 1 kHz, AV = 1, RL = 100 kΩ VO = 4 VPP 0.001 f = 1 kHz, AV = 1, RL = 600Ω VO = 4 VPP 0.004 4 V μA % Note 2: Human Body Model, applicable std. MIL-STD-883, Method 3015.7. Machine Model, applicable std. JESD22-A115-A (ESD MM std. of JEDEC) Field-Induced Charge-Device Model, applicable std. JESD22-C101-C (ESD FICDM std. of JEDEC). Note 3: The maximum power dissipation is a function of TJ(MAX), θJA. The maximum allowable power dissipation at any ambient temperature is PD = (TJ(MAX) - TA)/θJA. All numbers apply for packages soldered directly onto a PC Board. Note 4: Typical values represent the most likely parametric norm as determined at the time of characterization. Actual typical values may vary over time and will also depend on the application and configuration. The typical values are not tested and are not guaranteed on shipped production material. Note 5: Limits are 100% production tested at 25°C. Limits over the operating temperature range are guaranteed through correlations using the Statistical Quality Control (SQC) method. Note 6: Offset voltage average drift is determined by dividing the change in VOS at the temperature extremes by the total temperature change. Note 7: Positive current corresponds to current flowing into the device. Note 8: This parameter is guaranteed by design and/or characterization and is not tested in production. Note 9: The short circuit test is a momentary open loop test. Connection Diagrams 6-Pin TSOT23 10-Pin MSOP 20150301 Top View 20150302 Top View Ordering Information Package Part Number Package Marking LMP7711MK 6-Pin TSOT23 10-Pin MSOP LMP7711MKE Transport Media AC3A 250 Units Tape and Reel LMP7711MKX 3k Units Tape and Reel LMP7712MM 1k Units Tape and Reel LMP7712MME NSC Drawing 1k Units Tape and Reel AD3A 250 Units Tape and Reel LMP7712MMX MK06A MUB10A 3.5k Units Tape and Reel 5 www.national.com LMP7711/LMP7712 Note 1: Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for which the device is intended to be functional, but specific performance is not guaranteed. For guaranteed specifications and the test conditions, see the Electrical Characteristics Tables. LMP7711/LMP7712 Typical Performance Characteristics Unless otherwise noted: TA = 25°C, VS = 5V, VCM = VS/2, VEN = V+. Offset Voltage Distribution TCVOS Distribution (LMP7711) 20150303 20150381 Offset Voltage Distribution TCVOS Distribution (LMP7712) 20150322 20150380 Offset Voltage vs. VCM Offset Voltage vs. VCM 20150310 www.national.com 20150311 6 LMP7711/LMP7712 Offset Voltage vs. VCM Offset Voltage vs. Supply Voltage 20150321 20150312 Offset Voltage vs. Temperature CMRR vs. Frequency 20150356 20150309 Input Bias Current Over Temperature Input Bias Current Over Temperature 20150323 20150324 7 www.national.com LMP7711/LMP7712 Supply Current vs. Supply Voltage (LMP7711) Supply Current vs. Supply Voltage (LMP7712) 20150305 20150377 Supply Current vs. Supply Voltage (Shutdown) Crosstalk Rejection Ratio (LMP7712) 20150376 20150306 Supply Current vs. Enable Pin Voltage (LMP7711) Supply Current vs. Enable Pin Voltage (LMP7711) 20150308 www.national.com 20150307 8 Supply Current vs. Enable Pin Voltage (LMP7712) 20150378 20150379 Sourcing Current vs. Supply Voltage Sinking Current vs. Supply Voltage 20150320 20150319 Sourcing Current vs. Output Voltage Sinking Current vs. Output Voltage 20150350 20150354 9 www.national.com LMP7711/LMP7712 Supply Current vs. Enable Pin Voltage (LMP7712) LMP7711/LMP7712 Output Swing High vs. Supply Voltage Output Swing Low vs. Supply Voltage 20150317 20150315 Output Swing High vs. Supply Voltage Output Swing Low vs. Supply Voltage 20150316 20150314 Output Swing High vs. Supply Voltage Output Swing Low vs. Supply Voltage 20150318 www.national.com 20150313 10 LMP7711/LMP7712 Open Loop Frequency Response Open Loop Frequency Response 20150373 20150341 Phase Margin vs. Capacitive Load Phase Margin vs. Capacitive Load 20150345 20150346 Overshoot and Undershoot vs. Capacitive Load Slew Rate vs. Supply Voltage 20150330 20150329 11 www.national.com LMP7711/LMP7712 Small Signal Step Response Large Signal Step Response 20150338 20150337 Small Signal Step Response Large Signal Step Response 20150334 20150333 THD+N vs. Output Voltage THD+N vs. Output Voltage 20150326 www.national.com 20150304 12 LMP7711/LMP7712 THD+N vs. Frequency THD+N vs. Frequency 20150357 20150355 PSRR vs. Frequency Time Domain Voltage Noise 20150382 20150328 Input Referred Voltage Noise vs. Frequency Closed Loop Frequency Response 20150339 20150336 13 www.national.com LMP7711/LMP7712 Closed Loop Output Impedance vs. Frequency 20150332 CAPACITIVE LOAD The unity gain follower is the most sensitive configuration to capacitive loading. The combination of a capacitive load placed directly on the output of an amplifier along with the output impedance of the amplifier creates a phase lag which in turn reduces the phase margin of the amplifier. If phase margin is significantly reduced, the response will be either underdamped or the amplifier will oscillate. The LMP7711/LMP7712 can directly drive capacitive loads of up to 120 pF without oscillating. To drive heavier capacitive loads, an isolation resistor, RISO in Figure 1, should be used. This resistor and CL form a pole and hence delay the phase lag or increase the phase margin of the overall system. The larger the value of RISO, the more stable the output voltage will be. However, larger values of RISO result in reduced output swing and reduced output current drive. Application Notes LMP7711/LMP7712 The LMP7711/LMP7712 are single and dual, low noise, low offset, rail-to-rail output precision amplifiers with a wide gain bandwidth product of 17 MHz and low supply current. The wide bandwidth makes the LMP7711/LMP7712 ideal choices for wide-band amplification in portable applications. The low supply current along with the enable feature that is built-in on the LMP7711/LMP7712 allows for even more power efficient designs by turning the device off when not in use. The LMP7711/LMP7712 are superior for sensor applications. The very low input referred voltage noise of only 5.8 nV/ at 1 kHz and very low input referred current noise of only 10 mean more signal fidelity and higher signal-to-noise fA/ ratio. The LMP7711/LMP7712 have a supply voltage range of 1.8V to 5.5V over a wide temperature range of 0°C to 125°C. This is optimal for low voltage commercial applications. For applications where the ambient temperature might be less than 0° C, the LMP7711/LMP7712 are fully operational at supply voltages of 2.0V to 5.5V over the temperature range of −40°C to 125°C. The outputs of the LMP7711/LMP7712 swing within 25 mV of either rail providing maximum dynamic range in applications requiring low supply voltage. The input common mode range of the LMP7711/LMP7712 extends to 300 mV below ground. This feature enables users to utilize this device in single supply applications. The use of a very innovative feedback topology has enhanced the current drive capability of the LMP7711/LMP7712, resulting in sourcing currents as much as 47 mA with a supply voltage of only 1.8V. The LMP7711 is offered in the space saving TSOT23 package and the LMP7712 is offered in a 10-pin MSOP. These small packages are ideal solutions for applications requiring minimum PC board footprint. National Semiconductor is heavily committed to precision amplifiers and the market segments they serves. Technical support and extensive characterization data is available for sensitive applications or applications with a constrained error budget. www.national.com 20150361 FIGURE 1. Isolating Capacitive Load INPUT CAPACITANCE CMOS input stages inherently have low input bias current and higher input referred voltage noise. The LMP7711/LMP7712 enhance this performance by having the low input bias current of only 50 fA, as well as, a very low input referred voltage noise of 5.8 nV/ . In order to achieve this a larger input stage has been used. This larger input stage increases the input capacitance of the LMP7711/LMP7712. Figure 2 shows typical input common mode input capacitance of the LMP7711/LMP7712. 14 20150375 FIGURE 2. Input Common Mode Capacitance This input capacitance will interact with other impedances such as gain and feedback resistors, which are seen on the inputs of the amplifier to form a pole. This pole will have little or no effect on the output of the amplifier at low frequencies and under DC conditions, but will play a bigger role as the frequency increases. At higher frequencies, the presence of this pole will decrease phase margin and also causes gain peaking. In order to compensate for the input capacitance, care must be taken in choosing feedback resistors. In addition to being selective in picking values for the feedback resistor, a capacitor can be added to the feedback path to increase stability. The DC gain of the circuit shown in Figure 3 is simply −R2/ R1. 20150359 FIGURE 4. Closed Loop Frequency Response As mentioned before, adding a capacitor to the feedback path will decrease the peaking. This is because CF will form yet another pole in the system and will prevent pairs of poles, or complex conjugates from forming. It is the presence of pairs of poles that cause the peaking of gain. Figure 5 shows the frequency response of the schematic presented in Figure 3 with different values of CF. As can be seen, using a small value capacitor significantly reduces or eliminates the peaking. 20150364 FIGURE 3. Compensating for Input Capacitance For the time being, ignore CF. The AC gain of the circuit in Figure 3 can be calculated as follows: 20150360 FIGURE 5. Closed Loop Frequency Response TRANSIMPEDANCE AMPLIFIER In many applications, the signal of interest is a very small amount of current that needs to be detected. Current that is transmitted through a photodiode is a good example. Barcode scanners, light meters, fiber optic receivers, and industrial sensors are some typical applications utilizing photodiodes (1) This equation is rearranged to find the location of the two poles: 15 www.national.com LMP7711/LMP7712 (2) As shown in Equation 2, as the values of R1 and R2 are increased, the magnitude of the poles are reduced, which in turn decreases the bandwidth of the amplifier. Figure 4 shows the frequency response with different value resistors for R1 and R2. Whenever possible, it is best to chose smaller feedback resistors. LMP7711/LMP7712 for current detection. This current needs to be amplified before it can be further processed. This amplification is performed using a current-to-voltage converter configuration or transimpedance amplifier. The signal of interest is fed to the inverting input of an op amp with a feedback resistor in the current path. The voltage at the output of this amplifier will be equal to the negative of the input current times the value of the feedback resistor. Figure 6 shows a transimpedance amplifier configuration. CD represents the photodiode parasitic capacitance and CCM denotes the common-mode capacitance of the amplifier. The presence of all of these capacitances at higher frequencies might lead to less stable topologies at higher frequencies. Care must be taken when designing a transimpedance amplifier to prevent the circuit from oscillating. With a wide gain bandwidth product, low input bias current and low input voltage and current noise, the LMP7711/ LMP7712 are ideal for wideband transimpedance applications. 20150331 FIGURE 7. Modified Transimpedance Amplifier SENSOR INTERFACE The LMP7711/LMP7712 have low input bias current and low input referred noise, which make them ideal choices for sensor interfaces such as thermopiles, Infra Red (IR) thermometry, thermocouple amplifiers, and pH electrode buffers. Thermopiles generate voltage in response to receiving radiation. These voltages are often only a few microvolts. As a result, the operational amplifier used for this application needs to have low offset voltage, low input voltage noise, and low input bias current. Figure 8 shows a thermopile application where the sensor detects radiation from a distance and generates a voltage that is proportional to the intensity of the radiation. The two resistors, RA and RB, are selected to provide high gain to amplify this signal, while CF removes the high frequency noise. 20150369 FIGURE 6. Transimpedance Amplifier A feedback capacitance CF is usually added in parallel with RF to maintain circuit stability and to control the frequency response. To achieve a maximally flat, 2nd order response, RF and CF should be chosen by using Equation 3 20150327 (3) FIGURE 8. Thermopile Sensor Interface Calculating CF from Equation 3 can sometimes result in capacitor values which are less than 2 pF. This is especially the case for high speed applications. In these instances, its often more practical to use the circuit shown in Figure 7 in order to allow more sensible choices for CF. The new feedback capacitor, C′F, is (1+ RB/RA) CF. This relationship holds as long as RA